Display panel and display device

Abstract

A display panel comprises: a substrate (10) comprising a display area (AA) and a fan-out area (FA); a chip (IC), wherein the fan-out area (FA) is located between the display area (AA) and the chip (IC); a plurality of data routing lines (600) located in the fan-out area (FA), respectively electrically connecting a plurality of data lines (DL) to the chip (IC); a plurality of touch routing lines (800) located in the fan-out area (FA), respectively electrically connecting a plurality of touch signal lines (TL) to the chip (IC). A portion of the plurality of data routing lines (600) is located in a first conductive layer, and the remaining portion is located in a second conductive layer. A portion of the plurality of touch routing lines (800) is located in at least one of the first conductive layer and the second conductive layer, and the remaining portion is located in a third conductive layer. The pitch between any two adjacent routing lines in the first conductive layer is the first routing pitch (pt1), the pitch between any two adjacent routing lines in the second conductive layer is the second routing pitch (pt2), and the pitch between any two adjacent routing lines in the third conductive layer is the third routing pitch (pt3). Either the first routing pitch (pt1) or the second routing pitch (pt2) is smaller than the third routing pitch (pt3).

Description

Technical Field

[0001] Embodiments of the present disclosure relate to the field of display technology, and particularly to a display panel and a display device. Background Art

[0002] With the development of display technology, full screen has gradually become one of the trends of display devices. The design of full screen is to pursue narrow border or borderless design in each border position, and pursue a screen-to-body ratio close to 100%. The lower border of the display panel is mainly limited by the height of the fan-out area routing, and the height of the fan-out area routing is mainly limited by the number of wiring layers, the number of wirings and the wiring pitch. In the related art, the height of the fan-out area routing is relatively high, which makes it impossible to further reduce the lower border of the display panel.

[0003] The above information disclosed in this section is only for understanding the background of the technical concept of the present disclosure and therefore, the above information may contain information that does not constitute the prior art. Summary of the invention

[0004] In one aspect, a display panel is provided, comprising:

[0005] A base substrate, the base substrate comprising a display area and a first side area, the first side area is located at a first side of the display area, and the first side area comprises a fan-out area;

[0006] A plurality of pixel units, at least some of the plurality of pixel units are arranged in an array along a first direction and a second direction in a display area of ​​the base substrate, the first direction and the second direction intersecting;

[0007] A plurality of touch control units, at least some of which are arranged in an array along a first direction and a second direction in a display area of ​​the base substrate;

[0008] a plurality of data lines, at least a portion of which is located in the display area, and the plurality of data lines are electrically connected to the plurality of pixel units, respectively, for supplying data signals to the respective pixel units;

[0009] a plurality of touch signal lines, at least a portion of which is located in the display area, and the plurality of touch signal lines are electrically connected to the plurality of touch units, respectively, for supplying touch signals to the respective touch units;

[0010] A chip, wherein the chip is located in the first side area, and the fan-out area is located between the display area and the chip;

[0011] A plurality of data routing lines, the plurality of data routing lines are located in the fan-out area, and the plurality of data routing lines electrically connect the plurality of data lines to the chip respectively;

[0012] a plurality of touch lines, the plurality of touch lines being located in the fan-out area, the plurality of touch lines electrically connecting the plurality of touch signal lines to the chip respectively,

[0013] The display panel includes a first conductive layer, a second conductive layer and a third conductive layer arranged on the base substrate.

[0014] A portion of the plurality of data routing lines is located in the first conductive layer, and a remaining portion of the plurality of data routing lines is located in the second conductive layer.

[0015] A portion of the plurality of touch traces is located in at least one of the first conductive layer and the second conductive layer, and a remaining portion of the plurality of touch traces is located in the third conductive layer,

[0016] The pitch between any two adjacent routing lines in the first conductive layer is the first routing pitch, the pitch between any two adjacent routing lines in the second conductive layer is the second routing pitch, the pitch between any two adjacent routing lines in the third conductive layer is the third routing pitch, and either the first routing pitch or the second routing pitch is smaller than the third routing pitch.

[0017] According to some exemplary embodiments, in the fan-out area, the space occupied by each routing in the first conductive layer and the first routing interval between each routing has a first width, the space occupied by each routing in the second conductive layer and the second routing interval between each routing has a second width, and the space occupied by each routing in the third conductive layer and the third routing interval between each routing has a third width; the ratio of any two of the first width, the second width and the third width is between 0.95 and 1.05.

[0018] According to some exemplary embodiments, the number of the plurality of data wirings is m, and the number of the plurality of touch wirings is n;

[0019] In the first conductive layer of the fan-out region, m1 data wirings and n1 touch wirings are arranged;

[0020] In the second conductive layer of the fan-out area, m2 data wirings and n2 touch wirings are arranged;

[0021] In the third conductive layer of the fan-out region, n3 touch control wirings are arranged.

[0022] Among them, m=m1+m2, n=n1+n2+n3; and m1+n1=m2+n2, wherein m, n, m1, m2, n3 are all positive integers greater than or equal to 2, n1 and n2 are integers greater than or equal to 0, and n1 and n2 are not 0 at the same time.

[0023] According to some exemplary embodiments, (m1+n1)×pt1=(m2+n2)×pt2, wherein pt1 represents the first routing pitch, and pt2 represents the second routing pitch.

[0024] According to some exemplary embodiments, pr represents a ratio of the first width to the third width, and pr is between 0.95 and 1.05.

[0025] According to some exemplary embodiments, the pixel unit includes a pixel driving circuit, the pixel driving circuit includes a thin film transistor, the thin film transistor includes an active layer, a gate, a source and a drain, the gate is located in the third conductive layer, and the source and the drain are located in the first conductive layer.

[0026] According to some exemplary embodiments, the touch control unit includes a touch control electrode, and the touch control electrode is located in the second conductive layer.

[0027] According to some exemplary embodiments, the display panel includes a light-shielding portion located between the base substrate and the active layer, and an orthographic projection of the light-shielding portion on the base substrate at least partially overlaps with an orthographic projection of the active layer on the base substrate; the light-shielding portion is located in the second conductive layer.

[0028] According to some exemplary embodiments, a portion of the multiple touch lines located at both side edges of the fan-out area is located in at least one of the first conductive layer and the second conductive layer; or, for multiple touch lines, the touch lines located at odd positions are located in at least one of the first conductive layer and the second conductive layer, or, the touch lines located at even positions are located in at least one of the first conductive layer and the second conductive layer.

[0029] According to some exemplary embodiments, m1 data lines are located in the first conductive layer, m2 data lines are located in the second conductive layer, n1 touch lines are located in the first conductive layer, n2=0, the data lines electrically connected to the m1 data lines and the touch signal lines electrically connected to the n1 touch lines are both located at odd positions; the data lines electrically connected to the m2 data lines are located at even positions.

[0030] According to some exemplary embodiments, m1 data lines are located in the first conductive layer, m2 data lines are located in the second conductive layer, n2 touch lines are located in the second conductive layer, n1=0, the data lines electrically connected to the m1 data lines are located at odd positions, and the touch signal lines electrically connected to the n2 touch lines are located at even positions; the data lines electrically connected to the m2 data lines are located at even positions.

[0031] According to some exemplary embodiments, m1 data lines are located in the first conductive layer, m2 data lines are located in the second conductive layer, n1 touch lines are located in the second conductive layer, and n2 touch lines are located in the second conductive layer, n1 and n2 are both positive integers, the data lines electrically connected to the m1 data lines are located at odd positions, the touch signal lines electrically connected to the n1 touch lines are located at odd positions, the data lines electrically connected to the m2 data lines are located at even positions, and the touch signal lines electrically connected to the n2 touch lines are located at even positions; or, the data lines electrically connected to the m1 data lines are located at even positions, the touch signal lines electrically connected to the n1 touch lines are located at even positions, the data lines electrically connected to the m2 data lines are located at odd positions, and the touch signal lines electrically connected to the n2 touch lines are located at odd positions.

[0032] According to some exemplary embodiments, the multiple data lines or the multiple touch lines include a first line located at a side edge of the fan-out area and a second line located at a middle position of the fan-out area, the first line includes an inclined portion and a vertical portion, the vertical portion extends parallel to the second direction, the inclined portion extends obliquely relative to the second direction, the second line includes only a vertical portion, and a ratio of the vertical portion of the second line to the vertical portion of the first line is greater than 2.

[0033] According to some exemplary embodiments, the display panel also includes a plurality of jumpers, the fan-out area includes a jumper area, the jumper area is located between the plurality of data lines and the plurality of touch lines and the chip, and the plurality of jumpers are used to electrically connect the plurality of data lines and the plurality of touch lines to the chip, and the jumper area is located between the vertical portion and the chip, so that the length of the vertical portion of the second line is less than 1 mm.

[0034] According to some exemplary embodiments, at least some of the orthographic projections of the individual routings in the first conductive layer on the substrate, the orthographic projections of the individual routings in the second conductive layer on the substrate, and the orthographic projections of the individual routings in the third conductive layer on the substrate are not spaced apart.

[0035] In another aspect, a display device is provided, comprising the display panel as described above. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] Features and advantages of the present disclosure will become more apparent by describing in detail exemplary embodiments of the present disclosure with reference to the accompanying drawings.

[0037] Figure 1 is a plan view of a display panel according to an embodiment of the present disclosure, in which pixel units, data lines and data routing lines are schematically shown.

[0038] Figure 2 is a schematic plan view of a display panel according to some exemplary embodiments of the present disclosure, in which a touch unit, a touch signal line, and a touch routing line are schematically shown.

[0039] Figure 3 The display panel according to the embodiment of the present disclosure is Figure 2 Schematic cross-sectional view taken along line AA'.

[0040] Figure 4 is a partially enlarged view of a fan-out area of ​​a display panel according to an embodiment of the present disclosure.

[0041] FIG. 5A to FIG. 5C They are schematic diagrams of the layout of wiring in each conductive layer of the fan-out region of the display panel according to the embodiments of the present disclosure.

[0042] Figure 6 4 is a schematic cross-sectional view of routing lines in each conductive layer of a fan-out region of a display panel according to an embodiment of the present disclosure.

[0043] Figure 7 is a schematic diagram of a fan-out area of ​​a display panel according to an embodiment of the present disclosure, which schematically shows the relationship between the width of the space occupied by the wiring in the fan-out area and the height of the fan-out area.

[0044] Figure 8 is a partially enlarged view of a fan-out area of ​​a display panel according to some other embodiments of the present disclosure.

[0045] 9A to 9C Different implementations of arranging wiring in a fan-out region of a display panel according to an embodiment of the present disclosure are schematically shown.

[0046] Fig. 10A and Fig. 10B Schematic diagrams of jumper areas in a display panel according to embodiments of the present disclosure are schematically shown respectively.

[0047] Fig.11 is a schematic diagram of a display device according to some exemplary embodiments of the present disclosure. DETAILED DESCRIPTION

[0048] In order to make the purpose, technical solution and advantages of the embodiments of the present disclosure clearer, the technical solution of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the accompanying drawings. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0049] It should be noted that in the drawings, the size and relative size of the elements may be exaggerated for the purpose of clarity and / or description. Thus, the size and relative size of each element are not necessarily limited to the size and relative size shown in the drawings. In the specification and drawings, the same or similar reference numerals indicate the same or similar parts.

[0050] When an element is described as being "on" another element, "connected to" another element or "coupled to" another element, the element may be directly on the other element, directly connected to the other element or directly coupled to the other element, or there may be an intermediate element. However, when an element is described as being "directly on" another element, "directly connected to" another element or "directly coupled to" another element, there is no intermediate element. Other terms and / or expressions used to describe the relationship between elements should be interpreted in a similar manner, for example, "between..." versus "directly between...", "adjacent" versus "directly adjacent" or "on..." versus "directly on...", etc. In addition, the term "connection" may refer to a physical connection, an electrical connection, a communication connection and / or a fluid connection. In addition, the X-axis, the Y-axis and the Z-axis are not limited to the three axes of a rectangular coordinate system, and may be interpreted in a broader sense. For example, the X-axis, the Y-axis and the Z-axis may be perpendicular to each other, or may represent different directions that are not perpendicular to each other. For the purpose of this disclosure, "at least one of X, Y, and Z" and "at least one selected from the group consisting of X, Y, and Z" may be interpreted as only X, only Y, only Z, or any combination of two or more of X, Y, and Z such as XYZ, XYY, YZ, and ZZ. As used herein, the term "and / or" includes any and all combinations of one or more of the listed associated items.

[0051] It should be noted that, although the terms "first", "second", etc. may be used herein to describe various parts, components, elements, regions, layers and / or parts, these parts, components, elements, regions, layers and / or parts should not be limited by these terms. Instead, these terms are used to distinguish one part, component, element, region, layer and / or part from another. Thus, for example, the first part, first member, first element, first region, first layer and / or first part discussed below may be referred to as the second part, second member, second element, second region, second layer and / or second part without departing from the teachings of the present disclosure.

[0052] For ease of description, spatial relational terms, such as "upper", "lower", "left", "right", "middle", "both sides", "inner" and "outer", etc., may be used herein to describe the relationship of one element or feature to another element or feature as shown in the figure. It should be understood that the spatial relational terms are intended to cover other different orientations of the device in use or operation in addition to the orientation described in the figure. For example, if the device in the figure is turned upside down, the elements described as "below" or "beneath" other elements or features will be oriented "above" or "above" the other elements or features.

[0053] Those skilled in the art should understand that, in this document, unless otherwise specified, the expression "height" or "thickness" refers to the dimension along the surface of each film layer arranged perpendicular to the display panel, that is, the dimension along the light emitting direction of the display panel, or the dimension along the normal direction of the display device, or the dimension along the Z direction in the accompanying drawings.

[0054] Herein, unless otherwise specified, the expression "patterning process" generally includes steps such as photoresist coating, exposure, development, etching, photoresist stripping, etc. The expression "one-time patterning process" means a process of forming patterned layers, components, members, etc. using one mask.

[0055] It should be noted that the expressions "same layer", "same layer arrangement" or similar expressions refer to a layer structure formed by using the same film-forming process to form a film layer for forming a specific pattern, and then using the same mask to pattern the film layer through a single composition process. Depending on the specific pattern, a single composition process may include multiple exposure, development or etching processes, and the specific pattern in the formed layer structure may be continuous or discontinuous. These specific patterns may also be at different heights or have different thicknesses.

[0056] In this document, unless otherwise specified, the terms "connected" and "connection" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, or an electrical connection; it can be a direct connection, or an indirect connection through an intermediate, or the internal communication of two elements, or the two parts are formed in one piece. For ordinary technicians in this field, the specific meanings of the above terms in this disclosure can be understood according to specific circumstances.

[0057] An embodiment of the present disclosure provides a display panel, comprising: a substrate, the substrate comprising a display area and a first side area, the first side area being located at a first side of the display area, the first side area comprising a fan-out area; a plurality of pixel units, at least some of the plurality of pixel units being arranged in an array along a first direction and a second direction in the display area of ​​the substrate; a plurality of touch units, at least some of the plurality of touch units being arranged in an array along a first direction and a second direction in the display area of ​​the substrate; a plurality of data lines, at least a portion of the data lines being located in the display area, the plurality of data lines being electrically connected to the plurality of pixel units, respectively, for supplying data signals to the respective pixel units; a plurality of touch signal lines, at least a portion of the touch signal lines being located in the display area, the plurality of touch signal lines being electrically connected to the plurality of touch units, respectively, for supplying touch signals to the respective touch units; a chip, the chip being located in the first side area, the fan-out area being located between the display area and the chip; a plurality of data routings, the plurality of data routings being located in the display area; the fan-out area, the plurality of data routing lines electrically connecting the plurality of data lines to the chip respectively; and a plurality of touch routing lines, the plurality of touch routing lines being located in the fan-out area, the plurality of touch routing lines electrically connecting the plurality of touch signal lines to the chip respectively, wherein the display panel comprises a first conductive layer, a second conductive layer and a third conductive layer arranged on the base substrate, a portion of the plurality of data routing lines being located in the first conductive layer, the remaining portion of the plurality of data routing lines being located in the second conductive layer, a portion of the plurality of touch routing lines being located in at least one of the first conductive layer and the second conductive layer, the remaining portion of the plurality of touch routing lines being located in the third conductive layer, a pitch between any two adjacent routing lines in the first conductive layer being a first routing pitch, a pitch between any two adjacent routing lines in the second conductive layer being a second routing pitch, a pitch between any two adjacent routing lines in the third conductive layer being a third routing pitch, and any one of the first routing pitch and the second routing pitch being smaller than the third routing pitch. In an embodiment of the present disclosure, in the fan-out area, a double-layer conductive layer with a smaller routing pitch is used to arrange the routing, and a single-layer conductive layer with a smaller routing pitch is used to arrange the routing. By evenly arranging the routing on three conductive layers, the height of the fan-out area can be reduced, thereby reducing the bezel size of the display panel, which is conducive to realizing a display panel and display device with a narrow bezel.

[0058] Figure 1 is a plan view of a display panel according to an embodiment of the present disclosure, in which pixel units, data lines and data routing lines are schematically shown. Figure 2 is a schematic plan view of a display panel according to some exemplary embodiments of the present disclosure, in which a touch unit, a touch signal line, and a touch routing line are schematically shown. Figure 3The display panel according to the embodiment of the present disclosure is Figure 2 Schematic cross-sectional view taken along line AA'.

[0059] Reference Figure 1 According to an embodiment of the present disclosure, the display panel may include: a substrate 10, for example, the substrate 10 may be formed of glass, plastic, polyimide, etc. The substrate 10 includes a display area AA and a peripheral area (or non-display area) NA located at least on one side of the display area AA.

[0060] The display panel may include a plurality of pixel units P (in the display area AA) disposed in the display area AA. Figure 1 (shown schematically in a dotted box in FIG. 1 ), a plurality of pixel units P may be arranged in an array on the substrate 10 along a first direction X and a second direction Y. Each pixel unit P may further include a plurality of sub-pixels, such as a red sub-pixel, a green sub-pixel, and a blue sub-pixel. Figure 1 , one sub-pixel SP is schematically shown.

[0061] For example, the first direction X and the second direction Y may intersect, for example, the two may be perpendicular to each other.

[0062] For example, the display panel includes a signal input side IN1 ( Figure 1 ). On the signal input side IN1, a data driver chip IC may be provided, and the data driver chip IC may be electrically connected to the pixel unit P located in the display area through a plurality of signal wires, and the pixel driving circuit may be electrically connected to the data driver chip IC. In this way, signals such as data signals, scanning signals, touch signals, etc. may be transmitted from the signal input side IN1 to the plurality of pixel units P.

[0063] For example, Figure 1 As shown, the peripheral area NA may be located on four sides of the display area AA, that is, it surrounds the display area AA.

[0064] It should be noted that in the drawings, the pixel units and sub-pixels are schematically shown in a rectangular shape, but this does not constitute a limitation on the shapes of the pixel units and sub-pixels included in the display panel provided by the embodiments of the present disclosure.

[0065] In an embodiment of the present disclosure, each of the pixel units P may include a pixel driving circuit and a light emitting device electrically connected to the pixel driving circuit. For example, the light emitting device may be an organic light emitting diode (OLED) or a quantum dot light emitting diode (QLED). The light emitting device may include a first electrode, a second electrode, and a light emitting layer disposed between the first electrode and the second electrode.

[0066] One of the first electrode and the second electrode is an anode, and the other is a cathode. For example, the first electrode can be an anode. The second electrode can be a cathode. The light-emitting layer can be a multilayer structure, for example, it can include a multilayer structure formed by a hole injection layer, a hole transport layer, an organic light-emitting layer, an electron transport layer and an electron injection layer.

[0067] It should be noted that, for example, the light-emitting device of the organic light-emitting diode can be actively driven or passively driven. The passively driven OLED array substrate is composed of a cathode and an anode, and the intersection of the anode and the cathode can emit light. The driving circuit can be externally mounted by connection methods such as tape carrier packaging or glass chip carrier. The actively driven OLED array substrate can be equipped with a pixel driving circuit for each pixel, and the pixel driving circuit can include a thin film transistor with a switching function (i.e., a switching transistor), a thin film transistor with a driving function (i.e., a driving transistor) and a charge storage capacitor. In addition, the pixel driving circuit can also include other types of thin film transistors with compensation functions. It should be understood that in the embodiments of the present disclosure, the display panel can be equipped with various types of known pixel driving circuits, which will not be repeated here. For example, each pixel unit P can include a pixel driving circuit with a circuit structure such as 7T1C, 7T2C, 8T2C or 4T1C in the art, and the pixel driving circuit works under the control of a data signal transmitted through a data line and a gate scanning signal and a light-emitting control signal transmitted through a signal line to drive the light-emitting device to emit light, thereby realizing operations such as display.

[0068] For example, the display panel may include a driving circuit layer, and the pixel driving circuit may be disposed in the driving circuit layer. An insulating layer may be disposed between the driving circuit layer and the light emitting device, and the insulating layer may be a single insulating film layer or a stack of multiple insulating film layers.

[0069] For example, the display panel may further include various signal lines arranged on the base substrate 10, wherein the various signal lines include data lines, gate scanning signal lines, light-emitting control signal lines, first power lines, second power lines, etc., so as to provide various signals such as data signals, gate scanning signals, light-emitting control signals, first power supply voltages, second power supply voltages, etc. to the pixel driving circuit in each sub-pixel. Figure 1 In the illustrated embodiment, scan lines GL and data lines DL are schematically illustrated. The scan lines GL and data lines DL may be electrically connected to each pixel unit P. For example, at least a portion of the data lines DL is located in the display area AA, and the plurality of data lines AA are electrically connected to the plurality of pixel units P, respectively, for supplying data signals to each pixel unit P.

[0070] Combined with reference Figures 1 to 3According to an embodiment of the present disclosure, the display panel has a display area AA and a peripheral area NA surrounding the display area AA. The peripheral area NA includes a first side area NA1, a second side area NA2, a third side area NA3 and a fourth side area NA4. For example, the first side area NA1, the second side area NA2, the third side area NA3 and the fourth side area NA4 can be respectively regarded as the lower frame, the upper frame, the left frame and the right frame of the display panel.

[0071] Observed from the front of the display panel, the display panel according to the embodiment of the present disclosure has a display area and a peripheral area. The display area of ​​the display panel is arranged with luminous pixels and can display images. The display area is surrounded by a peripheral area. Typically, when observed from the front, the display area is surrounded by side areas. However, some display panels, from the perspective of aesthetics, hope that the side areas are as narrow as possible. Therefore, in applications such as full-screen mobile phones, the display area may not be provided with side areas on the left, right and top. Nevertheless, the display panel still needs to have at least one side area for centrally accommodating circuits that are difficult to bend but necessary, and this side area is usually located below the display area. For example, even in the current full-screen mobile phone applications, there is still a lower side area below the mobile phone that does not display an image. It should be understood that "upper", "lower", "left", "right", "front" and "back" in this article are only for describing the relative positions between components rather than absolute positions. In the present disclosure, the lower frame is only for the convenience of describing the relative position, but it does not mean that it is necessarily located below the display screen. In addition, although the conventional display panel is rectangular and the lower side region is a rectangular area of ​​one of its four sides, display panels of other outer contour shapes may also have side regions of any shape in which circuits are centrally accommodated. Any frame with centralized circuit wiring in the display panel can be considered as the lower frame, and it is specified in the present disclosure that it is located at the bottom, and the display area is correspondingly located at the top.

[0072] In an embodiment of the present disclosure, at least a portion of the first side area NA1 can be bent to the non-display side of the display panel, thereby reducing the area of ​​the non-display area in the display side of the display panel, thereby realizing a large-screen display panel and a narrow frame design. For example, the first side area NA1 may include a first sub-side area NA11, a second sub-side area NA12, and a bending area B, the first sub-side area NA11 is located on the side of the second sub-side area NA12 close to the display area AA, and the bending area B is arranged between the first sub-side area NA11 and the second sub-side area NA12. The bending area B can be bent along the bending axis BX, so that the second sub-side area NA12 can be bent to the non-display side of the display panel. For example, a driving chip (IC) and a flexible circuit board (FPC) and other structures for controlling the display and touch of the display area AA can be arranged in the second sub-side area NA12.

[0073] Combined with reference Figures 1 to 3The display panel may include a base substrate 10, a driving circuit layer, a packaging layer and a touch layer 30. The driving circuit layer, the packaging layer and the touch layer are arranged in a direction away from the base substrate 10 in sequence.

[0074] For example, the touch layer may include an FMLOC film layer. With the development of technology, the market has put forward higher and higher requirements for the thinning of display devices (such as mobile phones), and the Flexible Multi-Layer On Cell (FMLOC) technology has emerged. In the FMLOC process, a metal grid electrode layer is made on the packaging layer of the display module to realize the touch function, without the need for an external touch structure, thereby reducing the overall thickness of the display screen.

[0075] In an embodiment of the present disclosure, the display panel may further include a plurality of touch control units, and at least some of the plurality of touch control units are arranged in an array along a first direction X and a second direction Y in a display area AA of the base substrate. For example, the touch layer 30 may include a first touch layer, a second touch layer, and a touch insulating layer arranged between the first touch layer and the second touch layer. For example, in the display area AA, the plurality of touch control units may include a first touch control electrode TX and a second touch control electrode RX, for example, the first touch control electrode TX may be a touch control driving electrode TX, and the second touch control electrode RX may be a touch control sensing electrode RX. The plurality of first touch control electrodes TX may be arranged along a first direction X, and the plurality of second touch control electrodes RX may be arranged along a second direction intersecting the first direction. In some embodiments, the first direction is perpendicular to the second direction. For example, as Figure 2 As shown in the example, the first direction may be the width direction of the display panel, and the second direction may be the length direction of the display panel.

[0076] As an example, in Figure 2 In the example of FIG. 1 , the first touch electrode TX and the second touch electrode RX are in a rhombus shape. However, the embodiments of the present disclosure are not limited thereto, and those skilled in the art should understand that in other embodiments, the first touch electrode TX and the second touch electrode RX may be in other shapes.

[0077] For example, the display panel may also include a plurality of touch signal lines TL, at least a portion of the touch signal lines TL are located in the display area AA, and the plurality of touch signal lines TL are respectively electrically connected to the plurality of touch units (first touch electrodes TX and second touch electrodes RX) for supplying touch signals to each touch unit.

[0078] Continue to refer to Figure 1 and Figure 2The first side area NA1 may include a fan-out area (i.e., fan-out area) FA of the display panel, and the fan-out area FA is located between the display area AA and the chip IC. It should be understood that a plurality of densely arranged signal lines are provided in the fan-out area FA for transmitting a plurality of signals to each pixel unit and the touch unit. In the fan-out area FA, each signal line is arranged in a fan-shaped wiring manner.

[0079] In an embodiment of the present disclosure, the display panel may include a plurality of data routing lines 600, the plurality of data routing lines 600 being located in the fan-out area FA, and the plurality of data routing lines 600 electrically connecting the plurality of data lines DL to the chip IC, respectively. In this way, the data signal provided by the chip IC may be supplied to each pixel unit.

[0080] In an embodiment of the present disclosure, the display panel may include a plurality of touch lines 800, the plurality of touch lines 800 are located in the fan-out area FA, and the plurality of touch lines 800 electrically connect the plurality of touch signal lines TL to the chip IC, respectively. In this way, the touch signal provided by the chip IC can be supplied to each touch unit.

[0081] Combined with reference Figures 1 to 3 In the display area AA, the display panel may include a base substrate 10, a buffer layer 11 arranged on the base substrate 10, a semiconductor layer ACT arranged on a side of the buffer layer 11 away from the base substrate 10, a first gate conductive layer 41 arranged on a side of the semiconductor layer ACT away from the base substrate 10, a second gate conductive layer 42 arranged on a side of the first gate conductive layer 41 away from the base substrate 10, a first source-drain conductive layer 43 arranged on a side of the second gate conductive layer 42 away from the base substrate 10, and a second source-drain conductive layer 44 arranged on a side of the first source-drain conductive layer 43 away from the base substrate 10. The display panel may also be provided with a first insulating layer GI1 between the semiconductor layer ACT and the first gate conductive layer 41, a second insulating layer GI2 between the first gate conductive layer 41 and the second gate conductive layer 42, a third insulating layer ILD1 between the second gate conductive layer 42 and the first source-drain conductive layer 43, and a fourth insulating layer between the first source-drain conductive layer 43 and the second source-drain conductive layer 44. For example, the fourth insulating layer may include a passivation layer PVX and a first planarization layer PLN1. The passivation layer PVX may be provided on a side of the third conductive layer 42 away from the base substrate 10, and the first planarization layer PLN1 may be provided on a side of the passivation layer PVX away from the base substrate 10.

[0082] For example, the display panel may include a plurality of pixel units and a pixel driving circuit for driving the plurality of pixel units, and the pixel driving circuit may include a plurality of thin film transistors and a storage capacitor. The thin film transistor may include an active layer, a gate, a source electrode, and a drain electrode, and the storage capacitor may include a first electrode plate and a second electrode plate. Figure 3 , a thin film transistor and a storage capacitor are schematically shown. For example, the active layer of the thin film transistor may be located in the semiconductor layer ACT, the gate G1 of the thin film transistor and the first electrode C1 of the storage capacitor may be located in the first gate conductive layer 41, the second electrode C2 of the storage capacitor may be located in the second gate conductive layer 42, and the source S1 and the drain D1 of the thin film transistor may be located in the first source-drain conductive layer 43.

[0083] In the display area AA, the display panel may further include a first electrode layer 45 disposed on a side of the second source-drain conductive layer 44 away from the base substrate 10, a light-emitting material layer EL disposed on a side of the first electrode layer 45 away from the base substrate 10, and a second electrode layer 46 disposed on a side of the light-emitting material layer EL away from the base substrate 10. The display panel may further include a second planarization layer PLN2 disposed between the second source-drain conductive layer 44 and the first electrode layer 45.

[0084] For example, the pixel unit may include a light-emitting element, such as an organic light-emitting diode. The light-emitting element includes an anode, a light-emitting layer, and a cathode. The anode of the light-emitting element may be located in the first electrode layer 45, the light-emitting layer of the light-emitting element may be located in the light-emitting material layer EL, and the cathode of the light-emitting element may be located in the second electrode layer 46. A conductive connection portion 47 for electrically connecting the thin film transistor and the light-emitting element may be located in the second source-drain conductive layer 44.

[0085] For example, the display panel may further include a pixel defining layer PDL, where the pixel defining layer PDL is located on a side of the first electrode layer 45 away from the base substrate 10 and is used to define an opening of each pixel unit.

[0086] For example, the semiconductor layer ACT may be formed of a semiconductor material such as low temperature polysilicon, and the film thickness thereof may be in the range of 400 to 800 angstroms, for example, 500 angstroms. The first gate conductive layer 41 and the second gate conductive layer 42 may be formed of a conductive material forming a gate of a thin film transistor, for example, the conductive material may be Mo, and the film thickness thereof may be in the range of 2000 to 4000 angstroms, for example, 3000 angstroms. The first source-drain conductive layer 43 and the second source-drain conductive layer 44 may be formed of a conductive material forming a source and a drain of a thin film transistor, for example, the conductive material may include Ti, Al, etc. The first source-drain conductive layer 43 may have a stacked structure formed of Ti / Al / Ti, and the film thickness thereof may be in the range of 6000 to 9000 angstroms. For example, in the case where the first source-drain conductive layer 43 or the second source-drain conductive layer 44 has a stacked structure formed of Ti / Al / Ti, the thickness of each layer of Ti / Al / Ti may be approximately 500 angstroms, 6000 angstroms, and 500 angstroms, respectively. For example, the first insulating layer GI1 and the second insulating layer GI2 may be formed of silicon oxide, silicon nitride or silicon oxynitride, and each layer may have a thickness of about 1000 to 2000 angstroms. For example, the third insulating layer IDL1 and the passivation layer PVX may be formed of silicon oxide, silicon nitride or silicon oxynitride, and have a thickness of about 3000 to 6000 angstroms.

[0087] The display panel may further include an encapsulation layer covering the light-emitting element. The encapsulation layer may include a film layer formed alternately of an inorganic layer and an organic layer, for example, may include a first encapsulation sublayer 201, a second encapsulation sublayer 202, and a third encapsulation sublayer 203 arranged in sequence. For example, the first encapsulation sublayer 201 and the third encapsulation sublayer 203 may be composed of an inorganic material, and the second encapsulation sublayer 202 may be composed of an organic material. For example, the first encapsulation sublayer 201 and the third encapsulation sublayer 203 may be formed by processes such as chemical vapor deposition (ie, CVD), and the second encapsulation sublayer 202 may be formed by processes such as inkjet printing (IJP).

[0088] In the embodiment of the present disclosure, the touch layer 30 is formed on a side of the second encapsulation sublayer 202 away from the base substrate 10. For example, the touch layer 30 may include a conductive material for forming a touch electrode.

[0089] Optionally, the display panel may further include a light shielding layer 210. The light shielding layer 210 is disposed on a side of the active layer ACT close to the base substrate 10. The orthographic projection of the light shielding layer 210 on the base substrate 10 covers the orthographic projection of the active layer ACT on the base substrate 10, so that the influence of external light on the active layer ACT can be avoided. The display panel may further include a blocking layer or a buffer layer 220 disposed between the light shielding layer 210 and the active layer ACT. For example, the light shielding layer 210 may include a metal opaque material.

[0090] Figure 4 is a partially enlarged view of a fan-out area of ​​a display panel according to an embodiment of the present disclosure. FIG. 5A to FIG. 5C They are schematic diagrams of the layout of wiring in each conductive layer of the fan-out region of the display panel according to the embodiments of the present disclosure. Figure 6 4 is a schematic cross-sectional view of routing lines in each conductive layer of a fan-out region of a display panel according to an embodiment of the present disclosure.

[0091] Reference Figures 1 to 6 In an embodiment of the present disclosure, the display panel may include a first conductive layer, a second conductive layer, and a third conductive layer disposed on the base substrate 10. A portion of the plurality of data traces 600 is located in the first conductive layer, and the remaining portion of the plurality of data traces 600 is located in the second conductive layer. A portion of the plurality of touch traces 800 is located in at least one of the first conductive layer and the second conductive layer, and the remaining portion of the plurality of touch traces 800 is located in the third conductive layer.

[0092] For example, the first conductive layer may be one of the first source-drain conductive layer 43 and the second source-drain conductive layer 44. The second conductive layer may be one of the touch control layer 30 and the light shielding layer 210. The third conductive layer may be one of the first gate conductive layer 41 and the second gate conductive layer 42.

[0093] That is to say, in the embodiment of the present disclosure, in the fan-out area FA, the data wiring 600 and the touch wiring 800 are arranged in three layers, wherein the data wiring 600 is arranged in two layers, and the touch wiring 800 is arranged in two layers or three layers. For example, a part of the data wiring 600 and a part of the touch wiring 800 are arranged in the first source-drain conductive layer 43 or the second source-drain conductive layer 44, the remaining data wiring 600 is arranged in the touch layer 30 or the light shielding layer 210, and the remaining touch wiring 800 is arranged in the first gate conductive layer 41 or the second gate conductive layer 42. Alternatively, a part of the data wiring 600 is arranged in the first source-drain conductive layer 43 or the second source-drain conductive layer 44, a part of the touch wiring 800 and the remaining data wiring 600 are arranged in the touch layer 30 or the light shielding layer 210, and the remaining touch wiring 800 is arranged in the first gate conductive layer 41 or the second gate conductive layer 42. Alternatively, a portion of the data lines 600 and a portion of the touch lines 800 are arranged in the first source-drain conductive layer 43 or the second source-drain conductive layer 44, the remaining data lines 600 and another portion of the touch lines 800 are arranged in the touch layer 30 or the light shielding layer 210, and the remaining touch lines 800 are arranged in the first gate conductive layer 41 or the second gate conductive layer 42.

[0094] Reference FIG. 5A to FIG. 5CThe pitch between any two adjacent routing lines in the first conductive layer is the first routing pitch pt1, the pitch between any two adjacent routing lines in the second conductive layer is the second routing pitch pt2, and the pitch between any two adjacent routing lines in the third conductive layer is the third routing pitch pt3.

[0095] It should be noted that, in the embodiments of the present disclosure, the pitch between two adjacent routing lines may be the distance between the centers of the two adjacent routing lines. For example, the line width of each of the two adjacent routing lines is wdx, and the spacing distance between the two adjacent routing lines is spx, then the pitch ptx between the two adjacent routing lines may be equal to wdx+spx.

[0096] In an embodiment of the present disclosure, any one of the first routing pitch pt1 and the second routing pitch pt2 is smaller than the third routing pitch pt3. For example, the first routing pitch pt1 and the second routing pitch pt2 may be substantially equal.

[0097] For example, in an embodiment of the present disclosure, a dry etching process (i.e., a dry etching process) may be used to form routing lines (including various routing lines such as data routing lines and touch routing lines located in the first conductive layer). In the dry etching process, the routing pitch between routing lines can be controlled to be about 4.2 microns at a minimum. A dry etching process (i.e., a dry etching process) may be used to form routing lines (including various routing lines such as data routing lines and touch routing lines located in the second conductive layer). In the dry etching process, the routing pitch between routing lines can be controlled to be about 4.2 microns at a minimum. A wet etching process (i.e., a wet etching process) may be used to form routing lines (including various routing lines such as data routing lines and touch routing lines located in the third conductive layer). In the wet etching process, the routing pitch between routing lines can be controlled to be about 5.5 microns at a minimum.

[0098] It should be understood that the third conductive layer may be a gate conductive layer. In the manufacturing process of the display panel, in order to realize a self-alignment process or a self-alignment area in the gate conductive layer, a wet etching process is usually used to form various conductive components such as gate lines and gate electrodes in the gate conductive layer.

[0099] That is, in the embodiment of the present disclosure, the first routing pitch pt1 and the second routing pitch pt2 may be approximately 4.2 micrometers, and the third routing pitch pt3 may be approximately 5.5 micrometers.

[0100] In an embodiment of the present disclosure, in the fan-out area, more routing lines are arranged in the two conductive layers with smaller routing pitches, and fewer routing lines are arranged in the conductive layer with larger routing pitches. The space occupied by each routing line can be evenly arranged in each conductive layer. In this way, the height of the fan-out area can be reduced, thereby reducing the border of the display panel, which is conducive to realizing a display panel and display device with a narrow border.

[0101] In an embodiment of the present disclosure, in the fan-out area FA, the space occupied by each routing in the first conductive layer and the first routing interval between each routing has a first width wd1, the space occupied by each routing in the second conductive layer and the second routing interval between each routing has a second width wd2, and the space occupied by each routing in the third conductive layer and the third routing interval between each routing has a third width wd3. The ratio of any two of the first width wd1, the second width wd2, and the third width wd3 is between 0.95 and 1.05. That is, any two of the first width wd1, the second width wd2, and the third width wd3 are substantially equal to each other.

[0102] For example, the number of the plurality of data lines 600 is m, and the number of the plurality of touch lines 800 is n. In the first conductive layer of the fan-out region, m1 data lines and n1 touch lines are arranged; in the second conductive layer of the fan-out region, m2 data lines and n2 touch lines are arranged; in the third conductive layer of the fan-out region, n3 touch lines are arranged, wherein m=m1+m2, n=n1+n2+n3; and m1+n1=m2+n2. Wherein, m, n, m1, m2, n3 are all positive integers greater than or equal to 2, n1 and n2 are integers greater than or equal to 0, and n1 and n2 are not 0 at the same time.

[0103] For example, (m1+n1)×pt1=(m2+n2)×pt2. That is, the first width wd1 is equal to the second width wd2.

[0104] For example, Wherein, pr represents the ratio of the first width to the third width, and pr is between 0.95 and 1.05. That is, the first width wd1 is substantially equal to the third width wd3.

[0105] Figure 7 is a schematic diagram of a fan-out area of ​​a display panel according to an embodiment of the present disclosure, which schematically shows the relationship between the width of the space occupied by the wiring in the fan-out area and the height of the fan-out area.

[0106] like Figure 7As shown, a represents half of the width of the protruding portion of the display area AA relative to the chip IC, that is, a is related to the setting position of the chip IC. b represents half of the width of the overlapping portion of the display area AA and the chip IC, that is, b is related to the width of the display area AA of the display panel. h represents the height of the fan-out area FA. e represents the inclination angle of the routing in the fan-out area. d represents the connection line between the middle position of the display area AA and the pin of the chip IC, and d is related to the number of routings in the fan-out area and the routing pitch. c is the height of the auxiliary line perpendicular to the edge routing.

[0107] According to similar triangles, c / d=a / (a+b), so c=ad / (a+b).

[0108] According to sin(e)=c / a, we can obtain e=arcsin(d / (a+b)).

[0109] According to tan(e)=h / a, we can obtain h=a*tan(e).

[0110] According to the above formulas, the height h of the fan-out area is related to a and e, and e is related to b and d. Under the premise that the size of the display panel (determines b) and the position of the chip IC (determines a) are fixed, the height h of the fan-out area FA is only positively correlated with d. In other words, the height h of the fan-out area FA is only positively correlated with the width of the space occupied by the wiring in the fan-out area (i.e., the first width wd1, the second width wd2, and the third width wd3 mentioned above). In an embodiment of the present disclosure, by reasonably arranging the wiring in the three conductive layers in the fan-out area, the width of the space occupied by the wiring in the fan-out area can be reduced, thereby reducing the height of the fan-out area. In this way, the width of the lower frame where the fan-out area is located can be reduced, which is conducive to realizing a display panel with a narrow frame.

[0111] In the embodiments of the present disclosure, referring to Figure 4 , a portion of the touch lines 800 located at both side edges of the fan-out area FA is located in at least one of the first conductive layer and the second conductive layer. That is, the touch lines 800 arranged in the same layer as part of the data lines 600 are arranged at both side edges of the fan-out area FA.

[0112] Figure 8 is a partial enlarged view of a fan-out region of a display panel according to some other embodiments of the present disclosure. Figure 8In the embodiment of the present disclosure, for a plurality of touch lines 600, the touch lines 600 located at odd positions are located in at least one of the first conductive layer and the second conductive layer, or the touch lines 600 located at even positions are located in at least one of the first conductive layer and the second conductive layer. That is, the touch lines 800 arranged in the same layer as some of the data lines 600 are evenly arranged with the data lines 600 in the same layer.

[0113] 9A to 9C Different implementations of arranging wiring in a fan-out region of a display panel according to an embodiment of the present disclosure are schematically shown.

[0114] Reference Fig. 9A , part of the data lines are located in the first conductive layer, the remaining data lines are located in the second conductive layer, part of the touch lines are located in the first conductive layer, and the remaining touch lines are located in the third conductive layer. That is, m1 data lines are located in the first conductive layer, m2 data lines are located in the second conductive layer, and n1 touch lines are located in the first conductive layer, and n2=0. In the display area AA, the data lines DL and the touch signal lines TL are respectively electrically connected to the data lines 600 and the touch lines 800 in the fan-out area. For example, Fig. 9A As shown, the data lines electrically connected to the m1 data lines, the touch signal lines electrically connected to the n1 touch lines, and the data lines electrically connected to the m2 data lines are numbered consecutively, and the numbers are used to indicate their locations. For example, the data lines electrically connected to the m1 data lines and the touch signal lines electrically connected to the n1 touch lines are all located at odd positions (e.g. Fig. 9A 1, 3, 5, 7, 9); the data lines electrically connected to the m2 data lines are located at even positions (such as Fig. 9A 2, 4, 6, 8, 10).

[0115] Reference Fig. 9B , part of the data lines are located in the first conductive layer, the remaining data lines are located in the second conductive layer, part of the touch lines are located in the second conductive layer, and the remaining touch lines are located in the third conductive layer. That is, m1 data lines are located in the first conductive layer, m2 data lines are located in the second conductive layer, and n2 touch lines are located in the second conductive layer, where n1=0. In the display area AA, the data lines DL and the touch signal lines TL are electrically connected to the data lines 600 and the touch lines 800 in the fan-out area, respectively. For example, Fig. 9BAs shown, the data lines electrically connected to the m1 data lines, the touch signal lines electrically connected to the n2 touch lines, and the data lines electrically connected to the m2 data lines are numbered consecutively, and the numbers are used to indicate their locations. For example, the data lines electrically connected to the m1 data lines are located at odd positions (e.g. Fig. 9B 1, 3, 5, 7, 9), the touch signal lines electrically connected to the n2 touch lines are located at even positions (such as Fig. 9B 2, 8); the data lines electrically connected to the m2 data lines are located at even positions (such as Fig. 9B 4, 6, 10).

[0116] Reference Fig. 9C , part of the data lines are located in the first conductive layer, the remaining data lines are located in the second conductive layer, part of the touch lines are located in the first conductive layer, another part of the touch lines are located in the second conductive layer, and the remaining touch lines are located in the third conductive layer. That is, m1 data lines are located in the first conductive layer, m2 data lines are located in the second conductive layer, n1 touch lines are located in the second conductive layer, n2 touch lines are located in the second conductive layer, and n3 touch lines are located in the third conductive layer, and m1, m2, n1, n2, and n3 are all positive integers greater than 0. In the display area AA, the data lines DL and the touch signal lines TL are electrically connected to the data lines 600 and the touch lines 800 in the fan-out area respectively. For example, as Fig. 9C As shown, the data lines electrically connected to the m1 data lines, the touch signal lines electrically connected to the n1 touch lines, the data lines electrically connected to the m2 data lines, and the touch signal lines electrically connected to the n2 touch lines are numbered consecutively, and the numbers are used to indicate their locations. For example, the data lines electrically connected to the m1 data lines are located at odd positions (e.g. Fig. 9C 1, 5, 7, 9), the touch signal lines electrically connected to the n1 touch lines are located at odd positions (such as Fig. 9C 3), the data lines electrically connected to the m2 data lines are located at even positions (such as Fig. 9C 2, 4, 6, 10), the touch signal lines electrically connected to the n2 touch lines are located at even positions (such as Fig. 9C In the embodiment of the present disclosure, alternatively, the data lines electrically connected to the m1 data lines may be located at even positions, the touch signal lines electrically connected to the n1 touch lines may be located at even positions, the data lines electrically connected to the m2 data lines may be located at odd positions, and the touch signal lines electrically connected to the n2 touch lines may be located at odd positions.

[0117] Fig. 10A and Fig. 10B Schematic diagrams of jumper areas in a display panel according to embodiments of the present disclosure are schematically shown respectively.

[0118] Reference Figures 1 to 10B In an embodiment of the present disclosure, in the fan-out area FA, all data routing lines and a part of the touch routing lines are arranged in the first conductive layer and the second conductive layer, so that the arrangement rules of the data lines DL and the touch signal lines TL in the display area AA are different from the arrangement rules of the data signal pins and the touch signal pins on the chip IC for providing data signals and touch signals. In this case, it is necessary to add an additional jumper area TA to connect the data lines DL and the touch signal lines TL in the display area AA to the corresponding pins respectively. That is, in an embodiment of the present disclosure, the display panel also includes a plurality of jumpers, the fan-out area includes a jumper area TA, the jumper area TA is located between the plurality of data routing lines and the plurality of touch routing lines and the chip IC, and is used for a plurality of jumpers to electrically connect the plurality of data routing lines and the plurality of touch routing lines to the chip. For example, the plurality of jumpers may include a first jumper and a second jumper. The first jumper may be used to electrically connect the routing lines located in the first conductive layer, and the second jumper may be electrically connected to the routing lines in the second conductive layer.

[0119] Reference Fig. 10A and Fig. 10B The plurality of data lines or the plurality of touch lines include a first line 601 located at a side edge of the fan-out area FA (the left area in the figure) and a second line 602 located at a middle position of the fan-out area FA (the left area in the figure), the first line 601 includes an inclined portion 6011 and a vertical portion 6012, the vertical portion 6012 extends parallel to the second direction Y, and the inclined portion 6011 extends obliquely relative to the second direction Y. The second line 602 includes only a vertical portion.

[0120] like Fig. 10A As shown in FIG. 1 , from both sides of the chip IC to the middle of the chip IC, the inclined portion 6011 of the routing line in the fan-out area FA gradually becomes shorter, and the vertical portion 6012 gradually becomes longer. The jumper area TA is located below the vertical portion 6012 of the routing line. That is, in this embodiment, the jumper area TA is additionally added, which will increase the width of the lower side frame of the display panel, which is not conducive to realizing a display panel with a narrow frame.

[0121] like Fig. 10B As shown, from both sides of the chip IC to the middle of the chip IC, the vertical portion 6012 of the routing line in the fan-out area is gradually pulled up, that is, relative to Fig. 10AIn the embodiment, the vertical part of the routing in the fan-out area is gradually shortened, so that the jumper area TA can occupy the space for the vertical part of the routing in the fan-out area to be pulled up and avoided. In this embodiment, the jumper area TA does not affect the overall height of the fan-out area, thereby ensuring that the width of the lower side frame of the display panel does not increase.

[0122] For example, in Fig. 10B In the illustrated embodiment, the ratio of the length of the vertical portion of the second wiring 602 (ie, the entire second wiring) to the length of the vertical portion 6012 of the first wiring 601 is greater than 2.

[0123] For example, the jumper area FA is located between the vertical portion and the chip, so that the length of the vertical portion of the second wiring 602 is less than 1 mm. For example, the length of the vertical portion 6012 of the first wiring 601 is less than 0.5 mm.

[0124] In the embodiments of the present disclosure, at least some of the orthographic projections of the individual routing lines in the first conductive layer on the substrate, the orthographic projections of the individual routing lines in the second conductive layer on the substrate, and the orthographic projections of the individual routing lines in the third conductive layer on the substrate are arranged at intervals. For example, there are at least some unobstructed areas between the orthographic projections of the individual routing lines in the first conductive layer on the substrate, the orthographic projections of the individual routing lines in the second conductive layer on the substrate, and the orthographic projections of the individual routing lines in the third conductive layer on the substrate, and the width of the unobstructed area along the first direction X is more than 25% of the overall width of the fan-out area. In this way, when UV light (i.e., ultraviolet light) is used to cure the frame sealant of the display panel, it can be ensured that the fan-out area has sufficient transmittance to UV light to avoid abnormal curing of the frame sealant.

[0125] Fig.11 1 is a schematic diagram of a display device according to some exemplary embodiments of the present disclosure. The display device 1000 includes the above-mentioned display panel.

[0126] The display device may include any device or product having a display function. For example, the display device may be a smart phone, a mobile phone, an e-book reader, a desktop computer (PC), a laptop PC, a netbook PC, a personal digital assistant (PDA), a portable multimedia player (PMP), a digital audio player, a mobile medical device, a camera, a wearable device (such as a head-mounted device, an electronic clothing, an electronic bracelet, an electronic necklace, an electronic accessory, an electronic tattoo, or a smart watch), a television, etc.

[0127] It should be understood that the display device according to the embodiment of the present disclosure has all the characteristics and advantages of the above-mentioned display panel, and the details can be found in the above description.

[0128] Although some embodiments of the overall technical concept of the present disclosure have been shown and described, those skilled in the art will appreciate that changes may be made to these embodiments without departing from the principles and spirit of the overall technical concept, and the scope of the present disclosure is defined by the claims and their equivalents.

Claims

1. A display panel, characterized in that: include: A base substrate, the base substrate comprising a display area and a first side area, the first side area is located at a first side of the display area, and the first side area comprises a fan-out area; A plurality of pixel units, at least some of the plurality of pixel units are arranged in an array along a first direction and a second direction in a display area of ​​the base substrate, the first direction and the second direction intersecting; A plurality of touch control units, at least some of which are arranged in an array along a first direction and a second direction in a display area of ​​the base substrate; a plurality of data lines, at least a portion of which is located in the display area, and the plurality of data lines are electrically connected to the plurality of pixel units, respectively, for supplying data signals to the respective pixel units; a plurality of touch signal lines, at least a portion of which is located in the display area, and the plurality of touch signal lines are electrically connected to the plurality of touch units, respectively, for supplying touch signals to the respective touch units; A chip, wherein the chip is located in the first side area, and the fan-out area is located between the display area and the chip; A plurality of data routing lines, the plurality of data routing lines are located in the fan-out area, and the plurality of data routing lines electrically connect the plurality of data lines to the chip respectively; a plurality of touch lines, the plurality of touch lines being located in the fan-out area, the plurality of touch lines electrically connecting the plurality of touch signal lines to the chip respectively, The display panel includes a first conductive layer, a second conductive layer and a third conductive layer arranged on the base substrate, the third conductive layer is a gate conductive layer, and the third conductive layer includes a gate line and a gate formed by a wet etching process. A portion of the plurality of data routing lines is located in the first conductive layer, and a remaining portion of the plurality of data routing lines is located in the second conductive layer. A portion of the plurality of touch traces is located in at least one of the first conductive layer and the second conductive layer, and a remaining portion of the plurality of touch traces is located in the third conductive layer, A pitch between any two adjacent routing lines in the first conductive layer is a first routing pitch, a pitch between any two adjacent routing lines in the second conductive layer is a second routing pitch, a pitch between any two adjacent routing lines in the third conductive layer is a third routing pitch, and either the first routing pitch or the second routing pitch is smaller than the third routing pitch; as well as The number of routing lines in the first conductive layer is greater than the number of routing lines in the third conductive layer; and / or, The number of routing lines in the second conductive layer is greater than the number of routing lines in the third conductive layer.

2. The display panel according to claim 1, wherein: In the fan-out area, the space occupied by each routing in the first conductive layer and the first routing interval between the routings has a first width, the space occupied by each routing in the second conductive layer and the second routing interval between the routings has a second width, and the space occupied by each routing in the third conductive layer and the third routing interval between the routings has a third width; A ratio of any two of the first width, the second width and the third width is between 0.95 and 1.

05.

3. The display panel according to claim 2, wherein: The number of the plurality of data wirings is m, and the number of the plurality of touch wirings is n; In the first conductive layer of the fan-out region, m1 data wirings and n1 touch wirings are arranged; In the second conductive layer of the fan-out area, m2 data wirings and n2 touch wirings are arranged; In the third conductive layer of the fan-out region, n3 touch control wirings are arranged. Among them, m=m1+m2, n=n1+n2+n3; and, m1+n1=m2+n2, wherein m, n, m1, m2, n3 are all positive integers greater than or equal to 2, n1 and n2 are integers greater than or equal to 0, and n1 and n2 are not 0 at the same time.

4. The display panel according to claim 3, wherein: (m1+n1)×pt1= (m2+n2)×pt2, wherein pt1 represents the first routing pitch, and pt2 represents the second routing pitch.

5. The display panel according to claim 4, wherein: , pr represents the ratio of the first width to the third width, and pr is between 0.95 and 1.

05.

6. The display panel according to any one of claims 1 to 5, wherein: The pixel unit includes a pixel driving circuit, the pixel driving circuit includes a thin film transistor, the thin film transistor includes an active layer, a gate, a source and a drain, the gate is located in the third conductive layer, and the source and the drain are located in the first conductive layer.

7. The display panel according to claim 6, wherein: The touch control unit includes a touch control electrode, and the touch control electrode is located in the second conductive layer.

8. The display panel according to claim 6, wherein: The display panel comprises a light shielding portion located between the base substrate and the active layer, wherein an orthographic projection of the light shielding portion on the base substrate at least partially overlaps with an orthographic projection of the active layer on the base substrate; The light shielding portion is located in the second conductive layer.

9. The display panel according to claim 7 or 8, wherein: A portion of the plurality of touch control traces located at both side edges of the fan-out region is located in at least one of the first conductive layer and the second conductive layer; or, For multiple touch lines, the touch lines at odd positions are located in at least one of the first conductive layer and the second conductive layer, or the touch lines at even positions are located in at least one of the first conductive layer and the second conductive layer.

10. The display panel according to claim 3, wherein: m1 data lines are located in the first conductive layer, m2 data lines are located in the second conductive layer, n1 touch lines are located in the first conductive layer, and n2=0. The data lines electrically connected to the m1 data wirings and the touch signal lines electrically connected to the n1 touch wirings are both located at odd positions; The data lines electrically connected to the m2 data lines are located at even positions.

11. The display panel according to claim 3, wherein: m1 data wirings are located in the first conductive layer, m2 data wirings are located in the second conductive layer, n2 touch wirings are located in the second conductive layer, n1=0, The data lines electrically connected to the m1 data wirings are located at odd positions, and the touch signal lines electrically connected to the n2 touch wirings are located at even positions; The data lines electrically connected to the m2 data lines are located at even positions.

12. The display panel according to claim 3, wherein: m1 data lines are located in the first conductive layer, m2 data lines are located in the second conductive layer, n1 touch lines are located in the second conductive layer, n2 touch lines are located in the second conductive layer, and n1 and n2 are both positive integers. The data lines electrically connected to the m1 data lines are located at odd positions, the touch signal lines electrically connected to the n1 touch lines are located at odd positions, the data lines electrically connected to the m2 data lines are located at even positions, and the touch signal lines electrically connected to the n2 touch lines are located at even positions; or, the data lines electrically connected to the m1 data lines are located at even positions, the touch signal lines electrically connected to the n1 touch lines are located at even positions, the data lines electrically connected to the m2 data lines are located at odd positions, and the touch signal lines electrically connected to the n2 touch lines are located at odd positions.

13. The display panel according to claim 1 or 2, wherein: The plurality of data routings or the plurality of touch routings include a first routing located at a side edge of the fan-out region and a second routing located at a middle position of the fan-out region, the first routing includes an inclined portion and a vertical portion, the vertical portion extends parallel to the second direction, the inclined portion extends obliquely relative to the second direction, and the second routing includes only the vertical portion, A ratio of a vertical portion of the second routing line to a vertical portion of the first routing line is greater than 2.

14. The display panel according to claim 13, wherein: The display panel further includes a plurality of jumpers, the fan-out area includes a jumper area, the jumper area is located between the plurality of data lines and the plurality of touch lines and the chip, and the plurality of jumpers are used to electrically connect the plurality of data lines and the plurality of touch lines to the chip, The jumper area is located between the vertical portion and the chip, so that the length of the vertical portion of the second routing line is less than 1 mm.

15. The display panel according to claim 1 or 2, wherein: At least some of the orthographic projections of each routing line in the first conductive layer on the substrate, the orthographic projections of each routing line in the second conductive layer on the substrate, and the orthographic projections of each routing line in the third conductive layer on the substrate are arranged at intervals.

16. A display device, characterized in that: Comprising the display panel according to any one of claims 1-15.

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