Array substrate, display panel and display device

Abstract

The application discloses an array substrate, a display panel and a display device. The array substrate has a display area and a non-display area surrounding the display area at least partially, and comprises: a gate driving circuit located in the non-display area and comprising a plurality of shift register units connected in cascade; a clock signal line electrically connected with the plurality of shift register units; and a trigger signal line electrically connected with at least one shift register unit. At least one of the clock signal line and the trigger signal line is located in the display area. According to the embodiment of the application, a narrow frame can be achieved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of display, in particular to an array substrate, a display panel and a display device. BACKGROUND

[0002] With the continuous updating of display panel technology, display panels are gradually developing towards thinness, high screen ratio and ultra-narrow frame.

[0003] The display panel usually includes a driving circuit and a signal line for providing a signal to the driving circuit. How to arrange the signal line to achieve a narrow frame is a technical problem faced by those skilled in the art. SUMMARY

[0004] The array substrate, the display panel and the display device provided by the embodiments of the present application are beneficial to achieve a narrow frame.

[0005] In a first aspect, the embodiments of the present application provide an array substrate having a display area and a non-display area at least partially surrounding the display area, the array substrate comprising: a gate driving circuit located in the non-display area and comprising a plurality of shift register units connected in cascade; a clock signal line electrically connected to the plurality of shift register units; a trigger signal line electrically connected to at least one shift register unit; and at least one of the clock signal line and the trigger signal line being located in the display area.

[0006] Based on the same inventive concept, in a second aspect, the embodiments of the present application provide a display panel comprising the array substrate as described in the first aspect.

[0007] Based on the same inventive concept, in a third aspect, the embodiments of the present application provide a display device comprising the display panel as described in the second aspect.

[0008] According to the display panel and the display device provided by the embodiments of the present application, the clock signal line and / or the trigger signal line are located in the display area, which is not only beneficial to reduce the left and right side frames, but also beneficial to reduce the lower frame. BRIEF DESCRIPTION OF DRAWINGS

[0009] Other features, objects and advantages of the present application will become more apparent from the following detailed description of non-limiting embodiments with reference to the drawings, in which like or similar designations denote like or similar features, and in which:

[0010] Figure 1 Fig. 1 shows a top view schematic diagram of an array substrate provided by an embodiment of the present application;

[0011] Figure 2 Fig. 2 shows another top view schematic diagram of an array substrate provided by an embodiment of the present application;

[0012] Fig. 3 shows a top view schematic diagram of a display panel provided by an embodiment of the present application; and Fig. 4 shows a top view schematic diagram of a display device provided by an embodiment of the present application.Figure 3 Fig. 1 shows a schematic diagram of a structure of a winding in an array substrate according to an embodiment of the present application;

[0013] Figure 4 Fig. 2 shows another schematic diagram of a top view structure of an array substrate according to an embodiment of the present application;

[0014] Figure 5 Fig. 3 shows a schematic diagram of a top view structure of a local area in an array substrate according to an embodiment of the present application;

[0015] Figure 6 Fig. 4 shows a timing diagram of an array substrate according to an embodiment of the present application;

[0016] Figure 7 Fig. 5 shows a schematic diagram of a shift register unit in an array substrate according to an embodiment of the present application;

[0017] Figure 8 Fig. 6 shows another schematic diagram of a top view structure of a local area in an array substrate according to an embodiment of the present application;

[0018] Figure 9 Fig. 7 shows a schematic diagram of a film layer structure of an array substrate according to an embodiment of the present application;

[0019] Figure 10 Fig. 8 shows another schematic diagram of a top view structure of an array substrate according to an embodiment of the present application;

[0020] Figure 11 Fig. 9 shows another schematic diagram of a top view structure of an array substrate according to an embodiment of the present application;

[0021] Figure 12 Fig. 10 shows another schematic diagram of a top view structure of a local area in an array substrate according to an embodiment of the present application;

[0022] Figure 13 Fig. 11 shows another schematic diagram of a top view structure of a local area in an array substrate according to an embodiment of the present application;

[0023] Figure 14 Fig. 12 shows a schematic diagram of a pixel circuit in an array substrate according to an embodiment of the present application;

[0024] Figure 15 Fig. 13 shows a schematic diagram of a top view structure of a display device according to an embodiment of the present application.

[0025] Legend of reference signs:

[0026] 100, array substrate;

[0027] AA, display area; NA, non-display area; BA, step area;

[0028] 10, gate driving circuit; 11, first gate driving circuit; 12, second gate driving circuit;

[0029] VSR, shift register unit; VSR1, first shift register unit; VSR2, second shift register unit

[0030] 21, clock signal line; 21a, first type clock signal line; 21b, second type clock signal line;

[0031] 211, first clock signal line; 212, second clock signal line;

[0032] 22, trigger signal line; 221, first trigger signal line; 222, second trigger signal line;

[0033] 31, lead wire; 32, electrostatic protection wire;

[0034] 41, first winding; 42, second winding; 43, third winding; 44, connecting winding;

[0035] 50, connecting line; 51, first connecting line; 52, second connecting line; 53, third connecting line; 54, fourth connecting line;

[0036] 60, gate trace line;

[0037] 71, pixel circuit; 72, virtual pixel circuit; 711, connecting part;

[0038] 80, data line;

[0039] 90, shielding structure; 91, first shielding structure; 92, second shielding structure;

[0040] 1000, display device. DETAILED DESCRIPTION

[0041] The features and exemplary embodiments of various aspects of the present application will be described in detail below with reference to the drawings. The following detailed description is provided to provide further understanding of the present application, and is not intended to limit the scope of the present application. The present application can be implemented without some of the specific details, which will be apparent to those skilled in the art. The following description of the embodiments is merely provided to provide a better understanding of the present application by showing examples of the present application.

[0042] It should be noted that, in the present document, the terms such as first and second, etc. are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between such entities or operations. Also, the terms "comprises", "comprising", or any other variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but can also include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by an "includes" statement does not exclude the presence of additional identical elements in the process, method, article, or apparatus that includes the element.

[0043] It should be understood that, in describing the structure of a component, when one layer, one region is referred to as being "on" or "above" another layer, another region, it can mean being directly on or above the other layer, the other region, or other layers or regions can be included therebetween. Also, if the component is turned over, the layer, the region will be "under" or "below" the other layer, the other region.

[0044] It should be understood that the term "and / or" used herein only describes an association relationship of associated objects, which means that there can be three relationships, for example, A and / or B, which can represent the three cases of A existing alone, A and B existing together, and B existing alone. In addition, the character " / " in the present document generally represents an "or" relationship between the front and rear associated objects.

[0045] In the embodiments of the present application, the term "electrically connected" can mean that two components are directly electrically connected, or can mean that two components are electrically connected via one or more other components.

[0046] Various modifications and changes can be made to the present application without departing from the spirit or scope of the present application, which will be apparent to one skilled in the art. Thus, the present application intends to cover the modifications and changes of this application falling within the scope of the corresponding claims (claimed technical solutions) and their equivalents. It should be noted that the embodiments provided by the present application can be combined with each other without contradiction.

[0047] The embodiments of the present application provide an array substrate, a display panel and a display device, which will be described below in combination with the accompanying drawings.

[0048] As Figure 1As shown, the array substrate 100 has a display area AA and a non-display area NA at least partially surrounding the display area AA. The array substrate 100 can include a gate driving circuit 10, a clock signal line 21 and a trigger signal line 22.

[0049] The gate driving circuit 10 is located in the non-display area NA, and the gate driving circuit 10 can include a plurality of shift register units VSR cascaded. For example, the display area AA of the array substrate 100 can include a plurality of rows of pixel circuits (not shown in the figure), and the scan signals output by the shift register units VSR can be used to control the turn-on or turn-off of at least some transistors in the pixel circuits. The plurality of cascaded shift register units VSR can output the scan signals step by step to scan the plurality of rows of pixel circuits row by row. Figure 1

[0050] The clock signal line 21 is electrically connected with each shift register unit VSR, and the clock signal line 21 can be used to transmit a clock signal to each shift register unit VSR.

[0051] The trigger signal line 22 is electrically connected with at least one shift register unit VSR, and the trigger signal line 22 is used to transmit a trigger signal to the shift register unit VSR electrically connected therewith. For example, the trigger signal line 22 is electrically connected with the first stage shift register unit VSR. The signal output by the i-th stage shift register unit VSR can be used as the trigger signal of the i+1-th stage shift register unit VSR, i≥1, and i is an integer, for example, i=1.

[0052] At least one of the clock signal line 21 and the trigger signal line 22 can be located in the display area AA. Figure 1 It is not intended to limit the present application by the example that both of them are located in the display area AA.

[0053] For example, the clock signal line 21 and the trigger signal line 22 can both extend along a first direction X, and the clock signal line 21 and the trigger signal line 22 can be arranged in a second direction Y, and the first direction X and the second direction Y intersect. For example, the first direction X can be the column direction, and the second direction Y can be the row direction.

[0054] For example, the non-display area NA can include a step area BA, and the step area BA can include a plurality of signal terminals pad, and the clock signal line 21 and the trigger signal line 22 can be connected to different signal terminals pad through different leads 31, and the signal terminals pad can be connected with a driving chip (not shown in the figure). Figure 1 ​The clock signal line 21 and / or the trigger signal line 22 can be electrically connected to the lead line 31. It can be understood that, if the clock signal line 21 and / or the trigger signal line 22 is located in the display area AA, the lead line 31 can extend directly along the first direction X. If the clock signal line 21 and the trigger signal line 22 are both located in the non-display area NA, the lead line 31 needs to bypass the edge area to be connected to the clock signal line 21 and the trigger signal line 22, which requires increasing the width of the lower bezel in the first direction X. Therefore, the clock signal line 21 and / or the trigger signal line 22 located in the display area AA is beneficial to reducing the left and right bezels and the lower bezel.

[0055] In the process of manufacturing the array substrate, or when the array substrate is used in a display panel, static electricity can be generated in the display process. In order to release or dissipate the static electricity, as shown in FIG. 1, an electrostatic protection line 32 can be arranged. The electrostatic protection line 32 is located in the non-display area NA and away from the display area AA on the side of the gate drive circuit 10. The electrostatic protection line 32 can be grounded GND. The electrostatic protection line 32 can be used for electro-static discharge (ESD). Figure 1

[0056] In order to avoid the electrostatic protection line 32 being broken down by static electricity, the width of the electrostatic protection line 32 can be relatively thick.

[0057] It can be understood that the clock signal line 21 and the trigger signal line 22 are relatively long lines, and the clock signal line 21 and the trigger signal line 22 are prone to accumulate static electricity. In the case that the polarity of the static electricity on the clock signal line 21 and the trigger signal line 22 is different from that on the electrostatic protection line 32, the relatively thin clock signal line 21 and the trigger signal line 22 are prone to be broken down.

[0058] In the embodiments of the present application, the clock signal line 21 and / or the trigger signal line 22 is located in the display area AA, so that the clock signal line 21 and / or the trigger signal line 22 is spaced apart from the electrostatic protection line 32 by the gate drive circuit 10, which is beneficial to avoiding the clock signal line 21 and / or the trigger signal line 22 being broken down by static electricity.

[0059] In some embodiments, as shown in FIG. 1, at least the clock signal line 21 is located in the display area AA, and the non-display area NA includes a step area BA. The array substrate 100 can further include a first winding 41 and a second winding 42. The clock signal line 21 is electrically connected to the plurality of shift register units VSR through the first winding 41 and the second winding 42. The first winding 41 is connected between the clock signal line 21 and the second winding 42, and the second winding 42 is connected to the shift register unit VSR. The first winding 41 and the second winding 42 are both located in the non-display area NA, and the first winding 41 is spaced apart from the step area BA by the display area AA. Figure 2 In some embodiments, as shown in FIG. 1, at least the clock signal line 21 is located in the display area AA, and the non-display area NA includes a step area BA. The array substrate 100 can further include a first winding 41 and a second winding 42. The clock signal line 21 is electrically connected to the plurality of shift register units VSR through the first winding 41 and the second winding 42. The first winding 41 is connected between the clock signal line 21 and the second winding 42, and the second winding 42 is connected to the shift register unit VSR. The first winding 41 and the second winding 42 are both located in the non-display area NA, and the first winding 41 is spaced apart from the step area BA by the display area AA. In some embodiments, as shown in FIG. 1, at least the clock signal line 21 is located in the display area AA, and the non-display area NA includes a step area BA. The array substrate 100 can further include a first winding 41 and a second winding 42. The clock signal line 21 is electrically connected to the plurality of shift register units VSR through the first winding 41 and the second winding 42. The first winding 41 is connected between the clock signal line 21 and the second winding 42, and the second winding 42 is connected to the shift register unit VSR. The first winding 41 and the second winding 42 are both located in the non-display area NA, and the first winding 41 is spaced apart from the step area BA by the display area AA.

[0060] Taking the lower bezel as an example, the lower bezel needs to be provided with more fan-out lines. In the embodiment of the present application, the first wire 41 is located on the upper bezel, and the number of lines to be provided on the upper bezel is relatively less than that on the lower bezel. Therefore, the first wire 41 is arranged on the upper bezel, so as to save the space of the lower bezel, thereby facilitating the reduction of the lower bezel.

[0061] As shown in Figure 2 , the trigger signal line 22 can be connected to the first-stage shift register unit VSR through the third wire 43. The third wire 43 is located in the non-display area NA, and the third wire 43 is spaced apart from the step area BA by the display area AA. In this way, the third wire 43 is also arranged on the upper bezel, so as to save the space of the lower bezel.

[0062] As shown in Figure 2 , the second wire 42 can be connected to the shift register unit VSR through the connection wire 44, and the connection wire 44 can be located in the non-display area NA.

[0063] In some embodiments, as introduced above, the extension direction of the clock signal line 21 is the first direction X. Please refer to Figure 2 , in the second direction Y, the second wire 42 extends along the first direction X, and the gate drive circuit 10 can be located between the second wire 42 and the display area AA.

[0064] As shown in Figure 3 , the second wire 42 can include a plurality of wire segments connected to each other, and at least two wire segments are located in different film layers.

[0065] For example, the second wire 42 can include a first wire segment 421 and a second wire segment 422 connected to each other, the first wire segment 421 and the second wire segment 422 are located in different metal layers, and the first wire segment 421 and the second wire segment 422 can be connected through a first via h1. The first wire segment 421 and the second wire segment 422 can be alternately distributed in the first direction X.

[0066] The second wire 42 needs to be connected to each shift register unit VSR, so that the length of the lines on the second wire 42 as a whole is relatively long. In the embodiment of the present application, the second wire 42 is divided into a plurality of wire segments, which is equivalent to dividing the relatively long second wire 42 into a plurality of relatively short wire segments. In this way, the possibility of accumulating static electricity on the second wire 42 can be reduced, so as to improve the reliability of the second wire 42.

[0067] In some embodiments, as Figure 1As shown, the gate driving circuit 10 may include a first gate driving circuit 11 and a second gate driving circuit 12. The first gate driving circuit 11 includes a plurality of cascaded first shift registers VSR1, and the second gate driving circuit 12 includes a plurality of cascaded second shift registers VSR2.

[0068] The first shift register unit VSR1 and the second shift register unit VSR2 are located on both sides of the display area AA in the second direction Y. That is, the first shift register unit VSR1 and the second shift register unit VSR2 are spaced apart from the display area AA in the second direction Y.

[0069] The clock signal line 21 may include a first type of clock signal line 21a and a second type of clock signal line 21b. The first type of clock signal line 21a is close to and electrically connected to the first shift register unit VSR1, and the second type of clock signal line 21b is close to and electrically connected to the second shift register unit VSR2.

[0070] In this embodiment, various clock signal lines and their electrically connected shift register units are arranged close together, which can help shorten the length of the connection line between the clock signal lines and their electrically connected shift register units.

[0071] As an example, the first shift register unit VSR1 and the second shift register unit VSR2 can be used to output different gate control signals. For instance, the first shift register unit VSR1 can output a scan signal, which can be used to control whether data signals are written to the pixel circuit. The second shift register unit VSR2 can output a light emission control signal, which can be used to control whether the pixel circuit enters the light emission stage.

[0072] As another example, the first shift register unit VSR1 and the second shift register unit VSR2 can also be used to output the same gate control signal. The first shift register unit VSR1 and the second shift register unit VSR2 can be connected to both ends of the same gate trace to achieve dual-end drive and reduce the impact of signal delay.

[0073] In other embodiments, such as Figure 4 As shown, taking the clock signal line 21 located in the display area AA and extending along the first direction X as an example, the array substrate 100 may also include a connecting line 50, through which the clock signal line 21 can be electrically connected to a plurality of shift register units VSR. In the second direction Y, the connecting line 50 is located between the clock signal line 21 and the shift register unit VSR.

[0074] In this embodiment, instead of providing a winding connecting the clock signal line 21 and the shift register unit VSR on the left and right sides, a connecting line is directly provided between the clock signal line 21 and the shift register unit VSR. This further saves space on the left and right sides.

[0075] In some embodiments, such as Figure 5 As shown, clock signal line 21 may include a first clock signal line 211 and a second clock signal line 212. The clock signals provided on the first clock signal line 211 and the second clock signal line 212 may be different. For example, as... Figure 6 As shown, taking a low level as the conduction level as an example, the conduction levels of the clock signals provided on the first clock signal line 211 and the second clock signal line 212 can be interleaved in time.

[0076] like Figure 5 As shown, the connecting line 50 may include a first connecting line 51, a second connecting line 52, a third connecting line 53, and a fourth connecting line 54. Specifically, the first connecting line 51 can be connected between the first clock signal line 211 and the i-th level shift register unit VSR(i), the second connecting line 52 is connected between the second clock signal line 212 and the (i+1)-th level shift register unit VSR(i+1), the third connecting line 53 is connected between the second connecting line 52 and the i-th level shift register unit VSR(i), and the fourth connecting line 54 is connected between the first connecting line 51 and the (i+1)-th level shift register unit VSR(i+1), where i is an odd number. For example, i = 1.

[0077] Understandably, the i-th stage shift register unit VSR(i) is directly connected to the first clock signal line 211 via the first connection line 51, and the i-th stage shift register unit VSR(i) is connected to the second clock signal line 212 via the third connection line 53 and the second connection line 52 in sequence. The third connection line 53 is equivalent to a transition connection line between the i-th stage shift register unit VSR(i) and the second clock signal line 212.

[0078] The (i+1)th stage shift register unit VSR(i+1) is directly connected to the second clock signal line 212 via the second connection line 52. The (i+1)th stage shift register unit VSR(i+1) is connected to the first clock signal line 211 via the fourth connection line 54 and the first connection line 51 in sequence. The fourth connection line 54 is equivalent to a transition connection line between the (i+1)th stage shift register unit VSR(i+1) and the first clock signal line 211.

[0079] Instead of each shift register unit being directly connected to the first clock signal line 211 and the second clock signal line 212 via a connecting line, in this embodiment, the shift register unit is connected to one of the first clock signal line 211 and the second clock signal line 212 via a third connecting line 53 or a fourth connecting line 54, which allows for flexible arrangement of the positions of the third connecting line 53 and the fourth connecting line 54.

[0080] As an example, such as Figure 5As shown, the third connection line 53 and the fourth connection line 54 can be located in the non-display area NA. Since the signal on the clock signal line frequently switches between high and low levels, when the third connection line 53 and the fourth connection line 54 are located in the non-display area, the coupling between the third connection line 53 and the fourth connection line 54 and the pixel circuit 71 in the display area AA can be reduced, which can help improve the display quality.

[0081] In addition, the first connecting line 51 and the second connecting line 52 can extend along the second direction Y, with at least a portion of the first connecting line 51 located in the display area AA, and at least a portion of the second connecting line 52 located in the display area AA.

[0082] In some embodiments, such as Figure 5 As shown, the display area AA of the array substrate 100 may include multiple gate traces 60, which may be scan lines or light emission control signal lines.

[0083] The output terminal out of the i-th stage shift register unit VSR(i) is electrically connected to the i-th gate line 60(i), and the output terminal of the (i+1)-th stage shift register unit VSR(i+1) is electrically connected to the (i+1)-th gate line 60(i+1).

[0084] like Figure 6 As shown, the i-th stage shift register unit VSR(i) can generate a gate control signal based on the signal on the second clock signal line 212, and the (i+1)-th stage shift register unit VSR(i+1) can generate a gate control signal based on the signal on the first clock signal line 211.

[0085] For example, taking a low level as the conduction level, the low level output by the i-th stage shift register unit VSR(i) is generated based on the low level on the second clock signal line 212, and the low level output by the (i+1)-th stage shift register unit VSR(i+1) is generated based on the low level on the first clock signal line 211.

[0086] like Figure 5 As shown, in the first direction X, the distance between the first connection line 51 connected to the i-th stage shift register unit VSR(i) and the i-th gate line 60(i) is d1, and the distance between the second connection line 52 connected to the (i+1)-th stage shift register unit VSR(i+1) and the i-th gate line 60(i) is d2, where d1 < d2.

[0087] The distance between the first connection line 51 connected to the i-th shift register unit VSR(i) and the i+1 gate line 60(i+1) is d3, and the distance between the second connection line 52 connected to the i+1 shift register unit VSR(i+1) and the i+1 gate line 60(i+1) is d4, where d3 > d4.

[0088] Since the i-th shift register unit VSR(i) generates the gate control signal based on the signal on the second clock signal line 212, in the case of d1 < d2, it is beneficial to avoid the output signal of the i-th shift register unit VSR(i) being further coupled by the signal on the second clock signal line 212, for example, to avoid the output signal of the i-th shift register unit VSR(i) being further coupled and pulled high by the signal on the second clock signal line 212. Similarly, since the i+1-th shift register unit VSR(i+1) generates the gate control signal based on the signal on the first clock signal line 211, in the case of d3 > d4, it is beneficial to avoid the output signal of the i+1-th shift register unit VSR(i+1) being further coupled by the signal on the first clock signal line 211.

[0089] For example, the circuit structure of the shift register unit can be as shown in Figure 7 , Figure 7 wherein VGH represents a high-level signal terminal, VGL represents a low-level signal terminal, IN represents a trigger signal terminal, and ck and xck represent two clock signal terminals. Figure 7 This is merely an example and is not intended to limit the specific circuit structure of the shift register unit.

[0090] In some embodiments, as shown in Figure 5 , the display area AA of the array substrate further includes a plurality of rows of pixel circuits 71, and the i-th gate wire 60(i) is electrically connected to the i-th row of pixel circuits 71. For example, the signal on the i-th gate wire 60(i) can be used to control whether data signals are written to the i-th row of pixel circuits 71.

[0091] The i+1-th gate wire 60(i+1) can be connected to the i+1-th row of pixel circuits 71. For example, the signal on the i+1-th gate wire 60(i+1) can be used to control whether data signals are written to the i+1-th row of pixel circuits 71.

[0092] The first connection line 51 connected to the i-th shift register unit VSR(i) can overlap in orthographic projection on the plane of the array substrate with the i-th row of pixel circuits 71, and the first connection line 51 connected to the i-th shift register unit VSR(i) can not overlap in orthographic projection on the plane of the array substrate with the i+1-th row of pixel circuits 71.

[0093] The second connection line 52 connected to the i+1-th shift register unit VSR(i+1) can not overlap in orthographic projection on the plane of the array substrate with the i-th row of pixel circuits 71, and the second connection line 52 connected to the i+1-th shift register unit VSR(i+1) can overlap in orthographic projection on the plane of the array substrate with the i+1-th row of pixel circuits 71.

[0094] In this way, the first connection line 51 and the second connection line 52 can only overlap with one of the two adjacent rows of pixel circuits, and the coupling effect of the first connection line 51 and the second connection line 52 on the pixel circuit can be reduced.

[0095] In some embodiments, as shown in FIG. 1, the display area AA of the array substrate further includes a data line 80. The clock signal line 21 and / or the trigger signal line 22 in the display area AA and the data line 80 can be located in different film layers. In this way, the coupling between the clock signal line 21 and / or the trigger signal line 22 and the data line 80 in the display area AA can be reduced. Figure 8

[0096] For example, as shown in FIG. 1, the array substrate can include a laminated semiconductor layer b, a first metal layer M1, a second metal layer M2, a third metal layer M3, a fourth metal layer M4, and an anode layer RE. The clock signal line 21 and / or the trigger signal line 22 in the display area AA can be located in the fourth metal layer M4, and the data line 80 can be located in the third metal layer M3. Figure 9

[0097] The array substrate can further include a substrate 01 and a gate insulating layer GI, a capacitor insulating layer IMD, an interlayer dielectric layer ILD, a first planarization layer PLN1, a second planarization layer PLN2, a pixel definition layer PDL, and a support PS.

[0098] For example, as shown in FIG. 1, the array substrate 100 includes a pixel circuit 71 and a virtual pixel circuit 72. The pixel circuit 71 is located in the display area AA. The pixel circuit 71 can be used to drive the light emitting element of the display panel to emit light. The virtual pixel circuit 72 is not used to drive the light emitting element to emit light. Figure 10 In the second direction Y, the virtual pixel circuit 72 can be located between the gate driving circuit 10 and the pixel circuit 71. Still taking the extension direction of the clock signal line 21 as the first direction X as an example, the second direction Y intersects the first direction X.

[0099] The orthogonal projection of the clock signal line 21 and / or the trigger signal line 22 in the display area AA on the plane where the array substrate is located can at least partially overlap with the orthogonal projection of the virtual pixel circuit 72 on the plane where the array substrate is located.

[0100] Since the virtual pixel circuit 72 is not used to drive the light emitting element, in the case where the clock signal line 21 and / or the trigger signal line 22 overlap with the virtual pixel circuit 72, the coupling of the clock signal line 21 and / or the trigger signal line 22 on the pixel circuit 71 can be reduced, thereby being beneficial to improving the display effect.

[0101] In other embodiments, as shown in FIG. 2, the display area AA of the array substrate further includes a data line 80. The clock signal line 21 and / or the trigger signal line 22 in the display area AA and the data line 80 can be located in different film layers. In this way, the coupling between the clock signal line 21 and / or the trigger signal line 22 and the data line 80 in the display area AA can be reduced.

[0102] Figure 11 ​​​As shown, the normal projection of the clock signal line 21 and / or the trigger signal line 22 in the display area AA on the plane of the array substrate can at least partially overlap with the normal projection of the pixel circuit 71 on the plane of the array substrate.

[0103] Since the dummy pixel circuit 72 is arranged close to the edge of the display area, in the case that the clock signal line 21 and / or the trigger signal line 22 overlap with the pixel circuit 71, it is more advantageous for the clock signal line 21 and / or the trigger signal line 22 to be close to the signal terminal pad to which it is connected, so as to be more advantageous for the lead line 31 to extend directly along the first direction X. It is further more advantageous to reduce the lower bezel.

[0104] In some embodiments, as shown, Figure 12 As shown, the display area AA of the array substrate further comprises a data line 80 and a shielding structure 90, the shielding structure 90 comprises a first shielding structure 91, the first shielding structure 91 is located between the data line 80 and the clock signal line 21 or the trigger signal line 22 in the display area AA. The first shielding structure 91 can be advantageous to avoid coupling between the clock signal line 21 or the trigger signal line 22 in the display area AA and the data line 80.

[0105] For example, in the case that the normal projection of the clock signal line 21 or the trigger signal line 22 in the display area on the plane of the array substrate does not overlap with the normal projection of the data line 80 on the plane of the array substrate, the normal projection of the first shielding structure 91 on the plane of the array substrate can be located between the normal projection of the clock signal line 21 or the trigger signal line 22 in the display area on the plane of the array substrate and the normal projection of the data line 80 on the plane of the array substrate.

[0106] For another example, in the case that the normal projection of the clock signal line 21 or the trigger signal line 22 in the display area on the plane of the array substrate overlaps with the normal projection of the data line 80 on the plane of the array substrate, the film layer in which the first shielding structure 91 is located can be located between the film layer in which the clock signal line 21 or the trigger signal line 22 is located and the film layer in which the data line 80 is located, and the normal projection of the first shielding structure 91 on the plane of the array substrate, the normal projection of the clock signal line 21 or the trigger signal line 22 in the display area on the plane of the array substrate, and the normal projection of the data line 80 on the plane of the array substrate can all overlap.

[0107] The first shielding structure 91 can be in a floating state, or the first shielding structure 91 can be used to connect a fixed signal terminal.

[0108] It should be noted that, in order to clearly distinguish different signal lines or structures, Figure 12The data line 80 is schematically shown by a thick solid line, the clock signal line 21 and the trigger signal line 22 are schematically shown by thin solid lines, and the first shielding structure 91 is schematically shown by a dashed line, which does not define the thickness or continuity of the signal lines or structures.

[0109] In some embodiments, as shown in FIG. 7A, the pixel circuit 71 can include a driving transistor M13 and a connection part 711 connected to the gate g3 of the driving transistor M13. For example, the connection part 711 can be connected to the gate g3 of the driving transistor M13 through a via h2. Figure 13

[0110] The display area of the array substrate can further include a shielding structure 90, which can include a second shielding structure 92 located between the connection part 711 and the clock signal line 21 or the trigger signal line 22 in the display area. Similarly, the second shielding structure 92 can be beneficial to avoid coupling between the clock signal line 21 or the trigger signal line 22 and the connection part 711 in the display area AA, and thus beneficial to avoid the influence of the potential jump of the clock signal line 21 or the trigger signal line 22 on the gate potential of the driving transistor M13.

[0111] For example, in the case that the orthogonal projection of the clock signal line 21 or the trigger signal line 22 in the display area on the plane where the array substrate is located does not overlap with the orthogonal projection of the connection part 711 on the plane where the array substrate is located, the orthogonal projection of the second shielding structure 92 on the plane where the array substrate is located can be located between the orthogonal projection of the clock signal line 21 or the trigger signal line 22 in the display area on the plane where the array substrate is located and the orthogonal projection of the connection part 711 on the plane where the array substrate is located.

[0112] For another example, in the case that the orthogonal projection of the clock signal line 21 or the trigger signal line 22 in the display area on the plane where the array substrate is located overlaps with the orthogonal projection of the connection part 711 on the plane where the array substrate is located, the film layer where the second shielding structure 92 is located can be located between the film layer where the clock signal line 21 or the trigger signal line 22 is located and the film layer where the connection part 711 is located, and the orthogonal projection of the second shielding structure 92 on the plane where the array substrate is located, the orthogonal projection of the clock signal line 21 or the trigger signal line 22 in the display area on the plane where the array substrate is located, and the orthogonal projection of the connection part 711 on the plane where the array substrate is located can all overlap.

[0113] The second shielding structure 92 can be in a floating state, or the first shielding structure 91 can be used to connect a fixed signal end.

[0114] In some embodiments, the display area of the array substrate can further include a reset signal line and a power signal line. For example, as shown in FIG. 7B, the pixel circuit 71 can include a reset transistor M14 and a connection part 712 connected to the gate g4 of the reset transistor M14. For example, the connection part 712 can be connected to the gate g4 of the reset transistor M14 through a via h3. Figure 14 ​As shown, the reset signal line can include a first reset signal line Vref1 and a second reset signal line Vref2. The first reset signal line Vref1 can be used to transmit a first reset signal to the gate of the driving transistor M13 in the pixel circuit, and the second reset signal line Vref2 can be used to transmit a second reset signal to the anode of the light emitting element D.

[0115] The power signal line PVDD can be used to increase the positive power voltage.

[0116] For example, at least one of the first reset signal line Vref1 and the second reset signal line Vref2 can be multiplexed as the shielding structure 90 in the above example. For another example, the power signal line PVDD can be multiplexed as the shielding structure 90 in the above example. In this way, the structure of the array substrate can be simplified.

[0117] It should be noted that, Figure 14 The structure of the pixel circuit 71 shown is only an example and is not intended to limit the present application.

[0118] Based on the same inventive concept, the present application also provides a display panel. The display panel provided by the embodiments of the present application can include the array substrate described in any of the above embodiments. The display panel provided by the embodiments of the present application can be an organic light-emitting diode (OLED) display panel.

[0119] Those skilled in the art should understand that in other implementations of the present application, the display panel can also be a micro light-emitting diode (Micro LED) display panel, a quantum dot display panel, etc.

[0120] The display panel provided by the embodiments of the present application has the beneficial effects of the array substrate provided by the embodiments of the present application. For details, refer to the specific description of the array substrate in the above embodiments, which will not be repeated here.

[0121] The present application also provides a display device including the display panel provided by the present application. Please refer to Figure 15 , Figure 15 FIG. 1 is a structural schematic diagram of a display device provided by an embodiment of the present application. Figure 15 The display device 1000 provided by the present application includes the display panel provided by any of the above embodiments of the present application. Figure 15The embodiments are described by taking the mobile phone as an example to describe the display device 1000, and it can be understood that the display device provided by the embodiments of the present application can be a wearable product, a computer, a television, a vehicle-mounted display device, or other display devices having a display function, and the present application does not make specific limitations thereon. The display device provided by the embodiments of the present application has the beneficial effects of the display panel provided by the embodiments of the present application, and specific descriptions can be made with reference to the specific descriptions of the display panel in the above embodiments, and the embodiments will not be described herein again.

[0122] In accordance with the embodiments of the present application as described above, the embodiments do not describe all the details, nor limit the application to only the specific embodiments described. Obviously, many modifications and variations can be made in light of the above descriptions. The embodiments are selected and specifically described in this specification in order to better explain the principles and practical applications of the present application, so that those skilled in the art can well utilize the present application and make modifications and uses on the basis of the present application. The present application is limited only by the claims and their full scope and equivalents.

Claims

1. An array substrate, characterized in that, The array substrate includes a display area and a non-display area at least partially surrounding the display area. The gate driving circuit, located in the non-display area, includes multiple cascaded shift register units; A clock signal line is electrically connected to multiple shift register units; A trigger signal line is electrically connected to at least one of the shift register units; At least one of the clock signal line and the trigger signal line is located in the display area; The clock signal line is located in the display area and extends along a first direction. The array substrate also includes a connecting line. The clock signal line is electrically connected to a plurality of shift register units through the connecting line. In a second direction, the connecting line is located between the clock signal line and the shift register unit. The second direction intersects the first direction. The clock signal line includes a first clock signal line and a second clock signal line. The connecting line includes a first connecting line, a second connecting line, a third connecting line, and a fourth connecting line. The first connecting line is connected between the first clock signal line and the i-th level shift register unit. The second connecting line is connected between the second clock signal line and the (i+1)-th level shift register unit. The third connecting line is connected between the second connecting line and the i-th level shift register unit. The fourth connecting line is connected between the first connecting line and the (i+1)-th level shift register unit, where i is an odd number.

2. The array substrate according to claim 1, characterized in that, At least the clock signal line is located in the display area, and the non-display area includes a stepped area; The array substrate further includes a first winding and a second winding. The clock signal line is electrically connected to a plurality of shift register units through the first winding and the second winding. The first winding is connected between the clock signal line and the second winding, and the second winding is connected to the shift register unit. Both the first winding and the second winding are located in the non-display area, and the first winding is spaced from the step area by the display area.

3. The array substrate according to claim 2, characterized in that, The clock signal line extends along a first direction, and in a second direction, the gate driving circuit is located between the second winding and the display area. The second winding includes a plurality of interconnected winding segments, at least two of the winding segments are located in different film layers, and the second direction intersects with the first direction.

4. The array substrate according to claim 1, characterized in that, The gate driving circuit includes a first gate driving circuit and a second gate driving circuit. The first gate driving circuit includes a plurality of cascaded first shift register units, and the second gate driving circuit includes a plurality of cascaded second shift register units. The first shift register unit and the second shift register unit are located on both sides of the display area. The clock signal lines include a first type of clock signal line and a second type of clock signal line. The first type of clock signal line is close to and electrically connected to the first shift register unit, and the second type of clock signal line is close to and electrically connected to the second shift register unit.

5. The array substrate according to claim 1, characterized in that, At least a portion of the first connecting line is located in the display area, at least a portion of the second connecting line is located in the display area, and the third and fourth connecting lines are located in the non-display area.

6. The array substrate according to claim 5, characterized in that, The display area of ​​the array substrate also includes multiple gate traces. The output terminal of the i-th stage shift register unit is electrically connected to the i-th gate trace, and the output terminal of the (i+1)-th stage shift register unit is electrically connected to the (i+1)-th gate trace. The shift register unit of the i-th stage generates a gate control signal based on the signal on the second clock signal line, and the shift register unit of the (i+1)-th stage generates a gate control signal based on the signal on the first clock signal line. In the extension direction of the clock signal line, the distance between the first connection line connected to the i-th stage shift register unit and the i-th gate trace is d1, and the distance between the second connection line connected to the (i+1)-th stage shift register unit and the i-th gate trace is d2, where d1 < d2. The distance between the first connection line connected to the i-th stage shift register unit and the gate trace of the (i+1)-th stage is d3, and the distance between the second connection line connected to the (i+1)-th stage shift register unit and the gate trace of the (i+1)-th stage is d4, where d3 > d4.

7. The array substrate according to claim 6, characterized in that, The display area of ​​the array substrate also includes multiple rows of pixel circuits, with the i-th gate line electrically connected to the i-th row of pixel circuits and the (i+1)-th gate line electrically connected to the (i+1)-th row of pixel circuits. The first connection line connected to the shift register unit of the i-th level overlaps with the orthographic projection of the pixel circuit of the i-th row on the plane of the array substrate, and the first connection line connected to the shift register unit of the i-th level does not overlap with the orthographic projection of the pixel circuit of the (i+1)-th row on the plane of the array substrate. The second connection line connected to the shift register unit of the (i+1)th level does not overlap with the orthographic projection of the pixel circuit of the (i+1)th row on the plane of the array substrate, and the second connection line connected to the shift register unit of the (i+1)th level overlaps with the orthographic projection of the pixel circuit of the (i+1)th row on the plane of the array substrate.

8. The array substrate according to claim 1, characterized in that, The display area of ​​the array substrate also includes data lines, and the clock signal line and / or the trigger signal line in the display area are located on different film layers from the data lines.

9. The array substrate according to claim 1, characterized in that, The array substrate further includes: Pixel circuitry is located in the display area; In the second direction, the virtual pixel circuit is located between the gate driving circuit and the pixel circuit, the clock signal line extends in the first direction, and the second direction intersects with the first direction; The orthographic projection of the clock signal line and / or the trigger signal line in the display area onto the plane where the array substrate is located at least partially overlaps with the orthographic projection of the virtual pixel circuit onto the plane where the array substrate is located.

10. The array substrate according to claim 1, characterized in that, The array substrate further includes: Pixel circuitry is located in the display area; A virtual pixel circuit, located between the gate driving circuit and the pixel circuit in the second direction; The orthographic projection of the clock signal line and / or the trigger signal line in the display area onto the plane where the array substrate is located at least partially overlaps with the orthographic projection of the pixel circuit onto the plane where the array substrate is located.

11. The array substrate according to claim 10, characterized in that, The display area of ​​the array substrate also includes data lines and a shielding structure. The shielding structure includes a first shielding structure, which is located between the data lines and the clock signal line or the trigger signal line in the display area.

12. The array substrate according to claim 10, characterized in that, The pixel circuit includes a driving transistor and a connection portion, the connection portion being connected to the gate of the driving transistor. The display area of ​​the array substrate further includes a shielding structure, the shielding structure including a second shielding structure, the second shielding structure being located between the connection portion and the clock signal line or the trigger signal line in the display area.

13. The array substrate according to claim 11 or 12, characterized in that, The display area also includes a reset signal line, which is multiplexed as the shielding structure. Alternatively, the display area may also include power signal lines, which are multiplexed as the shielding structure.

14. A display panel, characterized in that, Includes the array substrate as described in any one of claims 1 to 13.

15. A display device, characterized in that, Includes the display panel as described in claim 14.

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