Ramp signal compensation circuit and image sensor

Abstract

The application provides a ramp signal compensation circuit and an image sensor, the ramp signal compensation circuit comprising: a source follower module outputting a follow-up signal of the reference ramp voltage; a current mirror module copying a mirror current of the driving current to the current convergence point; a sampling compensation module sampling the power supply voltage to obtain a sampling signal and outputting a bias current corresponding to the sampling signal to the current convergence point; and a constant current module providing a constant current signal and converging the driving current and the bias current through the current convergence point, so that the driving current and the bias current are linearly correlated based on the constant current signal. The application linearly correlates the driving current and the bias current based on the constant current, enhances the driving capability of the reference ramp voltage signal, introduces the same power supply jitter into the input end of the comparator, reduces the influence of the power supply voltage on the quantization result, and realizes the stable output of the column-level comparator.

Description

Technical Field

[0001] This application relates to the field of sensor technology, specifically to a ramp signal compensation circuit and an image sensor. Background Technology

[0002] With the development of electronic device technology, more and more users are taking pictures using electronic devices. The demand for taking photos and videos is increasing, and there are also higher requirements for the shooting experience. In the pixel signal processing module architecture of an image sensor, each pixel line connects to a pixel in the pixel array to transmit the voltage signal converted by the pixel array after exposure, which is then input to a column comparator. The other input of the column comparator is a reference ramp voltage generated by a ramp generator. By comparing the voltage signal representing the pixel signal with the reference ramp voltage, the column comparator is inverted, thereby controlling the counter to count, storing quantized data, and finally outputting the corresponding digital signal.

[0003] In conceiving and formulating this application, the applicant discovered that in complex image sensors, due to the tens of millions of pixels in the pixel array, the corresponding number of column-level comparators is large. The driving capability of the reference ramp voltage generated by the ramp generator is limited, necessitating the addition of a ramp buffer with a certain driving capability to drive multiple column-level comparators to operate simultaneously. Furthermore, due to the parasitic coupling capacitance between the pixel lines and the power supply voltage, the voltage signal output by the pixel array is affected by power supply VDD jitter, impacting the comparator quantization results, i.e., a lower power supply rejection ratio (PSRR), severely affecting the output stability of the column-level comparators. Summary of the Invention

[0004] To alleviate the above problems, this application provides a ramp signal compensation circuit, including:

[0005] The source follower module is driven by the driving current generated by the power supply voltage. The input terminal of the source follower module is connected to a reference ramp voltage, and the output terminal of the source follower module outputs a following signal of the reference ramp voltage.

[0006] A current mirror module, wherein a first side of the current mirror module is connected to the output terminal of the source follower module, and a second side of the current mirror module is connected to a current confluence point to replicate the mirror current of the driving current to the current confluence point;

[0007] A sampling compensation module, wherein the first side of the sampling compensation module is grounded and the second side of the sampling compensation module is connected to the current confluence point, for sampling the power supply voltage to obtain a sampling signal, and outputting a bias current corresponding to the sampling signal to the current confluence point;

[0008] The constant current module is connected to the current mirror module and the sampling compensation module respectively, and is used to provide a constant current signal. It also merges the drive current and the bias current through the current confluence point, so that the drive current and the bias current are linearly correlated based on the constant current signal.

[0009] Optionally, the sampling compensation module includes a first transistor and a first capacitor unit. The first capacitor unit includes a first capacitor and a capacitor switch. The first terminal of the first capacitor is connected in series with the capacitor switch and connected to the power supply voltage through the capacitor switch. The second terminal of the first capacitor is connected to the control terminal of the first transistor. The first terminal of the first transistor is grounded. Under the drive of the driving current generated by the power supply voltage, the control terminal of the first transistor receives a first sampling signal. The second terminal of the first transistor is connected to the current confluence point and outputs a bias current corresponding to the sampling signal to the constant current module.

[0010] Optionally, the sampling compensation module further includes a second capacitor unit, the first end of which is connected to the control terminal of the first transistor, and the second end of which is grounded.

[0011] Optionally, the sampling compensation module further includes a first switch, the first end of which is connected to the control terminal of the first transistor, and the second end of which is connected to the first sampling signal.

[0012] Optionally, the sampling compensation module includes multiple first capacitor units, which are connected in parallel, and the capacitances of the first capacitors of the multiple capacitor units are in a multiple relationship.

[0013] Optionally, the source follower module includes a third transistor, the control terminal of the third transistor is connected to the reference ramp voltage, the first terminal of the third transistor is connected to the power supply voltage, and the second terminal of the third transistor outputs the follower signal.

[0014] Optionally, the current mirror module includes a fourth transistor and a fifth transistor;

[0015] The control terminal of the fourth transistor is connected to the control terminal of the fifth transistor, and the control terminal of the fourth transistor, the control terminal of the fifth transistor, and the first terminal of the fifth transistor are all connected to the current confluence point. The first terminal of the fourth transistor is connected to the output terminal of the source follower module, and the second terminal of the fourth transistor and the second terminal of the fifth transistor are both grounded.

[0016] Optionally, the current mirror module further includes a sixth transistor, which is connected in series between the source follower module and the current mirror module, and the control terminal of the sixth transistor is connected to a first preset voltage.

[0017] Optionally, the constant current module includes a seventh transistor, the control terminal of the seventh transistor is connected to a second sampling signal, the first terminal of the seventh transistor is connected to the current confluence point to combine the drive current and the bias current, and the constant current signal is generated based on the second sampling signal, and the second terminal of the seventh transistor is connected to the power supply voltage.

[0018] Optionally, the constant current module further includes a second switching element, the first end of which is connected to the control terminal of the seventh transistor, and the second end of which is connected to the second sampling signal.

[0019] Optionally, the constant current module includes an eighth transistor, which is connected in series with the seventh transistor to form a common gate common source circuit, and the control terminal of the eighth transistor is connected to a second preset voltage.

[0020] This application also provides an image sensor, including a ramp voltage generator, a comparator, and a counting memory. The image sensor also includes the ramp signal compensation circuit described above.

[0021] The ramp voltage generator is connected to the ramp signal compensation circuit to provide a reference ramp voltage;

[0022] The ramp signal compensation circuit is connected to the first input terminal of the comparator to output a follower signal of the reference ramp voltage;

[0023] The second input terminal of the comparator is connected to the photosensitive voltage of the photosensitive pixel, and the output terminal of the comparator is connected to the counting memory to output the comparison result;

[0024] The counting memory is used to count and store the comparison results to calculate the photosensitive result of the photosensitive pixel.

[0025] As described above, the ramp signal compensation circuit and image sensor provided in this application replicate the mirror current of the driving current to the current confluence point through the current mirror module. The constant current module is connected to the current mirror module and the sampling compensation module respectively to provide a constant current, so that the driving current of the source follower module and the bias current of the sampling compensation module are linearly correlated based on the constant current. On the basis of enhancing the driving capability of the reference ramp voltage signal, the same power supply jitter is introduced to the input of the comparator, reducing the influence of the power supply voltage on the quantization result and realizing the stable output of the column comparator. Attached Figure Description

[0026] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application. To more clearly illustrate the technical solutions of the embodiments of this application, the drawings used in the description of the embodiments will be briefly introduced below. Obviously, those skilled in the art can obtain other drawings based on these drawings without any creative effort.

[0027] Figure 1 This is a block diagram of a ramp signal compensation circuit according to an embodiment of this application.

[0028] Figure 2 This is a schematic diagram of a ramp signal compensation circuit according to an embodiment of this application. Figure 1 .

[0029] Figure 3 This is a schematic diagram of a ramp signal compensation circuit according to an embodiment of this application. Figure 2 .

[0030] Figure 4 This is a block diagram of an image sensor according to an embodiment of this application.

[0031] The realization of the objectives, functional features, and advantages of this application will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. The accompanying drawings have illustrated specific embodiments of this application, which will be described in more detail below. These drawings and textual descriptions are not intended to limit the scope of the concept in any way, but rather to illustrate the concepts of this application to those skilled in the art through reference to specific embodiments. Detailed Implementation

[0032] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numbers in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this application as detailed in the appended claims.

[0033] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element. Furthermore, components, features, and elements with the same names in different embodiments of this application may have the same meaning or different meanings, the specific meaning of which must be determined by its interpretation in that specific embodiment or further in conjunction with the context of that specific embodiment.

[0034] It should be understood that the specific embodiments described herein are merely illustrative of this application and are not intended to limit this application.

[0035] First Embodiment

[0036] This application provides a ramp signal compensation circuit. Figure 1 This is a block diagram of a ramp signal compensation circuit according to an embodiment of this application.

[0037] like Figure 1 As shown, in one embodiment, the ramp signal compensation circuit includes a source follower module 11, a sampling compensation module 13, a constant current module 14, and a current mirror module.

[0038] Driven by the driving current generated by the power supply voltage, the source follower module 11 has a reference ramp voltage connected to its input terminal, and outputs a following signal of the reference ramp voltage.

[0039] During image sensor operation, the quantization circuit, through a comparator, compares and quantizes the pixel signal input to the pixel unit with a ramp voltage, and outputs it to the storage unit via a counter. For example, a common-drain amplifier, also known as a "source follower," acts as a voltage buffer and is often used as the output stage of a multi-stage amplifier. Optionally, the drain of the transistor is connected to a common input-output reference node, the gate of the transistor is used as the input, and the source drives the load. The follower can employ a field-effect transistor (FET) as an impedance transformer and voltage follower circuit to improve the load-carrying capacity of the followed signal.

[0040] The first side of the current mirror module 12 is connected to the output terminal of the source follower module 11, and the second side of the current mirror module 12 is connected to the current confluence point Q, so as to copy the mirror current of the driving current to the current confluence point Q.

[0041] For example, a current mirror can be a mirrored constant current source. A mirrored constant current source is a standard component commonly found in analog integrated circuits, where the controlled current is equal to the input reference current, i.e., the input-output current transfer ratio is equal to 1. Its characteristic is that the output current is a proportional "copy" of the input current, used to generate bias current and as an active load.

[0042] The first side of the sampling compensation module 13 is grounded, and the second side of the sampling compensation module 13 is connected to the current confluence point Q. It is used to sample the power supply voltage to obtain a sampling signal and output a bias current corresponding to the sampling signal to the current confluence point Q.

[0043] For example, in order to mitigate the impact of power supply voltage fluctuations on the follower signal of the reference ramp voltage output by the source follower module 11, the power supply voltage can be connected to the sampling compensation module 13, and the power supply voltage can be sampled and calculated to compensate the follower signal output by the source follower module 11 with reasonable circuit parameters, thereby reducing the impact of power supply voltage fluctuations on the follower signal.

[0044] The constant current module 14 is connected to the current mirror module 12 and the sampling compensation module 13 respectively, and is used to provide a constant current signal. It also merges the drive current and the bias current through the current confluence point Q, so that the drive current and the bias current are linearly correlated based on the constant current signal.

[0045] For example, the constant current module 14 provides a constant current for total locking based on the mirror current of the drive current and the convergence of the bias current, thereby making the drive current and the bias current linearly correlated in the same direction. When the power supply voltage is disturbed, if the bias current decreases, the mirror current of the drive current increases accordingly due to the total locking, and the drive current also increases accordingly, thereby offsetting the disturbance effect of the power supply voltage on the source follower module 11 during the driving process. At this time, outputting the follower signal with reduced disturbance effect to the comparator can effectively improve the accuracy of the quantization result of the image sensor.

[0046] Figure 2 This is a schematic diagram of a ramp signal compensation circuit according to an embodiment of this application. Figure 1 .

[0047] like Figure 2 As shown, optionally, the sampling compensation module 13 includes a first transistor M1 and a first capacitor unit, wherein the first capacitor unit includes a first capacitor C1 and a capacitor switch Sc.

[0048] The first terminal of the first capacitor C1 is connected in series with the capacitor switch S2 and connected to the power supply voltage VDD through the capacitor switch S2. The second terminal of the first capacitor C1 is connected to the control terminal of the first transistor M1. The first terminal of the first transistor M1 is grounded. Under the drive of the drive current generated by the power supply voltage VDD, the input terminal of the first transistor M4 is connected to the first sampling signal Vbiasn. The second terminal of the first transistor M1 is connected to the current confluence point Q and outputs a bias current I1 corresponding to the sampling signal to the constant current module 14.

[0049] Optionally, the sampling compensation module 13 further includes a second capacitor unit, which includes a second capacitor C2. The second capacitor C2 is a filter capacitor, with its first terminal connected to the control terminal of the first transistor M1 and its second terminal grounded.

[0050] A filter capacitor is an energy storage device installed across a rectifier circuit to reduce AC ripple and improve the efficiency of DC output. Through its charging and discharging capabilities, the filter capacitor can smooth the voltage across its terminals. For example, a second capacitor C2, with one end grounded, can provide filtering for the control terminal of the first transistor M1, thereby ensuring the operational stability of the first transistor M1.

[0051] Please refer to Figure 2 For example, the first transistor M1 is an NMOS transistor. When the power supply voltage VDD jitters, assuming it jitters upwards, since the source of the first transistor M1 is connected to the current confluence point Q, and the gate of the first transistor M1 is coupled to the power supply voltage VDD through the first capacitor C1, the gate voltage will also rise upwards, with a rise ratio of C1 / (C1+C2)<1. Therefore, the bias current I1 through the first transistor M1 increases. Since the mirror current I0 of the drive current and the bias current I1 are connected to the constant current Idc provided by the constant current module 14 through the current confluence point Q, the drive current I0 through the source follower module 11 decreases, the follower node is charged more, and the follower signal vramp_out output by the drive branch of the source follower module 11 will jitter upwards, thereby offsetting the effect caused by the jitter of the power supply voltage VDD. Similarly, when the power supply voltage VDD jitters downward, the drive current I0 through the source follower module 11 increases, the follower node is discharged more, and the follower signal vramp_out will also jitter downward, thus realizing that the follower signal vramp_out follows the fluctuation of the power supply voltage VDD, thereby offsetting the effect caused by the jitter of the power supply voltage VDD.

[0052] Optionally, the sampling compensation module 13 further includes a first switch S0, the first end of which is connected to the control terminal of the second capacitor C2, and the second end of which is connected to the first sampling signal Vbiasn.

[0053] In electrical engineering, a switching device is an electrical component that can disconnect or connect a conductive path in a circuit, interrupting the current in that path. For example, when the first switching device S0 is on, the first sampling signal Vbiasn can be connected to the control terminal of the first transistor M1. When the first switching device S0 is off, the first sampling signal Vbiasn stops being connected to the control terminal of the first transistor M1.

[0054] Optionally, the source follower module 11 includes a third transistor M3, the input terminal of the third transistor M3 is connected to the reference ramp voltage vramp in, the first terminal of the third transistor M3 is connected to the power supply voltage VDD, and the second terminal of the third transistor M3 outputs the follower signal vramp out.

[0055] Source followers have very low output impedance, making them particularly suitable for driving heavy loads (low-impedance loads). Simultaneously, transistors generally have high power and excellent thermal breakdown resistance. Exemplarily, during comparator quantization, the ramp voltage of the follower signal `vramp out` begins to decrease, the counter starts counting, and when the ramp voltage and pixel voltage overlap, the comparator outputs 0, the counting stops, and the quantized value of the reset signal is obtained. After the reset signal quantization ends, the ramp voltage can return to the reference state. In another embodiment, the counter may perform the counting operation during the rise of the ramp voltage of the follower signal `vramp out`. This application does not limit this to a specific embodiment.

[0056] Optionally, the current mirror module 12 includes a fourth transistor M4 and a fifth transistor M5.

[0057] The control terminal of the fourth transistor M4 is connected to the control terminal of the fifth transistor M5, and the control terminal of the fourth transistor M4, the control terminal of the fifth transistor M5, and the first terminal of the fifth transistor M5 are all connected to the current confluence point Q. The first terminal of the fourth transistor M4 is connected to the output terminal of the source follower module 11, and the second terminal of the fourth transistor M4 and the second terminal of the fifth transistor M5 are both grounded.

[0058] For example, by establishing a current mirror, the current flowing through the fourth transistor M4 and the fifth transistor M5 on both sides of the current mirror remains the same, so that the current on both sides of the current mirror can change synchronously and in the same direction, thereby responding to the compensation signal of the sampling compensation module 13.

[0059] Optionally, the current mirror module 12 further includes a sixth transistor M6, which is connected in series between the source follower module 11 and the current mirror module 12, and the control terminal of the sixth transistor M6 is connected to a first preset voltage Vcasc1.

[0060] For example, the common-source cascode structure is a structure in CMOS analog integrated circuits, referring to the connection of the source terminals of two transistors to the depletion layer. CMOS stands for Complementary Metal-Oxide-Semiconductor, a material widely used in integrated circuit chip manufacturing. The depletion layer is a high-resistivity region in a PN junction where the number of charge carriers is very low due to the combined effects of drift motion and diffusion. The depletion layer forms in the PN junction, and electrons and holes are very scarce. Because of the low number of charge carriers in the depletion layer, its characteristics are similar to a capacitor, and this capacitance is also called junction capacitance. For example, the sixth transistor M6 is common-source, with its gate terminal serving as the input, and the fourth transistor M4 is common-gate, with its depletion layer terminal serving as the output.

[0061] Optionally, the constant current module 14 includes a seventh transistor M7, the input terminal of the seventh transistor M7 is connected to the second sampling signal Vbiasp, the first terminal of the seventh transistor M7 is connected to the current convergence point Q to converge the mirrored drive current I0 and the bias current I1, and the constant current signal Idc is generated based on the second sampling signal Vbiasp, and the second terminal of the seventh transistor M7 is connected to the power supply voltage VDD.

[0062] A constant current source is a type of power supply whose output current remains constant. Optionally, the constant current source can adaptively adjust its output voltage to maintain a constant current based on a negative feedback circuit. For example, the change in the constant current Idc can be fed back to a second sampling signal Vbiasp, causing the second sampling signal Vbiasp to control the output voltage and suppress changes in the constant current Idc. Since the constant current Idc is the sum of the mirrored drive current I0 and the bias current I1, when the constant current Idc remains constant, the drive current I0 and the bias current I1 exhibit an inverse linear relationship. When the bias current I1 increases, the drive current I0 on both sides of the current mirror decreases; when the bias current I1 decreases, the drive current I0 on both sides of the current mirror increases.

[0063] Optionally, the constant current module 14 further includes a second switch S0, the first end of which is connected to the control terminal of the seventh transistor M7, and the second end of which is connected to the second sampling signal Vbiasp.

[0064] In electrical engineering, a switching device is an electrical component that can disconnect or connect a conductive path in a circuit, interrupting the current in that path. For example, when the second switch S0 is on, the second sampling signal Vbiasp can be connected to the control terminal of the seventh transistor M7. When the second switch S0 is off, the second sampling signal Vbiasp is no longer connected to the control terminal of the seventh transistor M7.

[0065] Optionally, the constant current module includes an eighth transistor M8, which is connected in series with the seventh transistor M7 to form a common gate common source circuit, and the control terminal of the eighth transistor M8 is connected to a second preset voltage Vcasc2.

[0066] Optionally, the second preset voltage is an additional applied bias voltage. For example, the cascode structure is a structure in CMOS analog integrated circuits, referring to two transistors whose source terminals are connected to the depletion layer. CMOS stands for Complementary Metal-Oxide-Semiconductor, a material widely used in integrated circuit chip manufacturing. The depletion layer is a high-resistivity region in a PN junction where the number of charge carriers is very low due to the combined effects of drift motion and diffusion. The depletion layer forms in the PN junction, and electrons and holes are very scarce. Because of the low number of charge carriers in the depletion layer, its characteristics are similar to a capacitor, and this capacitance is also called junction capacitance. For example, the seventh transistor M7 is cascode, with its gate terminal serving as the input, and the eighth transistor M8 is common-gate, with its depletion layer terminal serving as the output.

[0067] Second Embodiment

[0068] Figure 3 This is a schematic diagram of a ramp signal compensation circuit according to an embodiment of this application. Figure 2 .

[0069] Optionally, based on the first embodiment, the sampling compensation module 13 includes a plurality of first capacitor units, which are connected in parallel, and the capacitances of the first capacitors C11, C12, C13, C14... of the plurality of capacitor units are in a multiple relationship.

[0070] Please also refer to Figure 2 and Figure 3 The coupling coefficient, i.e., the proportion by which the node changes with the power supply voltage, is determined by the ratio of the coupling capacitance C between the gate of the first transistor M1 and the power supply voltage VDD to the total capacitance (C1+C2) of that node. For example... Figure 3As shown, by adding several coupling capacitor positions to the gate of the first transistor M1, such as switch Sc1 controlling the connection capacitor C11, switch Sc2 controlling the connection capacitor C12, switch Sc3 controlling the connection capacitor C13, switch Sc4 controlling the connection capacitor C14, ..., where C11, C12, C13, C14... increase in a 2x relationship, and the switches Sc1, Sc2, Sc3, Sc4... are controlled by binary encoding. By controlling different positions to connect coupling capacitors of different sizes to the power supply VDD, the coupling coefficient can be adjusted. This can cover the uncertainty of the parasitic coupling between the bitline and the power supply voltage VDD.

[0071] Third Embodiment

[0072] This application also provides an image sensor. Figure 4 This is a block diagram of an image sensor according to an embodiment of this application.

[0073] like Figure 4 As shown, the image sensor includes a ramp voltage generator (rampdac), a column comparator, and a counter memory. The image sensor also includes a ramp signal compensation circuit (ramp buffer) as described above.

[0074] The ramp voltage generator rampdac is connected to the ramp signal compensation circuit ramp buffer to provide a reference ramp voltage;

[0075] The ramp signal compensation circuit, or ramp buffer, is connected to the first input terminal of the column comparator to output a follower signal of the reference ramp voltage.

[0076] The second input terminal of the column comparator is connected to the photosensitive voltage of the photosensitive pixel through the photosensitive column line bitline, and the output terminal of the column comparator is connected to the countermemory to output the comparison result.

[0077] The counter memory is used to count and store the comparison results in order to calculate and output the digital signal of the photosensitive pixel.

[0078] As described above, the ramp signal compensation circuit and image sensor provided in this application replicate the mirror current of the driving current to the current confluence point through the current mirror module. The constant current module is connected to the current mirror module and the sampling compensation module respectively to provide a constant current, so that the driving current of the source follower module and the bias current of the sampling compensation module are linearly correlated based on the constant current. On the basis of enhancing the driving capability of the reference ramp voltage signal, the same power supply jitter is introduced to the input of the comparator, reducing the influence of the power supply voltage on the quantization result and realizing the stable output of the column comparator.

[0079] The embodiments of the image sensor provided in this application may include all the technical features of any of the above-described circuit embodiments. The extended and explained contents of the specification are basically the same as the embodiments of the above methods, and will not be repeated here.

[0080] It is understood that the above scenarios are merely examples and do not constitute a limitation on the application scenarios of the technical solutions provided in the embodiments of this application. The technical solutions of this application can also be applied to other scenarios. For example, as those skilled in the art will know, with the evolution of system architecture and the emergence of new business scenarios, the technical solutions provided in the embodiments of this application are also applicable to similar technical problems.

[0081] The sequence numbers of the embodiments in this application are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.

[0082] The steps in the method of this application embodiment can be adjusted, combined, or deleted according to actual needs.

[0083] The units in the device of this application embodiment can be merged, divided, and deleted according to actual needs.

[0084] In this application, the same or similar terms, concepts, technical solutions and / or application scenario descriptions are generally described in detail only when they appear for the first time. When they appear again, they are generally not repeated for the sake of brevity. When understanding the technical solutions and other contents of this application, the same or similar terms, concepts, technical solutions and / or application scenario descriptions that are not described in detail later can be referred to their previous relevant detailed descriptions.

[0085] In this application, the descriptions of the various embodiments have different focuses. For parts that are not described in detail or recorded in a certain embodiment, please refer to the relevant descriptions of other embodiments.

[0086] The technical features of the present application can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of the present application.

[0087] The above are merely preferred embodiments of this application and do not limit the patent scope of this application. Any equivalent structural or procedural transformations made using the content of this application's specification and drawings, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of this application.

Claims

1. A ramp signal compensation circuit, characterized in that, include: The source follower module is driven by the driving current generated by the power supply voltage. The input terminal of the source follower module is connected to a reference ramp voltage, and the output terminal of the source follower module outputs a following signal of the reference ramp voltage. A current mirror module, wherein a first side of the current mirror module is connected to the output terminal of the source follower module, and a second side of the current mirror module is connected to a current confluence point to replicate the mirror current of the driving current to the current confluence point; A sampling compensation module, wherein the first side of the sampling compensation module is grounded and the second side of the sampling compensation module is connected to the current confluence point, for sampling the power supply voltage to obtain a sampling signal, and outputting a bias current corresponding to the sampling signal to the current confluence point; The constant current module is connected to the current mirror module and the sampling compensation module respectively, and is used to provide a constant current signal. It also merges the drive current and the bias current through the current confluence point, so that the drive current and the bias current are linearly correlated based on the constant current signal.

2. The ramp signal compensation circuit as described in claim 1, characterized in that, The sampling compensation module includes a first transistor and a first capacitor unit. The first capacitor unit includes a first capacitor and a capacitor switch. The first terminal of the first capacitor is connected in series with the capacitor switch and connected to the power supply voltage through the capacitor switch. The second terminal of the first capacitor is connected to the control terminal of the first transistor. The first terminal of the first transistor is grounded. Under the drive of the driving current generated by the power supply voltage, the control terminal of the first transistor receives a first sampling signal. The second terminal of the first transistor is connected to the current confluence point and outputs a bias current corresponding to the sampling signal to the constant current module.

3. The ramp signal compensation circuit as described in claim 2, characterized in that, The sampling compensation module further includes a second capacitor unit, the first end of which is connected to the control terminal of the first transistor, and the second end of which is grounded.

4. The ramp signal compensation circuit as described in claim 3, characterized in that, The sampling compensation module further includes a first switch, the first end of which is connected to the control terminal of the first transistor, and the second end of which is connected to the first sampling signal.

5. The ramp signal compensation circuit as described in claim 2, characterized in that, The sampling compensation module includes multiple first capacitor units, which are connected in parallel, and the capacitance of the first capacitors of the multiple first capacitor units is in a multiple relationship.

6. The ramp signal compensation circuit as described in claim 1, characterized in that, The source follower module includes a third transistor, the control terminal of which is connected to the reference ramp voltage, the first terminal of which is connected to the power supply voltage, and the second terminal of which outputs the follower signal.

7. The ramp signal compensation circuit as described in claim 1, characterized in that, The current mirror module includes a fourth transistor and a fifth transistor; The control terminal of the fourth transistor is connected to the control terminal of the fifth transistor, and the control terminal of the fourth transistor, the control terminal of the fifth transistor, and the first terminal of the fifth transistor are all connected to the current confluence point. The first terminal of the fourth transistor is connected to the output terminal of the source follower module, and the second terminal of the fourth transistor and the second terminal of the fifth transistor are both grounded.

8. The ramp signal compensation circuit as described in claim 1, characterized in that, The current mirror module further includes a sixth transistor, which is connected in series between the source follower module and the current mirror module, and the control terminal of the sixth transistor is connected to a first preset voltage.

9. The ramp signal compensation circuit as described in any one of claims 1-8, characterized in that, The constant current module includes a seventh transistor. The control terminal of the seventh transistor is connected to a second sampling signal. The first terminal of the seventh transistor is connected to the current convergence point to converge the drive current and the bias current, and generates the constant current signal based on the second sampling signal. The second terminal of the seventh transistor is connected to the power supply voltage.

10. The ramp signal compensation circuit as described in claim 9, characterized in that, The constant current module further includes a second switching element, the first end of which is connected to the control terminal of the seventh transistor, and the second end of which is connected to the second sampling signal.

11. The ramp signal compensation circuit as described in claim 9, characterized in that, The constant current module includes an eighth transistor, which is connected in series with the seventh transistor to form a common gate common source circuit, and the control terminal of the eighth transistor is connected to a second preset voltage.

12. An image sensor, characterized in that, The image sensor includes a ramp voltage generator, a comparator, and a counting memory, and further includes a ramp signal compensation circuit as described in any one of claims 1-11. The ramp voltage generator is connected to the ramp signal compensation circuit to provide a reference ramp voltage; The ramp signal compensation circuit is connected to the first input terminal of the comparator to output a follower signal of the reference ramp voltage; The second input terminal of the comparator is connected to the photosensitive voltage of the photosensitive pixel, and the output terminal of the comparator is connected to the counting memory to output the comparison result; The counting memory is used to count and store the comparison results to calculate the photosensitive result of the photosensitive pixel.

Images