Dual power bus transceiver with low dropout linear regulator, voltage conversion circuit, and display system

Abstract

The application discloses a dual power bus transceiver with low dropout linear voltage regulator, a voltage conversion circuit and a display system. The dual power bus transceiver with low dropout linear voltage regulator comprises a first power pin for connecting a first power supply, a second power pin for connecting a second power supply, at least one first pin electrically connected to the first power supply and leading to an input port, at least one second pin electrically connected to the second power supply and leading to an output port, a third pin, a voltage conversion module comprising at least one voltage conversion unit, an input end of the voltage conversion unit being connected to the first power supply, an output end of the voltage conversion unit being connected to the second power supply, and a low dropout linear voltage regulator connected to the third pin.

Description

Technical Field

[0001] This utility model relates to the field of conversion circuit technology, specifically to a dual-power bus transceiver, and more particularly to a dual-power bus transceiver with a low-dropout linear regulator, a voltage conversion circuit, and a display system. Background Technology

[0002] Figure 1 This is a schematic diagram of a dual-power bus transceiver in the prior art, such as... Figure 1 As shown, the 9-bit dual-power bus transceiver uses two independent voltage sources to determine the input and output voltages. Terminal A (input: A0-A8) is connected to voltage source VCCA, and terminal B (output: B0-B8) is connected to voltage source VCCB. The voltage level is changed through an internal voltage converter. Utility Model Content

[0003] The purpose of this invention is to provide a dual-power bus transceiver with a low-dropout linear regulator, which can solve one or more defects of the prior art.

[0004] To achieve the above objectives, this invention provides a dual-power bus transceiver with a low-dropout linear regulator, comprising: a first power supply pin for connecting to a first power supply; a second power supply pin for connecting to a second power supply; at least one first pin electrically connected to the first power supply and respectively leading out an input port; at least one second pin electrically connected to the second power supply and respectively leading out an output port; a third pin; a voltage conversion module comprising at least one voltage conversion unit, the input terminal of the voltage conversion unit being connected to the first power supply and the output terminal of the voltage conversion unit being connected to the second power supply; and a low-dropout linear regulator connected to the third pin.

[0005] According to one embodiment of this invention, the dual-supply bus transceiver with a low-dropout linear regulator further includes: two fourth pins; and a slew rate control circuit whose input is connected to the two fourth pins and whose output is connected to a second power supply.

[0006] According to one embodiment of this invention, the dual-supply bus transceiver with a low-dropout linear regulator further includes: a watchdog circuit, the input of which is connected to a first pin, and the output of which is connected to each voltage conversion unit.

[0007] According to one embodiment of this invention, a low-dropout linear regulator includes: a switching transistor; and an error amplifier that compares a reference voltage with a feedback value of the voltage at a third pin to generate a drive signal to drive the switching transistor to operate.

[0008] According to one embodiment of this invention, the dual-supply bus transceiver with a low-dropout linear regulator also includes a bandgap reference circuit connected to an error amplifier for providing a reference voltage.

[0009] According to one embodiment of this case, the voltage range of the first power supply is 1.65V-5.5V, and the voltage range of the second power supply is 1.65V-5.5V.

[0010] According to one embodiment of this invention, the package form of the dual-supply bus transceiver with a low dropout linear regulator includes SSOP24, QFN24 or WLCSP.

[0011] According to one embodiment of this invention, the dual-supply bus transceiver with a low-dropout linear regulator also includes a ground pin for grounding.

[0012] This application also provides a voltage conversion circuit, comprising: a dual-power bus transceiver with a low-dropout linear regulator; an FPGA chip, at least one pin of which is connected to at least one first pin of the dual-power bus transceiver; and a FlashChip chip, at least one pin of which is connected to at least one second pin of the dual-power bus transceiver.

[0013] According to one embodiment of this case, the third pin of the dual-power bus transceiver is connected to the second power supply and a pin of the Flash Chip chip, and the third pin is also connected to ground through the first capacitor.

[0014] According to one embodiment of this case, the two fourth pins of the dual-power bus transceiver are connected to the first power supply, one of the two fourth pins is connected to ground through a first resistor and a second capacitor; the other of the two fourth pins is connected to ground through a second resistor and a second capacitor.

[0015] This application also provides a display system comprising: a display module including at least one display screen; a dual-power bus transceiver with a low-dropout linear regulator; a Flash Chip electrically connected to the third pin of the dual-power bus transceiver; a horizontal output control integrated circuit module, the input of which is connected to the dual-power bus transceiver and the output of which is connected to at least one display screen; and at least one constant current integrated circuit module, the input of which is connected to the dual-power bus transceiver and the output of which is connected to one display screen.

[0016] The dual-power bus transceiver provided in this case combines high drive capability, dynamic stability, and low power consumption mode, exhibiting superior performance and reliability. Attached Figure Description

[0017] To more clearly illustrate the technical solution implemented in this case, the accompanying drawings used in the embodiments will be briefly introduced below.

[0018] Figure 1 This is a schematic diagram of a dual-power bus transceiver in the prior art;

[0019] Figure 2 This is a schematic diagram of the package of the dual-power bus transceiver in the first embodiment;

[0020] Figure 3 This is a schematic diagram of the internal circuit structure of the dual-power bus transceiver in the first embodiment.

[0021] Figure 4 This is a schematic diagram showing the connection of a low-dropout linear regulator in a dual-power bus transceiver.

[0022] Figure 5 This is a schematic diagram showing the connection of the conversion rate control circuit in a dual-power bus transceiver.

[0023] Figure 6 This is a schematic diagram of the watchdog circuit connection in a dual-power bus transceiver.

[0024] Figure 7 This is a schematic diagram of the package of the dual-power bus transceiver in the second embodiment;

[0025] Figure 8 This is a schematic diagram of the package of the dual-power bus transceiver according to the third embodiment.

[0026] Figure 9 This is a schematic diagram of a voltage conversion circuit.

[0027] Figure 10 This is a schematic diagram of the structure of a display screen device.

[0028] Additional aspects and advantages of this case will be set forth in part in the description which follows, and in part will become apparent from the description or may be learned through practice of this case. Detailed Implementation

[0029] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this work will be thorough and complete, and will fully and completely convey the concept of the exemplary embodiments to those skilled in the art.

[0030] In describing the elements / components / etc. described and / or illustrated herein, the terms “a,” “an,” “the,” “the,” and “at least one” are used to indicate the presence of one or more elements / components / etc. The terms “comprising,” “including,” and “having” are used to indicate an open-ended inclusion and mean that additional elements / components / etc. may exist in addition to those listed. Furthermore, the terms “first,” “second,” etc., in the claims are used only as illustrative marks and are not intended to limit the numerical scope of the subject matter. The same numbers in the drawings represent the same or similar components. On the other hand, well-known components and steps are not described in the embodiments to avoid unnecessarily limiting this disclosure. Furthermore, for the sake of simplicity, some known conventional structures and elements are illustrated in the drawings in a simple schematic manner.

[0031] Figure 2 This is a schematic diagram of the package of the dual-power bus transceiver provided in the first embodiment of this case. Figure 3 This is a schematic diagram of the internal circuit structure of the dual-power bus transceiver provided in the first embodiment of this case, combined with... Figure 2 and Figure 3 The dual-supply bus transceiver includes pins 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, and 24. Pin 1 is the first power supply pin, used to connect to the first power supply VCCA. Pins 2 and 3 are the second power supply pins, used to connect to the second power supply VCCB. Pins 2, 3, 4, 5, 6, 7, 8, 9, and 10 are the first pins, corresponding to pins A8, A0, A1, A2, A3, A4, A5, and A6, respectively. A7 is connected to an input port (port A). Each first pin is also electrically connected to the first power supply VCCA. Pins 14, 15, 16, 17, 18, 19, 20, 21, and 22 are second pins, corresponding to pins B7, B6, B5, B4, B3, B2, B1, B0, and B8 respectively, and each is connected to an output port (port B). Each second pin is also electrically connected to the second power supply VCCB. Pin 24 is the third pin, corresponding to pin V3P3. Pin 13 is connected to a ground terminal (GND) for circuit grounding.

[0032] like Figure 3 As shown, the dual-power bus transceiver internally includes a voltage conversion module, a low-dropout linear regulator C2, a conversion rate control circuit C3, and a watchdog circuit C4. The voltage conversion module includes multiple voltage conversion units C1. The input terminal of each voltage conversion unit C1 is connected to the first power supply VCCA, and the output terminal of each voltage conversion unit C1 is connected to the second power supply VCCB.

[0033] The low-dropout linear regulator C2 is connected to the third pin V3P3 of the dual-power bus transceiver. The third pin V3P3 provides a voltage (typically 3.3V) to the low-dropout linear regulator C2. The low-dropout linear regulator C2 ensures the stability of the output voltage by adjusting the difference between the first power supply voltage VCCA and the voltage on the third pin V3P3. Figure 4 This is a schematic diagram of the connection of the low dropout linear regulator C2 in the dual-supply bus transceiver. Specifically, the low dropout linear regulator C2 includes a switching transistor C21 and an error amplifier C22. The error amplifier C22 obtains the feedback value of the voltage at the third pin V3P3 and a reference voltage, compares the feedback value with the reference voltage, and generates a drive signal to drive the switching transistor C22 to operate, so that the dual-supply bus transceiver has a stable output voltage.

[0034] Combination Figure 3 and Figure 4 The dual-supply bus transceiver also includes a bandgap reference circuit C5, which is connected to the input of error amplifier C22 and is used to provide a reference voltage to error amplifier C22.

[0035] Figure 5 This is a schematic diagram showing the connection of the conversion rate control circuit C3 in a dual-power bus transceiver, as shown below. Figure 5 As shown, pins 11 and 12 of the dual-supply bus transceiver are the fourth pins SL0 and SL1, respectively. The input of the conversion rate control circuit C3 is connected to the fourth pins SL0 and SL1, and its output is connected to the second power supply VCCB. In this embodiment, the user determines the output drive current capability and the required voltage conversion rate by selecting the voltage input to the fourth pins SL0 and SL1. Four different voltage conversion rates can be achieved using the two pins SL0 and SL1. Specifically, different conversion rate modes are selected by combining high and low levels of the two pins SL0 and SL1. For example, when both pins SL0 and SL1 are connected to a high potential, the dual-supply bus transceiver has the fastest conversion rate; when both pins SL0 and SL1 are connected to a low potential, the dual-supply bus transceiver has the slowest conversion rate, and so on. (Continue referring to...) Figure 5 A first switch K1 is also connected between the conversion rate control circuit C3 and the second power supply VCCB. The conversion rate control circuit C3 also controls the conversion rate of the dual power supply bus transceiver by controlling the conduction degree of the first switch K1. For example, when SL0 and SL1 are connected to a low potential, the conduction degree of K1 is minimal and the conversion rate of the dual power supply bus transceiver is the slowest. When SL0 and SL1 are connected to a high potential, the conduction degree of K1 is maximum and the conversion rate of the dual power supply bus transceiver is the fastest.

[0036] Figure 6 This is a schematic diagram showing the connection of the watchdog circuit C4 in a dual-supply bus transceiver, as shown below. Figure 6As shown, the input of the watchdog circuit C4 is connected to the first pin A0, and its output is connected to each voltage conversion unit C1. In this embodiment, the watchdog circuit C4 determines whether the dual-power bus transceiver should continuously transmit signals to port B by monitoring the state of the input signal at the first pin A0. If the first pin A0 continuously receives a low or high potential from the outside for a period of time (approximately 100ms), the internal watchdog circuit C4 determines that it is currently in sleep mode and forces all port B outputs to a low potential. However, once the signal input to the first pin A0 restarts switching, port B will immediately reset. Figure 6 As shown, a second switch K2 is connected between the watchdog circuit C4 and the voltage conversion unit C1. The watchdog circuit C4 monitors the operating status of the dual-power bus transceiver. When the duration of the signal input from the outside to the first pin A0 does not exceed a time threshold, the second switch K2 remains closed. When the duration of the signal input from the outside to the first pin A0 exceeds the time threshold, the watchdog circuit C4 outputs a control signal to open the second switch K2. The monitoring function of the watchdog circuit C4 can ensure the stable operation of the dual-power bus transceiver.

[0037] In the first embodiment, the dual-power bus transceiver is packaged in SSOP24. In other embodiments, the dual-power bus transceiver may also include other package types. Figure 7 This is a schematic diagram of the package of the dual-power bus transceiver in the second embodiment. The package of the dual-power bus transceiver is QFN24. Figure 8 This is a schematic diagram of the package of the dual-power bus transceiver according to the third embodiment. The package of the dual-power bus transceiver is WLCSP. In other embodiments, the dual-power bus transceiver may have other package forms, and this invention is not limited to these. The internal circuit structure of the dual-power bus transceiver in the second and third embodiments is the same as that of the dual-power bus transceiver in the first embodiment, and will not be described in detail here.

[0038] In the embodiments of this application, the voltage range of the first power supply VCCA is 1.65V-5.5V, and the voltage range of the second power supply VCCB is 1.65V-5.5V.

[0039] The first to third embodiments of this invention illustrate a 9-channel dual-supply bus transceiver with a low-dropout linear regulator. In other embodiments, the dual-supply bus transceiver may include other numbers of first and second pins to form dual-supply bus transceivers with other numbers of channels, and this invention is not limited thereto. The dual-supply bus transceiver of this invention offers superior performance and reliability, integrating a 100mA low-dropout linear regulator (LDO) that provides stable power even at extremely low input-output voltage differences. It also allows for different slew rate modes via two control pins, SL0 and SL1, and a slew rate control circuit. When VCCA = 4.5V, the dual-supply bus transceiver has a 32mA high-current output drive capability, capable of driving high-load peripherals. The V3P3 pin can be fitted with any 10μF ceramic capacitor. Furthermore, the dual-supply bus transceiver automatically enters a power-saving mode during a 150ms period of no-signal switching. The dual-supply bus transceiver also exhibits excellent load / power transient response characteristics and fast startup time.

[0040] This application also provides a voltage conversion circuit comprising a dual-power bus transceiver with a low-dropout linear regulator, an FPGA chip, and a Flash Chip chip, wherein at least one pin of the FPGA chip is connected to at least one first pin of the dual-power bus transceiver, and at least one pin of the Flash Chip chip is connected to at least one second pin of the dual-power bus transceiver.

[0041] Figure 9 This is a schematic diagram of one embodiment of a voltage conversion circuit, as shown below. Figure 9 As shown, the voltage conversion circuit includes a dual-supply bus transceiver with a low-dropout linear regulator, an FPGA chip, and a Flash Chip chip. The four pins of the FPGA chip are connected to the four first pins (A0, A1, A2, A3) of the dual-supply bus transceiver, and the four pins of the Flash Chip chip are connected to the four second pins (B0, B1, B2, B3) of the dual-supply bus transceiver. The third pin V3P3 of the dual-supply bus transceiver is connected to the second power supply VCCB and the V3P3 pin of the Flash Chip chip, supplying power to the Flash Chip chip. The third pin V3P3 of the dual-supply bus transceiver is also connected to ground (GND) through a first capacitor M to stabilize the internal control loop. The two fourth pins SL0 and SL1 of the dual-supply bus transceiver are connected to the first power supply VCCA. The fourth pin SL0 is connected to ground (GND) through a resistor R1 and a second capacitor N, and the fourth pin SL1 is connected to ground (GND) through a resistor R2 and a second capacitor N.

[0042] In voltage conversion circuits, dual-supply bus transceivers with low-dropout linear regulators can be used for level conversion applications, serving as interfaces for devices or systems operating at different interface voltages. When the dual-supply bus transceiver powers a Flash Chip at 3.3V, the maximum output current can reach 24mA.

[0043] This application also provides a display system comprising a display module, a dual-power bus transceiver, a Flash Chip, a horizontal output control integrated circuit module, and at least one constant current integrated circuit module. The display module includes at least one display screen. The Flash Chip is electrically connected to the third pin of the dual-power bus transceiver. The input terminal of the horizontal output control integrated circuit module is connected to the dual-power bus transceiver, and the output terminal is connected to at least one display screen. The input terminal of each constant current integrated circuit module is connected to the dual-power bus transceiver, and the output terminal of each constant current integrated circuit module is connected to a display screen.

[0044] Figure 10 A schematic diagram of the structure of one embodiment of the system is shown, as follows: Figure 10 As shown, the display system includes a display module, a dual-power bus transceiver as described above, a Flash Chip, a horizontal output control integrated circuit module C7, and multiple constant current integrated circuit modules C6. The display module includes multiple displays S1. The VCC pin of the Flash Chip is connected to the third pin V3P3 of the dual-power bus transceiver. The input terminal of the horizontal output control integrated circuit module C7 is connected to the output pins (DIN, BK, LCK) of the dual-power bus transceiver, and the output terminal of the horizontal output control integrated circuit module C7 is connected to the multiple displays S1. The multiple constant current integrated circuit modules C6 are connected in series, as shown below. Figure 10 As shown, the output terminal DAO of each constant current integrated circuit module C6 is connected to the input terminal DAI of the next constant current integrated circuit module C6, and the series-connected constant current integrated circuit modules C6 are also connected to one output pin (DAI) of the dual power supply bus transceiver. The input terminal of each constant current integrated circuit module C6 is connected to the output pin (DCK, GCK, LAI) of the dual power supply bus transceiver, and the output terminal of each constant current integrated circuit module C6 is connected to a display screen S1.

[0045] In display systems, dual-supply bus transceivers, besides their use for voltage conversion, can also be used to change the input and output voltage levels. This allows for low-to-high conversion of the controller input voltage signal in common-anode displays, for example, boosting a 3.3V controller input to a 5V output signal for the display to supply the constant current IC module C6 and the horizontal output control IC module C7. It can also be used for low-to-high conversion of the input voltage signal in common-cathode displays, for example, converting a 3.8V input to a 2.8V output to supply the constant current for the red LED. Furthermore, the 3.3V voltage source commonly used in flash chips in display systems can also be directly supplied via the V3P3 pin of the dual-supply bus transceiver, reducing the need for LDOs on the display.

[0046] Although embodiments of this invention have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of this invention, the scope of protection of which is determined by the appended claims.

Claims

1. A dual-power bus transceiver with a low-dropout linear regulator, characterized in that, Include: The first power supply pin is used to connect to the first power supply; The second power supply pin is used to connect to the second power supply. At least one first pin is electrically connected to the first power supply, and an input port is brought out from each of them; At least one second pin is electrically connected to the second power supply, and each pin has an output port. Third pin; A voltage conversion module includes at least one voltage conversion unit, wherein the input terminal of the voltage conversion unit is connected to a first power supply, and the output terminal of the voltage conversion unit is connected to a second power supply; and The low-dropout linear regulator is connected to the third pin.

2. The dual-power bus transceiver with a low-dropout linear regulator according to claim 1, characterized in that, Also includes: Two fourth pins; and The conversion rate control circuit has its input connected to the two fourth pins and its output connected to the second power supply.

3. The dual-power bus transceiver with a low-dropout linear regulator according to claim 1, characterized in that, Also includes: The watchdog circuit has its input connected to the first pin and its output connected to each of the voltage conversion units.

4. The dual-power bus transceiver with a low-dropout linear regulator according to claim 1, characterized in that, The low-dropout linear regulator includes: Switching transistor; as well as An error amplifier compares the reference voltage with the feedback value of the voltage at the third pin to generate a drive signal to drive the switch transistor to operate.

5. The dual-power bus transceiver with a low-dropout linear regulator according to claim 4, characterized in that, Also includes: A bandgap reference circuit, connected to the error amplifier, is used to provide the reference voltage.

6. The dual-power bus transceiver with a low-dropout linear regulator according to claim 1, characterized in that, The voltage range of the first power supply is 1.65V-5.5V, and the voltage range of the second power supply is 1.65V-5.5V.

7. The dual-power bus transceiver with a low-dropout linear regulator according to claim 1, characterized in that, The dual-power bus transceiver is available in SSOP24, QFN24, or WLCSP packages.

8. The dual-power bus transceiver with a low-dropout linear regulator according to claim 1, characterized in that, It also includes a grounding pin for grounding.

9. A voltage conversion circuit, characterized in that, Include: Dual-supply bus transceiver with a low-dropout linear regulator as described in any one of claims 1-8; An FPGA chip, wherein at least one pin of the FPGA chip is connected to at least one of the first pins of the dual-power bus transceiver; A Flash Chip, wherein at least one pin of the Flash Chip is connected to at least one of the second pins of the dual-power bus transceiver.

10. The voltage conversion circuit according to claim 9, characterized in that, The third pin of the dual-power bus transceiver is connected to the second power supply and a pin of the Flash Chip chip, and the third pin is also connected to ground through the first capacitor.

11. The voltage conversion circuit according to claim 9, characterized in that, The two fourth pins of the dual-power bus transceiver are connected to the first power supply. One of the two fourth pins is connected to ground through a first resistor and a second capacitor, and the other of the two fourth pins is connected to ground through a second resistor and a second capacitor.

12. A display system, characterized in that, Include: A display module, comprising at least one display screen; Dual-supply bus transceiver with a low-dropout linear regulator as described in any one of claims 1-8; The Flash Chip is electrically connected to the third pin of the dual-power bus transceiver; A row control integrated circuit module, the input of which is connected to the dual power bus transceiver, and the output of which is connected to the at least one display screen; At least one constant current integrated circuit module, the input terminal of each constant current integrated circuit module is connected to the dual power supply bus transceiver, and the output terminal of each constant current integrated circuit module is connected to a display screen.

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