High-resolution and light-efficiency optimized display array substrate
By placing the gate signal line in the third metal layer and vertically overlapping it with the TFT gate in the dual-gate driving design, and moving the touch signal line to the first metal layer, combined with the dual-layer data line design, the problems of transmittance reduction and touch interference in dual-gate driving are solved, achieving high resolution and optimized light effect, and supporting 8K resolution driving.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- CPT TECH GRP
- Filing Date
- 2025-07-03
- Publication Date
- 2026-06-23
AI Technical Summary
In dual-gate drive designs, issues arise such as decreased panel transmittance due to increased gate count, a sharp increase in S-IC power consumption, and insufficient driving capability. Additionally, interference between the touch signal lines and the signals from the upper common electrode and pixel electrodes leads to poor touch feedback.
By optimizing the metal layer wiring, the gate signal line is placed on the third metal layer and vertically overlapped with the TFT gate, and the touch signal line is moved down to the first metal layer. Combined with the double-layer equipotential data line design, the data line impedance is reduced, and the light-shielding area and touch interference are reduced.
It effectively improves panel transmittance, reduces data line impedance, enhances IC driving capability, improves touch feedback effect, and supports driving up to 8K resolution.
Smart Images
Figure CN224399712U_ABST
Abstract
Description
[Technical Field]
[0001] This utility model relates to the field of liquid crystal display technology, and is particularly applicable to a high-resolution and light-efficiency optimized display array substrate for dual-gate driving architecture. It solves the problems of reduced light-shielding rate and touch interference by optimizing the metal layer wiring. [Background Technology]
[0002] In the field of liquid crystal displays (LCDs), lighting up an LCD panel typically requires two types of driver ICs: a source driver IC that drives the signals on the X-axis of the panel, and a gate driver IC that drives the signals on the Y-axis. Since driver ICs account for a significant portion of the raw material cost of display panels, reducing the number of ICs used is one of the important development directions for the industry to lower module costs.
[0003] Currently, gate-on-array (GOA) technology is widely used. This technology eliminates the need for a Y-axis gate driver IC by integrating the gate circuitry directly to the edge of the array glass. GOA circuit design has played a significant role in reducing the number of G-ICs used and facilitating ultra-thin bezels. However, using a source driver IC on the X-axis remains crucial, and the cost of a source IC is significantly higher than that of a gate IC (typically 3-5 times more expensive). To further reduce display panel manufacturing costs and decrease the number of source ICs used, dual-gate driving technology has become one of the main directions of technological development in the industry.
[0004] Figure 1 For the existing Dual Gate array substrate wiring design, the metal layers are arranged from bottom to top as follows: a first metal layer 1' (including TFT gate 11' and gate signal line 12'), a semiconductor layer 2', a second metal layer 3' (including TFT source 31', TFT drain 32' and data signal line 33'), and a third metal layer 4' (including touch signal line 41'). Figure 1As shown, the core of the DualGate driving architecture lies in controlling the gates of two columns of sub-pixels through a single data signal line (Source Line), achieving efficient signal multiplexing. Compared to the traditional Single-gate architecture (each column of sub-pixels has its own independent data line), the number of data lines in DualGate is reduced by 50%, significantly reducing the number of source driver chips (Source ICs). For example, for 4K (UHD) resolution TV panels, dual-gate driving technology reduces the number of Source ICs in a 65-inch 4K panel from 12 to 6. However, compared to Single-gate, while dual-gate technology halves the number of data lines, it doubles the number of gates (GOA levels). Consequently, the number of gate metal signal lines and TFT gates in the display area of the panel doubles, resulting in a larger light-shielding area (e.g., Figure 1 The position of the dashed box in the image has increased significantly, resulting in a decrease in the backlight transmittance of the panel.
[0005] While the advantage of Dual Gate driving lies in controlling the gates of two columns of sub-pixels with a single data line, reducing the number of data lines by 50% compared to the traditional Single-gate architecture (independent data lines for each column of sub-pixels), the load on each data line also doubles. Due to the number of display pixels and the resistance of the data lines, the S-IC power consumption increases sharply and the driving capability is insufficient. Currently, Dual Gate is only suitable for panel designs with resolutions of 4K and below.
[0006] Therefore, how to solve the problem of decreased panel transmittance due to the increase in the number of gates in dual-gate design, as well as the problem of sharp increase in S-IC power consumption and insufficient driving capability leading to the inability to improve resolution, are the urgent improvement directions that need to be addressed in the current driving technology.
[0007] Additionally, see Figure 1 In existing dual-gate array wiring designs, the first metal layer closest to the substrate is used as the gate signal line. However, the horizontally running gate signal line leaves no area in the middle of this first metal layer where vertically arranged touch signal lines can be placed. Therefore, the touch signal lines are generally placed in the third metal layer, which is farther from the substrate. This results in the touch signal lines being too close to the upper common electrode and pixel electrode, making them susceptible to signal interference and causing an excessively high touch signal-to-noise ratio, significantly affecting the touch feedback effect. To reduce signal interference between the touch signal lines and the upper common electrode and pixel electrode, existing technologies generally increase the thickness of the insulating layer above the third metal layer (touch signal line). This increases the manufacturing cost of the display panel. [Summary of the Invention]
[0008] The technical problem to be solved by this utility model is to provide a high-resolution and light-efficiency optimized display array substrate, which solves the problems of reduced light-shielding rate and touch interference by optimizing the metal layer wiring, and overcomes the problem of insufficient S-IC driving capability caused by the increased data line load under the dual-gate driving design of high-resolution panels.
[0009] The present invention achieves the above-mentioned technical problem as follows:
[0010] A high-resolution and light-efficiency optimized display array substrate includes: a substrate,
[0011] A first metal layer is disposed on the substrate. The first metal layer includes a TFT gate, a gate contact area, a touch signal line, and a data signal line unit. The TFT gate is connected to the corresponding gate contact area.
[0012] A gate insulating layer is disposed on the first metal layer;
[0013] A semiconductor layer is disposed on the gate insulating layer, and the position of the semiconductor layer corresponds to the position of the TFT gate.
[0014] A second metal layer is disposed on the semiconductor layer. The second metal layer includes a TFT source, a TFT drain, and a second data signal line unit. The TFT source and the TFT drain are respectively connected to the two ends of the semiconductor layer. The second data signal line unit is located above the first data signal line unit, and the first data signal line unit and the second data signal line unit are electrically connected to each other to form a data signal line.
[0015] A passivation layer is disposed on the second metal layer;
[0016] A planarization layer is disposed on the passivation layer. A gate contact hole is disposed on the planarization layer. The gate contact hole penetrates the passivation layer and the gate insulating layer in sequence downwards and exposes the upper surface of the gate contact area.
[0017] A third metal layer is disposed on the planarization layer. The third metal layer includes a gate signal line, which is electrically connected to the gate contact area through the gate contact hole, and the gate signal line overlaps with the TFT gate in the vertical direction.
[0018] Furthermore, a first data contact hole is formed on the gate insulating layer, and the first data contact hole is disposed above the corresponding data signal line unit one; the data signal line unit two is located above the corresponding data signal line unit one, and the data signal line unit one and the data signal line unit two are electrically connected through the first data contact hole to form a data signal line together.
[0019] Furthermore, a second data contact hole is also provided on the planarization layer. The second data contact hole is located above the corresponding data signal line unit one. A first branch hole and a second branch hole extend below the second data contact hole respectively. The first branch hole penetrates the passivation layer and the gate insulating layer in sequence downwards and exposes the upper surface of the data signal line unit one. The second branch hole penetrates the passivation layer downwards and exposes the upper surface of the data signal line unit two.
[0020] The third metal layer also includes a bridging wire, the two ends of which are respectively connected through the first and second pin holes of the second data contact hole to bridge the data signal line unit one and the data signal line unit two, together forming a data signal line.
[0021] Furthermore, it also includes: a fourth insulating layer disposed on top of the third metal layer, the thickness of the fourth insulating layer being...
[0022] A transparent conductive layer is disposed on the fourth insulating layer, and the transparent conductive layer includes a pixel electrode or a common electrode.
[0023] This utility model has the following advantages:
[0024] 1. Vertical Overlapping Structure: This utility model innovatively proposes to use the third metal layer as the gate signal line of the display area and to contact the TFT gate of the first metal layer through a through hole. Since the gate signal line and the gate are located in different metal layers, the gate signal line and the gate can overlap each other in the vertical direction. Compared with the existing Dual gate array wiring design, the light-shielding area affected by the gate can be reduced by 50%.
[0025] 2. Touch signal line relocation: By moving the gate signal line to the third metal layer, the first metal layer area no longer has a horizontally penetrating gate signal line. The vertically arranged touch signal line can be placed on the first metal layer, away from the upper common electrode and pixel electrode. Compared with the existing design that sets the third metal layer as the touch signal line, the problem of excessive touch signal-to-noise ratio caused by interference from the upper common electrode and pixel electrode signal can be greatly reduced, effectively improving the touch feedback effect.
[0026] Meanwhile, as one of the advantages of the touch structure of this utility model, compared with the thickness of conventional structures... To meet the requirements, the fourth insulating layer in this invention can effectively reduce its thickness to [amount missing]. It has the advantages of increasing production capacity and reducing manufacturing costs.
[0027] 3. Dual-layer data signal line drive structure design: Due to the upward shift of the gate signal line, the first metal layer area no longer has a horizontally penetrating gate signal line. A data signal line can be added to the first metal layer, which is at the same potential as the data signal line of the second metal layer, forming a dual-layer data line drive structure design. Without increasing the metal layer thickness, metal line width, metal material, etc., the data line impedance can be significantly reduced to half of the original (impedance reduction of 50%), effectively improving the IC driving capability (driving performance is improved by 1 time), and supporting up to 8K resolution driving.
[0028] In summary, this invention solves the problems of increased light-shielding area and touch interference in the Dual-Gate architecture by placing the gate signal line on the third metal layer and vertically overlapping the TFT gate, and moving the touch signal line to the first metal layer. At the same time, the optimized solution uses double-layer equipotential data lines to reduce impedance, effectively improving the IC driving capability and supporting up to 8K resolution driving. [Attached Image Description]
[0029] The present invention will be further described below with reference to the accompanying drawings and embodiments.
[0030] Figure 1 A schematic diagram of the wiring design for an existing Dual Gate array substrate (the dashed box represents the light-shielding area in the display area).
[0031] Figure 2 This is a schematic diagram of the wiring design of a high-resolution and light-efficiency optimized display array substrate according to this utility model (the dashed box represents the light-shielding area in the display area).
[0032] Figure 3 for Figure 2 A schematic diagram of the cross-section along the AA direction.
[0033] Figure 4 is a flowchart of the fabrication process of a high-resolution and light-efficiency optimized display array substrate of this utility model; where a represents steps 1-4 and b represents steps 5-8; the right figure shows the structural diagram of the TFT device and signal traces in the process flow, and the pixel electrode layer or common electrode layer and related insulating layer and contact holes are not shown; the left figure is a cross-sectional schematic diagram of the right figure along the AA direction.
[0034] Figure 5 This is one of the data contact hole structures of a high-resolution and light-efficiency optimized display array substrate according to the present invention. Figure b is a cross-sectional view of Figure a along the BB direction.
[0035] Figure 6 This is the second data contact hole structure of a high-resolution and light-efficiency optimized display array substrate according to this utility model. Figure b is a cross-sectional view of Figure a along the BB direction.
[0036] The numbers in the image are as follows:
[0037] substrate1;
[0038] First metal layer 2, TFT gate 21, gate contact area 22, touch signal line 23, data signal line unit 1 24;
[0039] Gate insulating layer 3, first data contact hole 31;
[0040] Semiconductor layer 4;
[0041] Second metal layer 5, TFT source 51, TFT drain 52, data signal line unit 2 53;
[0042] Passivation layer 6;
[0043] Planarization layer 7, gate contact hole 71, second data contact hole 72, first sub-hole 721, second sub-hole 722;
[0044] Third metal layer 8, gate signal line 81, bridge line 82.
Detailed Implementation Methods
[0045] The following will be combined with the appendix Figure 2-6 The technical solution of this utility model is clearly and completely described in detail with specific embodiments. All other embodiments obtained by those skilled in the art based on the embodiments of this utility model without creative effort are within the scope of protection of this utility model. Where specific conditions are not specified in the embodiments, conventional conditions or conditions recommended by the manufacturer shall apply. Reagents or instruments whose manufacturers are not specified are all conventional products that can be purchased commercially.
[0046] In the description of this utility model, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicating the orientation or positional relationship, are based on the orientation or positional relationship shown in the accompanying drawings and are only for the convenience of describing this utility model and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this utility model. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.
[0047] In the description of this utility model, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "joining" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in this utility model based on the specific circumstances.
[0048] See Figure 2 -4, This utility model relates to a high-resolution and light-efficiency optimized display array substrate, comprising: substrate 1,
[0049] A first metal layer 2 is disposed on the substrate 1. The first metal layer includes a TFT gate 21, a gate contact area 22, a touch signal line 23, and a data signal line unit 24. The TFT gate 21 is connected to the corresponding gate contact area 22. The touch signal line 23 is integrated into the first metal layer 2 (on the same layer as the TFT gate 21) and is far away from the upper electrode layer, which can improve the touch signal-to-noise ratio.
[0050] A gate insulating layer 3 is disposed on the first metal layer 2;
[0051] A semiconductor layer 4 is disposed on the gate insulating layer 3, and the position of the semiconductor layer 4 corresponds to the position of the TFT gate 21.
[0052] The second metal layer 5 is disposed on the semiconductor layer 4. The second metal layer 5 includes a TFT source 51, a TFT drain 52, and a second data signal line unit 53. The TFT source 51 and the TFT drain 52 are respectively connected to the two ends of the semiconductor layer 4. The second data signal line unit 53 is located above the corresponding first data signal line unit 24, and the first data signal line unit 24 and the second data signal line unit 53 are electrically connected to each other to form a data signal line 100. The first metal layer 2 is provided with a data signal line unit, which is at the same potential as the data signal line unit of the second metal layer 5 through a data contact hole, and together they form a complete data signal line, which can reduce the data line impedance by 50% and support 8K resolution driving.
[0053] A passivation layer 6 is disposed on the second metal layer 5;
[0054] A planarization layer 7 is disposed on the passivation layer 8. A gate contact hole 71 is disposed on the planarization layer 7. The gate contact hole 71 penetrates the passivation layer 6 and the gate insulating layer 3 in sequence and exposes the upper surface of the gate contact area 22. The planarization layer 7 isolates the third metal layer 8 from the lower TFT device to avoid signal interference.
[0055] A third metal layer 8 is disposed on the planarization layer 7. The third metal layer 8 includes a gate signal line 81, which is electrically connected to the gate contact region 22 through the gate contact hole 71, and the gate signal line 81 overlaps with the TFT gate 21 in the vertical direction. By moving the gate signal line 81 to the third metal layer 8 and making it vertically overlapped with the TFT gate 21 of the first metal layer 2, the light-shielding area is reduced by 50% (see [reference]). Figure 2 The position of the dashed box in the middle, and Figure 1 (The relative positions of the dashed boxes).
[0056] A fourth insulating layer 9 is disposed on top of the third metal layer 8, and the thickness of the fourth insulating layer 9 is [missing information].
[0057] A transparent conductive layer is disposed on the fourth insulating layer 9, and the transparent conductive layer includes a pixel electrode or a common electrode.
[0058] See Figure 5 In a preferred embodiment, the gate insulating layer 3 is provided with a first data contact hole 31, which is disposed above the corresponding data signal line unit 1 24; the data signal line unit 2 53 is located above the corresponding data signal line unit 1 24, and the data signal line unit 1 24 and the data signal line unit 2 53 are electrically connected through the data contact hole 31 to form a data signal line 100 together.
[0059] See Figure 6 In a preferred embodiment, the planarization layer 7 is further provided with a second data contact hole 72, which is disposed above the corresponding data signal line unit 24. A first branch hole 721 and a second branch hole 722 extend below the second data contact hole 72. The first branch hole 721 penetrates the passivation layer 6 and the gate insulating layer 3 in sequence and exposes the upper surface of the data signal line unit 24. The second branch hole 722 penetrates the passivation layer 6 and exposes the upper surface of the data signal line unit 53.
[0060] The third metal layer 8 further includes a bridging wire 82. The two ends of the bridging wire 82 are respectively connected through the first branch hole 721 and the second branch hole 722 of the second data contact hole 72 to bridge the data signal line unit 1 24 and the data signal line unit 2 53, forming a data signal line 100 together. The third metal layer 8 connects the gate contact hole 71 and the data contact hole, which can save one photomask.
[0061] As can be seen, in the optimized structural design, data signal line unit 24 and data signal line unit 53 can directly contact each other through the data contact hole of the first insulating layer, i.e., the gate insulating layer 3, or they can be bridged using the upper conductor layer. For example, the two ends of the bridging wire of the third metal layer 8 are bridged through the first branch hole 721 and the second branch hole 722 of the data contact hole, respectively, to achieve signal transmission. The advantage of bridging is that the data contact hole and the gate contact hole 71 can be fabricated simultaneously, saving one photomask.
[0062] Meanwhile, the data contact hole can be located in the display area or at the edge of the display panel.
[0063] The fabrication steps of the above-mentioned high-resolution and light-efficiency optimized display array substrate are as follows:
[0064] Step 1: A first metal layer 2 is formed on substrate 1 to prepare a TFT gate 21, a gate contact area 22, a touch signal line 23 and a data signal line unit 24. The TFT gate 21 is connected to the corresponding gate contact area 22.
[0065] Step 2: A first insulating layer is formed on the first metal layer 2, and this first insulating layer serves as the gate insulating layer 3 in the panel display area;
[0066] Step 3: Fabricate a semiconductor layer 4 on the gate insulating layer 3, and open a data contact hole on the gate insulating layer 3 at the corresponding position of the data signal line unit 24, exposing the upper surface of the data signal line unit 24.
[0067] Step 4: A second metal layer 5 is formed on the semiconductor layer 4, and a TFT source 51, a TFT drain 52, and a second data signal line unit 53, or other signal lines, are fabricated. The TFT source 51 and the TFT drain 52 are respectively connected to both ends of the semiconductor layer 4. The second data signal line unit 53 is located above the corresponding first data signal line unit 24, and the first data signal line unit 24 and the second data signal line unit 53 are electrically connected through data contact holes to form a data signal line 100.
[0068] Step 5: Form a second insulating layer, namely the passivation layer 6, on the second metal layer 5;
[0069] Step 6: A third insulating layer, namely a planarization layer 7, is formed on the passivation layer 6, and a gate contact hole 71 is provided at the corresponding position of the gate contact region 22. The gate contact hole 71 penetrates the passivation layer 6 and the gate insulating layer 3 in sequence downwards and exposes the upper surface of the gate contact region 22 of the first metal layer 2.
[0070] Step 7: A third metal layer 8 is formed on the planarization layer 7, and a gate signal line 81 is fabricated, with the gate signal line 81 overlapping the TFT gate 21 in the vertical direction; the gate signal line 81 contacts the gate contact area 22 of the first metal layer 2 through the gate contact hole 71 to realize the gate signal input and control the TFT switch.
[0071] Step 8: Form a fourth insulating layer on the third metal layer 8; the thickness of the fourth insulating layer is...
[0072] Step 9: Form a transparent conductive layer on the fourth insulating layer and prepare pixel electrodes or common electrodes.
[0073] In another embodiment, based on the transmittance improvement structure proposed by this utility model, there is still room for improvement in transmittance depending on the actual wiring differences. By adjusting the placement of the gate signal line and the contact area, unnecessary space occupancy can be reduced, and the metal light-blocking area can be further reduced to improve transmittance.
[0074] While specific embodiments of the present invention have been described above, those skilled in the art should understand that the specific embodiments described are merely illustrative and not intended to limit the scope of the present invention. Equivalent modifications and variations made by those skilled in the art in accordance with the spirit of the present invention should be covered within the scope of protection of the claims of the present invention.
Claims
1. A high-resolution and light-efficiency optimized display array substrate, characterized in that: include: substrate, A first metal layer is disposed on the substrate. The first metal layer includes a TFT gate, a gate contact area, a touch signal line, and a data signal line unit. The TFT gate is connected to the corresponding gate contact area. A gate insulating layer is disposed on the first metal layer; A semiconductor layer is disposed on the gate insulating layer, and the position of the semiconductor layer corresponds to the position of the TFT gate. A second metal layer is disposed on the semiconductor layer. The second metal layer includes a TFT source, a TFT drain, and a second data signal line unit. The TFT source and the TFT drain are respectively connected to the two ends of the semiconductor layer. The second data signal line unit is located above the first data signal line unit, and the first data signal line unit and the second data signal line unit are electrically connected to each other to form a data signal line. A passivation layer is disposed on the second metal layer; A planarization layer is disposed on the passivation layer. A gate contact hole is disposed on the planarization layer. The gate contact hole penetrates the passivation layer and the gate insulating layer in sequence downwards and exposes the upper surface of the gate contact area. A third metal layer is disposed on the planarization layer. The third metal layer includes a gate signal line, which is electrically connected to the gate contact area through the gate contact hole, and the gate signal line overlaps with the TFT gate in the vertical direction.
2. The high-resolution and light-efficiency optimized display array substrate according to claim 1, characterized in that: A first data contact hole is formed on the gate insulating layer, and the first data contact hole is disposed above the corresponding data signal line unit one; the second data signal line unit is located above the corresponding data signal line unit one, and the first data signal line unit and the second data signal line unit are electrically connected through the first data contact hole to form a data signal line together.
3. The high-resolution and light-efficiency optimized display array substrate according to claim 1, characterized in that: The planarization layer is further provided with a second data contact hole, which is disposed above the corresponding data signal line unit one. Below the second data contact hole, there are a first branch hole and a second branch hole respectively. The first branch hole penetrates the passivation layer and the gate insulating layer in sequence downwards and exposes the upper surface of the data signal line unit one. The second branch hole penetrates the passivation layer downwards and exposes the upper surface of the data signal line unit two. The third metal layer also includes a bridging wire, the two ends of which are respectively connected through the first and second pin holes of the second data contact hole to bridge the data signal line unit one and the data signal line unit two, together forming a data signal line.
4. A high-resolution and light-efficiency optimized display array substrate according to any one of claims 1-3, characterized in that: Also includes: A fourth insulating layer is disposed on top of the third metal layer, and the thickness of the fourth insulating layer is [missing information]. A transparent conductive layer is disposed on the fourth insulating layer, and the transparent conductive layer includes a pixel electrode or a common electrode.