Low-voltage high-brightness reverse polarity red LED chip and preparation method thereof

Abstract

This invention discloses a low-voltage, high-brightness, reverse-polarity red LED chip and its fabrication method. The chip includes a Si support substrate, an epitaxial stack disposed on the Si support substrate, a P-side electrode disposed on the P-type side of the epitaxial stack, and an N-side electrode disposed on the N-type side of the epitaxial stack. The P-side electrode includes multiple semi-circular electrode units, each having a straight edge and a rounded edge. The semi-circular electrode units are positioned close to the projection area of ​​the N-side electrode in the chip plane direction. The straight edges of the semi-circular electrode units form linear or planar current injection boundaries. This invention enables the current to extend laterally from the linear or planar current injection boundaries formed by the straight edges of the semi-circular electrode units towards the chip plane, reducing current spreading resistance, improving current distribution uniformity, and reducing the electrode shading area, thereby achieving low operating voltage and high light output.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor optoelectronic device technology, specifically relating to a low-voltage, high-brightness, reverse polarity red LED chip and its preparation method. Background Technology

[0002] As LED lighting technology develops towards higher power and higher luminous efficiency, especially in applications such as advertising light boxes, stage backgrounds, architectural exterior lighting, plant lighting, large-size displays, or backlight modules, higher requirements are placed on the current expansion capability, operating voltage, luminous uniformity, and light output efficiency of red LED chips.

[0003] Reverse polarity red LED chips typically use GaAs or AlGaInP material systems. These chips can improve light emission efficiency and heat dissipation through structural designs such as substrate transfer, mirrors, Si-supported substrates, and surface roughening, and are therefore widely used in high-brightness red light-emitting devices.

[0004] In existing reverse polarity red LED chips, the P-side electrodes typically employ circular or near-circular electrode arrays. While circular electrodes offer symmetrical patterns and simple fabrication processes, they still present the following drawbacks in large-size chips: First, the circular P-side electrode can easily block the light generated below its corresponding area, resulting in a reduction in the effective light-emitting area and affecting the overall light output of the chip.

[0005] Second, the circular P-side electrode is smaller in size, and its effective current injection boundary is relatively concentrated. In the planar correspondence with the N-side electrode, it is approximately represented as a local point-like current expansion initiation region, and the current needs to expand laterally from the local point-like region to the surrounding area. For rectangular or square chips, the path for current to expand to the far end, edge, or corner region is longer, which can easily lead to insufficient current density in the edge or corner region.

[0006] Third, to improve the uniformity of current spread, existing technologies typically reduce the current spread resistance by increasing the area of ​​the circular electrode or increasing the number of electrodes, but this further increases the light-blocking area; if the electrode area is reduced to improve light output, it may lead to current congestion, increased local voltage drop, and increased operating voltage. Therefore, traditional circular P-surface electrode solutions face the problem of not being able to simultaneously improve brightness and reduce voltage.

[0007] Therefore, it is necessary to provide a new reverse polarity red LED chip electrode structure that can improve the current spread correspondence between the P-side electrode and the N-side electrode, shorten the lateral current spread path in the chip plane, reduce the operating voltage, and improve light output and light emission uniformity without significantly increasing the process complexity. Summary of the Invention

[0008] The purpose of this invention is to provide a low-voltage, high-brightness, reverse-polarity red LED chip and its fabrication method. By designing the P-side electrode near the N-side electrode region as a semi-circular electrode unit, the straight edge of the semi-circular electrode unit faces or is close to the projection area of ​​the N-side electrode in the chip plane direction, and the straight edge forms a linear or planar current injection boundary. This changes the traditional current expansion method where a point-like corresponding area is mainly formed between the circular P-side electrode and the N-side electrode, thereby reducing the current expansion resistance, improving the light emission uniformity, and increasing the light output while reducing the light-shielding area.

[0009] To achieve the above objectives, the present invention provides a low-voltage, high-brightness, reverse-polarity red LED chip, comprising a Si support substrate, an epitaxial stack, a P-side electrode, and an N-side electrode.

[0010] The epitaxial stack is disposed on one side of the Si support substrate. The epitaxial stack is formed based on the GaAs material system and includes at least an n-type semiconductor layer, a light-emitting active layer, and a p-type semiconductor layer.

[0011] The P-side electrode is disposed on the side of the epitaxial stack closest to the p-type semiconductor layer. The N-side electrode is disposed on the side of the epitaxial stack away from the P-side electrode.

[0012] The P-side electrode includes multiple semi-circular electrode units, each having a straight edge and a rounded edge. The semi-circular electrode units are positioned close to the projection area of ​​the N-side electrode in the chip plane direction, and the straight edge of the semi-circular electrode unit faces or is close to the projection area. The straight edge of the semi-circular electrode unit forms a linear or planar current injection boundary, allowing the current to extend laterally from the straight edge of the semi-circular electrode unit toward the chip plane.

[0013] The "linear or planar current injection boundary" described in this application refers to a current injection initiation boundary formed by the straight edge of a semi-circular electrode unit, which has a larger length or area than the local point-like injection region of a traditional circular electrode. This straight edge is positioned towards or close to the projection area of ​​the N-side electrode in the chip plane direction to improve the planar correspondence between the P-side and N-side electrodes. The arrows in the figure illustrate the trend of current laterally expanding from this straight edge towards the chip plane, and do not indicate that the device current flows only on the chip surface; during actual device operation, the current still completes vertical conduction through the p-type semiconductor layer, the light-emitting active layer, and the n-type semiconductor layer.

[0014] In a preferred embodiment, the P-side electrode further includes multiple circular electrode units disposed between two rows of semi-circular electrode units. Thus, the region of the chip near the N-side electrode forms a linear or planar current injection boundary through the semi-circular electrode units, while the central region of the chip forms a supplementary injection region through the circular electrode units, thereby constituting a composite electrode structure combining edge line / plane corresponding expansion with central point-like supplementary injection.

[0015] In a preferred embodiment, the radius R of the semi-circular electrode unit satisfies R≥4μm; more preferably, the radius R is 5~9μm. This radius range can reduce the area of ​​the electrode blocking the light-emitting region while ensuring current injection capability.

[0016] In a preferred embodiment, a plurality of the semi-circular electrode units are arranged at intervals along the edge of the chip, and the array spacing of the electrode array containing the semi-circular electrode units is 15 to 50 μm.

[0017] In an optional embodiment, in addition to the semi-circular electrode unit 4021, a current spreading strip connected to the semi-circular electrode unit can also be provided. The current spreading strip extends along the chip plane and is used to guide the current at the boundary of the linear or planar current injection to the internal region of the chip. The width of the current spreading strip can be 3 to 6 μm; the distance of the current spreading strip from the edge of the Mesa can be 5 to 25 μm; and the spacing between two adjacent current spreading strips can be 100 to 130 μm.

[0018] In a preferred embodiment, the epitaxial stack comprises, from the N-type side to the P-type side, an n-GaAs ohmic contact layer, an n-AlGaInP roughening and extension layer, an MQW light-emitting active layer, a p-AlGaInP confinement layer, a p-AlInP transition layer, a p-AlInP / AlGaInP Bragg mirror, and a p-GaP ohmic contact semiconductor layer.

[0019] In a preferred embodiment, the P-side electrode includes an ITO transparent conductive contact layer, which is directly disposed on the side of the p-GaP ohmic contact semiconductor layer away from the p-AlInP / AlGaInP Bragg mirror, and the thickness of the ITO transparent conductive contact layer is 20-200 nm.

[0020] In a preferred embodiment, an ODR interface, a metal mirror, and a bonding layer are further disposed on the side of the P-side electrode away from the epitaxial stack. The ODR interface includes a SiO2 layer and a DBR layer composed of SiO2 / TiO2; the metal mirror includes an Ag / TiW / Ti / Pt / Au stacked structure; the bonding layer includes a first bonding metal layer formed on one side of the metal mirror and a second bonding metal layer formed on one side of the Si support substrate, the first bonding metal layer and the second bonding metal layer being connected through an Au / In bonding interface.

[0021] This invention also provides a method for preparing the above-mentioned low-voltage, high-brightness, reverse-polarity red LED chip, comprising: S1. An epitaxial stack is sequentially grown on a GaAs substrate using the MOCVD method. The epitaxial stack includes at least an n-type semiconductor layer, a light-emitting active layer, and a p-type semiconductor layer. S2. Deposit an ITO transparent conductive contact layer on the side of the epitaxial stack near the p-type semiconductor layer; S3. Perform photolithography and etching on the ITO transparent conductive contact layer to form a P-side electrode pattern including a semi-circular electrode unit, so that the semi-circular electrode unit has a straight edge and a rounded edge. S4. Etch a portion of the epitaxial layer on one side of the p-type semiconductor layer to define the p-side electrode region; S5. An ODR interface, a metal mirror and a bonding layer are formed on one side of the P-side electrode, and bonded to the Si support substrate. S6. Remove the GaAs substrate and etching stop layer, and form an N-side electrode on the side of the epitaxial stack away from the P-side electrode. S7. Perform patterned etching on the epitaxial stack to define the light-emitting area, and perform surface roughening and passivation treatment; S8. The Si support substrate is thinned and a back gold layer is formed. After cutting and splitting, a single LED chip is formed.

[0022] Compared with the prior art, the present invention has at least the following beneficial effects: First, the straight edge of the semi-circular electrode unit of the present invention forms a linear or planar current injection boundary, which transforms the traditional point-like lateral expansion method into a linear or planar lateral expansion method, shortens the average expansion path of the current in the chip plane, and reduces the current expansion resistance.

[0023] Secondly, the present invention sets a semi-circular electrode unit in the region near the N-side electrode, which can reduce the light-blocking area and release the light output area compared with the traditional circular electrode, thereby improving the chip light output.

[0024] Third, the present invention uses a combination of a semi-circular electrode unit and a central circular electrode unit to achieve more uniform current injection in both the edge and central regions of the chip, which is beneficial to improving the light emission uniformity of large-size chips.

[0025] Fourth, this invention is mainly achieved by modifying the photolithographic pattern of the P-side electrode, without significantly increasing the complexity of epitaxial growth or chip manufacturing process, and has good process compatibility. Attached Figure Description

[0026] Figure 1 This is a cross-sectional structural diagram of a low-voltage, high-brightness, reverse-polarity red LED chip provided in an embodiment of the present invention.

[0027] Figure 2 This is a schematic diagram of the planar arrangement of circular P-face electrodes in the prior art.

[0028] Figure 3 This is a schematic diagram of a planar structure in an embodiment of the present invention, which uses a combination of semi-circular P-surface electrodes and circular P-surface electrodes.

[0029] Figure 4 This is a schematic diagram showing the correspondence between the N-side electrode and the P-side electrode in the chip plane projection direction in an embodiment of the present invention.

[0030] Explanation of reference numerals in the attached figures: Epitaxial stack; 101, n-GaAs ohmic contact layer; 102, n-AlGaInP roughening and extension layer; 103, MQW light-emitting active layer; 104, p-AlGaInP confinement layer; 105, p-AlInP transition layer; 106, p-AlInP / AlGaInP Bragg mirror; 107, p-GaP ohmic contact semiconductor layer; 201, ITO transparent conductive contact layer; 202, ODR interface; 203, metal mirror; 204, bonding layer; 205, N-plane electrode; 206, passivation layer; 207, back gold layer; 300, Si support substrate; 401, N-plane electrode projection area; 402, P-plane electrode; 4021, semi-circular electrode unit; 4022, circular electrode unit; 403, linear or planar current injection boundary; 404, lateral current extension direction. Detailed Implementation

[0031] The present invention will be further described below with reference to the accompanying drawings and specific embodiments. It should be understood that the following embodiments and examples are only used to illustrate the technical solutions of the present invention, and are not intended to limit the scope of protection of the present invention.

[0032] Overview of chip structure and fabrication methods: like Figure 1As shown, the present invention provides a low-voltage, high-brightness, reverse polarity red LED chip, which includes a back gold layer 207, a Si support substrate 300, a bonding layer 204, a metal reflector 203, an ODR interface 202, a P-side electrode, an epitaxial stack 100, and an N-side electrode 205.

[0033] The epitaxial stack 100 is disposed on one side of the Si support substrate 300. The epitaxial stack 100 is formed based on the GaAs material system and includes, in the order of epitaxial growth, an n-GaAs ohmic contact layer 101, an n-AlGaInP roughening and extension layer 102, an MQW light-emitting active layer 103, a p-AlGaInP confinement layer 104, a p-AlInP transition layer 105, a p-AlInP / AlGaInP Bragg mirror 106, and a p-GaP ohmic contact semiconductor layer 107.

[0034] The p-AlInP / AlGaInP Bragg mirror 106 has a total thickness of 100–500 nm and a reflectivity greater than 99% within the target emission wavelength range. The p-GaP ohmic contact semiconductor layer 107 is C-doped with a doping concentration greater than 5 × 10⁻⁶. 19 cm -3 The thickness is 50–250 nm.

[0035] The p-side electrode is disposed on the side of the epitaxial stack 100 near the p-GaP ohmic contact semiconductor layer 107. The p-side electrode includes an ITO transparent conductive contact layer 201 and a patterned p-side electrode pattern. The ITO transparent conductive contact layer 201 cooperates with the p-GaP ohmic contact semiconductor layer 107 to achieve conductive contact and current spread on the p-type side, and its thickness is 20-200 nm.

[0036] like Figures 3 to 4 As shown, the P-side electrode 402 includes multiple semi-circular electrode units 4021 and multiple circular electrode units 4022. The semi-circular electrode units 4021 are located near the N-side electrode projection area 401, and the circular electrode units 4022 are located between two rows of semi-circular electrode units 4021.

[0037] exist Figure 3 In the illustrated embodiment, the lateral current extension direction 404 is schematically shown to extend from the straight edge of the semi-circular electrode unit 4021 toward the chip boundary; in other embodiments, the lateral extension direction can be adjusted according to the relative position of the N-side electrode projection area and the P-side electrode.

[0038] The semi-circular electrode unit 4021 has a straight edge and a rounded edge. The straight edge faces or is close to the N-plane electrode projection area 401, and the rounded edge faces the internal region of the chip.

[0039] Traditionally, a localized point-like current expansion region is formed between the circular P-side electrode and the N-side electrode, with the current spreading laterally from this point-like region to the periphery within the chip plane. In this invention, because the straight edge of the semi-circular electrode unit 4021 is positioned close to the projection area 401 of the N-side electrode, this straight edge forms a linear or planar current injection boundary 403 with a certain length or area. This allows the current to spread laterally outward from the linear or planar current injection boundary formed by the straight edge of the semi-circular electrode unit. The current expansion starting region changes from point-like to linear or planar, thereby shortening the lateral expansion path, reducing the current expansion resistance, and improving the uniformity of current distribution.

[0040] In some embodiments, the radius R of the semi-circular electrode unit 4021 is 5 to 9 μm, and the spacing between adjacent electrode units is 15 to 50 μm; preferably, the radius R of the semi-circular electrode unit 4021 is 7.5 μm, and the spacing between adjacent electrode units is 25 μm.

[0041] In an optional embodiment, the P-side electrode 402 further includes a current spreading strip connected to the semi-circular electrode unit 4021. The current spreading strip extends along the chip plane and is used to further guide the current at the linear or planar current injection boundary 403 to the internal region of the chip. The width of the current spreading strip is 3–6 μm, preferably 4 μm; the distance from the current spreading strip to the edge of the Mesa is 5–25 μm, preferably 15 μm; the spacing between two adjacent current spreading strips is 100–130 μm, preferably 110 μm.

[0042] The N-side electrode 205 is disposed on the side of the epitaxial stack 100 away from the P-side electrode 402, that is, on the side close to the n-GaAs ohmic contact layer 101. The N-side electrode 205 can be a strip-shaped electrode portion extending along the chip edge direction or an N-side electrode structure with a continuous conductive region. The N-side electrode 205 and the P-side electrode 402 cooperate with each other in the chip plane projection direction, so that the straight edge of the semi-circular electrode unit 4021 near the N-side electrode projection area 401 forms a linear or planar current injection boundary.

[0043] In some embodiments, the N-side electrode 205 adopts an Au / AuGeNi / Au stacked structure with a total thickness of 2 to 4 μm, preferably 3 μm.

[0044] The ODR interface 202 is located on the side of the P-side electrode away from the epitaxial stack 100. The ODR interface 202 includes a SiO2 layer and a DBR layer composed of SiO2 / TiO2. The SiO2 layer has a thickness of 100–600 nm, and there are 2–5 pairs of SiO2 / TiO2 layers. A metal mirror 203 is located on the side of the ODR interface 202 away from the epitaxial stack 100, and the metal mirror 203 adopts an Ag / TiW / Ti / Pt / Au stack structure. A bonding layer 204 is located between the metal mirror 203 and the Si support substrate 300, used to bond the epitaxial stack 100 to the Si support substrate 300.

[0045] The preparation method of the present invention may include the following steps: S1. Epitaxial Growth: Metal-organic chemical vapor deposition (MOCVD) was used to sequentially grow a GaAs buffer layer, a GaInP etch stop layer, an n-GaAs ohmic contact layer 101, an n-AlGaInP roughening and extension layer 102, an MQW light-emitting active layer 103, a p-AlGaInP confinement layer 104, a p-AlInP transition layer 105, a p-AlInP / AlGaInP Bragg mirror 106, and a p-GaP ohmic contact semiconductor layer 107 on a GaAs substrate. After epitaxial growth was completed, the surface of the epitaxial wafer was cleaned.

[0046] S2. Deposition of ITO transparent conductive contact layer: An ITO transparent conductive contact layer 201 is deposited on the surface of the p-GaP ohmic contact semiconductor layer 107 using electron beam evaporation. The ITO transparent conductive contact layer 201 and the p-GaP ohmic contact semiconductor layer 107 cooperate to form a P-type side conductive contact and are used for P-side current extension.

[0047] S3. Patterning of ITO transparent conductive contact layer: Photolithographic patterns of circular electrode units and semi-circular electrode units are formed by photolithography process, and then ITO etching solution is used to etch the ITO transparent conductive contact layer 201 into a P-side electrode pattern including semi-circular electrode unit 4021 and circular electrode unit 4022.

[0048] S4. Definition of P electrode region: The p-GaP ohmic contact semiconductor layer 107 and the p-AlInP / AlGaInP Bragg mirror 106 are etched using inductively coupled plasma (ICP) and etched to the p-AlInP transition layer 105. The photoresist is then removed to form the P electrode region.

[0049] S5, ODR interface and metal mirror fabrication: A SiO2 layer is deposited by PECVD and combined with electron beam evaporation to form a DBR layer composed of SiO2 / TiO2 to form an ODR interface 202; then a metal mirror 203 is formed, which adopts an Ag / TiW / Ti / Pt / Au stacked structure. After the metal mirror 203 is formed, it is annealed.

[0050] S6. Bonding: A first bonding metal layer is formed on the side of the metal mirror 203 away from the epitaxial stack 100, and a second bonding metal layer is formed on the side of the Si support substrate 300. The first bonding metal layer comprises a Ti / Pt / Au stack structure, and its surface away from the epitaxial stack 100 is the Au surface; the second bonding metal layer comprises a Ti / Pt / Au / In stack structure, and its surface away from the Si support substrate 300 is the In surface. Subsequently, the Au surface of the first bonding metal layer and the In surface of the second bonding metal layer are aligned and bonded, and Au / In bonding is performed in a bonding machine to form the bonding layer 204.

[0051] S7. Remove GaAs substrate: Use a wet solution to remove the GaAs substrate and GaInP etching stop layer in sequence, so as to expose the n-type epitaxial layer.

[0052] S8. N-plane patterning and N-plane electrode fabrication: The desired n-GaAs ohmic contact layer pattern is formed by photolithography, and the unwanted n-GaAs material on the surface is removed by chemical solution method. Subsequently, the N-plane electrode 205 is formed by electron beam evaporation and then annealed.

[0053] S9. Define the light-emitting area: A pattern corresponding to the size of the light-emitting layer is formed by photolithography, and the epitaxial layer structure is etched by ICP method to define the size of the light-emitting area.

[0054] S10. Surface roughening: The exposed AlGaInP surface is subjected to chemical wet roughening treatment to improve light extraction efficiency.

[0055] S11, Passivation layer protection: A surface passivation layer 206 is deposited using PECVD. After photolithography, the passivation layer on the surface of the light-emitting area is removed using BOE solution, leaving only the passivation protection of the sidewall area.

[0056] S12, thinning, back metallization and separation: The Si support substrate 300 is thinned, and a back gold layer 207 is formed by electron beam evaporation. Finally, the wafer is separated into individual LED chips by laser cutting and dicing.

[0057] Example 1: This embodiment prepares a low-voltage, high-brightness, reverse-polarity red LED chip as a semi-circular design sample of the present invention for subsequent performance testing.

[0058] In this embodiment, the epitaxial stack 100 includes, in the order of epitaxial growth, an n-GaAs ohmic contact layer 101, an n-AlGaInP roughening and extension layer 102, an MQW light-emitting active layer 103, a p-AlGaInP confinement layer 104, a p-AlInP transition layer 105, a p-AlInP / AlGaInP Bragg mirror 106, and a p-GaP ohmic contact semiconductor layer 107.

[0059] The p-AlInP / AlGaInP Bragg mirror 106 has a total thickness of 300 nm; the p-GaP ohmic contact semiconductor layer 107 is C-doped with a doping concentration greater than 5 × 10⁻⁶. 19 cm -3 The thickness is 110nm.

[0060] An ITO transparent conductive contact layer 201 with a thickness of 60 nm was deposited on the surface of the p-GaP ohmic contact semiconductor layer 107 using electron beam evaporation.

[0061] A photolithographic pattern of circular electrode unit 4022 and semi-circular electrode unit 4021 is formed by photolithography, wherein the radius R of the semi-circular electrode unit 4021 is 7.5 μm and the electrode unit array spacing is 25 μm. Subsequently, the ITO transparent conductive contact layer 201 is etched into a P-side electrode pattern including the semi-circular electrode unit 4021 and the circular electrode unit 4022 by immersing in ITO etching solution at 60°C for 100 s.

[0062] The semi-circular electrode unit 4021 has a straight edge and a circular edge. The straight edge is positioned toward or close to the N-plane electrode projection area 401 and forms a linear or planar current injection boundary 403. The circular electrode unit 4022 is positioned between the two rows of semi-circular electrode units 4021.

[0063] ICP etching is used to etch the p-GaP ohmic contact semiconductor layer 107 and the p-AlInP / AlGaInP Bragg mirror 106, and etching is continued until the p-AlInP transition layer 105 is cut off to form the P electrode region.

[0064] A SiO2 layer was deposited using PECVD, and a DBR layer composed of SiO2 / TiO2 was formed using electron beam evaporation to create the ODR interface 202. The DBR layer consists of three pairs of SiO2 / TiO2, with a total thickness of 510 nm.

[0065] Subsequently, a metal reflector 203 is formed, which adopts an Ag / TiW / Ti / Pt / Au stacked structure with corresponding thicknesses of 400nm / 100nm / 200nm / 200nm / 800nm. After the metal reflector 203 is formed, it is annealed at 320℃ for 20 minutes.

[0066] A first bonding metal layer is formed on the side of the metal mirror 203 away from the epitaxial stack 100, and a second bonding metal layer is formed on the side of the Si support substrate 300. The first bonding metal layer comprises a Ti / Pt / Au stack structure, and its surface away from the epitaxial stack 100 is an Au surface; the second bonding metal layer comprises a Ti / Pt / Au / In stack structure, and its surface away from the Si support substrate 300 is an In surface. Subsequently, the Au surface of the first bonding metal layer and the In surface of the second bonding metal layer are aligned and bonded, and Au / In bonding is performed at 210°C to form the bonding layer 204.

[0067] After bonding is completed, a wet solution is used to remove the GaAs substrate and GaInP etching stop layer in sequence, exposing the n-type epitaxial layer.

[0068] The desired n-GaAs ohmic contact layer pattern is formed by photolithography, and the unwanted n-GaAs material on the surface is removed by chemical solution method. Subsequently, N-face electrodes 205 are formed by electron beam evaporation. The N-face electrode 205 is an Au / AuGeNi / Au stacked structure with a total thickness of 3 μm. After evaporation, the photoresist is stripped, and the electrode is annealed at 320°C for 10 min.

[0069] Subsequently, a pattern corresponding to the size of the light-emitting layer is formed by photolithography, and the epitaxial layer structure is etched by ICP to define the size of the light-emitting region. The exposed AlGaInP surface is subjected to chemical wet roughening treatment. A SiNx passivation layer 206 with a thickness of 540 nm is deposited by PECVD. After photolithography, the SiNx layer on the surface of the light-emitting region is removed by BOE solution, leaving only the SiNx passivation protection in the sidewall region.

[0070] Finally, the Si support substrate 300 is thinned to 180 μm, and a back gold layer 207 is formed by electron beam evaporation. The material of the back gold layer 207 is Ti / Au, and the thickness is 100 nm. After laser cutting and dicing, a single semi-circular LED chip of the present invention is formed.

[0071] Comparative Example 1: This comparative example fabricates a conventional circular P-side electrode chip, which will serve as a conventional circular design sample for subsequent performance testing.

[0072] The difference between this comparative example and Example 1 is that the P-side electrode pattern only uses circular electrode units 4022 and does not include semi-circular electrode units 4021; the radius, array spacing, ITO transparent conductive contact layer thickness, epitaxial stacked structure, ODR interface, metal mirror, bonding layer, N-side electrode, surface roughening, passivation layer, back gold layer and other preparation process conditions of the circular electrode units are the same as those of Example 1.

[0073] Since this comparative example uses a traditional circular P-side electrode pattern, its effective current injection boundary is relatively concentrated, and in the planar correspondence with the N-side electrode, it is approximately represented as a local point-like current expansion initiation region.

[0074] Performance testing: To verify the technical effect of the present invention, the conventional circular P-side electrode chip prepared in Comparative Example 1 was used as a comparative example, and the chip prepared in Example 1 with a combination of semi-circular P-side electrodes and circular P-side electrodes was used as an embodiment of the present invention. Wafer-level testing was performed using a vertical testing system with a test current of 700mA.

[0075] The test results are shown in the table below: sample Electrode design Test current Optical power (PO) test reading Operating voltage VF PO change VF change Sample 1 Traditional circular design 700mA 851mW 2.00V 0 0 Sample 1 The invention features a semi-circular design. 700mA 862mW 1.95V +approximately 1% -0.05V Sample 2 Traditional circular design 700mA 545mW 2.00V 0 0 Sample 2 The invention features a semi-circular design. 700mA 570mW 1.91V + Approximately 5% -0.09V The test results above show that, under the same 700mA test current condition, compared with the traditional circular P-side electrode design, the optical power PO test reading of this embodiment of the invention is increased by approximately 1% to 5%, and the operating voltage VF is reduced by approximately 0.05 to 0.09V. This result indicates that, by forming a linear or planar current injection boundary on the straight edge of the semi-circular electrode unit and positioning this straight edge towards or close to the N-side electrode projection area, the present invention can effectively reduce the current spreading resistance and improve the current distribution uniformity, thereby increasing light output while reducing the operating voltage.

[0076] The above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention. Any equivalent substitutions, modifications, or improvements made within the scope of the present invention's technical concept should fall within the protection scope of the present invention.

Claims

1. A low voltage high brightness reverse polarity red LED chip, characterized in that, include: Si-supported substrate; An epitaxial stack is disposed on one side of the Si support substrate. The epitaxial stack is formed based on the GaAs material system and includes at least an n-type semiconductor layer, a light-emitting active layer, and a p-type semiconductor layer. The P-side electrode is disposed on the side of the epitaxial stack near the p-type semiconductor layer; The N-side electrode is disposed on the side of the epitaxial stack away from the P-side electrode; The P-surface electrode comprises multiple semi-circular electrode units, each having a straight edge and a rounded edge. The semi-circular electrode unit is positioned close to the projection area of ​​the N-plane electrode in the chip plane direction, and the straight edge of the semi-circular electrode unit faces or is close to the projection area. The straight edge of the semi-circular electrode unit forms a linear or planar current injection boundary, allowing the current to extend laterally from the straight edge of the semi-circular electrode unit toward the chip plane.

2. The low voltage high brightness reverse polarity red LED chip of claim 1, wherein, The P-side electrode also includes multiple circular electrode units, which are disposed between the two rows of semi-circular electrode units.

3. The low voltage high brightness anti-parallel red LED chip of claim 1, wherein, The radius R of the semi-circular electrode unit satisfies: R≥4μm.

4. The low-voltage, high-brightness, reverse-polarity red LED chip according to claim 1, characterized in that, Multiple semi-circular electrode units are arranged at intervals along the edge of the chip, and the array spacing of the electrode array containing the semi-circular electrode units is 15 to 50 μm.

5. The low-voltage, high-brightness, reverse-polarity red LED chip according to claim 1, characterized in that, The epitaxial stack, from the N-type side to the P-type side, includes an n-GaAs ohmic contact layer, an n-AlGaInP roughening and extension layer, an MQW light-emitting active layer, a p-AlGaInP confinement layer, a p-AlInP transition layer, a p-AlInP / AlGaInP Bragg mirror, and a p-GaP ohmic contact semiconductor layer.

6. The low-voltage, high-brightness, reverse-polarity red LED chip according to claim 5, characterized in that, The P-side electrode includes an ITO transparent conductive contact layer, which is directly disposed on the side of the p-GaP ohmic contact semiconductor layer away from the p-AlInP / AlGaInP Bragg mirror. The thickness of the ITO transparent conductive contact layer is 20–200 nm.

7. The low-voltage, high-brightness, reverse-polarity red LED chip according to claim 1, characterized in that, The side of the P-side electrode away from the epitaxial stack is also provided with an ODR interface, a metal mirror and a bonding layer. The ODR interface includes a SiO2 layer and a DBR layer composed of SiO2 / TiO2; The metal reflector comprises an Ag / TiW / Ti / Pt / Au stacked structure; The bonding layer includes a first bonding metal layer formed on one side of the metal mirror and a second bonding metal layer formed on one side of the Si support substrate, wherein the first bonding metal layer and the second bonding metal layer are connected through an Au / In bonding interface.

8. The low-voltage, high-brightness, reverse-polarity red LED chip according to claim 1, characterized in that, The N-side electrode comprises an Au / AuGeNi / Au stacked structure, and the total thickness of the N-side electrode is 2–4 μm.

9. A method for fabricating a low-voltage, high-brightness, reverse-polarity red LED chip, characterized in that, The method for preparing the low-voltage, high-brightness, reverse-polarity red LED chip according to any one of claims 1 to 8 includes: S1. An epitaxial stack is sequentially grown on a GaAs substrate using the MOCVD method. The epitaxial stack includes at least an n-type semiconductor layer, a light-emitting active layer, and a p-type semiconductor layer. S2. Deposit an ITO transparent conductive contact layer on the side of the epitaxial stack near the p-type semiconductor layer; S3. Perform photolithography and etching on the ITO transparent conductive contact layer to form a P-side electrode pattern including a semi-circular electrode unit, so that the semi-circular electrode unit has a straight edge and a rounded edge. S4. Etch a portion of the epitaxial layer on one side of the p-type semiconductor layer to define the p-side electrode region; S5. An ODR interface, a metal mirror and a bonding layer are formed on one side of the P-side electrode, and bonded to the Si support substrate. S6. Remove the GaAs substrate and etching stop layer, and form an N-side electrode on the side of the epitaxial stack away from the P-side electrode. S7. Perform patterned etching on the epitaxial stack to define the light-emitting area, and perform surface roughening and passivation treatment; S8. The Si support substrate is thinned and a back gold layer is formed. After cutting and splitting, a single LED chip is formed.

10. The preparation method according to claim 9, characterized in that, In step S3, the radius of the semi-circular electrode unit is 5-9 μm, and the spacing between adjacent electrode units in the P-surface electrode pattern is 15-50 μm. The etching temperature for ITO is 45–70℃, and the etching time is 45–220s.

11. The preparation method according to claim 9, characterized in that, In step S4, the p-GaP ohmic contact semiconductor layer and the p-AlInP / AlGaInP Bragg mirror are etched using ICP, and the etching continues until the p-AlInP transition layer is cut off.

12. The preparation method according to claim 9, characterized in that, In step S5, the metal reflector adopts an Ag / TiW / Ti / Pt / Au stacked structure, wherein the Ag thickness is 200-600 nm, the TiW thickness is 50-400 nm, the Ti and Pt thicknesses are 100-300 nm and the Au thickness is 500-900 nm; after forming the metal reflector, it is annealed at 320-400℃ for 15-20 min.

13. The preparation method according to claim 9, characterized in that, In step S6, the N-side electrode adopts an Au / AuGeNi / Au stacked structure with a total thickness of 2-4 μm, and is annealed at 300-360°C for 10-15 min after formation.

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