A memory and a computer

Abstract

The present application discloses a memory and a computer for implementing computing functions within the memory, improving computing efficiency and alleviating the occupancy of the data bus and processor in the computer. The memory includes: a storage unit, a carry and borrow determination circuit, and a data write-back circuit; wherein the storage unit stores a count start value; the storage unit is connected to the carry and borrow determination circuit and the data write-back circuit, respectively, for outputting the count start value to the carry and borrow determination circuit; the carry and borrow determination circuit is connected to the data write-back circuit, for generating a second control signal based on a first control signal sent by the processor for calculating the count start value and the count start value; the data write-back circuit is used to receive the second control signal and, based on the second control signal, update the count start value stored in the storage unit.

Description

Technical Field

[0001] The present application relates to the field of computer technology, and in particular to a memory and a computer. Background Art

[0002] Counters are often used extensively during computer operations. In traditional von Neumann architecture computers, counters are placed in the processor. Each time the processor calculates a value stored in memory, it reads the value from memory via the data bus and sends it to the counter. Once the calculation is complete, the counter's result is written back to memory via the data bus.

[0003] In actual applications, the processor needs to transmit data with the memory and the counter. As the processor processes more data, the data bus is seriously occupied. In addition, there is a certain physical distance between the processor and the memory, which leads to certain data loss on the data bus and a long transmission time of data on the data bus, affecting the working efficiency of the counter. In addition, the above calculation method requires occupying the processor and the data bus for a long time, affecting the realization of other functions of the processor. Summary of the Invention

[0004] The present application provides a memory and a computer, which are used to provide a new memory structure, which can implement a counting function in the memory, improve computing efficiency and alleviate the occupancy of the data bus and processor.

[0005] In a first aspect, an embodiment of the present application provides a memory, which may include: a storage unit, a carry and borrow determination circuit, and a data write-back circuit, wherein a count start value is stored in the storage unit.

[0006] Among them, the storage unit is respectively connected to the carry and borrow determination circuit and the data write-back circuit, and is used to output the count starting value to the carry and borrow determination circuit; the carry and borrow determination circuit is connected to the data write-back circuit, and is used to generate a second control signal according to the first control signal sent by the processor for calculating the count starting value and the count starting value; the data write-back circuit is used to receive the second control signal and update the count starting value stored in the storage unit according to the second control signal.

[0007] With the above-mentioned memory structure, each time the processor performs a logical operation on a storage value stored in the memory or reads data stored in the memory, the carry and borrow determination circuit is used to calculate the currently stored count starting value, and the latest count starting value obtained after the calculation is rewritten into the storage unit through the data write-back circuit. The entire calculation process is completed inside the memory, which reduces data transmission delay and data transmission loss, improves calculation efficiency, and alleviates the occupancy of the processor and data bus.

[0008] In one possible design, the memory may also include: a controller.

[0009] The controller is used to control the carry and borrow determination circuit to generate a second control signal when receiving the first control signal, and to control the data write-back circuit to update the count start value stored in the storage unit.

[0010] Using the above-mentioned memory structure, when the processor needs to perform a logical operation on the initial count value stored in the memory, the processor can send a first control signal to the controller. When receiving the first control signal, the controller controls the carry and borrow determination circuit to calculate the starting count value stored in the storage unit, and uses the data write-back circuit to rewrite the calculation result into the storage unit to realize the update of the starting count value. The entire calculation process is completed in the memory.

[0011] In one possible design, the counting start value is an N-bit binary value, and the carry / borrow determination circuit includes a control circuit, a carry / borrow generation circuit corresponding one-to-one to each binary value, and a determination circuit connected one-to-one to each carry / borrow generation circuit. N may be an integer greater than or equal to 2.

[0012] Specifically, the i-th carry-borrow generation circuit is used to receive the i-th binary value of the counting starting value, and generate the i-th carry-borrow signal according to the first control signal and the i-th binary value, and output the i-th carry-borrow signal to the i+1-th carry-borrow generation circuit, the i+1-th carry-borrow generation circuit receives the i+1-th binary value of the counting starting value, and the i+1-th binary value is the adjacent high-order binary value of the i-th binary value; the i-th judgment circuit is connected to the control circuit, for receiving the i-th carry-borrow signal output by the connected i-th carry-borrow generation circuit, and sending a third control signal to the control circuit according to the received signal, the third control signal being used to indicate whether the i-th binary value has been updated; the control circuit is connected to the data write-back circuit, for generating a second control signal according to the third control signal output by each judgment circuit and outputting it to the data write-back circuit.

[0013] With the above-mentioned memory structure, since the counting starting value stored in the memory is an N-bit binary value, when counting the counting starting value stored in the memory, the state of one or more binary values ​​in the counting starting value may change and a carry-borrow signal may be generated. In order to obtain an accurate counting result, a carry-borrow generation circuit and a judgment circuit are respectively configured for each binary value to judge the update status of each binary value during the calculation process, thereby obtaining an accurate calculation result.

[0014] In a possible design, since the lowest-order binary value cannot receive the carry-borrow signal sent by the adjacent lower-order binary value, the carry-borrow generation circuit and the judgment circuit can respectively have the following two situations.

[0015] Case 1: i equals 1:

[0016] The i-th carry-borrow generation circuit is specifically used to receive the i-th binary value of the counting start value, and generate the i-th carry-borrow signal according to the first control signal and the i-th binary value, and output the i-th carry-borrow signal to the i+1-th carry-borrow generation circuit; the i-th judgment circuit is specifically used to: receive the i-th carry-borrow signal, and send a third control signal to the control circuit according to the received signal.

[0017] Case 2, i is greater than 1:

[0018] The i-th carry-borrow generation circuit is specifically used to receive the i-th binary value of the counting start value and the i-1-th carry-borrow signal, and generate the i-th carry-borrow signal according to the first control signal, the i-th binary value and the i-1-th carry-borrow signal, and output the i-th carry-borrow signal to the i+1-th carry-borrow generation circuit; the i-th judgment circuit is specifically used to: receive the i-th carry-borrow signal and the i-1-th carry-borrow signal, and send a third control signal to the control circuit according to the received signals.

[0019] In one possible design, the storage unit is provided with an output port; wherein the output port of the storage unit is used to output an N-bit binary value and the negation of the N-bit binary value. If i is greater than 1, the i-th carry-borrow generation circuit includes: an amplifier circuit, a first multiplexer, a first switching transistor, a second switching transistor, and a first AND gate circuit.

[0020] Among them, the first input end of the amplifier circuit is connected to the output port of the storage unit, the second input end of the amplifier circuit is connected to the output port of the storage unit, the first output end of the amplifier circuit is connected to the first input end of the first multiplexer, and the second output end of the amplifier circuit is connected to the second input end of the first multiplexer; the control end of the first multiplexer is used to receive a first control signal, and the output end of the first multiplexer is connected to the second input end of the first AND gate circuit; the first end of the first switch tube is used to receive the i-1th carry-borrow signal, and the second end of the first switch tube is respectively connected to the first input end of the first AND gate circuit and the second end of the second switch tube; the first end of the second switch tube is connected to the ground line; and the output end of the first AND gate circuit is used to output the i-th carry-borrow signal.

[0021] By adopting the above-mentioned memory structure, the carry and borrow generation signal can utilize the output port set by the storage unit to obtain the binary value of the i-th bit and the inverse value of the binary value of the i-th bit, and utilize the above-mentioned circuit structure to accurately obtain the update status of each binary value in the counting starting value during the calculation process.

[0022] In a possible design, if i is greater than 1, the i-th judgment circuit includes: a first delay circuit and a first XOR gate circuit.

[0023] Among them, the input end of the first delay circuit is connected to the corresponding carry-borrow generation circuit for obtaining the i-1th carry-borrow signal, and the output end of the first delay circuit is connected to the first input end of the first XOR gate circuit; the second input end of the first XOR gate circuit is connected to the corresponding i-th carry-borrow generation circuit for receiving the i-th carry-borrow signal, and the output end of the first XOR gate circuit is used to output the third control signal.

[0024] In a possible design, if i is greater than 1, the i-th judgment circuit includes: a second XOR gate circuit, a second delay circuit, and a second AND gate circuit.

[0025] Among them, the first input end of the second XOR gate circuit is connected to the corresponding i-th carry-borrow generation circuit for receiving the i-th carry-borrow signal, the second input end of the second XOR gate circuit is connected to the corresponding carry-borrow generation circuit for receiving the i-1-th carry-borrow signal, the output end of the second XOR gate circuit is respectively connected to the input end of the second delay circuit and the first input end of the second AND gate circuit; the output end of the second delay circuit is connected to the second input end of the second AND gate circuit; the output end of the second AND gate circuit is used to output a third control signal.

[0026] In one possible design, the control circuit includes: a third switch tube, a fourth switch tube corresponding one-to-one to each judgment circuit, and a fifth switch tube corresponding one-to-one to each fourth switch tube.

[0027] Specifically, the first end of the third switch tube is connected to the power supply, the second end of the third switch tube is connected to the first node, and the first node is used to output the second control signal; the first end of each fourth switch tube is connected to the first node, and the control end of each fourth switch tube is used to receive the third control signal output by the corresponding judgment circuit; the first end of each fifth switch tube is connected to the second end of the corresponding fourth switch tube, and the second end of each fifth switch tube is connected to the ground line.

[0028] Using the above-mentioned memory structure, a signal indicating whether the calculation of a binary value has been completed is received at the control end of the fourth switch tube. When it is determined that the calculation of multiple binary values ​​in the counting starting value has been completed, a second control signal is sent to the data write-back circuit through the first node, instructing the data write-back circuit to rewrite the calculation result into the storage unit.

[0029] In one possible design, the data write-back circuit includes: a sub-data write-back circuit connected to each carry-borrow generation circuit in a one-to-one correspondence.

[0030] Among them, the i-th sub-data write-back circuit is connected to the control circuit and the storage unit respectively, and is used to receive the second control signal and the connected carry-borrow generation circuit to output the i-th carry-borrow signal, and update the i-th binary value in the storage count starting value in the storage unit according to the received signal.

[0031] In one possible design, the i-th sub-data write-back circuit includes: a first NOT gate circuit, a third AND gate circuit, a second multiplexer, a third delay circuit, a second NOT gate circuit, a differential amplifier, and a third multiplexer.

[0032] Specifically, the input end of the first NOT gate circuit is connected to the output end of the control circuit, and the output end of the first NOT gate is connected to the second input end of the third AND gate circuit; the first input end of the third AND gate circuit is used to receive the first enable signal, the third input end of the third AND gate circuit is connected to the output end of the corresponding carry-borrow generation circuit, and the output end of the third AND gate circuit is connected to the first input end of the second multiplexer, and the first enable signal is generated by the processor calculating the counting start value; the second input end of the second multiplexer is connected to the first input end of the second AND gate circuit, and the output end of the second multiplexer is respectively connected to the input end of the third delay circuit and the input end of the second NOT gate circuit, and the control end of the second multiplexer is connected to the first input end of the second AND gate circuit. The device is configured to receive a second enable signal, where the second enable signal is generated by the processor accessing the memory. The output of the third delay circuit is connected to the memory unit. The output of the second NOT gate circuit is connected to the memory unit. The first input of the differential amplifier is configured to receive the i-th binary value. The second input of the differential amplifier is configured to receive the inverse of the i-th binary value. The output of the differential amplifier is connected to the first input of the third multiplexer. The second input of the third selector is connected to the data access port. The output of the third multiplexer is respectively connected to the input of the third delay circuit and the input of the second NOT gate circuit. The control terminal of the third multiplexer is configured to receive the second enable signal. The processor accesses the memory through the data access port.

[0033] In a possible design, the controller is further configured to control the data write-back circuit to store the data sent by the processor into the storage unit; or to output the data stored in the storage unit to the processor.

[0034] In a possible implementation, the counting start value is the address of the address register.

[0035] In a second aspect, an embodiment of the present application provides a computer comprising a processor and the memory provided in the first aspect of the present application and any possible design thereof.

[0036] The processor is connected to the memory.

[0037] Optionally, the computer further includes a data bus, and the processor and the memory are connected via the data bus.

[0038] Optionally, the computer further includes a controller, which is connected to the memory and the storage respectively. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] Figure 1 A schematic diagram of the structure of a computer provided in an embodiment of the present application Figure 1 ;

[0040] Figure 2 A schematic diagram of the structure of a memory provided in an embodiment of the present application Figure 1 ;

[0041] Figure 3 A schematic diagram of the structure of a carry and borrow determination circuit provided in an embodiment of the present application;

[0042] Figure 4 A schematic diagram of the correspondence between a carry and borrow generation circuit and a counting start value provided in an embodiment of the present application;

[0043] Figure 5 A schematic structural diagram of a carry-borrow generation circuit provided in an embodiment of the present application;

[0044] Figure 6 A schematic diagram of a calculation process of a carry and borrow generation circuit provided in an embodiment of the present application;

[0045] Figure 7 A schematic diagram of the initialization process of the carry and borrow generation circuit provided in an embodiment of the present application;

[0046] Figure 8 A schematic diagram of a judgment circuit provided in an embodiment of the present application Figure 1 ;

[0047] Figure 9 A schematic diagram of a judgment circuit provided in an embodiment of the present application Figure 2 ;

[0048] Figure 10 A schematic diagram of the structure of a control circuit provided in an embodiment of the present application;

[0049] Figure 11 A schematic structural diagram of a sub-data write-back circuit provided in an embodiment of the present application;

[0050] Figure 12 A schematic diagram of the structure of a memory provided in an embodiment of the present application Figure 2 ;

[0051] Figure 13 A schematic diagram of a memory access mode provided in an embodiment of the present application;

[0052] Figure 14 A schematic diagram of a calculation mode of a memory provided in an embodiment of the present application;

[0053] Figure 15 A computer structure diagram provided in the embodiment of the present application Figure 2 . DETAILED DESCRIPTION

[0054] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of them. All other embodiments obtained by ordinary technicians in this field based on the embodiments of the present invention without making any creative efforts shall fall within the scope of protection of the present invention.

[0055] The technical solutions of the embodiments of the present application can be applied to computer systems.

[0056] It should be understood that in the technical solutions provided by the embodiments of the present application, some repetitions may not be repeated in the introduction of the following specific embodiments, but these specific embodiments should be regarded as having been referenced to each other and can be combined with each other.

[0057] See also Figure 1 , is a schematic diagram of the structure of a computer system provided by an embodiment of the present invention. Figure 1 As shown, the computer system 100 may include at least a processor 10 and a memory 20 .

[0058] The processor 10 is the computing core and control unit of a computer system 100. The processor 10 can be a very large-scale integrated circuit. An operating system and other software programs are installed in the processor 10, so that the processor 10 can access the memory 20 of the computer system 100. Those skilled in the art will appreciate that the processor 10 can be a central processing unit (CPU), or a processing circuit including at least one processor core 12, or other application-specific integrated circuit (ASIC) configured to implement an embodiment of the present invention. With the advancement of integrated circuit technology, more and more processor cores can be integrated into the processor 10. When the processor 10 integrates multiple processor cores 12, the multiple processor cores 12 can be interconnected via an on-chip network. It is understood that in actual applications, a computer system may also include multiple processors. The embodiments of the present invention use a single processor as an example. The embodiments of the present invention do not limit the number of processors or the number of processor cores in a processor.

[0059] The memory 20 is a storage device of the computer system 100. The memory 20 is generally used to store various running software in the operating system, input and output data, and information exchanged with external devices. In order to improve the access speed of the processor 10, the memory 20 has the advantage of fast access speed. In traditional computer system architectures, dynamic random access memory (DRAM) is generally used as the memory 20. With the development of non-volatile memory (NVM) technology, new types of NVM such as phase-change random access memory (PCM), resistive random access memory (RRAM), magnetic random access memory (MRAM) or ferroelectric random access memory (FRAM) are gradually being used as memory. In the embodiment of the present invention, the specific storage medium of the memory 20 is not limited.

[0060] The computer system 100 may also include a data bus 30. When the processor 10 needs to access the memory 20, the processor 10 sends an access request to the memory 20 through the data bus 30. Based on the access request sent by the processor 1, the memory 20 writes data to the memory or reads data from the memory 20 and transmits the data to the processor 10 through the data bus 30.

[0061] The computer 100 also includes some external devices, such as input devices, for receiving input digital information, character information or contact touch operations / non-contact gestures, and generating signal inputs related to user settings and function controls of the computer 100.

[0062] In addition to the above, the computer 100 may also include a power supply for powering other modules. The computer 100 may also include one or more sensors, such as an image sensor, a brightness sensor, a light sensor, a GPS sensor, an infrared sensor, etc. The computer 100 may also include a radio frequency (RF) circuit for communicating with wireless network devices, and a WiFi module for communicating with other devices via WiFi to acquire images or data transmitted by other devices.

[0063] The following will be combined Figure 1 The computer system 100 shown in FIG. A detailed description of the process by which the processor 10 accesses the memory 20 is provided. The instruction queue of the processor 10 contains multiple pending computer instructions, which may include memory access instructions, arithmetic instructions, and other instructions. A memory access instruction instructs the processor 10 to access the memory 20. Memory access instructions may include load and store instructions. Arithmetic instructions instruct the processor 10 to perform calculations on values ​​stored in the memory 20. Arithmetic instructions may include addition instructions, subtraction instructions, and the like.

[0064] When the processor sends an operation instruction to the memory to calculate the storage value in the memory 20, the entire calculation process is carried out in the processor 10, and each calculation needs to first transfer the storage value to be calculated from the memory 20 to the processor 10 through the data bus 30. After the processor 10 completes the calculation, the calculation result is output to the memory 20 through the data bus 30 for re-storage. The long calculation process results in low calculation efficiency, and the data bus and the processor 10 will be occupied multiple times, affecting the realization of other functions of the processor.

[0065] Based on this, an embodiment of the present application provides a memory and a computer, which can be applied to the aforementioned computer architecture to implement computing functions within the memory, thereby improving computing efficiency while alleviating the occupancy of the data bus and processor.

[0066] See also Figure 2 As shown in FIG. 1 , a schematic diagram of the structure of a memory provided in an embodiment of the present application is shown in FIG. Figure 2 As shown, the memory 200 may include: a storage unit 201 , a carry and borrow determination circuit 202 , and a data write-back circuit 203 .

[0067] When the processor needs to calculate the storage value of the storage unit in the memory 200, the processor sends a first control signal to the memory 200 through the data bus. The count start value can be the storage value in the storage unit 201 in the memory 200. The first control signal is used to control the carry and borrow determination circuit 202 to calculate the count start value stored in the storage unit 201. After the memory 200 receives the first control signal, the carry and borrow determination circuit 202 calculates the count start value stored in the storage unit 201 according to the first control signal, and generates a second control signal representing the calculation result of the count start value, and rewrites the latest calculation result into the storage unit 201 through the data write-back circuit 203, thereby updating the count start value currently stored in the storage unit 201. The count start value can be a multi-bit binary value.

[0068] In one feasible method, in order to reduce the processor occupancy, part of the processor's logical calculations can be implemented through the memory 200, that is, the processor first sends the value to be calculated to the memory 200 as the counting starting value through the data bus, and sends a first control signal for calculating the counting starting value to the memory 200. After the processor completes the calculation of the counting starting value, the processor reads the calculation result through the data bus and sends the calculation result to the corresponding device, thereby reducing the processor occupancy.

[0069] In a possible implementation, the counting start value is the address stored in the address register.

[0070] It should be noted that the processor has an internal address register that stores the address of the target program instruction to be accessed by the processor. The processor retrieves the target program instruction based on the address currently stored in the address register. When the target program instruction is executed, the address register is automatically incremented by 1, allowing the processor to automatically execute the next program instruction. The address can be the segment number and / or line number of the target program instruction.

[0071] If the above-mentioned memory is used to update the address stored in the address register, the processor can first output the first address of the address register to the storage unit 201 of the memory 200 through the data bus as the starting value of the count. When the target program instruction corresponding to the first address is executed, the processor sends a first control signal to the memory 200. After receiving the first control signal, the memory 200 adds 1 to the first address to obtain the second address. The processor reads the second address through the data bus and outputs the second address to the address register.

[0072] Specifically, the storage unit 201 is respectively connected to the carry and borrow determination circuit 202 and the data write-back circuit 203, and is used to output the stored count starting value to the carry and borrow determination circuit 202; the carry and borrow determination circuit 202 is connected to the data write-back circuit 203, and is used to generate a second control signal based on the first control signal for calculating the count starting value and the count starting value sent by the processor; the data write-back circuit 203 is used to receive the second control signal and update the count starting value stored in the storage unit 201 according to the second control signal.

[0073] In actual use, the carry and borrow determination circuit 202 , the storage unit 201 and the data write-back circuit 203 in the memory 200 are connected and communicate with each other through a data transmission line.

[0074] In a specific implementation, the data write-back circuit 203 and the carry / borrow determination circuit 202 may be composed of components such as switches, multiplexers, and diodes. The operating states of the data write-back circuit 203 and the carry / borrow determination circuit 202 may be achieved by adjusting the operating states of these components (e.g., switches).

[0075] In the present application, the adjustment of the working states of the above-mentioned carry and borrow determination circuit 201 and the data write-back circuit 203 can be achieved through a processor or a controller, that is, the memory 200 can also include a controller (not shown), which can be used to control the carry and borrow determination circuit 202 to generate a second control signal after receiving a first control signal sent by the processor, and control the data write-back circuit 203 to update the count starting value stored in the storage unit 201.

[0076] In one example, if the count start value is the storage value of the storage unit 201 in the memory 200, when the controller receives the first control signal, it directly controls the carry-borrow determination circuit 202 to generate a second control signal, and controls the data write-back circuit 203 to update the count start value stored in the storage unit 201.

[0077] In another example, if the count start value is the address of the address register, when the controller determines that the storage unit 201 receives the count start value sent by the processor and receives the first control signal, it controls the carry-borrow determination circuit 202 to generate a second control signal, and controls the data write-back circuit 203 to update the count start value stored in the storage unit 201.

[0078] Specifically, if the switch tubes in the carry and borrow determination circuit 202 and the data write-back circuit 203 in the memory 200 are metal oxide semiconductor (MOS) tubes, the controller can be connected to the gate of the MOS tube, and generate a second control signal by controlling the on and off of the MOS tube, and control the data write-back circuit 203 to update the count starting value stored in the storage unit 201; if the switch tubes in the carry and borrow determination circuit 202 and the data write-back circuit 203 in the memory 200 are bipolar junction transistors (BJT), the controller can be connected to the base of the BJT, and generate a second control signal by controlling the on and off of the BJT, and control the data write-back circuit 203 to update the count starting value stored in the storage unit 201.

[0079] In a specific implementation, the controller can be a driver, which, after receiving the first control signal sent by the processor for calculating the starting value of the count, sends a corresponding drive signal to the switch tube in the data write back circuit 203 and the carry and borrow determination circuit 202 to control the state of the data write back circuit 203 and the carry and borrow determination circuit 202.

[0080] The driver may be a driving signal or a driving circuit composed of devices such as a switch tube. Of course, the specific form of the controller is not limited to the above examples.

[0081] Next, the specific structures of the storage unit 201 , the carry and borrow determination circuit 202 , and the data write-back circuit 203 in the memory 200 are introduced.

[0082] 1. Storage Unit 201

[0083] The storage unit 201 is connected to the carry and borrow determination circuit 202 and the data write-back circuit 203 respectively. The storage unit 201 is used to send the stored count start value to the carry and borrow determination circuit 202, and receive the updated count start value output by the data write-back circuit 203 to overwrite the currently stored count start value, thereby updating the count start value.

[0084] The storage unit 201 may be provided with an output port and an input port, wherein the output port may be used to output the stored multi-bit binary value and the inverse value of the multi-bit binary value, and the input port is used to receive the updated counting start value sent by the data write-back circuit 203 .

[0085] In one possible implementation, the storage unit 201 may include a first input port corresponding one-to-one to the multi-bit binary value in the counting start value, a second input port corresponding one-to-one to the multi-bit binary value, a first output port corresponding one-to-one to the multi-bit binary value, and a second output port corresponding one-to-one to the multi-bit binary value.

[0086] Among them, each first input port is connected to the data write-back circuit 203, and is used to receive the corresponding bit binary value in the updated count starting value sent by the data write-back circuit 203; each second input port is connected to the data write-back circuit 203, and is used to receive the inverse value of the corresponding bit binary value in the updated count starting value sent by the data write-back circuit 203; each first output port is connected to the carry and borrow determination circuit 202, and is used to output the stored corresponding bit binary value; each second output port is connected to the carry and borrow determination circuit 202, and is used to output the inverse value of the stored corresponding bit binary value.

[0087] In one possible implementation, the storage unit 201 may include a third input port for receiving an updated count start value sent by the data write-back circuit 203, a fourth input port for receiving the inverted value of the updated count start value sent by the data write-back circuit 203, a third output port for outputting a multi-bit binary value, and a fourth output port for outputting the inverted value of the multi-bit binary value.

[0088] In a specific implementation, the storage unit can be any one of DRAM, PCM, RRAM, MRAM, and FRAM. Of course, the specific form of the storage unit is not limited to the above examples.

[0089] 2. Carry / Borrow Determination Circuit 202

[0090] The carry and borrow determination circuit 202 is connected to the storage unit 201 and the data write-back circuit 203 respectively, and is used to receive the count start value stored in the storage unit 201, and calculate the currently stored count start value according to the first control signal sent by the processor for calculating the count start value, and send the second control signal representing the calculation result to the data write-back circuit 203 to control the data write-back circuit 203 to rewrite the calculation result into the storage unit 201.

[0091] It should be noted that the count start value may be an N-bit binary value. When the carry / borrow determination circuit receives the first control signal and calculates the count start value, multiple binary values ​​in the count start value may change. To accurately obtain the calculation result, a carry / borrow generation circuit is configured for each binary value in the N-bit binary value. The carry / borrow generation circuit can determine the change in each binary value in the count start value during the calculation process. N may be an integer greater than or equal to 2.

[0092] For details, see Figure 3 As shown, the carry-borrow determination circuit 202 includes a control circuit 2021, a carry-borrow generation circuit 2022 corresponding one-to-one to each binary value in the count start value, and a judgment circuit 2023 connected one-to-one to each carry-borrow generation circuit 2022.

[0093] Among them, each i-th carry-borrow generation circuit 2022 is connected to the storage unit 201, and is used to receive the i-th binary value in the count starting value, and generate the i-th carry-borrow signal according to the first control signal and the i-th binary value sent by the processor, and output the i-th carry-borrow signal to the i+1-th carry-borrow generation circuit, the i+1-th carry-borrow generation circuit receives the i+1-th binary value of the count starting value, and the i+1-th binary value is the adjacent high-order binary value of the i-th binary value; the i-th judgment circuit 2023 is connected to the control circuit 2021, and is used to receive the i-th carry-borrow signal, and according to the received signal, send a third control signal to the control circuit, the third control signal is used to indicate whether the i-th binary value has been updated; the control circuit 2021 is connected to the data write-back circuit 203, and is used to generate a second control signal according to the third control signal output by each judgment circuit 2022 and output it to the data write-back circuit 203.

[0094] See also Figure 4 As shown, assuming that the count starting value stored in the storage unit is 0101, then Figure 4 The first carry-borrow generating circuit receives the first binary value 1 of the lowest bit, the second carry-borrow generating circuit receives the second binary value 0, the third carry-borrow generating circuit receives the first binary value 1, and the fourth carry-borrow generating circuit receives the second binary value 0.

[0095] In one possible implementation, each carry / borrow generation circuit 2022 is connected to the first output port and the second output port of the storage unit 201 to obtain the corresponding binary value. The first output port is used to output the corresponding binary value, and the second output port is used to output the inverse of the corresponding binary value.

[0096] In another possible implementation, each carry-borrow generation circuit 2022 is respectively connected to the third output port of the storage unit 201, for obtaining the binary value of the corresponding bit of the carry-borrow generation circuit 2022, and each carry-borrow generation circuit 2022 is respectively connected to the fourth output port of the storage unit 201, for obtaining the inverse value of the binary value of the corresponding bit of the carry-borrow generation circuit 2022.

[0097] The function of the carry-borrow generation circuit 2022 is to determine the calculation result of the corresponding binary value in the process of calculating the counting starting value stored in the memory 201, and to determine whether the corresponding binary value of the carry-borrow generation circuit 2022 sends a carry-borrow signal to the adjacent higher-order binary value. It should be understood that when the carry-borrow generation circuit 2022 sends a carry-borrow signal to the adjacent higher-order binary value of the corresponding binary value, the state of the adjacent higher-order binary value of the corresponding binary value will be directly changed. The states of the binary values ​​include 0 and 1.

[0098] In one example, 0 may be a voltage signal whose voltage value is lower than a first threshold, and 1 may be a voltage signal whose voltage value is higher than a second threshold. The first threshold and the second threshold may be the same, and the second threshold may also be higher than the first threshold.

[0099] The function of setting the judgment circuit 2023 is to detect whether the state of the binary value of the corresponding bit of the connected carry-borrow generation circuit 2022 has been updated during the calculation of the counting starting value stored in the memory 201, and send a third control signal to the control circuit 2021 to indicate whether the state of the binary value of the corresponding bit of the connected carry-borrow generation circuit 2022 has been updated.

[0100] The function of setting the control circuit 2021 is to determine whether the status of all binary values ​​in the counting starting value has been updated through the third control signal output by each judgment circuit 2023, and when it is determined that the status of all binary values ​​in the counting starting value has been updated, send a second control signal to the data write back circuit 203 to control the data write back circuit 203 to update the counting starting value stored in the storage unit 201.

[0101] It should be noted that, during the calculation of the counting start value stored in the memory 201, the update status of the i-th binary value is not only related to the binary value of the i-th bit, but also to the carry and borrow signal of the i-1-th binary value. Therefore, the carry and borrow generation circuit 2022 corresponding to the i-th binary value can generate the i-th carry and borrow signal using the first control signal sent by the processor, the received i-th binary value, and the carry and borrow signal outputted for the i-1-th binary value, and send the i-th carry and borrow signal to the i+1-th carry and borrow generation circuit, so that the i+1-th carry and borrow generation circuit can determine the update status of the i+th binary value.

[0102] In actual use, since the lowest binary value in the counting starting value has no adjacent low-order binary value, the carry-borrow generation circuit corresponding to the lowest binary value generates the first carry-borrow signal based on the first control signal and the lowest binary value in the counting starting value.

[0103] For ease of understanding, the specific circuit structures of the carry-in borrow generation circuit 2022, the judgment circuit 2023 and the control circuit 2021 are respectively given below.

[0104] See also Figure 5 , is a schematic diagram of the structure of the i-th carry-borrow generating circuit 2022. Figure 5 As shown, the carry-borrow generation circuit 2022 may include: an amplifier circuit U1, a first multi-way selection switch K1, a first switch tube S1, a second switch tube S2 and a first AND gate circuit Z1.

[0105] Figure 5 The connection relationship of the various components in the i-th carry and borrow generation circuit 2022 shown can be: the first input end of U1 is connected to the third output port of the storage unit 201, for obtaining the i-th binary value in the counting start value, the second input end of U1 is connected to the fourth output port of the storage unit 201, for obtaining the inverted value of the i-th binary value, the first output end of U1 is connected to the first input end of K1, and the second output end of U1 is connected to the second input end of K1; the control end of K1 is used to receive the first control signal, and the output end of K1 is connected to the second input end of Z1; the first end of S1 is used for the i-1-th carry and borrow signal, and the second end of S1 is respectively connected to the first input end of Z1 and the second end of S2; the first end of S2 is connected to the ground line; and the output end of Z1 is used to output the i-th first carry and borrow signal.

[0106] In one example, when the signal amplitude of the binary value corresponding to the received count start value meets the starting amplitude of K1 and Z1, in order to reduce the size of the carry-borrow generation circuit, the carry-borrow generation circuit may only include K1, S1, S2 and Z1.

[0107] In specific implementation, the relationship between the second carry-borrow signal, the corresponding bit binary value, the first control signal and the first carry-borrow signal in the carry-borrow generation circuit 2022 can be shown in Table 1.

[0108] Table 1

[0109]

[0110]

[0111] The following combination Figure 15 As shown in Table 1, the process of the i-carry borrow generating circuit 2022 generating the first carry-borrow signal is described by taking the processor sending the first control signal for performing an addition operation on the counting start value as an example.

[0112] Assume that the counting start value is 0101, and if i is 3, the corresponding binary value of the i-th carry-borrow generating circuit 2022 is 1. The first input terminal of U1 obtains the corresponding binary value 1 through the connected third output port, and the second input terminal of U1 obtains the inverted value 0 of the corresponding binary value through the connected fourth output port, and amplifies the obtained signal. The first output terminal of U1 outputs the amplified corresponding binary value 1, and the second output terminal of U1 outputs the inverted value 0 of the amplified corresponding binary value. If the control terminal of K1 receives a high-level first control signal, K1 outputs the amplified 1 received at the first input terminal to the second input terminal of Z1. If the second carry-borrow signal received at the first input terminal of Z1 is a high-level signal 1, the first carry-borrow signal output by Z1 is a high-level signal. The high-level signal indicates that a carry is being performed to the adjacent high-order binary value of the corresponding binary value. Here, the carry-borrow determining circuit 202 performs an addition operation.

[0113] If i is 2, then the binary value of the corresponding bit of the i-th carry-borrow generating circuit 2022 is 0. For example, the first input terminal of U1 obtains the binary value 0 of the corresponding bit through the connected third output port, and the second input terminal of U1 obtains the inverted value 1 of the binary value of the corresponding bit through the connected fourth output port, and the obtained signal is amplified. The first output terminal of U1 outputs the amplified binary value 0 of the corresponding bit, and the second output terminal of U1 outputs the inverted value 1 of the amplified binary value of the corresponding bit. If the control terminal of K1 receives a first control signal of a high level signal, K1 outputs the amplified 0 received by the first input terminal to the second input terminal of Z1. If the second carry-borrow signal received by the first input terminal of Z1 is a high level signal 1, the first carry-borrow signal output by Z1 is a low level signal. The low level signal indicates that there is no need to carry to the adjacent high-order binary value of the corresponding bit. Here, the carry-borrow determining circuit 202 has an addition operation function.

[0114] The following combination Figure 5 As shown in Table 1, the process of the carry-borrow generating circuit 2022 generating the first carry-borrow signal is described by taking the processor sending the first control signal for performing a subtraction operation on the counting start value as an example.

[0115] Assume that the counting start value is 0101, and if i is 3, then the corresponding binary value of the i-th carry-borrow generating circuit 2022 is 1. The first input terminal of U1 obtains the corresponding binary value 1 through the connected third output port, and the second input terminal of U1 obtains the inverse value 0 of the corresponding binary value through the connected fourth output port. The obtained signal is amplified, and the first output terminal of U1 outputs the amplified corresponding binary value 1, and the second output terminal of U1 outputs the inverse value 0 of the amplified corresponding binary value. If the control terminal of K1 receives a low-level first control signal, K1 outputs the amplified 0 received at the second input terminal to the second input terminal of Z1. If the second carry-borrow signal received at the first input terminal of Z1 is a high-level signal 1, Z1 outputs the first carry-borrow signal as a low-level signal. This low-level signal indicates that there is no need to borrow from the adjacent high-level binary value of the corresponding binary value. In this case, the carry-borrow determining circuit 202 performs a subtraction operation.

[0116] For example, if i is 2, the corresponding binary value of the i-th carry-borrow generating circuit 2022 is 0. The first input terminal of U1 obtains the corresponding binary value 0 via the connected third output port, and the second input terminal of U1 obtains the inverted value 1 of the corresponding binary value via the connected fourth output port. The obtained signal is amplitude-amplified, and the first output terminal of U1 outputs the amplified corresponding binary value 0, while the second output terminal of U1 outputs the inverted value 1 of the amplified corresponding binary value. If the control terminal of K1 receives a low-level first control signal, K1 outputs the amplified 1 received at the second input terminal to the second input terminal of Z1. If the second carry-borrow signal received at the first input terminal of Z1 is a high-level signal 1, the first carry-borrow signal output by Z1 is a high-level signal, indicating a borrow from the adjacent higher-order binary value of the corresponding binary value. In this case, the carry-borrow determining circuit 202 functions as a subtractor.

[0117] Similarly, in the process of calculating the counting starting value, the carry and borrow conditions of each binary value in the counting starting value are determined by the carry and borrow generating circuit 2022 corresponding to the multiple binary values ​​in the counting starting value.

[0118] It should be noted that the carry-borrow generation circuit 2022 corresponding to the lowest binary value in the count starting value cannot receive the carry-borrow signal of the adjacent low-order binary value. When the controller or the memory 200 receives the first control signal for performing an addition operation on the count starting value, it sends a high-level signal representing the carry to the first end of S1 in the carry-borrow generation circuit 2022 corresponding to the lowest binary value, and when it receives the first control signal for performing a subtraction operation on the count starting value, it sends a low-level signal representing the borrow to the first end of S1 in the carry-borrow generation circuit corresponding to the lowest binary value.

[0119] In the following, with reference to an embodiment, the process of calculating the counting starting value using multiple carry-borrow generating circuits 2022 is described by taking the counting starting value as 000111 and the processor sending a first control signal of a high level signal to the memory 200 as an example.

[0120] like Figure 6As shown, when the processor sends a first control signal of a high-level signal, the carry-borrow generation circuit 2022 corresponding to the least significant binary value 1 performs an addition operation and simultaneously outputs a high-level signal 1 to the first carry-borrow generation circuit 2022 corresponding to the least significant binary value 1. At this time, the first carry-borrow generation circuit 2022 outputs a high-level signal 1 representing a carry and outputs it to the second carry-borrow generation circuit 2022. The second carry-borrow generation circuit 2022 performs an addition operation and outputs a high-level signal 1 for continuing the carry. The third carry-borrow generation circuit 2022 outputs a high-level signal and performs an addition operation, sending a high-level signal 1 for continuing the carry to the fourth carry-borrow generation circuit 2022. The fourth binary value 0 performs an addition operation. At this time, the fourth carry-borrow generation circuit 0 sends a low-level signal 0 for performing the borrow. The calculation of the entire counting starting value is completed.

[0121] In actual use, the carry-borrow generation circuit 2022 will only calculate the count starting value stored in the memory 200 when it receives the first control signal, so as to avoid the influence of the signal received when the count starting value was calculated last time on the current calculation. Each time the carry-borrow generation circuit 2022 calculates the carry-borrow situation of the corresponding binary value, the controller or processor can initialize the carry-borrow generation circuit 2022.

[0122] See also Figure 7 , is the initialization process of the i-th carry-borrow generating circuit 2022. Figure 7 As shown, when the controller or memory does not receive the first control signal, the clock CLK signal representing the operation of the carry-borrow generation circuit 2022 is a low-level signal. At this time, a low-level signal is sent to the control terminal of S1 and a high-level signal is sent to the control terminal of S2. S1 is disconnected and does not receive the i-1th carry-borrow signal. At the same time, S2 is turned on to ground the first input terminal of Z1, so that the first input terminal of Z1 cannot receive any signal. When the controller or memory receives the first control signal, the clock CLK signal representing the operation of the carry-borrow generation circuit 2022 is a low-level signal. A high-level signal is sent to the control terminal of S1 and a low-level signal is sent to the control terminal of S2. S1 is turned on to receive the i-1th carry-borrow signal. S1 is disconnected to output the i-1th carry-borrow signal transmitted by S2 to the first input terminal of Z1.

[0123] See also Figure 8 , is a structural diagram of the i-th judgment circuit 2023. Figure 8 As shown, the i-th judgment circuit 2023 may include: a first delay circuit D1 and a first XOR gate circuit Z2.

[0124] Figure 8The connection relationship of the various components in the judgment circuit 2023 shown can be: the input end of D1 is connected to the i-th carry-borrow generation circuit 2022, for receiving the i-1-th carry-borrow signal, and the output end of D1 is connected to the first input end of the Z2 circuit; the second input end of Z2 is connected to the i-th carry-borrow generation circuit 2022, for receiving the i-th carry-borrow signal, and the output end of Z2 is used to output a third control signal indicating whether the binary numerical state of the corresponding bit of the connected carry-borrow generation circuit 2022 has been updated.

[0125] pass Figure 8 When the i-th judgment circuit 2023 shown determines whether the state of the i-th binary value is updated, it determines whether the i-th binary value is updated by detecting the state of the i-th carry-borrow signal output by the connected carry-borrow generation circuit 2023 after receiving the i-1-th carry-borrow signal.

[0126] In a specific implementation, after the connected carry-borrow generation circuit 2022 receives the i-1th carry-borrow signal, it needs to go through calculation and delay by the internal components of the carry-borrow generation circuit 2022 before it can output the i-th carry-borrow signal. Therefore, there is a certain delay between the i-1th carry-borrow signal and the i-th carry-borrow signal. In order to ensure the accuracy of the detection result, the first delay circuit D1 added to the judgment circuit 2023 uses the i-th carry-borrow signal output after the delay of D1 and the i-1th carry-borrow signal received before the delay of D1 to generate a third control signal indicating whether the status of the i-th binary value has been updated.

[0127] In a specific implementation, the relationship between the first carry-borrow signal, the second carry-borrow signal and the third control signal can be shown in Table 2.

[0128] Table 2

[0129] The i-th carry-borrow signal The i-1th carry-borrow signal The third control signal 0 0 0 1 1 0 0 1 1

[0130] As shown in Table 2, when the judgment circuit 2023 receives the i-th carry-borrow signal and the i-1-th carry-borrow signal, both of which are low-level signals, it indicates that the i-th binary value has not received a carry-borrow signal, and the state of the connected i-th binary value does not need to be updated. When the i-th carry-borrow signal and the i-1-th carry-borrow signal are both high-level signals, it indicates that the i-th binary value has received the second carry-borrow signal sent by the adjacent lower binary value and has carried or borrowed to the adjacent higher binary value, then the state of the i+1-th binary value will still change.

[0131] It should be understood that when the i-th carry-borrow generating circuit 2023 connected to the i-th judgment circuit 2023 does not output the i-th carry-borrow signal, the state representing the i+1-th binary value will not change, and the entire counting starting value calculation is completed.

[0132] In actual use, in order to avoid the influence of the i-th carry-borrow signal output by the connected carry-borrow generation circuit 2022 during the last calculation and the i-1-th carry-borrow signal received on the detection, the second input end of Z2 can be connected to the second end of the first switch tube in the i-th carry-borrow generation circuit 2022, so as to obtain the i-1-th carry-borrow signal received by the connected carry-borrow generation circuit 2022 during the current calculation of the count starting value, so as to ensure the accuracy of the detection result.

[0133] See also Figure 9 , is another structural diagram of the i-th judgment circuit 2023. Figure 9 As shown, the i-th judgment circuit 2023 includes: a second XOR gate circuit Z3, a second delay circuit D2 and a second AND gate circuit Z4.

[0134] Figure 8 The connection relationship of each device in the judgment circuit 2023 shown can be: the first input terminal of Z3 is connected to the output terminal of the corresponding i-th carry-borrow generation circuit 2022, for receiving the i-th carry-borrow signal, the second input terminal of Z3 is connected to the input terminal of the corresponding i-th carry-borrow generation circuit 2022, for receiving the i-1-th carry-borrow signal, the output terminal of Z3 is respectively connected to the input terminal of D2 and the first input terminal of Z4; the output terminal of D2 is connected to the second input terminal of Z4; and the output terminal of Z4 is used to output the third control signal.

[0135] In specific implementation, the relationship between the i-th carry-borrow signal, the i-1-th carry-borrow signal and the third control signal can be seen in Table 2 above, and this application will not repeat it here.

[0136] In a specific implementation, the second end of Z3 may be connected to the second end of the first switch tube in the i-th carry-borrow generating circuit 2022 .

[0137] See also Figure 10 As shown in FIG, it is a structural diagram of the control circuit 2021. Figure 10 As shown, the control circuit 2021 may include: a third switch tube S3, a fourth switch tube S4 corresponding to each judgment circuit one-to-one, and a fourth switch tube S4 corresponding to each S3 one-to-one.

[0138] Figure 9The connection relationship between the components in the control circuit 2021 shown can be: the first end of S3 is connected to the power supply, the second end of S3 is connected to the first node, and the first node is used to output the second control signal; the first end of each S4 is connected to the first node, and the control end of each S4 is used to receive the third control signal output by the corresponding judgment circuit; the first end of each S5 is connected to the second end of the corresponding S4, and the second end of each S5 is connected to the ground line. The power supply can be the power supply inside the memory 200 or an external power supply connected to the memory 200.

[0139] use Figure 10 When the control circuit shown detects whether the status of each binary value in the count starting value has been updated, the control end of each S4 can receive a third control signal, and the third control signal is used to indicate whether the status update of the corresponding binary value of the connected carry-borrow generating circuit has been completed. When the third switch tube receives the third control signal of a high-level signal, indicating that no carry-borrow occurs in the corresponding binary value of the third control signal of the high-level signal, the status update of the entire count starting value is completed. At this time, S4 receiving the high-level signal third control signal is turned on, and the potential of the first node is pulled down to zero, and a low-level second control signal indicating that the count starting value has been updated is sent to the data write-back circuit 203 to control the data write-back circuit 203 to perform data write-back and write the most recent calculation result into the storage unit 201.

[0140] In actual use, the control circuit 2021 receives the third control signal once each time the processor sends the first control signal to modify the starting value of the count. When the starting value of the count is not modified, the multiple fourth control signals in the control circuit 2021 may present corresponding level states. In order to avoid detection errors, when the first control signal is not received, a low-level signal can be sent to the control end of the fifth switch tube in the control circuit 2021, the fifth switch tube is disconnected, and all fourth switch tubes cannot receive the third control signal. When the first control signal is received, a high-level signal is sent to the control end of the fifth switch tube, the fifth switch tube is turned on, the fourth switch tube receives the third control signal, and outputs the corresponding second control signal according to the first node of the third control signal.

[0141] 3. Data write-back circuit 203

[0142] The data write-back circuit 203 is connected to the storage unit 201 and the carry / borrow determination circuit 202 respectively, and is configured to receive a second control signal sent by the carry / borrow determination circuit 202 and update the count start value stored in the storage unit 201 according to the second control signal.

[0143] The data write-back circuit 203 may include a sub-data write-back circuit connected to each carry-borrow generating circuit 2022 in a one-to-one correspondence.

[0144] Specifically, the i-th sub-data write-back circuit is connected to the control circuit 2021 and the storage unit 201, respectively, and is used to receive the second control signal and the i-th carry-borrow signal output by the connected i-th carry-borrow generation circuit 2022, and update the i-th binary value in the counting start value stored in the storage unit 201 according to the received signal.

[0145] For ease of understanding, the specific circuit structures of the i-th sub-data write-back circuit are given below.

[0146] In a possible implementation, each sub-data write-back circuit is connected to the third input port and the fourth input port of the storage unit 201 .

[0147] In another possible implementation, the i-th sub-data write-back circuit is connected to the first input port in the storage unit 201 for receiving the i-th binary value, and each sub-data write-back circuit is connected to the second input port in the storage unit 201 for receiving the inverted value of the i-th binary value.

[0148] See also Figure 11 , is a schematic diagram of the structure of the sub-data write-back circuit. Figure 11 As shown, the sub-data write-back circuit includes: a first NOT gate circuit Z5, a third AND gate circuit Z6, a second multiplexer K2, a third delay circuit D3, a second NOT gate circuit Z7, a differential amplifier U2 and a third multiplexer K3.

[0149] Figure 10The connection relationship of each device in the sub-data write-back circuit shown is: the input end of Z5 is connected to the output end of the control circuit 2021, and the output end of Z5 is connected to the second input end of the third AND gate circuit; the first input end of Z6 is used to receive the first enable signal, the third input end of Z6 is connected to the input end of the corresponding carry-borrow generation circuit, and is used to receive the second carry-borrow signal, the output end of Z6 is connected to the first input end of K2, and the first enable signal is generated by the processor calculating the counting starting value; the second input end of K2 is connected to the first input end of the second AND gate circuit, and the output end of K2 is respectively connected to the input end of D3 and the input end of Z7, and the control end of K2 is used to receive the second enable signal. Signal, the second enable signal is generated by the processor accessing the memory; the output end of D3 is connected to the third input port in the storage unit 201; the output end of Z7 is connected to the fourth input port in the storage unit 201; the first input end of U2 is connected to the third output port of the storage unit 201, for receiving the i-th binary value, the second input end of U2 is connected to the fourth output port, for receiving the inverse value of the i-th binary value, the output end of U2 is connected to the first input end of K3; the second input end of K3 is connected to the data access port, the output end of K3 is respectively connected to the input end of D3 and the input end of Z7, and the control end of K3 receives the second enable signal. Among them, the processor accesses the memory 200 provided in the embodiment of the present application through the above-mentioned data access port. In specific implementation, the first enable signal and the second enable signal can be sent by the processor, or sent by the controller after receiving the first control signal.

[0150] In actual use, in order to avoid the influence of the i-th carry-borrow signal output by the connected carry-borrow generation circuit 2022 during the last calculation and the i-1-th carry-borrow signal received on the detection, the third input terminal of Z6 can be connected to the second end of the first switch tube in the carry-borrow generation circuit 2022, so as to obtain the second carry-borrow signal received by the connected carry-borrow generation circuit 2022 during the current calculation of the count starting value, so as to ensure the accuracy of the detection result.

[0151] use Figure 11When the i-th sub-data write-back circuit shown updates the i-th binary value, when the first control signal sent by the processor is received and the second control signal received is a low-level signal, if the second enable signal is a low-level signal, the sub-data write-back circuit outputs the data sent by the processor to the storage unit 201 through the data access port for storage. If the second enable signal is a high-level signal, the sub-data write-back circuit updates the i-th binary value stored in the storage unit. Specifically, when the second carry-borrow signal received by the carry-borrow generation circuit connected to Z6 is 0, it means that the state of the corresponding binary value has not changed, then K2 and K3 are closed, and the i-th binary value stored in the storage unit 201 remains unchanged. If the second carry-borrow signal received by the carry-borrow generation circuit of Z6 is 1, the state of the corresponding binary value changes, Z6 outputs a high-level signal, K2 is disconnected, and K3 outputs the inverted value of the i-th binary value stored in U2 to the storage unit.

[0152] In a specific implementation, after K3 outputs the updated binary value, Z7 and D3 are used to convert the K3 output signal into two signals with opposite states, which are then output to the storage unit for storage. The delay time of D3 is the same as the device delay time of Z7.

[0153] In a specific implementation, when the second enable signal is a high-level signal, it indicates that the processor directly reads the stored value in the memory, and the processor can directly read the data stored in the storage unit through the second input terminal of K3.

[0154] In one example, if the counting start value is the address of the address register, after the address is updated, the processor may send a high-level second enable signal through the memory and send the updated address to the address register through the data bus.

[0155] In combination with the above description, for example, a memory provided in an embodiment of the present application can be as follows Figure 12 shown.

[0156] The carry / borrow determination circuit includes multiple amplifier circuits U1 and U2, a multiplexer switch K1, switches S1, S2, S3, S4, and S5, delay circuits D1 and D3, a first AND gate circuit Z1, and a first XOR gate circuit Z2. K1, S1, S2, and Z1 form a carry / borrow generation circuit, D1 and Z2 form a judgment circuit, and S3, S4, and S5 form a control circuit.

[0157] The data write-back circuit includes: a plurality of first NOT gate circuits Z5, a third AND gate circuit Z6, second multiplexer switches K2 and K3, a third delay circuit D3, a second NOT gate circuit Z7, and a differential amplifier U2. Z5, Z6, K2, K3, D3, Z7, U2, and K3 constitute a sub-data write-back circuit.

[0158] The following combination Figure 12 The working process of the memory is described in detail.

[0159] See also Figure 13 , processor to Figure 12 When the memory sends an access instruction, the processor sends a second enable signal of 1 to the multiple sub-data write-back circuits. At this time, the memory operates in access mode. When the second enable signal is 0, the memory operates in calculation mode. 1 is a high-level signal, and 0 is a low-level signal.

[0160] In one example, the storage unit 201 can receive the value to be calculated sent by the processor and store it as the counting start value. The counting start value is an N-bit binary value. Take the i-th binary value of the counting start value stored in the storage unit as an example, Figure 12 As shown, when the second enable signal received by K2 and K3 in the i-th sub-data write-back circuit is 1, K3 outputs the data received at the data access port to D3 and Z7 respectively. At this time, the processor can output 1 to D3 and Z7 through the data access port, D3 delays 1, and Z7 inverts 1 to 0, and then stores 0 and 1 in the storage unit respectively through the data transmission line connected between the storage units.

[0161] In actual use, when the second enable signal 1 is received, after the transmission delay of the i-th sub-data write-back circuit and the storage delay of the storage unit, the first output port will re-store 1 output, and the second output port will output the inverse value 0 of the stored 1.

[0162] Taking the i-th binary value of the counting starting value as 0 as an example, when Figure 12 When the memory shown in FIG. 1 is operating in calculation mode, the third output port 0 and the fourth output port of the memory unit are 1 and output to the corresponding i-th carry-borrow generation circuit. Before receiving the first control signal, a temporary pulse signal of a low-level signal 0 is sent to the control terminal of S1 and a high-level signal 1 is sent to S2 to initialize the i-th carry-borrow generation circuit. The signal is as follows: Figure 14As shown, S1 is disconnected and does not receive the i-1th carry-borrow signal received during the last calculation. S2 is closed to pull the input end of Z1 down to 0, and Z1 does not receive the signal. When the pulse signals received by S1 and S2 end, S1 receives a high-level signal 1, receives the i-1th carry-borrow signal and outputs S2. S2 receives a low-level signal 1 and disconnects and transmits the i-1th carry-borrow signal received by S1 to Z1. If the i-1th carry-borrow signal is a high-level signal 1, the i-th carry-borrow signal output by Z1 is 0 and output to one input end of Z2. D1 outputs the delayed i-1th carry-borrow signal 1 to the other input end of Z2. Z2 outputs a high-level signal 1 and transmits it to the control end of S4. Before receiving the control signal sent by Z2 and after receiving the first control signal, S4 first sends a low-level signal pulse signal to the control end of S5. S5 is disconnected, and all S4 are Unable to receive a signal, wait for the pulse signal to end, S5 receives a high-level signal 1 and turns on, S4 receives a high-level signal 1 sent by Z2 and turns on, the potential of the first node is pulled down to 0, the signal is inverted by Z5 to 1 and output to one input terminal of Z6, the other input terminal of Z6 receives a high-level first enable signal 1 for controlling the calculation, and the other terminal of Z6 receives the i-1th carry-borrow signal 1, Z6 outputs a high-level signal 1, at this time K2 is disconnected, U2 outputs the inverted value 0 of the i-bit binary value received at the second input port to D3 and Z7, D3 delays the low-level signal 0 and outputs it to the third input port of the storage unit, Z7 inverts the low-level signal 0 to 1 and outputs it to the fourth input port of the storage unit, and after the signals output by D3 and Z7 are transmitted to the storage unit, the i-th binary value of the count start value stored in the storage unit is overwritten, thus updating the i-th binary value. At this time, the third input port of the storage unit outputs 0, and the fourth output port outputs 1.

[0163] And so on, all binary values ​​in the stored count start value are updated.

[0164] It should be noted that, based on the judgment circuit structure provided in the aforementioned embodiments and the different types of switching tubes in the memory, the over-power protection circuit provided in the embodiments of the present application also has other structures. The principles of other circuit structures are the same, and this application will not introduce them in detail one by one.

[0165] Based on the same inventive concept, the present application also provides a computer. Figure 15 The computer 1500 includes a processor 1501 and the aforementioned memory 200.

[0166] The processor 1501 is connected to the aforementioned memory 200.

[0167] Optionally, the computer also includes a data bus 1502 .

[0168] Specifically, the processor 1501 is connected to the memory via a data bus 1502 .

[0169] The computer 1500 also includes some external devices, such as input devices, for receiving input digital information, character information or contact touch operations / non-contact gestures, and generating signal inputs related to user settings and function controls of the computer 1500.

[0170] In addition to the above, computer 1500 may also include a power supply for powering other modules. Computer 1500 may also include one or more sensors, such as an image sensor, a brightness sensor, a light sensor, a GPS sensor, an infrared sensor, etc. Computer 1500 may also include a radio frequency (RF) circuit for communicating with wireless network devices, and a WiFi module for communicating with other devices via WiFi to acquire images or data transmitted by other devices.

[0171] It should be noted that the term "plurality" in this application refers to two or more.

[0172] The connection involved in this application describes the connection relationship between two objects and can represent two connection relationships. For example, the connection between A and B can represent two situations: A is directly connected to B, and A is connected to B through C.

[0173] In addition, it should be understood that, in the description of this application, words such as "first" and "second" are only used for the purpose of distinguishing the description, and cannot be understood as indicating or implying relative importance, nor can they be understood as indicating or implying order.

[0174] In addition, the system structure and business scenarios provided in the embodiments of this application are mainly intended to explain some possible implementation methods of the technical solution of this application and should not be interpreted as limiting the sole nature of the technical solution of this application. Those skilled in the art will appreciate that as the system evolves and newer business scenarios emerge, the technical solutions provided in this application will continue to be applicable to the same or similar technical problems.

[0175] Obviously, those skilled in the art may make various modifications and variations to this application without departing from the scope of protection of this application. Thus, if these modifications and variations of this application fall within the scope of the claims of this application and their equivalents, this application is intended to include these modifications and variations.

Claims

1. A memory, characterized in that: include: A storage unit, a carry and borrow determination circuit, and a data write-back circuit; wherein the storage unit stores a counting start value; The storage unit is used to output the counting starting value to the carry and borrow determination circuit; The carry and borrow determination circuit is configured to generate a second control signal according to a first control signal sent by the processor for modifying the counting start value and the counting start value; The data write-back circuit is used to receive the second control signal and update the counting start value stored in the storage unit according to the second control signal; The counting starting value is an N-bit binary value, and the carry-borrow determination circuit includes: a control circuit, a carry-borrow generation circuit corresponding one-to-one to each bit of the binary value, and a judgment circuit connected one-to-one to each carry-borrow generation circuit; wherein N is an integer greater than or equal to 2.

2. The memory according to claim 1, wherein The memory further includes: a controller; The controller is configured to control the carry and borrow determination circuit to generate the second control signal and control the data write-back circuit to update the count start value stored in the storage unit when receiving the first control signal.

3. The memory according to claim 1, wherein The i-th carry-borrow generating circuit is configured to receive the i-th binary value of the counting starting value, and generate an i-th carry-borrow signal according to the first control signal and the i-th binary value, and output the i-th carry-borrow signal to the i+1-th carry-borrow generating circuit; the i+1-th carry-borrow generating circuit receives the i+1-th binary value of the counting starting value, and the i+1-th binary value is a high-order binary value adjacent to the i-th binary value; The i-th judgment circuit is connected to the control circuit and is used to receive the i-th carry-borrow signal output by the i-th carry-borrow generating circuit, and send a third control signal to the control circuit based on the received signal, wherein the third control signal is used to indicate whether the i-th binary value has been updated; The control circuit is connected to the data write-back circuit, and is configured to generate the second control signal according to the third control signal output by each of the judgment circuits, and output the second control signal to the data write-back circuit.

4. The memory according to claim 3, wherein If i is equal to 1, the i-th carry-borrow generating circuit is specifically configured to receive the i-th binary value of the counting start value, generate an i-th carry-borrow signal according to the first control signal and the i-th binary value, and output the i-th carry-borrow signal to the i+1-th carry-borrow generating circuit; The i-th judgment circuit is specifically configured to: receive the i-th carry-borrow signal, and send a third control signal to the control circuit according to the received signal; If i is greater than 1, the i-th carry-borrow generating circuit is specifically configured to receive the i-th binary value of the counting start value and the i-1-th carry-borrow signal, generate the i-th carry-borrow signal according to the first control signal, the i-th binary value and the i-1-th carry-borrow signal, and output the i-th carry-borrow signal to the i+1-th carry-borrow generating circuit; The i-th judgment circuit is specifically configured to receive the i-th carry-borrow signal and the i-1-th carry-borrow signal, and send a third control signal to the control circuit based on the received signals.

5. The memory according to claim 4, wherein The storage unit is provided with an output port; wherein the output port of the storage unit is used to output the N-bit binary value and the inverse value of the N-bit binary value; If i is greater than 1, the i-th carry-borrow generating circuit includes: an amplifier circuit, wherein a first input end of the amplifier circuit is connected to the output port of the storage unit, a second input end of the amplifier circuit is connected to the output port of the storage unit, a first output end of the amplifier circuit is connected to the first input end of a first multiplexer, and a second output end of the amplifier circuit is connected to the second input end of the first multiplexer; The first multi-way selection switch, wherein the control end of the first multi-way selection switch is used to receive the first control signal, and the output end of the first multi-way selection switch is connected to the second input end of the first AND gate circuit; a first switching transistor, wherein a first end of the first switching transistor is used to receive the i-1 carry-borrow signals, and a second end of the first switching transistor is respectively connected to the first input end of the first AND gate circuit and the second end of the second switching transistor; The second switch tube, wherein the first end of the second switch tube is connected to the ground line; The first AND gate circuit, the output end of the first AND gate circuit is used to output the i-th carry-borrow signal.

6. The memory according to any one of claims 3 to 5, wherein: If i is greater than 1, the i-th judgment circuit includes: a first delay circuit, wherein an input end of the first delay circuit is connected to the corresponding i-th carry-borrow generating circuit and is configured to receive the (i-1)-th carry-borrow signal, and an output end of the first delay circuit is connected to a first input end of a first XOR gate circuit; The first XOR gate circuit, the second input end of the first XOR gate circuit is connected to the corresponding i-th carry-borrow generation circuit, for receiving the i-th carry-borrow signal, and the output end of the first XOR gate circuit is used to output the third control signal.

7. The memory according to any one of claims 3 to 5, wherein: If i is greater than 1, the i-th judgment circuit includes: a second XOR gate circuit, wherein a first input end of the second XOR gate circuit is connected to the corresponding i-th carry-borrow generating circuit for receiving the i-th carry-borrow signal, a second input end of the second XOR gate circuit is connected to the corresponding carry-borrow generating circuit for receiving the i-1-th carry-borrow signal, and an output end of the second XOR gate circuit is respectively connected to the input end of the second delay circuit and the first input end of the second AND gate circuit; the second delay circuit, wherein the output terminal of the second delay circuit is connected to the second input terminal of the second AND gate circuit; The second AND gate circuit, the output end of the second AND gate circuit is used to output the third control signal.

8. The memory according to any one of claims 3 to 5, wherein: The control circuit comprises: a third switch tube, wherein a first end of the third switch tube is connected to the power supply, and a second end of the third switch tube is connected to a first node, and the first node is used to output the second control signal; a fourth switch tube corresponding one-to-one to each of the judgment circuits, wherein a first terminal of each of the fourth switch tubes is connected to the first node, and a control terminal of each of the fourth switch tubes is used to receive a third control signal output by the corresponding judgment circuit; A fifth switching tube corresponds one-to-one to each fourth switching tube, a first end of each fifth switching tube is connected to the second end of the corresponding fourth switching tube, and a second end of each fifth switching tube is connected to the ground line.

9. The memory according to claim 7, wherein: The data write-back circuit includes: a sub-data write-back circuit connected to each of the carry-borrow generating circuits in a one-to-one correspondence; The i-th sub-data write-back circuit is connected to the control circuit and the storage unit respectively, and is used to receive the second control signal and the i-th carry-borrow signal, and update the i-th binary value in the counting start value stored in the storage unit according to the received signal.

10. The memory according to claim 9, wherein The i-th sub-data write-back circuit includes: a first NOT gate circuit, wherein an input end of the first NOT gate circuit is connected to an output end of the control circuit, and an output end of the first NOT gate circuit is connected to a second input end of a third AND gate circuit; The third AND gate circuit, wherein the first input terminal of the third AND gate circuit is used to receive a first enable signal, the third input terminal of the third AND gate circuit is connected to the output terminal of the corresponding carry-borrow generating circuit, the output terminal of the third AND gate circuit is connected to the first input terminal of the second multiplexer, and the first enable signal is generated by the processor by calculating the counting start value; the second multiplexer, wherein a second input terminal of the second multiplexer is connected to the first input terminal of the second AND gate circuit, an output terminal of the second multiplexer is respectively connected to an input terminal of the third delay circuit and an input terminal of the second NOT gate circuit, and a control terminal of the second multiplexer is configured to receive a second enable signal, where the second enable signal is generated by the processor when accessing the memory; The third delay circuit, wherein the output end of the third delay circuit is connected to the storage unit; The second NOT gate circuit, wherein the output end of the second NOT gate circuit is connected to the storage unit; a differential amplifier, wherein a first input terminal of the differential amplifier is used to receive the i-th binary value, a second input terminal of the differential amplifier is used to receive the inverted value of the i-th binary value, and an output terminal of the differential amplifier is connected to the first input terminal of the third multiplexer; The third multiplexer switch, the second input end of the third multiplexer switch is connected to the data access port, the output end of the third multiplexer switch is respectively connected to the input end of the third delay circuit and the input end of the second NOT gate circuit, the control end of the third multiplexer switch is used to receive the second enable signal, and the processor accesses the memory through the data access port.

11. The memory according to any one of claims 1 to 5, wherein: The controller is further configured to control the data write-back circuit to store the data sent by the processor into the storage unit; or The data stored in the storage unit is output to the processor.

12. The memory according to any one of claims 1 to 5, wherein: The counting start value is the address stored in the address register.

13. A computer, characterized in that: comprising a processor and a memory according to any one of claims 1 to 12; The processor is connected to the memory.

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