A low-voltage-dropout linear regulator, chip, and electronic device with current-limiting protection

Abstract

The present invention discloses a low-voltage-dropout linear regulator, chip, and electronic device with current-limiting protection. The low-voltage-dropout linear regulator includes an LDO main circuit, a control voltage circuit, and a current-limiting protection circuit. The input end of the LDO main circuit is connected to an externally introduced reference voltage end, the first output end is connected to the first input end of the current-limiting protection circuit, and the second output end is connected to the input end of the control voltage circuit and the output end of the low-voltage-dropout linear regulator, respectively; the output end of the control voltage circuit is connected to the second input end of the current-limiting protection circuit; and the output end of the current-limiting protection circuit is connected to the control end of the LDO main circuit. By adopting a technical solution of a dual-loop negative feedback structure, the low-voltage-dropout linear regulator achieves current-limiting protection for the low-voltage-dropout linear regulator when the load current exceeds the set current-limiting value, thereby improving the reliability of the power supply.

Description

Technical Field

[0001] The present invention relates to a low-voltage-dropout linear regulator with current-limiting protection, and also relates to an integrated circuit chip including the low-voltage-dropout linear regulator and corresponding electronic equipment, belonging to the technical field of analog integrated circuits. Background Art

[0002] A low-dropout linear regulator (LDO) is a voltage-regulated power supply featuring excellent performance characteristics such as low power consumption, low noise, and a high power supply rejection ratio. It is widely used in various integrated circuits and electronic devices. Therefore, the reliability of the LDO circuit's power supply is a very important performance indicator. In practical applications, when the load current of an LDO circuit exceeds its rated current, the power transistor will generate significant heat loss, and the power supply system may burn out. The configuration of a current-limiting protection function in the LDO circuit can greatly improve the reliability of the LDO circuit's power supply.

[0003] In addition, in the RF front-end module of the communication system, the power amplifier places higher demands on the overcurrent protection function of the LDO module. It not only requires the LDO overcurrent protection to have high accuracy, but also requires that when the current drawn by the power amplifier exceeds its maximum rated current, the LDO output current remains at the maximum rated current of the power amplifier while the LDO output voltage is required to drop to prevent burning of the power amplifier and RF devices such as filters on the same link.

[0004] Chinese patent application number 201710012599.4 discloses an overcurrent protection circuit for a low-dropout linear regulator. Its main principle is to accurately replicate the power tube current at a certain ratio, then use a current comparator to generate an overcurrent flip-flop signal. This signal is used to pull the power tube gate up to the system power supply voltage, thereby achieving current limiting. While this circuit can achieve current limiting to a certain extent, it has two significant problems: first, the current replication accuracy is limited; second, hard shutdown is required to achieve current limiting. Separately, Chinese invention patent number ZL201610362624.7 discloses an overcurrent protection circuit for a low-dropout linear regulator. This circuit operates by detecting the gate voltage of the power tube. As the current in the power tube increases, its gate voltage decreases, causing the transistor in the overcurrent protection execution circuit to turn on. The transistor's VBE clamps the gate voltage of the power tube, preventing the output current from increasing further, thus achieving current limiting. Although the working principle of this circuit is simple, its reliability is poor and the overcurrent protection execution circuit has poor anti-interference ability, which may lead to the problem of back-and-forth oscillation near the current limit point. Summary of the Invention

[0005] The primary technical problem to be solved by the present invention is to provide a low voltage dropout linear regulator with current limiting protection.

[0006] Another technical problem to be solved by the present invention is to provide an integrated circuit chip and an electronic device including the low voltage dropout linear regulator.

[0007] In order to achieve the above object, the present invention adopts the following technical solutions:

[0008] According to a first aspect of an embodiment of the present invention, a low-dropout linear regulator with current limiting protection is provided, comprising an LDO main circuit, a control voltage circuit and a current limiting protection circuit; wherein,

[0009] The LDO main circuit is used to generate an output voltage according to a reference voltage and provide it to the load circuit, and to generate a first control voltage and input it into the current limiting protection circuit;

[0010] The control voltage circuit is used to generate a second control voltage according to a reference current source and the output voltage and input the second control voltage into the current limiting protection circuit;

[0011] The current limiting protection circuit is used to turn on or off the current limiting protection function according to the first control voltage and the second control voltage; when the current limiting protection function is turned on, the gate voltage of the power tube in the LDO main circuit is clamped to achieve current limiting protection of the low voltage difference linear regulator.

[0012] Preferably, the input end of the LDO main circuit is connected to the externally introduced reference voltage end, the first output end is connected to the first input end of the current limiting protection circuit, and the second output end is respectively connected to the input end of the control voltage circuit and the output end of the low-voltage difference linear regulator; the output end of the control voltage circuit is connected to the second input end of the current limiting protection circuit; and the output end of the current limiting protection circuit is connected to the control end of the LDO main circuit, forming a closed control loop.

[0013] Preferably, the LDO main circuit includes a first operational amplifier, a first PMOS transistor, a first sampling resistor, a first feedback resistor and a second feedback resistor; wherein,

[0014] The first PMOS tube, the first operational amplifier, the first sampling resistor, and the first feedback resistor form a first negative feedback loop, which controls the normal operation of the low-dropout linear regulator and provides the stable output voltage.

[0015] Preferably, the inverting input terminal of the first operational amplifier is connected to an externally introduced reference voltage terminal, the output terminal of the first operational amplifier is connected to the gate of the first PMOS transistor on the one hand, and is connected to the output terminal of the current limiting protection circuit as a control terminal on the other hand; the source of the first PMOS transistor is connected to the power supply terminal, the drain of the first PMOS transistor is connected to the first sampling resistor on the one hand, and is connected to the first input terminal of the current limiting protection circuit as a first output terminal on the other hand; the other end of the first sampling resistor is connected to the first feedback resistor on the one hand, and is connected to the output terminal of the low-dropout linear regulator and the input terminal of the control voltage circuit as a second output terminal on the other hand; the other end of the first feedback resistor is connected to the second feedback resistor and the non-inverting input terminal of the first operational amplifier; and the other end of the second feedback resistor is connected to the ground potential terminal.

[0016] Preferably, the first control voltage generated by the LDO main circuit satisfies the following formula:

[0017] V N =I L R S +V OuT

[0018] Among them, V N is the first control voltage, I L is the load current, R S is the resistance value of the first sampling resistor, V OUT is the output voltage.

[0019] Preferably, the control voltage circuit includes a reference current source and a second sampling resistor; wherein,

[0020] An input end of the reference current source is connected to the power supply end, an output end of the reference current source is connected to the second sampling resistor on one hand, and is connected to the second input end of the current limiting protection circuit as an output end on the other hand; the other end of the second sampling resistor is connected to the output end of the low-dropout linear regulator on one hand as an input end, and is connected to the second output end of the LDO main circuit on the other hand.

[0021] Preferably, the second control voltage generated by the control voltage circuit satisfies the following formula:

[0022] V P =I ref R F +V OUT

[0023] Among them, V P is the second control voltage, I ref is the output current of the reference current source, R Fis the resistance value of the second sampling resistor, V OUT is the output voltage.

[0024] Preferably, the current limiting protection circuit includes a second operational amplifier and a second PMOS tube; wherein,

[0025] The inverting input terminal of the second operational amplifier is connected to the first output terminal of the LDO main circuit as the first input terminal; the non-inverting input terminal of the second operational amplifier is connected to the output terminal of the control voltage circuit as the second input terminal; the output terminal of the second operational amplifier is connected to the gate of the second PMOS transistor, the source of the second PMOS transistor is connected to the power supply terminal, and the drain of the second PMOS transistor is connected to the control terminal of the LDO main circuit as the output terminal.

[0026] Preferably, the second operational amplifier, the second PMOS transistor and the first PMOS transistor form a second negative feedback loop, which dominates the current limiting protection of the low-dropout linear regulator and limits the load current to a set current limiting value.

[0027] Preferably, when the load current is less than the set current limit value, the second control voltage is greater than the first control voltage, the current limiting protection function is in an off state, and the first negative feedback loop dominates the normal operation of the low-voltage difference linear regulator to provide a stable output voltage.

[0028] Preferably, when the load current is greater than the set current limit value, the second control voltage is less than the first control voltage, the current limiting protection function is in the on state, the second negative feedback loop dominates the current limiting protection of the low voltage difference linear regulator, and the load current begins to decrease.

[0029] Preferably, when the load current is equal to the set current limit value, the second control voltage is equal to the first control voltage, the current limiting protection function is turned on, and the second negative feedback loop clamps the gate voltage of the power tube to limit the load current to the set current limit value, and satisfies the following formula:

[0030]

[0031] Among them, I limit is the set current limit value, I ref is the output current of the reference current source, R F is the resistance value of the second sampling resistor, R S is the resistance value of the first sampling resistor.

[0032] According to a second aspect of an embodiment of the present invention, an integrated circuit chip is provided. The integrated circuit chip includes the above-mentioned low-dropout linear regulator with current limiting protection.

[0033] According to a third aspect of an embodiment of the present invention, an electronic device is provided, wherein the electronic device includes the above-mentioned low-dropout linear regulator with current limiting protection.

[0034] Compared with the prior art, the low-voltage dropout linear regulator with current-limiting protection provided by the present invention utilizes a dual-loop negative feedback structure. This ensures that when the load current exceeds the current limit, the first negative feedback loop switches to the second negative feedback loop, effectively protecting the power transistors and related electronic components in the LDO main circuit. This significantly improves power supply reliability while preventing the power supply system from experiencing a hard shutdown. Therefore, the low-voltage dropout linear regulator with current-limiting protection provided by the present invention offers the advantages of a clever and rational structural design, low design cost, high current-limiting protection accuracy, and excellent circuit performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] Figure 1 A circuit schematic diagram of a low-dropout linear regulator with current limiting protection provided by the present invention;

[0036] Figure 2 This is a current limiting effect diagram of a low-dropout linear regulator with current limiting protection in an embodiment of the present invention;

[0037] Figure 3 The figure is a schematic diagram of an electronic device using the low-dropout linear regulator with current limiting protection provided by the present invention. DETAILED DESCRIPTION

[0038] The technical content of the present invention is described in detail below with reference to the accompanying drawings and specific embodiments.

[0039] like Figure 1 As shown, the present invention provides a low-voltage difference linear regulator with current limiting protection, which includes an LDO main circuit, a control voltage circuit and a current limiting protection circuit. Among them, the input end of the LDO main circuit is connected to the reference voltage end introduced externally, the first output end is connected to the first input end of the current limiting protection circuit, and the second output end is respectively connected to the input end of the control voltage circuit and the output end of the low-voltage difference linear regulator; the output end of the control voltage circuit is connected to the second input end of the current limiting protection circuit; the output end of the current limiting protection circuit is connected to the control end of the LDO main circuit to form a closed control loop. In addition, the output end of the low-voltage difference linear regulator is connected to the load circuit to provide it with a power supply voltage V OUT In this application, the load circuit is connected in parallel with the load capacitor C L and the load resistor R L To express.

[0040] The LDO main circuit is used to input the reference voltage V REF , generating an output voltage V OUTProvided to the load circuit and forms the load current I L ; Generate a first control voltage V N Input current limiting protection circuit.

[0041] The control voltage circuit is used to control the current source I ref and the output voltage V OUT , generating a second control voltage V P , and input current limiting protection circuit.

[0042] The current limiting protection circuit is used to control the current according to the first control voltage V N and the second control voltage V P , turn on or off the current limiting protection function; when the current limiting protection function is turned on, the gate voltage of the power tube in the LDO main circuit is clamped and controlled to achieve current limiting protection for the low voltage difference linear regulator.

[0043] In one embodiment of the present invention, the LDO main circuit includes a first operational amplifier OP1, a first PMOS transistor PM1, a first sampling resistor R S , a first feedback resistor R1 and a second feedback resistor R2. The inverting input terminal of the first operational amplifier OP1 is connected to the externally introduced reference voltage terminal, the output terminal of the first operational amplifier OP1 is connected to the gate of the first PMOS transistor PM1 on one hand, and is connected to the output terminal of the current limiting protection circuit as a control terminal on the other hand; the source of the first PMOS transistor PM1 is connected to the power supply terminal VDD, and the drain of the first PMOS transistor PM1 is connected to the first sampling resistor R S connected, and on the other hand, connected as a first output terminal to a first input terminal of a current limiting protection circuit; a first sampling resistor R S The other end of the resistor R1 is connected to the first feedback resistor R1 on the one hand, and is connected to the output end of the low-dropout linear regulator and the input end of the control voltage circuit as the second output end on the other hand; the other end of the first feedback resistor R1 is connected to the second feedback resistor R2 and the non-inverting input end of the first operational amplifier OP1; the other end of the second feedback resistor R2 is connected to the ground potential end.

[0044] In the LDO main circuit, the first PMOS transistor PM1 is a power transistor (hereinafter referred to as power transistor PM1) and is the main object of current limiting protection; the first feedback resistor R1 and the first feedback resistor R2 form a voltage divider network to control the output voltage V OUT After voltage division, the feedback voltage V FB , is input to the non-inverting input terminal of the first operational amplifier OP1. The reference voltage V is input to the inverting input terminal of the first operational amplifier OP1. REF The first operational amplifier OP1 is based on the feedback voltage V FB and reference voltage V REFAdjust the gate voltage V of power tube PM1 G , to adapt to the load current I L When the feedback voltage V FB and reference voltage V REF When the voltages are equal, the output of the low-dropout linear regulator generates a stable output voltage V OUT Feedback voltage V FB and a stable output voltage V OUT Satisfies the following formula:

[0045]

[0046] V FB =V REF (2)

[0047]

[0048] Wherein, R1 and R2 are resistance values ​​of the first feedback resistor R1 and the second feedback resistor R2 respectively.

[0049] At the same time, in the LDO main circuit, the first control voltage V generated by the drain node of the power tube PM1 N for:

[0050] V N =I L R S +V OUT (4)

[0051] Among them, R S The first sampling resistor R S The resistance value of I L is the load current.

[0052] It can be seen from formula 4 that the first control voltage V N Can reflect the load current I L The LDO main circuit outputs the first control voltage V N to the current limiting protection circuit.

[0053] In one embodiment of the present invention, the control voltage circuit includes a reference current source I ref and the second sampling resistor R F . Among them, the reference current source I ref The input terminal is connected to the power supply terminal VDD, and the reference current source I ref The output terminal is connected to the second sampling resistor R F connected, and on the other hand, connected as an output terminal to the second input terminal of the current limiting protection circuit; the second sampling resistor R FThe other end is connected to the output of the low voltage drop linear regulator on one hand as the input end, and to the first sampling resistor R in the LDO main circuit on the other hand. S and the first feedback resistor R1.

[0054] The control voltage circuit is based on the reference current source I ref and the output voltage V OUT , the reference current source I ref and the second sampling resistor R F The second control voltage V generated by the connection node P for:

[0055] V P =I ref R F +V OUT (5)

[0056] Among them, R F The second sampling resistor R F The resistance value of I ref is the reference current source I ref The output current (hereinafter referred to as reference current I ref ).

[0057] It can be seen from formula 5 that the second control voltage V P Can reflect the reference current I ref The control voltage circuit outputs the second control voltage V P to the current limiting protection circuit.

[0058] In one embodiment of the present invention, the current limiting protection circuit includes a second operational amplifier OP2 and a second PMOS transistor PM2. The inverting input terminal of the second operational amplifier OP2 is connected as the first input terminal to the drain of the first PMOS transistor PM1 in the LDO main circuit and the first sampling resistor R S The non-inverting input terminal of the second operational amplifier OP2 is connected as the second input terminal to the reference current source I in the control voltage circuit ref The output terminal and the first sampling resistor R F The output terminal of the second operational amplifier OP2 is connected to the gate of the second PMOS transistor PM2, the source of the second PMOS transistor PM2 is connected to the power supply terminal VDD, and the drain of the second PMOS transistor PM2 is connected as an output terminal to the output terminal of the first operational amplifier OP1 in the LDO main circuit and the gate of the first PMOS transistor PM1.

[0059] The main function of the current limiting protection circuit is to control the voltage V N and the second control voltage V P, turning the current limiting protection function on or off. When the current limiting protection function is on, the gate voltage of power transistor PM1 in the LDO main circuit is clamped and controlled to maintain a constant gate voltage, thereby achieving current limiting protection for the power transistor and related electronic components. The specific working process and working principle of this current limiting protection are described in detail below.

[0060] The differential input voltage Vin of the second operational amplifier OP2 can be expressed as:

[0061] V in =V P -V N =I ref R F -I L R S (6)

[0062] The second operational amplifier OP2 generates an output voltage Vc according to the magnitude of the differential input voltage Vin to control the gate potential of the second PMOS transistor PM2, thereby turning the current limiting protection function on or off by controlling the on or off state of the second PMOS transistor PM2.

[0063] The first working condition of overcurrent in low-dropout linear regulator:

[0064] When the load current I L When the second control voltage V P Greater than the first control voltage V N , the differential input voltage V in =V P -V N >0, the output voltage Vc of the second operational amplifier OP2 is a high potential voltage close to the power supply voltage VDD, which turns off the second PMOS transistor PM2. At this time, the current limiting protection function is in the off state and does not participate in the work. The LDO main circuit works normally and generates a stable output voltage V OUT , and its voltage is shown in Formula 3.

[0065] If the load current I L Start from a smaller value and increase, when the load current I L When it increases to a certain value, the second control voltage V P Equal to the first control voltage V N , the differential input voltage V in =V P -V N=0, the input terminal is in a virtual short state, the output voltage Vc of the second operational amplifier OP2 drops to a certain potential value, making the second PMOS transistor PM2 conductive. At this time, the current limiting protection function is in the open state. The drain current of the second PMOS transistor PM2 is input into the output terminal of the first operational amplifier OP1 and the gate of the power transistor PM1 in the LDO main circuit, making the node voltage V G Maintain a constant value, that is, the gate-source voltage V gs Maintain a certain value so that the load current I L No longer increases, achieving the current limiting protection of the low voltage drop linear regulator. L That is the current limit value I limit , satisfying the following formula:

[0066]

[0067] The second working condition of the low-voltage dropout linear regulator when overcurrent occurs:

[0068] When the load current I L When the second control voltage V P Less than the first control voltage V N , the differential input voltage V in =V P -V N <0, the output voltage Vc of the second operational amplifier OP2 is a low potential voltage, which turns on the second PMOS transistor PM2. At this time, the current limiting protection function is in the on state. The drain current of the second PMOS transistor PM2 is input into the output end of the first operational amplifier OP1 and the gate of the power transistor PM1 in the LDO main circuit, changing the node voltage V G , so that the gate-source voltage of power tube PM1│V gs │Decrease, therefore, the drain current of the power tube PM1 decreases, and the load current I L As a result, the first control voltage V N It also decreases and eventually reaches the second control voltage V P Equal to the first control voltage V N , the differential input voltage V of the second operational amplifier OP2 in the current limiting protection circuit in =V P -V N =0, the input terminal is in a virtual short state, the load current I L The load current I L That is the current limit value I limit , current limit value I limit The size of satisfies Formula 7.

[0069] If the load resistance R L Smaller, at this time, the actual output voltage V OUT The actual feedback voltage V in the LDO main circuit will be lower than the output voltage in the steady state shown in Formula 3. FB It is also lower than the reference voltage V in the steady state shown in Formula 2. RE At this time, the first operational amplifier OP1 attempts to pull the gate potential of the power transistor PM1 down to a low potential, but the second PMOS transistor PM2 has no effect on the node potential V G The pull-up capability of the first operational amplifier OP1 is stronger than the pull-down capability of the first operational amplifier OP1. Therefore, when the current-limiting protection function is enabled, the gate voltage of the power transistor PM1 is primarily determined by the clamping control of the second PMOS transistor PM2 in the current-limiting protection circuit. At this point, the output current of the first operational amplifier OP1 in the LDO main circuit becomes the gate bias current of the second PMOS transistor PM2 in the current-limiting protection circuit. These units work together to achieve current-limiting protection for the low-dropout linear regulator.

[0070] If the load resistance R L Further reduction, due to the load current I L is limited to the current limit value I limit , therefore, the actual output voltage of the low dropout linear regulator V OUT The voltage will continue to decrease, and the power supply will not be hard shut down when overcurrent occurs.

[0071] The above is a detailed description of the current limiting protection function of the low voltage drop linear regulator in this embodiment. As can be seen from formula 7, the current limiting value I limit , its accuracy depends on the first sampling resistor R S and the second sampling resistor R F The ratio of the resistors can achieve a very high precision. Therefore, if a reference current source I is given ref The low voltage dropout linear regulator provided by the present invention can realize a high-precision current limiting protection function.

[0072] In the embodiment provided by the present invention, the circuit structure of the low voltage drop linear regulator is provided with two negative feedback loops. The first negative feedback loop is composed of the first operational amplifier OP1, the power tube PM1, the first sampling resistor R S and the first feedback resistor R1. The second negative feedback loop is composed of the power transistor PM1, the second operational amplifier OP2 and the second PMOS transistor PM2. L Less than the current limit value I limit When the current limiting protection function is in the off state and does not participate in the work, the first negative feedback loop dominates the low voltage drop linear regulator to output a stable voltage V OUT When the load current is greater than or equal to the current limit value Ilimit When the current limiting protection function is turned on, the second negative feedback loop dominates the current limiting protection of the low voltage drop linear regulator, and the load current I L is limited to the current limit value I limit , output voltage V OUT will vary with the load resistance R L decreases with the decrease of .

[0073] The current limiting effect of the low voltage difference linear regulator with current limiting protection provided by the embodiment of the present invention is as follows: Figure 2 As shown, the upper part is the output voltage V OUT With the load resistance R L The lower part is the load current I L With the load resistance R L The load current can be expressed as I L =V OUT / R L .from Figure 2 It can be seen that under normal working conditions (see the right side of the dotted line), the first negative feedback loop dominates the work, and the output voltage V OUT The output voltage remains stable regardless of load resistance. L When it gradually decreases and reaches a certain value, as shown by the dotted line in the figure, the load current I L Gradually increases and reaches the current limit value I limit At this time, the current limiting protection function is turned on, and the second negative feedback loop begins to take the lead. The load current I L is limited and no longer increases. As the load resistance R L The continuous decrease of the load current I L Limited, output voltage V OUT The output power of the low-dropout linear regulator gradually decreases as the load current increases, thus effectively protecting the power tube of the LDO main circuit and related electronic components.

[0074] An embodiment of the present invention further provides an integrated circuit chip including the aforementioned low-dropout linear regulator with current limiting protection, which is used as a key component of a power module in an integrated circuit system to provide a stable power supply voltage for the system. The specific structure of the low-dropout linear regulator with current limiting protection in this integrated circuit chip will not be further described herein.

[0075] The low voltage drop linear regulator with current limiting protection provided by the present invention can be used in electronic devices as an important component of the power supply component. Figure 3As shown, the electronic device includes at least a processor, a memory and a power supply component, and may further include a communication component, a sensor component, a multimedia component and an input / output interface according to actual needs. Among them, the memory, communication component, sensor component, power supply component, multimedia component and input / output interface are all connected to the processor. The memory can be a static random access memory (SRAM), an electrically erasable programmable read-only memory (EEPROM), an erasable programmable read-only memory (EPROM), a programmable read-only memory (PROM), a read-only memory (ROM), a magnetic memory, a flash memory, etc., and the processor can be a central processing unit (CPU), a graphics processing unit (GPU), a field programmable gate array (FPGA), an application-specific integrated circuit (ASIC), a digital signal processing (DSP) chip, etc. Other communication components, sensor components, multimedia components, etc. can all be implemented using general components and will not be described in detail here.

[0076] In summary, compared with the prior art, the low-voltage difference linear regulator with current limiting protection provided by the present invention, by adopting the technical solution of a dual-loop negative feedback structure, realizes that when the load current exceeds the current limit value, the first negative feedback loop is switched to the second negative feedback loop, effectively protecting the power tube and related electronic components of the LDO main circuit, greatly improving the reliability of power supply. At the same time, the phenomenon of hard shutdown of the power supply system output will not occur. Therefore, the low-voltage difference linear regulator with current limiting protection provided by the present invention has the beneficial effects of ingenious and reasonable structural design, low design cost, high current limiting protection accuracy, and excellent circuit performance.

[0077] It should be noted that the above embodiments are only examples, and the technical solutions of various embodiments can be combined and are all within the protection scope of the present invention.

[0078] It should be noted that the terms "first" and "second" are used for descriptive purposes only and should not be understood to indicate or imply relative importance or implicitly specify the number of the technical features indicated. Therefore, features defined as "first" or "second" may explicitly or implicitly include one or more of such features. In the description of the present invention, "plurality" means two or more, unless otherwise specifically defined.

[0079] The above describes in detail the low-dropout linear regulator with current-limiting protection, chip, and electronic device provided by the present invention. Any obvious modification to the present invention without departing from its essence would constitute an infringement of the present invention's patent rights and would incur corresponding legal liability.

Claims

1. A low-dropout linear regulator with current limiting protection, characterized in that It includes LDO main circuit, control voltage circuit and current limiting protection circuit; among them, The LDO main circuit is used to generate an output voltage according to a reference voltage and provide it to the load circuit, and to generate a first control voltage and input it into the current limiting protection circuit; The control voltage circuit is used to generate a second control voltage based on a reference current source and the output voltage, and input the second control voltage into the current limiting protection circuit; wherein the control voltage circuit includes a reference current source and a second sampling resistor; the input end of the reference current source is connected to the power supply end, the output end of the reference current source is connected to the second sampling resistor on the one hand, and is connected to the second input end of the current limiting protection circuit as an output end on the other hand; the other end of the second sampling resistor is connected to the output end of the low dropout linear regulator on the one hand, and is connected to the second output end of the LDO main circuit on the other hand; The current limiting protection circuit includes a second operational amplifier and a second PMOS transistor; wherein the inverting input terminal of the second operational amplifier is connected to the first output terminal of the LDO main circuit as the first input terminal; the non-inverting input terminal of the second operational amplifier is connected to the output terminal of the control voltage circuit as the second input terminal; the output terminal of the second operational amplifier is connected to the gate of the second PMOS transistor, the source of the second PMOS transistor is connected to the power supply terminal, and the drain of the second PMOS transistor is connected to the control terminal of the LDO main circuit as the output terminal; The current limiting protection circuit turns on or off the current limiting protection function according to the first control voltage and the second control voltage; when the current limiting protection function is turned on, the gate voltage of the power tube in the LDO main circuit is clamped to achieve current limiting protection of the low voltage difference linear regulator.

2. The low dropout linear regulator according to claim 1, wherein: The input end of the LDO main circuit is connected to an externally introduced reference voltage end, the first output end is connected to the first input end of the current limiting protection circuit, and the second output end is respectively connected to the input end of the control voltage circuit and the output end of the low-voltage difference linear regulator; the output end of the control voltage circuit is connected to the second input end of the current limiting protection circuit; and the output end of the current limiting protection circuit is connected to the control end of the LDO main circuit, forming a closed control loop.

3. The low dropout linear regulator according to claim 1, wherein: The LDO main circuit includes a first operational amplifier, a first PMOS transistor, a first sampling resistor, a first feedback resistor and a second feedback resistor; wherein, The first PMOS tube, the first operational amplifier, the first sampling resistor, and the first feedback resistor form a first negative feedback loop, which controls the normal operation of the low-dropout linear regulator and provides the stable output voltage.

4. The low dropout linear regulator according to claim 3, wherein: The inverting input terminal of the first operational amplifier is connected to an externally introduced reference voltage terminal. The output terminal of the first operational amplifier is connected to the gate of the first PMOS transistor on the one hand, and is connected to the output terminal of the current limiting protection circuit as a control terminal on the other hand. The source of the first PMOS transistor is connected to the power supply terminal. The drain of the first PMOS transistor is connected to the first sampling resistor on the one hand, and is connected to the first input terminal of the current limiting protection circuit as a first output terminal on the other hand. The other end of the first sampling resistor is connected to the first feedback resistor on the one hand, and is connected to the output terminal of the low-dropout linear regulator and the input terminal of the control voltage circuit as a second output terminal on the other hand. The other end of the first feedback resistor is connected to the second feedback resistor and the non-inverting input end of the first operational amplifier; the other end of the second feedback resistor is connected to the ground potential end.

5. The low-dropout linear regulator according to claim 1 or 3, wherein: The first control voltage generated by the LDO main circuit satisfies the following formula: Among them, V N is the first control voltage, I L is the load current, R S is the resistance value of the first sampling resistor, V OUT is the output voltage.

6. The low dropout linear regulator according to claim 1, wherein: The second control voltage generated by the control voltage circuit satisfies the following formula: Among them, V P is the second control voltage, I ref is the output current of the reference current source, R F is the resistance value of the second sampling resistor, V OUT is the output voltage.

7. The low dropout linear regulator according to claim 3, wherein: The second operational amplifier, the second PMOS transistor and the first PMOS transistor form a second negative feedback loop, which dominates the current limiting protection of the low-dropout linear regulator and limits the load current to a set current limiting value.

8. The low dropout linear regulator according to claim 3, wherein: When the load current is less than the set current limit value, the second control voltage is greater than the first control voltage, the current limiting protection function is in the off state, and the first negative feedback loop dominates the normal operation of the low-dropout linear regulator to provide a stable output voltage.

9. The low dropout linear regulator according to claim 7, wherein: When the load current is greater than the set current limit value, the second control voltage is less than the first control voltage, the current limiting protection function is in the on state, the second negative feedback loop dominates the current limiting protection of the low voltage difference linear regulator, and the load current begins to decrease.

10. The low dropout linear regulator according to claim 7, wherein: When the load current is equal to the set current limit value, the second control voltage is equal to the first control voltage, the current limiting protection function is turned on, and the second negative feedback loop clamps the gate voltage of the power tube to limit the load current to the set current limit value, and satisfies the following formula: Among them, I limit is the set current limit value, I ref is the output current of the reference current source, R F is the resistance value of the second sampling resistor, R S is the resistance value of the first sampling resistor.

11. An integrated circuit chip, characterized in that The invention comprises the low voltage dropout linear regulator according to any one of claims 1 to 10.

12. An electronic device, characterized in that The invention comprises the low voltage dropout linear regulator according to any one of claims 1 to 10.

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