Pixel circuit, driving method of pixel circuit, and display panel

Abstract

This invention discloses a pixel circuit, a driving method for the pixel circuit, and a display panel. The pixel circuit includes a first driving module, a second driving module, and a light-emitting module. The first driving module includes a first driving transistor and a first data voltage writing module. The first driving transistor drives the light-emitting module to emit light during the light-emitting phase based on the voltage at its gate and the voltage at its first electrode. The output terminal of the second driving module is connected to the first electrode of the first driving transistor. The second driving module controls the voltage at the first electrode of the first driving transistor based on a second data voltage and a frequency sweep signal to control the light-emitting time of the light-emitting module. The technical solution provided by this invention simplifies the complexity of external driving control signals and voltage signals, improves the reliability of the pixel circuit, increases the switching speed of the light-emitting module's brightness, and improves the switching effect of different grayscale displays at low grayscale levels.

Description

Technical Field

[0001] This invention relates to the field of display technology, and more particularly to a pixel circuit, a pixel circuit driving method, and a display panel. Background Technology

[0002] With the continuous development of display technology, micro light emitting diodes (Micro LEDs) are widely used in the display field due to their advantages such as wide color gamut, fast response speed, high brightness and long life.

[0003] Currently, Micro LED display panels typically include pixel circuits and light-emitting elements. The pixel circuits usually use analog pulse width modulation (PWM) to control the light-emitting elements. However, the external driving signals and voltage signals of the pixel circuits in existing technologies are relatively complex, leading to reduced reliability of the pixel circuits. Summary of the Invention

[0004] This invention provides a pixel circuit, a driving method for the pixel circuit, and a display panel to improve the reliability of the pixel circuit.

[0005] In a first aspect, embodiments of the present invention provide a pixel circuit, including: a first driving module, a second driving module, and a light-emitting module;

[0006] The first driving module includes a first driving transistor and a first data voltage writing module. The first data voltage writing module is used to transmit a first data voltage to the gate of the first driving transistor. The first driving transistor is used to drive the light-emitting module to emit light during the light-emitting phase according to the voltage of the gate and the voltage of the first electrode.

[0007] The output terminal of the second driving module is connected to the first electrode of the first driving transistor. The second driving module is used to control the voltage of the first electrode of the first driving transistor according to the second data voltage and the frequency sweep signal, so as to control the light emission time of the light-emitting module.

[0008] Within a display frame, the light-emitting stage includes multiple sub-light-emitting stages, the frequency sweep signal includes multiple sub-signals, each sub-light-emitting stage corresponds to one sub-signal, and the light-emitting module includes a bright state and a dark state in each sub-light-emitting stage.

[0009] Optionally, the sweep frequency signal includes a sawtooth wave signal or a triangular wave signal.

[0010] Optionally, the second driving module includes a second driving transistor, a first storage module, and a second data voltage writing module; a first terminal of the first storage module is connected to the sweep frequency signal, a second terminal of the first storage module is connected to the gate of the second driving transistor, the second data voltage writing module is used to transmit the second data voltage to the gate of the second driving transistor, and the second driving transistor is used to control the voltage of the first terminal of the first driving transistor according to its own gate voltage;

[0011] During the light-emitting phase, the first driving transistor operates in the saturation region, and the second driving transistor operates in the linear region.

[0012] Optionally, the second driving module further includes a first compensation module, a first light-emitting control module, and a second light-emitting control module. The first compensation module includes a first compensation transistor, the first light-emitting control module includes a first light-emitting control transistor, and the second light-emitting control module includes a second light-emitting control transistor. The second data voltage writing module includes a second data writing transistor, and the first storage module includes a first capacitor.

[0013] The gate of the second data writing transistor is connected to the first scan signal line, the first terminal of the second data writing transistor is connected to the second data voltage, the second terminal of the second data writing transistor is connected to the first terminal of the second driving transistor, the gate of the first compensation transistor is connected to the first scan signal line, the first terminal of the first compensation transistor is connected to the second terminal of the second driving transistor, and the second terminal of the first compensation transistor is connected to the gate of the second driving transistor.

[0014] The gates of the first and second light-emitting control transistors are both connected to the light-emitting control signal line. The first terminal of the first light-emitting control transistor is connected to the first power supply line. The second terminal of the first light-emitting control transistor is connected to the first terminal of the second driving transistor. The first terminal of the second light-emitting control transistor is connected to the second terminal of the second driving transistor. The second terminal of the second light-emitting control transistor is connected to the first terminal of the first driving transistor. The first terminal of the first capacitor is connected to the sweep frequency signal. The second terminal of the first capacitor is connected to the gate of the second driving transistor.

[0015] Preferably, the first data voltage writing module responds to the first data voltage while the second data voltage writing module responds to the second data voltage.

[0016] Optionally, the first driving module further includes a second storage module and a third light-emitting control module, the first data voltage writing module includes a first data writing transistor, the third light-emitting control module includes a third light-emitting control transistor, and the second storage module includes a second capacitor;

[0017] The gate of the third light-emitting control transistor is connected to the light-emitting control signal line. The first terminal of the third light-emitting control transistor is connected to the second terminal of the first driving transistor. The second terminal of the third light-emitting control transistor is connected to the first end of the light-emitting module. The second end of the light-emitting module is connected to the second power supply line. A fixed voltage is applied to the first terminal of the second capacitor. The second terminal of the second capacitor is connected to the gate of the first driving transistor. The gate of the first data writing transistor is connected to the second scan signal line. The first terminal of the first data writing transistor is applied to the first data voltage. The second terminal of the first data writing transistor is connected to the gate of the first driving transistor.

[0018] Optionally, the first driving module further includes a second storage module, a third light-emitting control module, and a second compensation module. The first data voltage writing module includes a first data writing transistor, the third light-emitting control module includes a third light-emitting control transistor, the second storage module includes a second capacitor, and the second compensation module includes a second compensation transistor.

[0019] The gate of the third light-emitting control transistor is connected to the light-emitting control signal line. The first terminal of the third light-emitting control transistor is connected to the second terminal of the first driving transistor. The second terminal of the third light-emitting control transistor is connected to the first end of the light-emitting module. The second end of the light-emitting module is connected to the second power supply line. A fixed voltage is applied to the first terminal of the second capacitor. The second terminal of the second capacitor is connected to the gate of the first driving transistor. The gate of the first data writing transistor is connected to the second scan signal line. The first terminal of the first data writing transistor is applied to the first data voltage. The second terminal of the first data writing transistor is connected to the first terminal of the first driving transistor. The gate of the second compensation transistor is connected to the second scan signal line. The first terminal of the second compensation transistor is connected to the second terminal of the first driving transistor. The second terminal of the second compensation transistor is connected to the gate of the first driving transistor.

[0020] Preferably, the first data voltage and the second data voltage share the same data line.

[0021] Optionally, the first driving module further includes a first initialization module, which includes a first initialization transistor, and the second driving module further includes a second initialization module, which includes a second initialization transistor.

[0022] The gate of the first initialization transistor is connected to the third scan signal line, the first terminal of the first initialization transistor is connected to the initialization signal line, the second terminal of the first initialization transistor is connected to the gate of the first driving transistor, the gate of the second initialization transistor is connected to the fourth scan signal line, the first terminal of the second initialization transistor is connected to the initialization signal line, and the second terminal of the second initialization transistor is connected to the gate of the second driving transistor.

[0023] Secondly, embodiments of the present invention also provide a driving method for a pixel circuit, the pixel circuit including a first driving module, a second driving module and a light-emitting module, the first driving module including a first driving transistor and a first data voltage writing module, and the output terminal of the second driving module being connected to the first electrode of the first driving transistor.

[0024] The driving method for the pixel circuit includes:

[0025] During the first data voltage writing stage, the first data voltage writing module transmits the first data voltage to the gate of the first driving transistor.

[0026] During the light-emitting phase, the second driving module controls the voltage of the first electrode of the first driving transistor according to the second data voltage and the frequency sweep signal, and the first driving transistor drives the light-emitting module to emit light according to the voltage of the gate and the voltage of the first electrode.

[0027] The light emission time of the light-emitting module is controlled by the second data voltage and the frequency sweep signal. Within a display frame, the light emission stage includes multiple sub-light emission stages, and the frequency sweep signal includes multiple sub-signals. Each sub-light emission stage corresponds to one sub-signal. The light-emitting module includes a bright state and a dark state in each sub-light emission stage.

[0028] Optionally, the second driving module includes a second driving transistor and a second data voltage writing module;

[0029] Prior to the light-emitting stage, the driving method of the pixel circuit further includes: in the second data voltage writing stage, the second data voltage writing module transmits the second data voltage to the gate of the second driving transistor.

[0030] Thirdly, embodiments of the present invention also provide a display panel, which includes the pixel circuit provided in any embodiment of the present invention.

[0031] The technical solution provided by this invention connects the output terminal of the second driving module to the first electrode of the first driving transistor, thus connecting the first and second driving modules in series. The second driving module controls the voltage of the first electrode of the first transistor to control the conduction time of the first transistor, thereby controlling the light-emitting time of the light-emitting module. The magnitude of the light-emitting current is controlled by the first driving module. Compared with the prior art, the technical solution provided by this invention uses the second driving module to directly control the light-emitting time of the light-emitting module, while the first driving module is only responsible for controlling the magnitude of the driving current. There is no direct signal control relationship between the first and second driving modules, allowing them to share the same operating voltage. This simplifies the complexity of external driving control signals and voltage signals, and improves the reliability of the pixel circuit. Furthermore, by dividing the light-emitting stage of the pixel circuit into multiple sub-light-emitting stages and the sweep frequency signal into multiple sub-signals, one sub-light-emitting stage corresponds to one sub-signal. This increases the slope of the sweep frequency signal, thereby increasing the switching speed of the driving current and the switching speed of the light-emitting module's brightness, improving the switching effect of different gray levels at low gray levels. Attached Figure Description

[0032] Figure 1 This is a schematic diagram of a pixel circuit provided in an embodiment of the present invention;

[0033] Figure 2 A timing control waveform diagram of a pixel circuit provided in an embodiment of the present invention;

[0034] Figure 3 A waveform diagram of a frequency sweep signal provided in an embodiment of the present invention;

[0035] Figure 4 This is a schematic diagram of another pixel circuit structure provided in an embodiment of the present invention;

[0036] Figure 5 This is a schematic diagram of another pixel circuit structure provided in an embodiment of the present invention;

[0037] Figure 6 This is a schematic diagram of another pixel circuit structure provided in an embodiment of the present invention;

[0038] Figure 7 This is a schematic diagram of another pixel circuit structure provided in an embodiment of the present invention;

[0039] Figure 8 This is a schematic diagram of another pixel circuit structure provided in an embodiment of the present invention;

[0040] Figure 9 A timing control waveform diagram of another pixel circuit provided in an embodiment of the present invention;

[0041] Figure 10 A simulation waveform diagram of a pixel circuit in the light-emitting stage provided for an embodiment of the present invention;

[0042] Figure 11 A timing control waveform diagram of another pixel circuit provided in an embodiment of the present invention;

[0043] Figure 12 A flowchart illustrating a pixel circuit driving method provided in an embodiment of the present invention;

[0044] Figure 13 A flowchart illustrating a pixel circuit driving method provided in an embodiment of the present invention;

[0045] Figure 14 This is a schematic diagram of the structure of a display panel provided in an embodiment of the present invention. Detailed Implementation

[0046] The present invention will now be described in further detail with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and not intended to limit it. Furthermore, it should be noted that, for ease of description, the accompanying drawings show only the parts relevant to the present invention, and not all of the structures.

[0047] As described in the background section, existing pixel circuits with analog PWM drive architectures suffer from poor reliability. The inventors have discovered that this problem arises because existing pixel circuits typically include a PWM drive module and a PAM (Pulse Amplitude Modulation) drive module. The PWM drive module converts the analog grayscale voltage into switching times that control the PAM drive module to generate drive current. Furthermore, a control relationship exists between the PWM and PAM drive modules; the PWM drive module controls the PAM drive module. To ensure the proper functioning of each module, the operating voltages and drive signals of the PWM and PAM drive modules need to be set separately. This complicates the external drive and voltage signals, making errors more likely and significantly reducing the reliability of the pixel circuit's drive performance. Moreover, because the PWM drive module controls the PAM drive module, a data write operation to the PAM drive module is required before each emission, which does not improve the switching speed of the drive current and is detrimental to low grayscale display.

[0048] To address the above problems, embodiments of the present invention provide a pixel circuit to improve the reliability of the pixel circuit. Figure 1 This is a schematic diagram of a pixel circuit provided in an embodiment of the present invention, with reference to... Figure 1The pixel circuit provided in this embodiment of the invention includes a first driving module 110, a second driving module 120, and a light-emitting module 130.

[0049] The first driving module 110 includes a first driving transistor T1 and a first data voltage writing module 101. The first data voltage writing module 101 is used to transmit a first data voltage VDATA1 to the gate G1 of the first driving transistor T1. The first driving transistor T1 is used to drive the light-emitting module 130 to emit light during the light-emitting stage according to the voltage of the gate G1 and the voltage of the first electrode N1.

[0050] The output terminal of the second driving module 120 is connected to the first terminal N1 of the first driving transistor T1. The second driving module 120 is used to control the voltage of the first terminal N1 of the first driving transistor T1 according to the second data voltage VDATA2 and the sweep frequency signal SWEEP, so as to control the light emission time of the light emission module 130.

[0051] Within a display frame, the light emission stage includes multiple sub-light emission stages, the sweep frequency signal SWEEP includes multiple sub-signals, each sub-light emission stage corresponds to one sub-signal, and the light emission module 130 includes a bright state and a dark state in each sub-light emission stage.

[0052] Specifically, the second driving module 120, the first driving module 110, and the light-emitting module 130 are connected between the first power line and the second power line. The first power line transmits the first power supply voltage VDD, and the second power line transmits the second power supply voltage VSS. The first driving module 110 generates a driving current in response to the first data voltage VDATA1 transmitted on the first data line to drive the light-emitting module 130 to emit light. The first driving module 110 includes a first driving transistor T1, which includes a gate G1, a first electrode N1, and a second electrode N2. The first data voltage writing module 101 can be connected to the gate of the first transistor T1 to transmit the first data voltage VDATA1 to the gate G1 of the first driving transistor T1. Of course, in other embodiments, the first data voltage writing module 101 can also be connected to the first electrode N1 of the first transistor T1 to write the first data voltage VDATA1 to the gate G1 of the first driving transistor T1 through a compensation circuit.

[0053] The second driving module 120 is connected between the first power line and the first terminal N1 of the first transistor T1. It is used to control the voltage of the first terminal N1 of the first driving transistor T1 according to the sweep frequency signal SWEEP and the second data voltage VDATA2 transmitted on the second data line, thereby controlling the conduction time of the first driving transistor T1 and thus controlling the light emission time of the light-emitting module 130.

[0054] In this embodiment, the first driving module 110 can be a PAM driving module. The first driving module 110 can control the magnitude of the driving current generated by the first driving transistor T1 according to the magnitude of the first data voltage VDATA1, that is, the magnitude of the light-emitting current of the light-emitting module 130 is controlled by the first driving module 110. The second driving module 120 can be a PWM driving module. The second driving module 120 can control the voltage at the first terminal N1 of the first driving transistor T1 according to the second data voltage VDATA2 and the sweep frequency signal SWEEP, so as to control the first driving transistor T1 to generate driving current. In other words, since the output terminal of the second driving module 120 is directly connected to the first terminal N1 of the first driving transistor T1, the conduction and cutoff of the driving current loop can be directly controlled by the second driving module 120, that is, the light-emitting time of the light-emitting module 130 can be controlled. Therefore, in this embodiment, it is not necessary to separately set the operating voltages of the first driving module 110 and the second driving module 120, thereby simplifying the external driving signals and voltages and improving the reliability of the pixel circuit.

[0055] Furthermore, in this embodiment, the sweep signal SWEEP can be an externally applied voltage signal used to perform signal scanning from high to low level or from low to high level during the light emission phase, thereby controlling the operating state (on or off) of the second driving module 120. Wherein, reference... Figure 2 Within a single display frame, the sweep signal SWEEP comprises multiple sub-signals. Figure 2 This is a timing control waveform diagram of a pixel circuit provided in an embodiment of the present invention. Taking the sweep signal SWEEP as a ramp signal as an example, in the light emission stage, each sub-signal divides the light emission stage into multiple sub-light emission stages. In each sub-light emission stage, the light emission module 130 transitions from a bright state to a dark state and then back to a bright state (the light emission module 130 is in a bright state when the sub-signal is low and in a dark state when it is high). Taking the sweep signal SWEEP as including three sub-signals as an example, the light emission stage is divided into three sub-light emission stages. In the second data voltage writing stage t1, the second data voltage VDATA2 is written into the second driving module 120 to control the second driving module 120 to conduct. In the light emission stage t2, the sweep signal SWEEP performs ramp scanning from low to high. When the sweep signal SWEEP is high, the second driving module 120 is controlled to turn off; when the sweep signal SWEEP is low, the second driving module 120 is controlled to turn on again. The first sub-luminescence stage t01, the second sub-luminescence stage t02, and the third sub-luminescence stage t03 each perform the same operation.

[0056] Figure 3 A waveform diagram of a frequency sweep signal provided in an embodiment of the present invention, for reference. Figure 3The thick solid line represents the sweep frequency signal SWEEP provided in this embodiment, and the dotted line represents the sweep frequency signal in the prior art. The slope of the sweep frequency signal SWEEP controls the brightness switching speed of the light-emitting module 130. Specifically, during the scanning process from low level to high level, the time taken for the voltage change ΔV using the prior art is b. However, this embodiment increases the slope of the sweep frequency signal SWEEP by dividing it into multiple sub-signals. Therefore, during the same voltage change ΔV process, the time taken by the technical solution provided in this embodiment is a, which greatly shortens the brightness switching time of the light-emitting module 130. That is, it increases the brightness switching speed of the light-emitting module 130 within the same light-emitting time. When performing grayscale switching, it is beneficial to improve the low grayscale display switching effect.

[0057] It should be noted that in the actual display process, the switching time between multiple sub-light-emitting stages is extremely short and almost imperceptible to the human eye. Therefore, by setting multiple sub-light-emitting stages for display, there will be no issues such as screen flickering that affect the display effect.

[0058] The technical solution provided by this invention connects the output terminal of the second driving module to the first electrode of the first driving transistor, thus connecting the first and second driving modules in series. The second driving module controls the voltage of the first electrode of the first transistor to control the conduction time of the first transistor, thereby controlling the light-emitting time of the light-emitting module. The magnitude of the light-emitting current is controlled by the first driving module. Compared with the prior art, the technical solution provided by this invention uses the second driving module to directly control the light-emitting time of the light-emitting module, while the first driving module is only responsible for controlling the magnitude of the driving current. There is no direct signal control relationship between the first and second driving modules, allowing them to share the same operating voltage. This simplifies the complexity of external driving control signals and voltage signals, and improves the reliability of the pixel circuit. Furthermore, by dividing the light-emitting stage of the pixel circuit into multiple sub-light-emitting stages and the sweep frequency signal into multiple sub-signals, one sub-light-emitting stage corresponds to one sub-signal. This increases the slope of the sweep frequency signal, thereby increasing the switching speed of the driving current and the switching speed of the light-emitting module's brightness, improving the switching effect of different gray levels at low gray levels.

[0059] The pixel circuits described above are not limited to any specific pixel circuit. Any pixel circuit that is applicable to the technical solutions provided in the embodiments of this invention falls within the scope of this invention. The following description uses specific pixel circuit structures, but the inventive concept of this invention is not limited to these specific pixel circuit structures.

[0060] Optionally, Figure 4 This is a schematic diagram of another pixel circuit structure provided in an embodiment of the present invention, with reference to... Figure 4Based on the above technical solution, the second driving module 120 includes a second driving transistor T2, a first storage module 122, and a second data voltage writing module 121. The first terminal of the first storage module 122 is connected to a sweep frequency signal SWEEP, and the second terminal of the first storage module 122 is connected to the gate G2 of the second driving transistor T2. The second data voltage writing module 121 is used to transmit a second data voltage VDATA2 to the gate G2 of the second driving transistor T2. The second driving transistor T2 is used to control the voltage of the first terminal N1 of the first driving transistor T1 according to its own gate voltage.

[0061] Specifically, the second driving transistor T2 is connected in series with the first driving transistor T1. The first terminal M1 of the second driving transistor T2 is connected to the first power supply line. The second data voltage writing module 121 is connected to the gate G2 of the second driving transistor T2 and is used to write the second data voltage VDATA2 to the gate G2 of the second driving transistor T2. The first storage module 122 is connected to the gate G2 of the second driving transistor T2 and is used to store the gate voltage of the second driving transistor T2. The second driving transistor T2 is turned on according to the second data voltage VDATA2, and transmits the first power supply voltage VDD transmitted on the first power supply line to the first terminal N1 of the first driving transistor T1. The first driving transistor T1 generates a driving current in response to the first data voltage VDATA1 at its gate G1, driving the light-emitting module 130 to emit light. During the light-emitting stage, the second driving transistor T2 is turned off in response to the sweep frequency signal SWEEP. The potential of the second terminal M2 of the second driving transistor T2 is equal to the potential of the first terminal N1 of the first driving transistor T1, and the potential decreases, causing the first driving transistor T1 to turn off. There is no current in the second terminal N2 of the first driving transistor T1, and the light-emitting module 130 does not emit light, thus realizing the control of the light-emitting time of the light-emitting module 130 by the second driving module 120.

[0062] Figure 5 This is a schematic diagram of another pixel circuit structure provided in an embodiment of the present invention, with reference to... Figure 5The second driving module 120 further includes a first compensation module 123, a first light-emitting control module 124, and a second light-emitting control module 125. The first terminal of the second data voltage writing module 121 writes the second data voltage VDATA2, and the second terminal of the second data voltage writing module 121 is connected to the first terminal M1 of the second driving transistor T2. The control terminal of the second data voltage writing module 121 is connected to the first scan signal line S1. The first terminal of the first compensation module 123 is connected to the second terminal M2 of the second driving transistor T2, and the second terminal of the first compensation module 123 is connected to the gate G2 of the second driving transistor T2. The control terminal of the first compensation module 123 is connected to the first scan signal line S1. The first terminal of the first light-emitting control module 124 is connected to the first power line, and the second terminal of the first light-emitting control module 124 is connected to the first terminal M1 of the second driving transistor T2. The first terminal of the second light-emitting control module 125 is connected to the second terminal M2 of the second driving transistor T2, and the second terminal of the second light-emitting control module 125 is connected to the first terminal N1 of the first driving transistor T1. The control terminals of both the first and second light-emitting control modules are connected to the light-emitting control signal line EM.

[0063] Specifically, for ease of description, this embodiment uses the same reference numerals to represent signal lines and their corresponding output signals. The first compensation module 123 includes a first compensation transistor T4, the first light-emitting control module 124 includes a first light-emitting control transistor T5, and the second light-emitting control module 125 includes a second light-emitting control transistor T6; the second data voltage writing module 121 includes a second data writing transistor T3, and the first storage module 122 includes a first capacitor C1; the gate of the second data writing transistor T3 is connected to the first scan signal line S1, the first terminal of the second data writing transistor T3 is connected to the second data voltage VDATA2, the second terminal of the second data writing transistor T3 is connected to the first terminal M1 of the second driving transistor T2, the gate of the first compensation transistor T4 is connected to the first scan signal line S1, the first terminal of the first compensation transistor T4 is connected to the second terminal M2 of the second driving transistor T2, and the second terminal of the first compensation transistor T4 is connected to the gate G2 of the second driving transistor T2. The gates of the first light-emitting control transistor T5 and the second light-emitting control transistor T6 are both connected to the light-emitting control signal line EM. The first terminal of the first light-emitting control transistor T5 is connected to the first power supply line, and the second terminal of the first light-emitting control transistor T5 is connected to the first terminal M1 of the second driving transistor T2. The first terminal of the second light-emitting control transistor T6 is connected to the second terminal M2 of the second driving transistor T2, and the second terminal of the second light-emitting control transistor T6 is connected to the first terminal N1 of the first driving transistor T1. The first terminal of the first capacitor C1 is connected to the sweep frequency signal SWEEP, and the second terminal of the first capacitor C1 is connected to the gate G2 of the second driving transistor T2. The first driving module 110 also includes a second storage module 102, which includes a second capacitor C2.

[0064] The operation of the pixel circuit provided in this embodiment of the invention includes at least a data voltage writing stage and a light emission stage, wherein the data voltage writing stage includes a first data voltage writing stage and a second data voltage writing stage.

[0065] During the first data voltage writing stage, all transistors in the second driving module 120 are in the off state. The first data voltage VDATA1 is written to the gate G1 of the first driving transistor T1 through the first data voltage writing module 101 and stored on the second capacitor C2.

[0066] During the second data voltage writing stage, the second data writing transistor T3 and the first compensation transistor T4 are turned on in response to the first scan signal S1 output from the first scan signal line. The second data voltage VDATA2 is written to the gate G2 of the second driving transistor T2 through the second data writing transistor T3 and the first compensation transistor T4, and stored in the first capacitor C1. Due to the presence of the first compensation transistor T4, the second driving module 120 has a threshold compensation function, which can compensate for the threshold voltage Vth2 of the second driving transistor T2 to ensure the accuracy of the analog data voltage conversion to PWM control and improve the reliability of the control of the second driving module 120. The gate voltage of the second driving transistor T2 is VDATA2 + Vth2.

[0067] During the light-emitting stage, the first light-emitting control transistor T5 and the second light-emitting control transistor T6 are turned on in response to the light-emitting control signal EM transmitted on the light-emitting control signal line. Since the second driving transistor T2 is in the on state, the first power supply voltage VDD transmitted on the first power supply line can be transmitted to the first terminal N1 of the first driving transistor T1. The first driving transistor T1 generates a driving current to drive the light-emitting module 130 to emit light. The magnitude of the driving current is determined by the first data voltage VDATA1, and the driving current can be expressed by the following formula:

[0068]

[0069] Where μ is the electron mobility of the first driving transistor T1, Cox is the channel capacitance per unit area of ​​the first driving transistor T1, W / L is the width-to-length ratio of the first driving transistor T1, and Vth1 is the threshold voltage of the first driving transistor T1.

[0070] Here, the light-emitting duration of the light-emitting module 130 can be determined by the sweep frequency signal SWEEP and the second data voltage VDATA2. Taking the second driving transistor T2 as a P-type transistor as an example, during the second data voltage writing stage, the gate voltage of the second driving transistor T2 is VDATA2 + Vth2. During the light-emitting stage, as the sweep frequency signal SWEEP changes from low to high level, due to the coupling effect of the first capacitor C1, the gate voltage of the second driving transistor T2 gradually increases. As a result, the voltage difference between the gate G2 and the first electrode M2 ​​of the second driving transistor T2 gradually decreases. When the voltage difference between the gate G2 and the first electrode M2 ​​of the second driving transistor T2 equals Vth2, the second driving transistor T2 enters the off state, causing the voltage of the first electrode N1 of the first driving transistor T1 to decrease. The first driving transistor T1 does not output driving current, and the light-emitting module 130 does not emit light. When the sweep signal SWEEP transitions from high to low, the voltage difference between the gate G2 and the first terminal M2 of the second driving transistor T2 increases, causing the second driving transistor T2 to turn on again. The voltage at the first terminal N1 of the first driving transistor T1 returns to the first power supply voltage VDD, and the first driving transistor T1 generates a driving current, causing the light-emitting module 130 to emit light. This process is repeated in each sub-light-emitting stage, thereby increasing the slope of the sweep signal SWEEP to improve the switching speed between the bright and dark states of the light-emitting module 130 and enhance the low grayscale display effect.

[0071] It should be noted that in this embodiment, during the light-emitting stage, the first driving transistor T1 operates in the saturation region, and the second driving transistor T2 operates in the linear region. It should be understood that the first driving transistor T1, operating in the saturation region, is used to generate a stable driving current to accurately control the brightness of the light-emitting module. However, since the second driving transistor T2 is connected in series with the first driving transistor T1, in order to reduce the influence of the second driving transistor T2 on the driving current, the second driving transistor T2 is set to operate in the saturation region, so that the second driving transistor T2 only acts as a switch, providing a conduction path for the driving current.

[0072] Optionally, while the first data voltage writing module 101 responds to the first data voltage VDATA1, the second data voltage writing module 121 responds to the second data voltage VDATA2. That is, the first data voltage writing stage and the second data voltage writing stage can be performed simultaneously, which helps save data writing time and increase the light emission ratio. Here, due to the functions of the first light emission control transistor T5 and the second light emission control transistor T6, even if the first data voltage VDATA1 and the second data voltage VDATA2 are written simultaneously, there will be no interference between them, ensuring the normal operation of the pixel circuit.

[0073] Optionally, Figure 6This is a schematic diagram of another pixel circuit structure provided in an embodiment of the present invention, with reference to... Figure 6 The first driving module 110 further includes a third light-emitting control module 103. The first data voltage writing module 101 includes a first data writing transistor T7. The third light-emitting control module 103 includes a third light-emitting control transistor T8. The gate of the third light-emitting control transistor T8 is connected to the light-emitting control signal line EM. The first terminal of the third light-emitting control transistor T8 is connected to the second terminal of the first driving transistor T1. The second terminal of the third light-emitting control transistor T8 is connected to the first end of the light-emitting module 130. The second end of the light-emitting module 130 is connected to the second power supply line. The first terminal of the second capacitor C2 is connected to a fixed voltage, such as the first power supply voltage VDD (or other voltages in other embodiments). The second terminal of the second capacitor C2 is connected to the gate of the first driving transistor T1. The gate of the first data writing transistor T7 is connected to the second scan signal line S2. The first terminal of the first data writing transistor T7 is connected to the first data voltage VDATA1. The second terminal of the first data writing transistor T7 is connected to the gate of the first driving transistor T1.

[0074] The specific working process of the second driving module 120 can be referred to the relevant description in the above embodiments, and will not be repeated here. The first driving module 110 is provided with a third light-emitting control transistor T8, which can effectively prevent the light-emitting module 130 from emitting light when the first data voltage VDATA1 is written to the gate G1 of the first driving transistor T1.

[0075] Furthermore, in order to ensure the uniformity of the driving current generated by the first driving transistor T1, a compensation module can be set in the first driving module 110 to compensate the threshold voltage of the first driving transistor T1. Figure 7 This is a schematic diagram of another pixel circuit structure provided in an embodiment of the present invention, with reference to... Figure 7 The first driving module 110 also includes a first data voltage writing module 101, a second storage module 102, a third light emission control module 103, and a second compensation module 104. The first data voltage writing module 101 includes a first data writing transistor T7, the third light emission control module 103 includes a third light emission control transistor T8, the second storage module 102 includes a second capacitor C2, and the second compensation module 104 includes a second compensation transistor T9.

[0076] The gate of the third light-emitting control transistor T8 is connected to the light-emitting control signal line EM. The first terminal of the third light-emitting control transistor T8 is connected to the second terminal of the first driving transistor T1. The second terminal of the third light-emitting control transistor T8 is connected to the first terminal of the light-emitting module 130. The second terminal of the light-emitting module 130 is connected to the second power supply line. The first terminal of the second capacitor C2 is connected to a fixed voltage, such as the first power supply voltage VDD. The second terminal of the second capacitor C2 is connected to the gate of the first driving transistor T1. The gate of the first data writing transistor T7 is connected to the second scan signal line S2. The first terminal of the first data writing transistor T7 is connected to the first data voltage VDATA1. The second terminal of the first data writing transistor T7 is connected to the first terminal N1 of the first driving transistor T1. The gate of the second compensation transistor T9 is connected to the second scan signal line S2. The first terminal of the second compensation transistor T9 is connected to the second terminal N2 of the first driving transistor T1. The second terminal of the second compensation transistor T9 is connected to the gate G1 of the first driving transistor T1.

[0077] Specifically, the fixed voltage connected to the first terminal of the second capacitor C2 can be the first power supply voltage VDD transmitted on the first power supply line, or it can be other types of voltage. The second capacitor C2 is used to store the gate voltage of the first driving transistor T1. During the first data voltage writing stage, the first data writing transistor T7 and the second compensation transistor T9 are turned on in response to the second scan signal line S2, respectively. The first data voltage VDATA1 is written to the gate G1 of the first driving transistor T1 through the first data writing transistor T7 and the second compensation transistor T9. The voltage of the gate G1 of the first driving transistor T1 is VDATA1 + Vth1, where Vth1 is the threshold voltage of the first driving transistor T1. The second capacitor C2 stores the voltage of the gate G1 of the first driving transistor T1. Since the gate voltage of the first driving transistor T1 is a voltage associated with the first data voltage VDATA1 and the threshold voltage, the data voltage writing and threshold voltage compensation of the first driving transistor T1 are realized to ensure that the driving current generated by the first driving transistor T1 according to the voltage of its gate G1 is consistent during the light-emitting stage, thereby improving the uniformity of the display brightness and thus improving the display effect.

[0078] In this embodiment, the light-emitting module 130 can be a self-emissive device such as an LED device, an OLED device, a QLED device, a Micro LED device, or a Mini LED device. For example, a Micro LED device is used in this embodiment; however, other self-emissive devices such as OLED devices can be used in other embodiments, and no limitation is made here.

[0079] Optionally, in this embodiment, the first data voltage VDATA1 and the second data voltage VDATA2 can share the same data line. That is, during the first data voltage writing stage, the data line transmits the first data voltage VDATA1 to the first driving module 110; during the second data voltage writing stage, the data line transmits the second data voltage VDATA2 to the second driving module 120. This can save one data line and reduce the number of external signal lines.

[0080] Optionally, Figure 8 This is a schematic diagram of another pixel circuit structure provided in an embodiment of the present invention, with reference to... Figure 8 Based on the above technical solutions, the first driving module 110 further includes a first initialization module 105. The control terminal of the first initialization module 105 is connected to the third scan signal line S3, the first terminal of the first initialization module 105 is connected to the initialization signal line Vref, and the second terminal of the first initialization module 105 is connected to the gate G1 of the first driving transistor T1. The second driving module 120 further includes a second initialization module 126. The control terminal of the second initialization module 126 is connected to the fourth scan signal line S4, the first terminal of the second initialization module 126 is connected to the initialization signal line Vref, and the second terminal of the second initialization module 126 is connected to the gate G2 of the second driving transistor T2. The first initialization module 105 is used to initialize the gate voltage of the first driving transistor T1 during the initialization phase, and the second initialization module 126 is used to initialize the gate voltage of the second driving transistor T2 during the initialization phase, so as to reduce the impact of the residual voltage of the previous display frame on the display of the current frame.

[0081] Specifically, the first initialization module 105 includes a first initialization transistor T10, and the second initialization module 126 includes a second initialization transistor T11. The gate of the first initialization transistor T10 is connected to the third scan signal line S3, the first terminal of the first initialization transistor T10 is connected to the initialization signal line Vref, the second terminal of the first initialization transistor T10 is connected to the gate G1 of the first driving transistor T1, the gate of the second initialization transistor T11 is connected to the fourth scan signal line S4, the first terminal of the second initialization transistor T11 is connected to the initialization signal line Vref, and the second terminal of the second initialization transistor T11 is connected to the gate G2 of the second driving transistor T2.

[0082] Figure 9 Another timing control waveform diagram of a pixel circuit provided in an embodiment of the present invention is applicable to... Figure 8 The pixel circuit shown. Combined with... Figure 8 and Figure 9Taking all transistors as P-type transistors as an example, the working process of the pixel circuit provided in this embodiment of the invention includes at least a first stage T01, a second stage T02 and a third stage T03. The first stage T01 includes a second initialization stage T11 and a second data voltage writing stage T12. The second stage T02 includes a first initialization stage T21 and a first data voltage writing stage T22.

[0083] In the second initialization phase T11, the first scan signal line is configured to transmit a high-level first scan signal S1, the second scan signal line is configured to transmit a high-level second scan signal S2, the third scan signal line is configured to transmit a high-level third scan signal S3, the fourth scan signal line is configured to transmit a low-level fourth scan signal S4, and the light emission control signal line is configured to transmit a high-level light emission control signal EM. Then, the second initialization transistor T11 is turned on, and the first initialization transistor T10, the first data writing transistor T7, the second data writing transistor T3, the first compensation transistor T4, the second compensation transistor T9, the first light emission control transistor T5, the second light emission control transistor T6, and the third light emission control transistor T3 are turned off. The initialization voltage Vref transmitted on the initialization signal line is written to the gate G2 of the second driving transistor T2 through the second initialization transistor T11, thereby initializing the gate potential of the second driving transistor T2.

[0084] During the second data voltage writing stage T12, the first scan signal line is configured to transmit a low-level first scan signal S1, the second scan signal line is configured to transmit a high-level second scan signal S2, the third scan signal line is configured to transmit a high-level third scan signal S3, the fourth scan signal line is configured to transmit a high-level fourth scan signal S4, and the light emission control signal line is configured to transmit a high-level light emission control signal EM. At this time, the second data writing transistor T3 and the first compensation transistor T4 are turned on, while the first initialization transistor T10, the second initialization transistor T11, the first data writing transistor T7, the second compensation transistor T9, the first light emission control transistor T5, the second light emission control transistor T6, and the third light emission control transistor T3 are turned off. The second data voltage VDATA2 is written to the gate G2 of the second driving transistor T2 through the second data writing transistor T3 and the first compensation transistor T4. When the gate voltage of the second driving transistor T2 is VDATA2 + Vth2, the second driving transistor T2 is turned off, and the first capacitor C1 stores this gate voltage, thus realizing data writing and threshold compensation for the second driving transistor T2. With this, Phase 1, T01, has ended.

[0085] In the first initialization phase T21, the first scan signal line is configured to transmit a high-level first scan signal S1, the second scan signal line is configured to transmit a high-level second scan signal S2, the third scan signal line is configured to transmit a low-level third scan signal S3, the fourth scan signal line is configured to transmit a high-level fourth scan signal S4, and the light emission control signal line is configured to transmit a high-level light emission control signal EM. Then, the first initialization transistor T10 is turned on, and the second initialization transistor T11, the first data writing transistor T7, the second data writing transistor T3, the first compensation transistor T4, the second compensation transistor T9, the first light emission control transistor T5, the second light emission control transistor T6, and the third light emission control transistor T3 are turned off. The initialization voltage Vref transmitted on the initialization signal line is written to the gate G1 of the first driving transistor T1 through the first initialization transistor T10, thereby initializing the gate potential of the first driving transistor T1.

[0086] During the first data voltage writing stage T22, the first scan signal line is configured to transmit a high-level first scan signal S1, the second scan signal line is configured to transmit a low-level second scan signal S2, the third scan signal line is configured to transmit a high-level third scan signal S3, the fourth scan signal line is configured to transmit a high-level fourth scan signal S4, and the light emission control signal line is configured to transmit a high-level light emission control signal EM. At this time, the first data writing transistor T7 and the second compensation transistor T9 are turned on, while the first initialization transistor T10, the second initialization transistor T11, the second data writing transistor T3, the first compensation transistor T4, the first light emission control transistor T5, the second light emission control transistor T6, and the third light emission control transistor T3 are turned off. The first data voltage VDATA1 is written to the gate G1 of the first driving transistor T1 through the first data writing transistor T7 and the second compensation transistor T9. When the gate voltage of the first driving transistor T1 is VDATA1 + Vth1, the first driving transistor T1 is turned off, and the second capacitor C2 stores this gate voltage, thus realizing data writing and threshold compensation for the first driving transistor T1. This concludes Phase Two, T02.

[0087] As can be seen from the above description, since there is no direct signal control relationship between the first drive module 110 and the second drive module 120, the operating voltage ranges of the first drive module 110 and the second drive module 120 can overlap, and they can share some signals, thereby simplifying the external drive signal and voltage signal, which is beneficial to simplifying the complexity of the external drive.

[0088] Of course, in other embodiments, the first stage T01 and the second stage T02 can also be performed simultaneously to reduce the overall data writing and initialization time of the pixel circuit.

[0089] In the third stage T03, which is the light-emitting stage, the first scan signal line is configured to transmit a high-level first scan signal S1, the second scan signal line is configured to transmit a high-level second scan signal S2, the third scan signal line is configured to transmit a high-level third scan signal S3, the fourth scan signal line is configured to transmit a high-level fourth scan signal S4, the light-emitting control signal line is configured to transmit a low-level light-emitting control signal EM, and the sweep frequency signal SWEEP is a ramp signal. Then, the first initialization transistor T10, the second initialization transistor T11, the first data writing transistor T7, the second data writing transistor T3, the first compensation transistor T4, and the second compensation transistor T9 are turned off, and the first light-emitting control transistor T5, the second light-emitting control transistor T6, and the third light-emitting control transistor T3 are turned on. Since the first light-emitting control transistor T5 is turned on, the voltage at the first terminal M1 of the second driving transistor T2 is the first power supply voltage VDD. By properly configuring the magnitude of the first power supply voltage VDD, the voltage difference between the gate G2 and the first terminal M1 of the second driving transistor T2 is made less than the threshold voltage Vth2 of the second driving transistor T2, thus controlling the second driving transistor T2 to turn on. At this time, the second driving transistor T2 operates in the linear region and only acts as a switch. The first power supply voltage VDD is transmitted to the first terminal N1 of the first driving transistor T1. The first driving transistor T1 generates a driving current under the voltage of its gate G1, driving the light-emitting module 130 to emit light. The driving current can be expressed by the following formula:

[0090]

[0091] In this embodiment, the magnitude of the driving current is determined by the magnitude of the first data voltage VDATA1, and is independent of the threshold voltage Vth1 of the first driving transistor T1, which is beneficial to improving the color uniformity of the light-emitting module 130. The light-emitting time of the light-emitting module 130 is determined by the second data voltage VDATA2 and the sweep frequency signal SWEEP. When the sweep frequency signal SWEEP is low, the light-emitting module 130 is in the bright state. During the sweep frequency signal SWEEP scanning from low to high level, the voltage of the first electrode of the first capacitor C1 gradually increases. Due to the coupling effect of the capacitor, the gate voltage of the second driving transistor T2 gradually increases to VDATA2 + Vth2 + ΔV, where ΔV is the voltage change of the sweep frequency signal SWEEP. When VDATA2 + Vth2 + ΔV - VDD = Vth2, the second driving transistor T2 is turned off, causing the voltage of the first electrode N1 of the first driving transistor T1 to decrease, thereby turning off the first driving transistor T1 and the light-emitting module 130 is in the dark state. Here, within the light-emitting phase of a display frame, the sweep frequency signal SWEEP includes multiple sub-signals, each corresponding to a sub-light-emitting phase. Each sub-signal of the sweep frequency signal SWEEP repeats the above operation process, thereby increasing the slope of the sweep frequency signal SWEEP and improving the switching speed between bright and dark states of the light-emitting module 130. This helps to improve the display problem caused by the slow switching speed of the light-emitting module from bright to dark states at low grayscale levels. Specifically, the sweep frequency signal SWEEP can be a sawtooth wave, triangular wave, or other oblique wave signal.

[0092] For example, Figure 10 A simulation waveform diagram of a pixel circuit during the light-emitting stage is provided as an embodiment of the present invention, with reference to... Figure 10 Taking the sweep frequency signal SWEEP as a triangular wave as an example, during the rising process of the sweep frequency signal SWEEP, the second driving transistor T2 is gradually turned off, and the driving current Id gradually decreases to 0. During the falling process of the sweep frequency signal SWEEP, the second driving transistor T2 is gradually turned on, and the driving current Id gradually increases, driving the light-emitting module 130 to emit light normally.

[0093] Optionally, Figure 11 This invention provides another timing control waveform diagram for a pixel circuit, specifically the timing control waveforms of all row pixel circuits in the display panel, where (1), (2)...(n) represent the first row pixel circuit, the second row pixel circuit...the nth row pixel circuit, respectively, and the first scan signal S1(1)(2)...(n), the second scan signal S2(1)(2)...(n), the third scan signal S3(1)(2)...(n) and the fourth scan signal S4(1)(2)...(n) represent the timing control waveforms of each row pixel circuit according to... Figure 9 The total time for scanning and refreshing the control timing shown is the sum of the time required. In other words, all pixel circuits within the display panel are scanned line by line. Figure 9 The timing sequence shown completes initialization and data writing line by line until the last row of pixel circuits finishes scanning. Then, the row of pixel circuits enters the light-emitting stage together, which helps to simplify the timing control of the pixel circuits.

[0094] Optionally, embodiments of the present invention also provide a method for driving a pixel circuit, combined with Figure 1 The pixel circuit includes a first driving module 110, a second driving module 120, and a light-emitting module 130. The first driving module 110 includes a first driving transistor T1 and a first data voltage writing module 101. The output terminal of the second driving module 120 is connected to the first pole N1 of the first driving transistor T1.

[0095] Figure 12 A flowchart of a pixel circuit driving method provided in an embodiment of the present invention is shown below. Figure 12 The driving method for this pixel circuit includes:

[0096] S110, During the first data voltage writing stage, the first data voltage writing module transmits the first data voltage to the gate of the first driving transistor.

[0097] S120. During the light-emitting stage, the second driving module controls the voltage of the first electrode of the first driving transistor according to the second data voltage and the frequency sweep signal, and the first driving transistor drives the light-emitting module to emit light according to the voltage of the gate and the voltage of the first electrode.

[0098] The light emission time of the light emission module 130 is controlled by the second data voltage and the frequency sweep signal. Within a display frame, the light emission stage includes multiple sub-light emission stages, and the frequency sweep signal includes multiple sub-signals. Each sub-light emission stage corresponds to one sub-signal. The light emission module includes a bright state and a dark state in each sub-light emission stage.

[0099] The technical solution provided by this invention connects the output terminal of the second driving module to the first electrode of the first driving transistor, thus connecting the first and second driving modules in series. The second driving module controls the voltage of the first electrode of the first transistor to control the conduction time of the first transistor, thereby controlling the light-emitting time of the light-emitting module. The magnitude of the light-emitting current is controlled by the first driving module. Compared with the prior art, the technical solution provided by this invention uses the second driving module to directly control the light-emitting time of the light-emitting module, while the first driving module is only responsible for controlling the magnitude of the driving current. There is no direct signal control relationship between the first and second driving modules, allowing them to share the same operating voltage. This simplifies the complexity of external driving control signals and voltage signals, and improves the reliability of the pixel circuit. Furthermore, by dividing the light-emitting stage of the pixel circuit into multiple sub-light-emitting stages and the sweep frequency signal into multiple sub-signals, one sub-light-emitting stage corresponds to one sub-signal, thereby increasing the slope of the sweep frequency signal and increasing the switching speed of the light-emitting module's brightness, improving the switching effect of different gray levels at low gray levels.

[0100] Optionally, Figure 13 A flowchart of a pixel circuit driving method provided in an embodiment of the present invention is shown below. Figure 8 and Figure 13 The second driving module includes a second driving transistor and a second data voltage writing module; the driving method of the pixel circuit includes:

[0101] S110, During the first data voltage writing stage, the first data voltage writing module transmits the first data voltage to the gate of the first driving transistor.

[0102] S210, During the second data voltage writing stage, the second data voltage writing module transmits the second data voltage to the gate of the second driving transistor.

[0103] S120. During the light-emitting stage, the second driving module controls the voltage of the first electrode of the first driving transistor according to the second data voltage and the frequency sweep signal, and the first driving transistor drives the light-emitting module to emit light according to the voltage of the gate and the voltage of the first electrode.

[0104] Specifically, this embodiment does not limit the execution order of steps S110 and S210. The first data voltage VDATA1 can be written first, or the second data voltage VDATA2 can be written first. Alternatively, the first data voltage VDATA1 and the second data voltage VDATA2 can be written simultaneously to the gates of their respective transistors. The path of the driving current is controlled by the first light-emitting control transistor T5, the second light-emitting control transistor T6, and the third light-emitting control transistor T8 to drive the light-emitting module 130 to emit light. The pixel circuit driving method provided in this embodiment is applicable to the pixel circuits provided in any of the above embodiments and possesses the beneficial effects described in any of the above embodiments, which will not be repeated here.

[0105] Optionally, embodiments of the present invention also provide a display panel, which includes the pixel circuit provided in embodiments of the present invention. Figure 14 This is a schematic diagram of a display panel provided in an embodiment of the present invention. This display panel can be applied to tablets, mobile phones, watches, wearable devices, as well as automotive displays, camera displays, televisions, computer screens, and all other display-related devices. Since this display panel includes the pixel circuits provided in any embodiment of the present invention, it also possesses the beneficial effects described in any embodiment of the present invention.

[0106] Note that the above description is merely a preferred embodiment of the present invention and the technical principles employed. Those skilled in the art will understand that the present invention is not limited to the specific embodiments described herein, and various obvious changes, readjustments, and substitutions can be made without departing from the scope of protection of the present invention. Therefore, although the present invention has been described in detail through the above embodiments, the present invention is not limited to the above embodiments, and may include many other equivalent embodiments without departing from the concept of the present invention, the scope of which is determined by the scope of the appended claims.

Claims

1. A pixel circuit, characterized in that, The application relates to a display device and a driving method thereof. The first driving module comprises a first driving transistor and a first data voltage writing module, the first data voltage writing module is used for transmitting a first data voltage to the gate of the first driving transistor, and the first driving transistor is used for driving the light-emitting module to emit light in a light-emitting stage according to the voltage of the gate and the voltage of the first pole; The output end of the second driving module is connected with the first pole of the first driving transistor, and the second driving module is used for controlling the voltage of the first pole of the first driving transistor according to a second data voltage and a sweep signal, so as to control the light-emitting time of the light-emitting module; In a display frame, the light-emitting stage comprises a plurality of sub-light-emitting stages, the sweep signal comprises a plurality of sub-signals, each sub-light-emitting stage corresponds to a sub-signal, and the light-emitting module comprises a bright state and a dark state in each sub-light-emitting stage. The second driving module comprises a second driving transistor, a first storage module and a second data voltage writing module; the first end of the first storage module is connected with the sweep signal, the second end of the first storage module is connected with the gate of the second driving transistor, the second data voltage writing module is used for transmitting the second data voltage to the gate of the second driving transistor, and the second driving transistor is used for controlling the voltage of the first pole of the first driving transistor according to the voltage of the gate; wherein the second data voltage writing module comprises a second data writing transistor, and the second data writing transistor is a P-type transistor. In the light-emitting stage, the first driving transistor works in a saturation region, and the second driving transistor works in a linear region. The sweep signal comprises a sawtooth wave signal or a triangular wave signal.

2. The pixel circuit of claim 1, wherein, The second driving module further comprises a first compensation module, a first light-emitting control module and a second light-emitting control module; the first compensation module comprises a first compensation transistor, the first light-emitting control module comprises a first light-emitting control transistor, the second light-emitting control module comprises a second light-emitting control transistor; the second data writing transistor is connected with a first scan signal line, the first pole of the second data writing transistor is connected with the second data voltage, the second pole of the second data writing transistor is connected with the first pole of the second driving transistor, the gate of the first compensation transistor is connected with the first scan signal line, the first pole of the first compensation transistor is connected with the second pole of the second driving transistor, and the second pole of the first compensation transistor is connected with the gate of the second driving transistor.

3. The pixel circuit of claim 1, wherein, ​ ​ The gate of the first light-emitting control transistor and the gate of the second light-emitting control transistor are connected to a light-emitting control signal line, the first electrode of the first light-emitting control transistor is connected to a first power supply line, the second electrode of the first light-emitting control transistor is connected to the first electrode of the second drive transistor, the first electrode of the second light-emitting control transistor is connected to the second electrode of the second drive transistor, and the second electrode of the second light-emitting control transistor is connected to the first electrode of the first drive transistor; the first electrode of the first capacitor is connected to the sweep signal, and the second electrode of the first capacitor is connected to the gate of the second drive transistor.

4. The pixel circuit of claim 1, wherein, The first data voltage writing module is responsive to the first data voltage, and the second data voltage writing module is responsive to the second data voltage.

5. The pixel circuit of claim 1, wherein, The first drive module further comprises a second storage module and a third light-emitting control module, the first data voltage writing module comprises a first data writing transistor, the third light-emitting control module comprises a third light-emitting control transistor, and the second storage module comprises a second capacitor. The gate of the third light-emitting control transistor is connected to a light-emitting control signal line, the first electrode of the third light-emitting control transistor is connected to the second electrode of the first drive transistor, the second electrode of the third light-emitting control transistor is connected to the first end of the light-emitting module, the second end of the light-emitting module is connected to a second power supply line; the first electrode of the second capacitor is connected to a fixed voltage, and the second electrode of the second capacitor is connected to the gate of the first drive transistor; the gate of the first data writing transistor is connected to a second scan signal line, the first electrode of the first data writing transistor is connected to the first data voltage, and the second electrode of the first data writing transistor is connected to the gate of the first drive transistor.

6. The pixel circuit of claim 1, wherein, The first drive module further comprises a second storage module, a third light-emitting control module and a second compensation module, the first data voltage writing module comprises a first data writing transistor, the third light-emitting control module comprises a third light-emitting control transistor, the second storage module comprises a second capacitor, and the second compensation module comprises a second compensation transistor. The gate of the third light-emitting control transistor is connected to a light-emitting control signal line, the first electrode of the third light-emitting control transistor is connected to the second electrode of the first drive transistor, the second electrode of the third light-emitting control transistor is connected to the first end of the light-emitting module, the second end of the light-emitting module is connected to a second power supply line; the first electrode of the second capacitor is connected to a fixed voltage, and the second electrode of the second capacitor is connected to the gate of the first drive transistor; the gate of the first data writing transistor is connected to a second scan signal line, the first electrode of the first data writing transistor is connected to the first data voltage, the second electrode of the first data writing transistor is connected to the first electrode of the first drive transistor, the gate of the second compensation transistor is connected to the second scan signal line, the first electrode of the second compensation transistor is connected to the second electrode of the first drive transistor, and the second electrode of the second compensation transistor is connected to the gate of the first drive transistor.

7. The pixel circuit of claim 1, wherein, The first data voltage and the second data voltage share the same data line.

8. The pixel circuit of claim 1, wherein, The first driving module further comprises a first initialization module including a first initialization transistor, and the second driving module further comprises a second initialization module including a second initialization transistor. The gate of the first initialization transistor is connected to a third scan signal line, the first electrode of the first initialization transistor is connected to an initialization signal line, the second electrode of the first initialization transistor is connected to the gate of the first driving transistor, the gate of the second initialization transistor is connected to a fourth scan signal line, the first electrode of the second initialization transistor is connected to the initialization signal line, and the second electrode of the second initialization transistor is connected to the gate of the second driving transistor.

9. A driving method of a pixel circuit, characterized by, A driving method of the pixel circuit according to any one of claims 1-8. The driving method of the pixel circuit comprises: In a first data voltage writing stage, the first data voltage writing module transmits the first data voltage to the gate of the first driving transistor; In a light emitting stage, the second driving module controls the voltage of the first electrode of the first driving transistor according to the second data voltage and a sweep signal, and the first driving transistor drives the light emitting module to emit light according to the voltage of the gate and the voltage of the first electrode; The light emitting time of the light emitting module is controlled by the second data voltage and the sweep signal, the light emitting stage comprises a plurality of sub-light emitting stages in one display frame, the sweep signal comprises a plurality of sub-signals, each sub-light emitting stage corresponds to a sub-signal, and the light emitting module comprises a bright state and a dark state in each sub-light emitting stage. The second driving module comprises a second driving transistor and a second data voltage writing module. Before the light emitting stage, the driving method of the pixel circuit further comprises: in a second data voltage writing stage, the second data voltage writing module transmits the second data voltage to the gate of the second driving transistor.

10. A display panel, characterized by, The pixel circuit according to any one of claims 1-8.

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