Method and apparatus for rate matching for communication and broadcasting systems

Abstract

A method and apparatus for rate matching for a communication and broadcasting system are provided. A communication method and system are provided for converging a 5th-Generation (5G) communication system for supporting higher data rates beyond a 4th-Generation (4G) system with a technology for Internet of Things (IoT). The disclosure can be applied to smart services, such as smart home, smart building, smart city, smart car, connected car, health care, digital education, smart retail, security and safety services, based on 5G communication technology and IoT-related technologies. A method and apparatus for polar encoding and rate matching are disclosed.

Description

[0001] This application is a divisional application of the Chinese Invention Patent with the application date of June 18, 2018, the application number of 201880041164.5, and the title of "Method and apparatus for rate matching for communication and broadcasting system". TECHNICAL FIELD

[0002] The present disclosure relates to error correction codes for correcting or recovering errors or losses when the errors or losses occur or are likely to occur due to various reasons such as noise or interference in the process of transmitting or storing data. More specifically, the present disclosure relates to methods, embodiments, and apparatuses for rate matching of polar codes. The present disclosure can be used in various fields, and can be effectively used for rate matching of polar codes used in mobile communication systems such as Global System for Mobile Communications (GSM), Wideband Code Division Multiple Access (WCDMA), Long Term Evolution (LTE), and Fifth Generation New Radio Access Technology (5G-NR). BACKGROUND

[0003] To meet the demand for wireless data traffic having increased since deployment of fourth generation (4G) communication systems, efforts have been made to develop an improved 5G or pre-5G communication system. Therefore, the 5G or pre-5G communication system is also called a "beyond 4G network" or a "post LTE system."

[0004] The 5G communication system is considered to be implemented in a higher frequency (millimeter wave) band, such as 60 GHz band, so as to implement a higher data rate. To decrease the propagation loss of the radio waves and increase the transmission distance, the beamforming, massive multiple-input multiple-output (MIMO), full dimensional MIMO (FD-MIMO), array antenna, analog beam forming, large scale antenna techniques are discussed in 5G communication systems.

[0005] In addition, the development of system network improvement is in progress based on advanced small cells, cloud radio access network (RAN), ultra-dense networks, a device-to-device (D2D) communication, wireless backhaul, a mobile network, a cooperative communication, coordinated multi-points (CoMP), reception-end interference cancellation and the like.

[0006] In 5G systems, hybrid frequency shift keying (FSK) and quadrature amplitude modulation (QAM) modulation (FSK and QAM modulation, FQAM), and sliding window superposition coding (SWSC) have been developed as advanced coding modulation (ACM), and filter bank multi carrier (FBMC), non-orthogonal multiple access (NOMA), and sparse code multiple access (SCMA) as advanced access technologies have been developed.

[0007] The Internet, a human-centric network of connected devices where humans generate and consume information, is evolving into the Internet of Things (IoT), in which distributed entities such as things exchange and process information without human intervention. The Internet of Everything (IoE) has emerged, combining IoT technology with big data processing technologies via connectivity to cloud servers. Because IoT implementations require technical elements such as sensing technology, wired / wireless communication and network infrastructure, service interface technology, and security technology, sensor networks, machine-to-machine (M2M) communication, and machine-type communication (MTC) have recently been researched. Such IoT environments can provide intelligent Internet technology services that create new value for human life by collecting and analyzing data generated by connected things. Through the convergence and integration of existing information technology (IT) and various industrial applications, the IoT can be applied to a variety of fields, including smart homes, smart buildings, smart cities, smart cars (connected vehicles), smart grids, healthcare, smart appliances, and advanced medical services.

[0008] In line with this, various attempts have been made to apply 5G communication systems to IoT networks. For example, technologies such as sensor networks, machine-type communications (MTC), and machine-to-machine (M2M) communications can be implemented using beamforming, MIMO, and array antennas. The application of cloud radio access networks (RAN), which are the aforementioned big data processing technologies, can also be considered an example of the convergence between 5G and IoT technologies.

[0009] Typically, when data is transmitted or received between a transmitter and a receiver in a communication system, data errors may occur due to noise present in the communication channel. Error-correcting coding schemes are designed to correct errors generated by the communication channel at the receiver. These error-correcting codes are also called channel codes. Error-correcting coding techniques add redundant bits to the data to be transmitted before transmitting that data.

[0010] There are various error correction coding techniques. For example, convolutional coding, turbo coding, low-density parity-check (LDPC) coding, and polar coding are known in the art. Polar coding is the first type of code theoretically proven to achieve point-to-point channel capacity by exploiting channel polarization. Polar coding allows for optimized code design for each channel or code rate using density evolution, Gaussian approximation (GA), reciprocal channel approximation (RCA), and other techniques.

[0011] 5G mobile communications technology, recently proposed as the next-generation mobile communications system, primarily addresses three scenarios: enhanced mobile broadband (eMBB), ultra-reliable and low latency communication (URLLC), and massive MTC (mMTC). Error-correcting codes designed to support these scenarios should also support a variety of bit rates with stable performance.

[0012] However, so far, a solution that satisfies all the above scenarios without increasing the complexity of the memory is not available. Therefore, it is necessary to provide such an encoding scheme.

[0013] The above information is presented as background information only to assist in understanding the present disclosure. No determination has been made, and no assertion is made, as to whether any of the above may be applicable as prior art with respect to the present disclosure. Summary of the Invention

[0014] Technical issues

[0015] The various aspects of the present disclosure are to at least address the above-mentioned problems and / or disadvantages and to provide at least the advantages described below. Therefore, one aspect of the present disclosure is to provide a rate matching operation with stable performance in a polar code encoding and decoding system. In particular, when rate matching is performed according to a method of interleaving the encoded bits in an appropriate order, storing the resulting bit sequence in a circular buffer, and then extracting the bits from the buffer, various embodiments of the present disclosure achieve excellent performance in a long-term evolution (LTE) or fifth-generation new radio access technology (5G-NR) communication system. In addition, various embodiments of the present disclosure achieve excellent performance in all cases where puncturing, shortening, and repetition occur due to rate matching through the above operations.

[0016] Additional aspects will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the presented embodiments.

[0017] Solution to the problem

[0018] According to one aspect of the present disclosure, a method performed by a transmitter in a communication system is provided, the method including: identifying a first bit sequence to be encoded, the first bit sequence including an information bit sequence and cyclic redundancy check (CRC) bits of the information bit sequence; identifying a second bit sequence by encoding the first bit sequence with a polar code; identifying a third bit sequence by interleaving the second bit sequence based on an interleaving pattern; performing rate matching on the third bit sequence by determining one of repetition, puncturing, or shortening as rate matching based on a length of the first bit sequence, a length of the second bit sequence, and a length of a rate matching output sequence; and obtaining the rate matching output sequence by performing the rate matching.

[0019] According to one aspect of the present disclosure, an apparatus in a communication system is provided, the apparatus including: a transceiver; and a controller coupled to the transceiver and configured to: identify a first bit sequence to be encoded, the first bit sequence including an information bit sequence and cyclic redundancy check (CRC) bits of the information bit sequence; identify a second bit sequence by encoding the first bit sequence with a polar code; identify a third bit sequence by interleaving the second bit sequence based on an interleaving pattern; determine one of repetition, puncturing, or shortening as rate matching based on a length of the first bit sequence, a length of the second bit sequence, and a length of a rate matching output sequence; perform the rate matching on the third bit sequence; and obtain the rate matching output sequence by performing the rate matching, wherein the interleaving pattern corresponds to {0, 1, 2, 4, 3, 5, 6, 7, 8, 16, 9, 17, 10, 18, 11, 19, 12, 20, 13, 21, 14, 22, 15, 23, 24, 25, 26, 28, 27, 29, 30, 31}.

[0020] According to one aspect of the present disclosure, a method for transmitting information using a polar code at a device is provided. The method includes identifying a first bit sequence, identifying a second bit sequence generated by encoding the first bit sequence using the polar code, dividing the second bit sequence into a predetermined number of sub-blocks, and identifying a third bit sequence based on a result of interleaving the sub-blocks according to a first pattern.

[0021] According to another aspect of the present disclosure, an apparatus for transmitting information using polar codes is provided. The apparatus includes a transceiver and at least one processor associated with the transceiver. The at least one processor is configured to identify a first bit sequence, identify a second bit sequence generated by encoding the first bit sequence with a polar code, divide the second bit sequence into a predetermined number of sub-blocks, and identify a third bit sequence based on a result of dividing the sub-blocks according to a first pattern interleaving.

[0022] According to another aspect of the present disclosure, a method for receiving information using a polar code at a device is provided. The method includes receiving at least one bit sequence and identifying information bits based on the at least one received bit sequence, generating a second bit sequence by encoding the first bit sequence with a polar code, dividing the second bit sequence into a predetermined number of sub-blocks, identifying a third bit sequence based on a result of interleaving the divided sub-blocks according to a first pattern, and generating the at least one received bit sequence based on the third bit sequence.

[0023] According to another aspect of the present disclosure, an apparatus for receiving information using polar codes is provided. The apparatus includes a transceiver and at least one processor associated with the transceiver. The at least one processor is configured to receive at least one bit sequence, identify information bits based on the at least one received bit sequence, generate a second bit sequence by encoding the first bit sequence using a polar code, divide the second bit sequence into a predetermined number of sub-blocks, identify a third bit sequence based on a result of interleaving the divided sub-blocks according to a first pattern, and generate the at least one received bit sequence based on the third bit sequence.

[0024] Beneficial effects of the present invention

[0025] According to various embodiments of the present disclosure, a polar code rate matching method, including selecting a mother code, selecting puncturing, shortening, or repetition techniques, configuring an interleaver, and operating a circular buffer, can achieve excellent and stable performance in communication and broadcast systems using polar codes. Furthermore, according to various embodiments of the present disclosure, the polar code rate matching method can simplify system operation by using a unified interleaver and circular buffer operation, regardless of puncturing, shortening, or repetition.

[0026] Other aspects, advantages, and salient features of the disclosure will become apparent to those skilled in the art from the following detailed description, which, taken in conjunction with the accompanying drawings, discloses various embodiments of the disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] The above and other aspects, features and advantages of certain embodiments of the present disclosure will become more apparent from the following description taken in conjunction with the accompanying drawings, in which:

[0028] Figure 1 is a block diagram illustrating a process of polar coding and rate matching according to an embodiment of the present disclosure;

[0029] Figure 2 is a flow chart illustrating a process of polar coding and rate matching according to an embodiment of the present disclosure;

[0030] Figure 3 1 is a diagram illustrating a process of determining a mother code size of a polar code according to an embodiment of the present disclosure;

[0031] Figure 4 is a diagram illustrating a process and criteria for selecting one of puncturing, shortening, and repetition for polar code rate matching according to an embodiment of the present disclosure;

[0032] Figure 5 is a diagram illustrating an interleaver operation based on sub-block permutation in the order of a small polar code sequence of size 8 according to an embodiment of the present disclosure;

[0033] Figure 6 is a diagram illustrating an interleaver operation based on sub-block permutation in the order of a small polar code sequence of size 16 according to an embodiment of the present disclosure;

[0034] Figure 7 is a diagram illustrating a process of storing a bit sequence obtained by performing a sub-block permutation-based interleaver operation in a buffer and loading bits from the buffer according to an embodiment of the present disclosure;

[0035] Figure 8 is a diagram illustrating an order in which bits stored in a circular buffer are extracted after a block permutation-based interleaver operation according to the first embodiment of the present disclosure;

[0036] Figure 9 is a diagram illustrating a process of determining a forced frozen subchannel in an encoding process when puncturing occurs in a rate matching operation for extracting bits after a block permutation-based interleaver operation according to a first embodiment of the present disclosure;

[0037] Figure 10 is a diagram illustrating a process of determining a forced frozen subchannel in an encoding process when shortening occurs in a rate matching operation for extracting bits after a block permutation-based interleaver operation according to a first embodiment of the present disclosure;

[0038] Figure 11 is a diagram illustrating an order in which bits stored in a circular buffer are extracted after a block permutation-based interleaver operation according to a second embodiment of the present disclosure;

[0039] Figure 12 is a diagram illustrating a process of determining a forced frozen subchannel in an encoding process when puncturing occurs in a rate matching operation for extracting bits after a block permutation-based interleaver operation according to a second embodiment of the present disclosure;

[0040] Figure 13 is a diagram illustrating an order of extracting bits stored in a circular buffer after a block permutation-based interleaver operation according to a third embodiment of the present disclosure;

[0041] Figure 14 is a diagram illustrating an order in which bits stored in a circular buffer are extracted after a cross-based interleaver operation according to a fourth embodiment of the present disclosure;

[0042] Figure 15 is a diagram illustrating a process of determining a forced frozen subchannel in an encoding process when puncturing occurs in a rate matching operation for extracting bits after a block permutation-based interleaver operation according to a fourth embodiment of the present disclosure;

[0043] Figure 16 This is a diagram showing the determination according to an embodiment of the present disclosure. Figure 2A flowchart of the detailed process of interleaving described in;

[0044] Figure 17 is a flowchart illustrating a process when a block permutation-based interleaver is used together with a sub-channel allocation adjustment operation or a permutation operation in a sub-block according to an embodiment of the present disclosure;

[0045] Figure 18 is a block diagram illustrating a transmitter apparatus according to an embodiment of the present disclosure; and

[0046] Figure 19 is a block diagram illustrating a receiver device according to an embodiment of the present disclosure.

[0047] Throughout the drawings, it should be noted that like reference numbers are used to depict the same or similar elements, features, and structures. DETAILED DESCRIPTION

[0048] The following description, with reference to the accompanying drawings, is provided to facilitate a more comprehensive understanding of the various embodiments of the present disclosure as defined by the claims and their equivalents. It includes various specific details to assist understanding, but these are to be considered merely exemplary. Therefore, those skilled in the art will recognize that various changes and modifications may be made to the various embodiments described herein without departing from the scope and spirit of the present disclosure. Furthermore, descriptions of well-known functions and structures may be omitted for clarity and conciseness.

[0049] The terms and words used in the following description and claims are not limited to the bibliographical meanings, but are merely used by the inventor to enable a clear and consistent understanding of the present disclosure. Therefore, it will be apparent to those skilled in the art that the following description of various embodiments of the present disclosure is provided for illustration purposes only and not for the purpose of limiting the present disclosure as defined by the appended claims and their equivalents.

[0050] It is to be understood that the singular forms "a," "an," and "the" include plural referents unless the context clearly dictates otherwise. Thus, for example, reference to "a component surface" includes reference to one or more of such surfaces.

[0051] In the following description of various embodiments, descriptions of technologies well known in the art and not directly related to the present disclosure are omitted. This is to clearly convey the subject matter of the present disclosure by omitting any unnecessary explanations.

[0052] For the same reason, some elements in the accompanying drawings are enlarged, omitted or schematically shown. In addition, the size of each element does not fully reflect the actual size. In the accompanying drawings, the same or corresponding elements are represented by the same reference numerals.

[0053] The advantages and features of the present disclosure and the manner in which they are achieved will become apparent with reference to the various embodiments described in detail below and with reference to the accompanying drawings. However, the present disclosure can be embodied in many different forms and should not be construed as being limited to the various embodiments set forth herein. On the contrary, these embodiments are provided to make the present disclosure thorough and complete and to fully convey the scope of the present disclosure to those skilled in the art. In order to fully disclose the scope of the present disclosure to those skilled in the art, the present disclosure is limited only by the scope of the claims.

[0054] It should be understood that each block in the flowchart illustration, as well as combinations of blocks in the flowchart illustration, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing device to produce a machine, such that the instructions executed by the processor of the computer or other programmable data processing device generate a device for implementing the functions specified in the flowchart block or multiple flowchart blocks. These computer program instructions can also be stored in a computer-usable or computer-readable memory, which can direct the computer or other programmable data processing device to operate in a specific manner so that the instructions stored in the computer-usable or computer-readable memory generate an article of manufacture including instruction means for implementing the functions specified in the flowchart block or multiple flowchart blocks. The computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operations are performed on the computer or other programmable device, thereby producing a computer-implemented process, such that the instructions executed on the computer or other programmable device provide operations for implementing the functions specified in the flowchart block or multiple flowchart blocks.

[0055] In addition, each block of the flowchart diagram may represent a module, segment or portion of code, which includes one or more executable instructions for implementing a specified (multiple) logical function. It should also be noted that in some alternative embodiments, the functions marked in the blocks may occur out of order. For example, depending on the functionality involved, two blocks shown in succession may actually be executed substantially simultaneously, or the blocks may sometimes be executed in reverse order.

[0056] The term "unit" as used herein may refer to software or hardware components or devices that perform certain tasks, such as field programmable gate arrays (FPGAs) or application specific integrated circuits (ASICs). Units may be configured to reside on addressable storage media and to be configured to execute on one or more processors. Therefore, as an example, modules or units may include components, such as software components, object-oriented software components, class components and task components, processes, functions, attributes, procedures, subroutines, program code segments, drivers, firmware, microcodes, circuit systems, data, databases, data structures, tables, arrays, and variables. The functionality provided in components and units may be combined into fewer components and units, or further separated into additional components and modules. In addition, components and units may be implemented as one or more central processing units (CPUs) in operating equipment or secure multimedia cards.

[0057] Now, various embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0058] Polar codes are error-correcting codes proposed by E. Arikan in 2008. They are the first codes proven to achieve channel capacity (i.e., the data transmission limit) in all binary discrete memoryless channels (B-DMC) while maintaining low coding and complexity performance. Compared to other channel capacity-approximating codes such as turbo codes and low-density parity-check (LDPC) codes, polar codes offer advantages in error correction performance and decoding complexity when transmitting short-length codes. As a result, in 2017, polar codes were identified for the transmission of short-length control information in the 3rd Generation Partnership Project (3GPP) NR standardization for fifth-generation (5G) mobile communications.

[0059] Figure 1 The polar code encoding process according to an embodiment of the present disclosure is shown.

[0060] refer to Figure 1 , discloses a polarization coding method.

[0061] In this embodiment, the number of information bits to be transmitted during the encoding process is K, and the number of codeword bits transmitted through the channel after encoding is M. In addition, the number of mother polar code bits of the polar code is N.

[0062] 1) Information bit generation

[0063] Given the information bit sequence to be sent b={b0,b1,...,b K-1}.

[0064] 2) External code

[0065] At operation 110, the information bit sequence b is encoded into an outer code for performance enhancement. The outer code used is an error detection code such as a cyclic redundancy check (CRC) code, an error correction code such as a Bose-Chaudhuri-Hocquenghem (BCH) code, or a single parity check code. The length of the parity generated by the outer code is determined by K outer Represented by, and the bit sequence caused by the external coding is represented by b'={b'0,b'1,...,b' K+Kouter-1} indicates that external encoding is not a necessary operation. Therefore, when external encoding is not considered, K outer =0 and b'=b.

[0066] 3) Subchannel allocation

[0067] At operation 120, for polar coding, the bit sequence b' is mapped to a bit sequence u = {u0, u1, ..., u N-1}. The length N indicating the size of the mother polar code is a power of 2, and the length N is determined by a preset criterion. The mother polar code is a codeword before shortening or puncturing, and will be further described in the generator matrix multiplication below. The letter u indicates the input bit sequence of the polarization code, and each bit of u can be interpreted as if passing through subchannels of different qualities generated by the channel polarization. Due to this feature, the process of mapping b' to u is called a subchannel allocation process. Generally, the subchannel allocation process of the polarization code consists of the following three operations, as shown below.

[0068] A. First, the locations of subchannels that cannot carry information through puncturing or shortening after encoding are determined. That is, the indices of the bits in the bit sequence u to which the outer coded bits are not mapped through puncturing or shortening are determined. Polar code puncturing refers to not transmitting a portion of the mother code bit sequence generated by the transmitter's encoding. Because the codeword bits are not transmitted even after they are generated, the receiver cannot know the probability information about the codeword bits, so the received value or log-likelihood ratio (LLR) value can be set to zero. Furthermore, polar code shortening refers to fixing a portion of the encoder input bit sequence to zero, causing a portion of the codeword bits generated by encoding to become zero. The transmitter does not transmit codeword bits that always become zero according to the encoding results. Knowing that a codeword bit has a zero value even when not received, the receiver sets the received value or LLR value of that bit to a very large value indicating a zero bit value. During this shortening process, the shortened bit at the encoder input and the corresponding bit at the output do not need to have a zero bit value; any value that satisfies the polar code encoding equation can be used. However, for ease of implementation, this value is typically fixed to zero. If the number of bits that are punctured or shortened after encoding is N p Indicates that N in the bit sequence u p bits will pass through an unused (incapable) subchannel or a shortened subchannel. In the case of puncturing, an unused subchannel appears, and in the case of shortening, a shortened subchannel appears. The position of the unused / shortened subchannel is determined by the position of the punctured or shortened bit in the encoding result. That is, taking into account the punctured or shortened bit, the index of the bit to which the outer coded bit is not mapped is determined among the bits of the polar encoder input bit sequence u.

[0069] B. Each bit of the input bit sequence b' is mapped to the remaining bits of u. The bit positions in sequence u to which the bits of b' are mapped are determined by the channel capacity of the subchannels through which each bit of sequence u will pass. In other words, b' is mapped so that it is transmitted on the subchannel with the largest channel capacity among the subchannels of sequence u. A sequence in which the subchannel indices of sequence u are arranged in order of channel capacity is used for this purpose. This is called a polar code sequence. The polar code sequence can be stored in the transmitter / receiver memory or obtained through specific operations at each transmission / reception.

[0070] C. The remaining bits of sequence u are called frozen bits. Although information can be transmitted as a result of the above operation, the bits of sequence u that pass through the subchannel with low channel capacity become frozen bits. Frozen bits are set to a value agreed upon by the transmitter and receiver and are usually fixed to zero unless otherwise specified.

[0071] 4) Generator matrix multiplication

[0072] At operation 130, the bit sequence u of length N is multiplied by the NxN generator matrix G of the polar code to generate a bit sequence x of length N. The bit sequence x is called the mother code of the polar code. When Arikan proposed the polar code, the generator matrix G was defined as follows.

[0073]

[0074] In the above formula, and superscript The n operation represents n times the Kronecker power. For example, and In addition, B N is a bit-reversal permutation matrix of size N×N. For example, multiplying {a0,a1,a2,a3,a4,a5,a6,a7} by B8 yields {a0,a4,a2,a6,a1,a5,a3,a7}. However, in the latest documents and systems including 5G-NR, the addition of B is considered. N A simple generator matrix other than is shown below.

[0075]

[0076] In the following, unless otherwise stated, the generator matrix is ​​assumed to be defined as The description based on this assumption can be easily applied to the bit-reversal permutation operation defined as Polar code generator matrix.

[0077] 5) Interleaving and rate matching

[0078] At operation 140, the bit sequence x of length N generated by the generator matrix multiplication is interleaved for efficient rate matching. At operation 150, the interleaved bit sequence is stored in a buffer of size N. In mobile communication systems such as Long Term Evolution (LTE) or 5G-NR, a virtual circular buffer is generally assumed. The interleaved bit sequence is stored sequentially in the virtual circular buffer, and M bits are loaded and sent sequentially therefrom. If M is less than N, NM bits can be punctured in the reverse order of the order stored in the virtual circular buffer, or shortened by NM bits in the order of storage. If M is greater than N, MN bits are repeated in the order stored in the virtual circular buffer. The interleaver should be designed to obtain stable performance even with puncturing, shortening and repetition.

[0079] The interleaver used for rate matching should be appropriately designed to suit the characteristics of polar codes. Some codeword bits may be punctured, shortened, or repeated due to rate matching, resulting in changes in the channel experienced by the bits of the x-vector at the polar code decoder. In the case of puncturing, the corresponding bits are not transmitted, so such bits can be considered to have experienced a very degraded channel. In the case of shortening, the value of the corresponding bit is precisely known, so such bits can be considered to have experienced a very good channel. In the case of repetition, soft combining is performed by receiving probability information about the corresponding bits two or more times, so such bits can be considered to have experienced a relatively good channel compared to non-repeated bits. Because such changes in the channel experienced by the bits of the x-vector significantly affect the performance of the polar code, it is necessary to appropriately select the locations of the punctured, shortened, and repeated bits. The bit interleaver performs this function.

[0080] Figure 2 The operation of the transmitter according to an embodiment of the present disclosure is conceptually illustrated in consideration of rate matching. Similarly, although not shown, the receiver may perform corresponding operations to configure the decoder in consideration of rate matching.

[0081] refer to Figure 2 , discloses the operation of a transmitter taking rate matching into consideration according to an embodiment of the present disclosure.

[0082] First, at operation 205, a length K of bits to be transmitted and a length M of codeword bits to be transmitted through a channel are given.

[0083] At operation 210, the transmitter determines a size N of a mother code to be used for polar encoding.

[0084] At operation 215, based on the above parameters N, K, and M and a predetermined criterion, the transmitter determines which rate matching operation of puncturing, shortening, and repetition is to be performed.

[0085] If it is determined to perform a puncturing or shortening operation, as described above, the transmitter determines a subchannel that cannot be selected from among the subchannels for information transmission at operation 220. At this time, the subchannel that cannot be selected is determined in consideration of the interleaving and rate matching operations to be performed subsequently. Specifically, in an embodiment, in consideration of the puncturing or shortening operation, all bits may be divided into subblocks, and this may be performed in consideration of the interleaving operation.

[0086] At operation 225, the transmitter performs subchannel allocation on information bits to be transmitted.

[0087] At operation 230, the transmitter performs polar encoding.

[0088] At operation 235, the transmitter interleaves a bit sequence obtained as a result of the encoding based on a predetermined scheme.

[0089] At operation 240, the transmitter stores the interleaved bit sequence in a buffer.

[0090] At operation 245, the transmitter loads M bits to be transmitted through the channel from the buffer. Thereafter, after performing channel interleaving, modulation, etc., the bits are transmitted through the channel. In the following, these operations will be described separately.

[0091] Figure 3 FIG. 4 shows a process of obtaining a mother code size N of a polar code from given parameters K and M according to an embodiment of the present disclosure.

[0092] refer to Figure 3 , shows a method for determining the mother code size N based on given parameters K and M.

[0093] At operation 305, a length K of bits to be transmitted and a length M of codeword bits to be transmitted through a channel are given.

[0094] At operation 310, N is calculated. M 、N R and N max In order to calculate N M , first calculate the smallest power of 2 that is greater than M, Then, if and Then N M Calculated as N DM / 2, and if not, then N M Calculated as N DM In one embodiment of the present disclosure, considering β=1.15 and R a =0.4, an appropriate mother code size can be selected. In one embodiment of the present disclosure, another parameter N R is calculated as And consider R b =1 / 6. Parameter N max is the maximum polar code size that the system can support.

[0095] At operation 315, based on the above-calculated values, the mother code size N of the polar code to be used for encoding and decoding with respect to K and M is determined to be N M 、N R and N max The minimum value among the calculated values.

[0096] Figure 4 A process of determining which operation to perform among puncturing, shortening, and repeating operations based on the above parameters K and M and the mother code size N obtained through the above process according to an embodiment of the present disclosure is shown.

[0097] refer to Figure 4 , based on K, M and N, it can be determined which operation among puncturing, shortening and repeating will be used to send data.

[0098] At operation 405, a length K of bits to be transmitted and a length M of codeword bits to be transmitted through a channel are given.

[0099] At operation 410 , it may be determined whether M is greater than N.

[0100] If M is greater than N, then it is determined at operation 415 that MN bits are repeated after encoding. In this case, since all bits generated by encoding are transmitted, there is no subchannel that is forced to be frozen by puncturing. Therefore, the relevant calculation process can be omitted.

[0101] On the other hand, if M is less than M, a puncturing or shortening operation will be performed.

[0102] At operation 420, it may be determined whether the code rate K / M is equal to or lower than a predetermined reference code rate R c .

[0103] If the code rate K / M is equal to or lower than the predetermined reference code rate R c , then at operation 425 , it is determined to puncture the NM bits of the obtained encoded x-bit vector.

[0104] If the code rate K / M is greater than the predetermined reference code rate R c , then the NM bits of the shortened coded x-bit vector are determined at operation 430. In one embodiment of the present disclosure, considering the performance, the reference code rate R for determining the puncturing and shortening is c It may be 0.35, and this value may vary according to various embodiments.

[0105] As described above, if M is less than N, whether to perform shortening or puncturing may be determined based on the code rate.

[0106] Figure 5 and Figure 6 is a diagram illustrating the operation of a sub-block permutation-based interleaver for rate matching according to an embodiment of the present disclosure.

[0107] refer to Figure 5 and Figure 6 , illustrating a sub-block permutation-based interleaver operation for rate matching according to various embodiments of the present disclosure.

[0108] The x-vector obtained by encoding the polar code with a mother code of size N at operation 505 is divided into T sub-blocks at operation 510, and then interleaving is performed based on the sub-blocks. Herein, T is a power of 2, which is smaller than N and is a relatively small value. Generally, T is determined to be 8, 16, or 32, and can be set to a larger value. Therefore, each sub-block contains N / T bits. The sub-blocks are arranged in a predetermined order (i.e., an interleaver pattern) P. T In one embodiment of the present disclosure, P T The polar code sequences Q8, Q3, and Q4 of length 8, 16, and 32 follow the order of the short polar code sequence. 16 and Q 32 has a deterministic form that is independent of the channel signal-to-noise ratio (SNR) and is given by the following equation.

[0109] Q8={0,1,2,4,3,5,6,7}...Equation 3

[0110] Q 16 ={0,1,2,4,8,3,5,6,9,10,12,7,11,13,14,15}...Equation 4

[0111] Q 32 ={0,1,2,4,8,16,3,5,6,9,10,17,12,18,20,24,7,11,13,19,14,21,

[0112] 22,25,26,28,15,23,27,29,30,31}...Equation 5

[0113] At operation 510, by using the T =Q8={0,1,2,4,3,5,6,7} interleaves the polar coding bit sequence in units of sub-blocks. At operation 515, the result is stored in a buffer.

[0114] The x vector obtained by encoding with the polar code having the mother code of size N at operation 605 is divided into T sub-blocks at operation 610, and then interleaving is performed based on the sub-blocks. Specifically, at operation 610, by using the vector determined as P T =Q 16 ={0,1,2,4,8,3,5,6,9,10,12,7,11,13,14,15}, interleaves the bit sequence generated by polar coding in units of sub-blocks. At operation 615, the result is stored in a buffer.

[0115] In various embodiments, P indicating the interleaver patternT does not necessarily equal the short length polar code sequence Q T However, in one embodiment of the disclosure, for excellent performance, it is possible to consider at least the partial order of Q T For example, to determine P 16 , the order of the first eight elements of Q 16 is used, and the order of the last eight elements follows the ascending order of numbers. As a result, P 16 is determined as P 16 ={0, 1, 2, 4, 8, 3, 5, 6, 7, 9, 10, 11, 12, 13, 14, 15}. This sequence is a simple example (not limited thereto), and the form of the sub-block permutation is not necessarily limited to a specific form.

[0116] Figure 7 shows a process of interleaving a bit sequence obtained by encoding based on a P8-based block permutation, storing it in a buffer, and then loading it for rate matching according to an embodiment of the disclosure.

[0117] Referring to Figure 7 , a technical feature of an embodiment in which, considering rate matching, bits after polar encoding are interleaved and then stored in a buffer is disclosed. Although an interleaver based on a P8-based sub-block permutation is assumed as an example for simplicity, any other sequence can also be used.

[0118] The x vector obtained by encoding at operation 705 with a polar code having a mother code of size N is divided into T sub-blocks at operation 710, and then interleaving is performed based on the sub-blocks. At operation 715, the bit sequence interleaved in units of sub-blocks is stored in a buffer, and then M bits are loaded from the buffer and transferred to a process such as a channel interleaver or a modulator. In various embodiments of the disclosure, as shown in Figure 7 , operations of a circular buffer used in a general communication system are considered. The following embodiments relate to operations of a circular buffer with respect to repetition, puncturing, and shortening.

[0119] Figure 8 is a diagram showing the order of bits stored in a circular buffer after the operation of a block permutation-based interleaver according to a first embodiment of the disclosure.

[0120] Referring to Figure 8 , a method of loading and extracting an interleaved bit sequence from a circular buffer is shown.

[0121] The x-vector obtained by encoding the polar code with a mother code of size N at operation 805 is divided into T sub-blocks at operation 810, and then interleaving is performed on a sub-block basis. At operation 815, the bits stored in the circular buffer can be loaded sequentially regardless of puncturing, shortening, and repeating operations. That is, first, the bits in the 0th sub-block are loaded sequentially, and then the bits in the first sub-block are loaded sequentially. Such bits are not loaded in units of sub-blocks. Therefore, in the case of puncturing or shortening, the NM bits stored in the rear portion of the buffer are punctured or shortened. And, in the case of repetition, the MN bits stored in the front portion of the buffer are repeated.

[0122] Figure 9 is a diagram illustrating a process of determining a forced frozen subchannel in an encoding process when puncturing occurs in a rate matching operation for extracting bits after a block permutation-based interleaver operation according to the first embodiment of the present disclosure.

[0123] refer to Figure 9 , a method for determining frozen subchannels in order to perform puncturing during an encoding process is shown.

[0124] In the case of puncturing, at operation 910, the NM bits stored in the rear portion of the buffer are punctured. Because the bits stored in the buffer are interleaved by subblock permutation, the punctured bits in the coding diagram of the polar code are interleaved in a pattern defined by the reverse process of interleaving. When extracting bits according to the first embodiment, at operation 905, the subchannels are forcibly frozen at the encoding end in the reverse order of the puncturing pattern. That is, if the last ten bits of the seventh subblock are punctured at operation 910, the subchannels of the first ten bits of the 0th subblock are forcibly frozen at operation 905. This is related to the duality of the puncturing pattern, and if the puncturing pattern is well designed, the forced freezing can be performed in the reverse order of the puncturing. Encoding is performed by replacing the forced frozen positions with values ​​(such as zero) agreed upon by the transmitter and receiver.

[0125] Figure 10 is a diagram illustrating a process of determining a forced frozen subchannel in an encoding process when shortening occurs in a rate matching operation for extracting bits after a block permutation-based interleaver operation according to the first embodiment of the present disclosure.

[0126] refer to Figure 10 , a method for determining frozen subchannels in an encoding process in order to perform shortening is shown.

[0127] In the case of shortening, at operation 1010, the NM bits stored in the rear portion of the buffer are shortened. Because the bits stored in the buffer are interleaved using subblock permutation, the shortened bits in the polar code's coding pattern are interleaved in a pattern defined by the inverse of the interleaving process. In the case of bit extraction according to the first embodiment, at operation 1005, the subchannels are forcibly frozen at the encoding end in the same order as the shortening pattern. Coding is performed by replacing the forcibly frozen positions with values ​​agreed upon by the transmitter and receiver. In embodiments, this committed value may be, but is not limited to, zero.

[0128] Figure 11 is a diagram illustrating an order in which bits stored in a circular buffer are extracted after a block permutation-based interleaver operation according to a second embodiment of the present disclosure.

[0129] refer to Figure 11 , shows a method of loading and extracting an interleaved bit sequence from a circular buffer.

[0130] The x-vector obtained by encoding into a polar code having a mother code of a determined size N at operation 1105 is divided into T sub-blocks at operation 1110, and then interleaving is performed based on the sub-blocks. At operation 1115, in the case of a shortening or repetition operation, the bits stored in the circular buffer may be loaded in forward sequence, and in the case of a puncturing operation, may be loaded in reverse sequence. That is, in the case of shortening or repetition, the bits in the 0th sub-block are first loaded sequentially, and then the bits in the first sub-block are loaded sequentially. On the other hand, in the case of puncturing, the bits in the seventh sub-block are first loaded in reverse, and then the bits in the sixth sub-block are loaded in reverse. Such bits are not loaded in units of sub-blocks. Therefore, in the case of shortening, the NM bits stored in the rear part of the buffer are shortened. In addition, in the case of puncturing, the NM bits stored in the front part of the buffer are punctured. And, in the case of repetition, the MN bits stored in the front part of the buffer are repeated. The determination of the sub-channels that are forcibly frozen at the encoding end by shortening follows Figure 10 The above embodiment.

[0131] Figure 12 is a diagram illustrating a process of determining a forced frozen subchannel in an encoding process when puncturing occurs in a rate matching operation for extracting bits after a block permutation-based interleaver operation according to a second embodiment of the present disclosure.

[0132] refer to Figure 12 , a method for determining frozen subchannels in order to perform puncturing during an encoding process is shown.

[0133] In the case of puncturing, at operation 1210, the NM bits stored in the front portion of the buffer are punctured. Because the bits stored in the buffer are interleaved using subblock permutation, the punctured bits in the code map of the polar code are interleaved in a pattern defined by the inverse of the interleaving process. When extracting bits according to the second embodiment, at operation 1205, the subchannels are forcibly frozen at the encoding end in the reverse order of the puncturing pattern. Encoding is performed by replacing the forcibly frozen positions with the values ​​agreed upon by the transmitter and receiver.

[0134] Figure 13 is a diagram illustrating an order of extracting bits stored in a circular buffer after a block permutation-based interleaver operation according to a third embodiment of the present disclosure.

[0135] refer to Figure 13 , showing a method of loading and extracting an interleaved bit sequence from a circular buffer.

[0136] The x-vector obtained by encoding into a polar code having a mother code of a determined size N at operation 1305 is divided into T sub-blocks at operation 1310, and then interleaving is performed on a sub-block basis. At operation 1315, in the case of a shortening operation, the bits stored in the circular buffer may be loaded in forward sequence, and in the case of a puncturing or repetition operation, may be loaded in reverse sequence. That is, in the case of shortening, the bits in the 0th sub-block are first loaded sequentially, and then the bits in the first sub-block are loaded sequentially. On the other hand, in the case of puncturing or repetition, the bits in the seventh sub-block are first loaded in reverse, and then the bits in the sixth sub-block are loaded in reverse. Such bits are not loaded in units of sub-blocks. Therefore, in the case of shortening, the NM bits stored in the rear part of the buffer are shortened. And, in the case of puncturing, the NM bits stored in the front part of the buffer are punctured. And, in the case of repetition, the MN bits stored in the rear part of the buffer are repeated. The determination of the sub-channels forcibly frozen at the encoding end by puncturing follows Figure 12 The above embodiment, and the determination of the sub-channel forced to be frozen at the encoding end by shortening follows Figure 10 The above embodiment.

[0137] Figure 14 is a diagram illustrating an order in which bits stored in a circular buffer are extracted after a cross-based interleaver operation according to a fourth embodiment of the present disclosure.

[0138] refer to Figure 14 , shows the order of bits stored in the buffer after the cross-based interleaver operation.

[0139] The output bit sequence encoded into the polar code at operation 1405 is divided into four sub-blocks {0, 1, 2, 3} in a cross-based interleaver at operation 1410. Then, at operation 1415, the bits of sub-blocks 1 and 2 are interleaved. For such an interleaving scheme, the following scheme has been used: Figure 13 The method for extracting bits from the buffer is shown. The presently disclosed embodiments consider a method for sequentially and uniformly loading bits, regardless of puncturing, shortening, or repetition, even after a cross-based interleaver operation. This is a transmission method that utilizes a binary relationship between the subchannels that are forcibly frozen at the code input and the bits that are punctured at the code output. By uniformly loading bits, uniform buffer management can be achieved.

[0140] Figure 15 is a diagram illustrating a process of determining a forced frozen subchannel in an encoding process when puncturing occurs in a rate matching operation for extracting bits after a block permutation-based interleaver operation according to a fourth embodiment of the present disclosure.

[0141] refer to Figure 15 , shows a method for determining frozen subchannels for puncturing during the encoding process. As described above, in this embodiment, the forcibly frozen subchannels are also determined in the reverse order of the puncturing pattern. In the case of puncturing, at operation 1510, the NM bits stored in the front portion of the buffer may be punctured. In the case of extracting bits according to the second embodiment, at operation 1505, the subchannels are forcibly frozen at the encoding end in the order of the puncturing pattern.

[0142] Meanwhile, in this embodiment, the size and number of sub-blocks used in the block permutation-based interleaver operation may vary depending on the size of the mother code. An embodiment of determining the number of sub-blocks for each mother code size is as follows.

[0143] 1) A method for determining the number of subblocks for each mother code size while fixing the subblock size: For example, if the subblock size used in a block permutation-based interleaver is fixed to 8, then the number of subblocks used when the mother code size is 64, 128, 256, 512, or 1024 is determined to be 8, 16, 32, 64, or 128. Similarly, if the subblock size is 16, then the number of subblocks is determined to be 4, 8, 16, 32, or 64 when the mother code size is 64, 128, 256, 512, or 1024. The number of subblocks can be determined in the same manner for other subblock sizes. This method can be advantageous in hardware implementations because the subblock size remains unchanged even if the mother code size changes.

[0144] 2) Method for independently determining the number of subblocks for each mother code size: The optimal number of subblocks is determined, taking into account the performance and implementation complexity of each mother code size. In this case, the number of subblocks used when the mother code size is 256 is independent of the number of subblocks used when the mother code size is 512. The number of subblocks can be determined by performing an optimization operation for each mother code size.

[0145] 3) Method for maintaining the number of sub-blocks for each mother code size: Even if the mother code size changes to 64, 128, 256, 512, 1024, etc., the number of sub-blocks used in the interleaver remains consistent.

[0146] In addition, the interleaving order P of the sub-blocks in the interleaver operation T It can be determined as follows.

[0147] 1) Used to determine P according to the number of sub-blocks used T Method: P is used differently according to the number of sub-blocks determined in the block permutation operation. T In this case, P can be determined by performing performance optimization for each given number of sub-blocks. T .

[0148] 2) Used to determine P according to the size of the mother code T Method: Use P differently according to the size of the mother code used T In this case, P can be determined by performing performance optimization on each mother code of a given size. T .

[0149] Interleaving order P T The characteristic of is that it satisfies the partial order condition. In this article, partial order is one of the characteristics of the polar code sequence considered in the polar code design, and is a condition indicating the reliability order (or channel state order or subchannel error rate order) between the subchannels of the polar code regardless of the physical channel environment. In order to maintain Figure 12 and 15 The relationship between rate matching and freezing described in the interleaving order P T Select from an order that satisfies the partial order.

[0150] In this embodiment, a partial order is a relationship between two integers. In the binary representation of two integers a and b, the set of positions where 1 exists is a subset of a that can be greater than or equal to b. This can be determined based on the binary representation of each sub-block index, as described in the above embodiment. For example, smaller indices can be placed at the front of the sequence.

[0151] One of the above embodiments is as follows: The following is a simple example (not limited thereto), and the number of sub-blocks used by each mother code and the interleaving order can be determined based on at least one of the above methods.

[0152] 1. When the mother code size is 64

[0153] - Number of sub-blocks: 4

[0154] -P T ={0,1,2,3}

[0155] 2. When the mother code size is 128

[0156] - Number of sub-blocks: 8

[0157] -P T ={0,1,2,4,3,5,6,7}

[0158] 3. When the mother code size is 256

[0159] - Number of sub-blocks: 16

[0160] -P T ={0,1,2,4,8,3,5,6,9,10,12,7,11,13,14,15}

[0161] 4. When the mother code size is 512

[0162] - Number of sub-blocks: 32

[0163] -P T ={0,1,2,4,8,16,3,5,6,9,10,17,12,18,20,24,7,11,21,22,25,26,28,15,23,27,29,30,31}

[0164] The above interleaving order P T An embodiment of is as follows. When the number of sub-blocks is A, the interleaving order P T It can be expressed as the following three parts:

[0165] P T ={P T1 ,P T2 ,P T3}

[0166] Here, P T1 is a sequence of length A1, and is generated by arranging the natural numbers from 0 to A1-1 in a partial order. For example, if A1 is 8, then P T1 An example of is {0,1,2,4,3,5,6,7}. And, P T3is a sequence of length A1 and is generated by arranging the natural numbers from A-A1 to A-1 in a partial order. For example, if A is 32 and A1 is 8, then P T3 An example of is {24,25,26,28,27,29,30,31}.

[0167] In addition, its length A2 is P of A-2A1 T2 is constructed by interweaving the natural numbers from A1 to A-A1-1 as shown below.

[0168]

[0169] For example, when A is 32 and A1 is 8, P T2 were identified as follows:

[0170] {8,16,9,17,10,18,11,19,12,20,13,21,14,22,15,23}.

[0171] And, when A is 32 and A1 is 8, the interleaving order P T An example is as follows:

[0172] P T ={0,1,2,4,3,5,6,7,8,16,9,17,10,18,11,19,12,20,13,21,14,22,15,

[0173] 23,24,25,26,28,27,29,30,31}.

[0174] As the interleaving order P T A possible representation of P is that a natural number can be added to the above P T For example, P T It is possible to start from 1 instead of 0. Also, the order of the symbols can be reversed.

[0175] P that satisfies the partial order T Representative examples are as follows:

[0176] Example 1) A=32, A1=8

[0177] P T ={0, 1, 2, 3, 4, 5, 6, 7, 8, 16, 9, 17, 10, 18, 11, 19, 12, 20, 13, 21, 14, 22, 15, 23, 24, 25, 26, 27, 28, 29, 30, 31}

[0178] P T={0, 1, 2, 3, 4, 5, 6, 7, 8, 16, 9, 17, 10, 18, 11, 19, 12, 20, 13, 21, 14, 22, 15, 23, 24, 25, 26, 28, 27, 29, 30, 31}

[0179] P T ={0, 1, 2, 4, 3, 5, 6, 7, 8, 16, 9, 17, 10, 18, 11, 19, 12, 20, 13, 21, 14, 22, 15, 23, 24, 25, 26, 27, 28, 29, 30, 31}

[0180] PT={0,1,2,4,3,5,6,7,8,16,9,17,10,18,11,19,12,20,13,21,14,22,15,23,24,25,26,28,27,29,30,31}

[0181] Example 2) A=32, A1=10

[0182] P T ={0, 1, 2, 4, 8, 3, 5, 9, 6, 7, 10, 16, 11, 17, 12, 18, 13, 19, 14, 20, 15, 21, 24, 25, 22, 26, 28, 23, 27, 29, 30, 31}

[0183] P T ={0, 1, 2, 4, 8, 3, 5, 6, 9, 7, 10, 16, 11, 17, 12, 18, 13, 19, 14, 20, 15, 21, 24, 22, 25, 26, 28, 23, 27, 29, 30, 31}

[0184] P T ={0, 1, 2, 4, 8, 3, 5, 6, 7, 9, 10, 16, 11, 17, 12, 18, 13, 19, 14, 20, 15, 21, 22, 24, 25, 26, 28, 23, 27, 29, 30, 31}

[0185] P T ={0, 1, 2, 4, 3, 8, 5, 9, 6, 7, 10, 16, 11, 17, 12, 18, 13, 19, 14, 20, 15, 21, 24, 25, 22, 26, 23, 28, 27, 29, 30, 31}

[0186] P T={0,1,2,4,3,8,5,6,9,7,10,16,11,17,12,18,13,19,14,20,15,21,24,22,25,26,23,28,27,29,30,31}

[0187] P T ={0,1,2,4,3,8,5,6,7,9,10,16,11,17,12,18,13,19,14,20,15,21,22,24,25,26,23,28,27,29,30,31}

[0188] P T ={0,1,2,4,3,5,8,9,6,7,10,16,11,17,12,18,13,19,14,20,15,21,24,25,22,23,26,28,27,29,30,31}

[0189] P T ={0,1,2,4,3,5,8,6,9,7,10,16,11,17,12,18,13,19,14,20,15,21,24,22,25,23,26,28,27,29,30,31{

[0190] P T ={0,1,2,4,3,5,8,6,7,9,10,16,11,17,12,18,13,19,14,20,15,21,22,24,25,23,26,28,27,29,30,31{

[0191] P T ={0,1,2,4,3,5,6,8,9,7,10,16,11,17,12,18,13,19,14,20,15,21,24,22,23,25,26,28,27,29,30,31}

[0192] P T -{0,1,2,4,3,5,6,8,7,9,10,16,11,17,12,18,13,19,14,20,15,21,22,24,23,25,26,28,27,29,30,31}

[0193] P T ={0,1,2,4,3,5,6,7,8,9,10,16,11,17,12,18,13,19,14,20,15,21,22,23,24,25,26,28,27,29,30,31}

[0194] P T ={0,1,2,3,4,8,5,9,6,7,10,16,11,17,12,18,13,19,14,20,15,21,24,25,22,26,23,27,28,29,30,31}

[0195] P T ={0,1,2,3,4,8,5,6,9,7,10,16,11,17,12,18,13,19,14,20,15,21,24,22,25,26,23,27,28,29,30,31}

[0196] P T ={0,1,2,3,4,8,5,6,7,9,10,16,11,17,12,18,13,19,14,20,15,21,22,24,25,26,23,27,28,29,30,31}

[0197] P T ={0,1,2,3,4,5,8,9,6,7,10,16,11,17,12,18,13,19,14,20,15,21,24,25,22,23,26,27,28,29,30,31}

[0198] p T ={0,1,2,3,4,5,8,6,9,7,10,16,11,17,12,18,13,19,14,20,15,21,24,22,25,23,26,27,28,29,30,31}

[0199] P T ={0,1,2,3,4,5,8,6,7,9,10,16,11,17,12,18,13,19,14,20,15,21,22,24,25,23,26,27,28,29,30,31}

[0200] P T ={0,1,2,3,4,5,6,8,9,7,10,16,11,17,12,18,13,19,14,20,15,21,24,22,23,25,26,27,28,29,30,31}

[0201] P T={0, 1, 2, 3, 4, 5, 6, 8, 7, 9, 10, 16, 11, 17, 12, 18, 13, 19, 14, 20, 15, 21, 22, 24, 23, 25, 26, 27, 28, 29, 30, 31}

[0202] P T ={0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 16, 11, 17, 12, 18, 13, 19, 14, 20, 15, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31}

[0203] Example 3) A=32, A1=12

[0204] P T ={0, 1, 2, 4, 8, 3, 5, 9, 6, 10, 7, 11, 12, 16, 13, 17, 14, 18, 15, 19, 20, 24, 21, 25, 22, 26, 28, 23, 27, 29, 30, 31}

[0205] P T ={0, 1, 2, 4, 8, 3, 5, 9, 6, 7, 10, 11, 12, 16, 13, 17, 14, 18, 15, 19, 20, 21, 24, 25, 22, 26, 28, 23, 27, 29, 30, 31}

[0206] P T ={0, 1, 2, 4, 8, 3, 5, 6, 9, 10, 7, 11, 12, 16, 13, 17, 14, 18, 15, 19, 20, 24, 21, 22, 25, 26, 28, 23, 27, 29, 30, 31}

[0207] P T ={0, 1, 2, 4, 8, 3, 5, 6, 9, 7, 10, 11, 12, 16, 13, 17, 14, 18, 15, 19, 20, 21, 24, 22, 25, 26, 28, 23, 27, 29, 30, 31}

[0208] P T ={0, 1, 2, 4, 8, 3, 5, 6, 7, 9, 10, 11, 12, 16, 13, 17, 14, 18, 15, 19, 20, 21, 22, 24, 25, 26, 28, 23, 27, 29, 30, 31}

[0209] P T={0,1,2,4,3,8,5,9,6,10,7,11,12,16,13,17,14,18,15,19,20,24,21,25,22,26,23,28,27,29,30,31}

[0210] P T ={0,1,2,4,3,8,5,9,6,7,10,11,12,16,13,17,14,18,15,19,20,21,24,25,22,26,23,28,27,29,30,31}

[0211] P T ={0,1,2,4,3,8,5,6,9,10,7,11,12,16,13,17,14,18,15,19,20,24,21,22,25,26,23,28,27,29,30,31}

[0212] P T ={0,1,2,4,3,8,5,6,9,7,10,11,12,16,13,17,14,18,15,19,20,21,24,22,25,26,23,28,27,29,30,31}

[0213] P T ={0,1,2,4,3,8,5,6,7,9,10,11,12,16,13,17,14,18,15,19,20,21,22,24,25,26,23,28,27,29,30,31{

[0214] P T ={0,1,2,4,3,5,8,9,6,10,7,11,12,16,13,17,14,18,15,19,20,24,21,25,22,23,26,28,27,29,30,31}

[0215] P T ={0,1,2,4,3,5,8,9,6,7,10,11,12,16,13,17,14,18,15,19,20,21,24,25,22,23,26,28,27,29,30,31{

[0216] P T ={0,1,2,4,3,5,8,6,9,10,7,11,12,16,13,17,14,18,15,19,20,24,21,22,25,23,26,28,27,29,30,31}

[0217] P T ={0,1,2,4,3,5,8,6,9,7,10,11,12,16,13,17,14,18,15,19,20,21,24,22,25,23,26,28,27,29,30,31}

[0218] P T ={0,1,2,4,3,5,8,6,7,9,10,11,12,16,13,17,14,18,15,19,20,21,22,24,25,23,26,28,27,29,30,31}

[0219] P T ={0,1,2,4,3,5,6,8,9,10,7,11,12,16,13,17,14,18,15,19,20,24,21,22,23,25,26,28,27,29,30,31}

[0220] P T ={0,1,2,4,3,5,6,8,9,7,10,11,12,16,13,17,14,18,15,19,20,21,24,22,23,25,26,28,27,29,30,31}

[0221] P T ={0,1,2,4,3,5,6,8,7,9,10,11,12,16,13,17,14,18,15,19,20,21,22,24,23,25,26,28,27,29,30,31}

[0222] P T ={0,1,2,4,3,5,6,7,8,9,10,11,12,16,13,17,14,18,15,19,20,21,22,23,24,25,26,28,27,29,30,31}

[0223] P T ={0,1,2,3,4,8,5,9,6,10,7,11,12,16,13,17,14,18,15,19,20,24,21,25,22,26,23,27,28,29,30,31}

[0224] P T={0,1,2,3,4,8,5,9,6,7,10,11,12,16,13,17,14,18,15,19,20,21,24,25,22,26,23,27,28,29,30,31}

[0225] P T ={0,1,2,3,4,8,5,6,9,10,7,11,12,16,13,17,14,18,15,19,20,24,21,22,25,26,23,27,28,29,30,31}

[0226] P T ={0,1,2,3,4,8,5,6,9,7,10,11,12,16,13,17,14,18,15,19,20,21,24,22,25,26,23,27,28,29,30,31}

[0227] P T ={o,1,2,3,4,8,5,6,7,9,10,11,12,16,13,17,14,18,15,19,20,21,22,24,25,26,23,27,28,29,30,31}

[0228] P T ={0,1,2,3,4,5,8,9,6,10,7,11,12,16,13,17,14,18,15,19,20,24,21,25,22,23,26,27,28,29,30,31}

[0229] P T ={0,1,2,3,4,5,8,9,6,7,10,11,12,16,13,17,14,18,15,19,20,21,24,25,22,23,26,27,28,29,30,31}

[0230] P T ={0,1,2,3,4,5,8,6,9,10,7,11,12,16,13,17,14,18,15,19,20,24,21,22,25,23,26,27,28,29,30,31}

[0231] P T ={0,1,2,3,4,5,8,6,9,7,10,11,12,16,13,17,14,18,15,19,20,21,24,22,25,23,26,27,28,29,30,31}

[0232] P T = {0, 1, 2, 3, 4, 5, 8, 6, 7, 9, 10, 11, 12, 16, 13, 17, 14, 18, 15, 19, 20, 21, 22, 24, 25, 23, 26, 27, 28, 29, 30, 31}

[0233] P T = {0, 1, 2, 3, 4, 5, 6, 8, 9, 10, 7, 11, 12, 16, 13, 17, 14, 18, 15, 19, 20, 24, 21, 22, 23, 25, 26, 27, 28, 29, 30, 31}

[0234] P T = {0, 1, 2, 3, 4, 5, 6, 8, 9, 7, 10, 11, 12, 16, 13, 17, 14, 18, 15, 19, 20, 21, 24, 22, 23, 25, 26, 27, 28, 29, 30, 31}

[0235] P T = {0, 1, 2, 3, 4, 5, 6, 8, 7, 9, 10, 11, 12, 16, 13, 17, 14, 18, 15, 19, 20, 21, 22, 24, 23, 25, 26, 27, 28, 29, 30, 31}

[0236] P T = {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 16, 13, 17, 14, 18, 15, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31}

[0237] Figure 16 is a diagram showing a part of the above transmitter operation according to an embodiment of the disclosure.

[0238] Referring to Figure 16 , a detailed procedure of the interleaving described in Figure 2 and the like is shown.

[0239] The block permutation-based interleaver operation can be used in combination with the following additional operations.

[0240] First, at operation 1605, a length K of bits to be transmitted and a length M of codeword bits to be transmitted through a channel are given.

[0241] At operation 1610, based on the above-described parameters K and M, the transmitter determines a size N of a mother code to be used for polar encoding.

[0242] At operation 1615, the transmitter may determine the size of the sub-block according to the size of the mother code. The sub-block size may be determined using one of the methods described in various embodiments of the present disclosure.

[0243] The transmitter may identify an interleaving pattern of the subblocks at operation 1620. In addition, the method of performing interleaving may include one of the following operations.

[0244] [Operation 1] Subchannel allocation adjustment can be performed. Specifically, for the transmission of information bits, subchannel allocation is generally performed according to the polar code sequence. The subchannel allocation adjustment includes a subchannel allocation operation that takes into account the rate matching operation. In detail, by reflecting the change in the mutual information or error probability of the subchannels in the rate matching operation of puncturing, shortening or repetition, it can include an operation of adjusting the order of the subchannels to which the information bits are allocated. This means that in addition to the useless subchannels generated by the above-mentioned rate matching operation, the impact on the remaining subchannels must also be considered. One method for simplifying the subchannel allocation adjustment is to divide all subchannels of the polar code into two parts based on the index, and adjust the number of information bits allocated to each part by taking into account puncturing, shortening and repetition.

[0245] [Operation 2] Bit permutation in sub-blocks: This means that in addition to the above-mentioned block permutation operation considered in the present disclosure, a bit permutation operation is also performed on the mixed bits included in the sub-blocks. When mixing the bits in the sub-blocks, all sub-blocks can be mixed in the same pattern or different patterns.

[0246] Figure 17 is a flow chart illustrating a coding and rate matching process according to an embodiment of the present disclosure, the coding and rate matching process including the sub-channel allocation adjustment operation and the bit permutation operation in the sub-block as described above.

[0247] refer to Figure 17 , discloses the operation of a transmitter considering rate matching according to an embodiment of the present disclosure.

[0248] First, at operation 1705, the length K of bits to be transmitted and the length M of codeword bits to be transmitted through a channel are given.

[0249] At operation 1710, the transmitter determines a size N of a mother code to be used for polar coding.

[0250] At operation 1715, based on the above-mentioned parameters N, K, and M and a predetermined criterion, the transmitter determines which rate matching operation among puncturing, shortening, and repetition is to be performed.

[0251] If it is determined that a puncturing or shortening operation is to be performed, the transmitter determines at operation 1720 that a subchannel cannot be selected from the subchannels for information transmission as described above. At this time, the subchannel that cannot be selected is determined in consideration of the interleaving and rate matching operations to be performed subsequently. Specifically, in one embodiment, in consideration of the puncturing or shortening operation, all bits may be divided into subblocks, and this may be performed in consideration of the interleaving operation.

[0252] At operation 1725, the transmitter performs subchannel allocation on information bits to be transmitted.

[0253] At operation 1730 , the transmitter may perform subchannel allocation adjustment.

[0254] At operation 1735, the transmitter may perform polarization encoding.

[0255] At operation 1740, the transmitter interleaves a bit sequence obtained as a result of the encoding based on a predetermined scheme.

[0256] At operation 1745 , the transmitter may interleave the bits within the sub-block.

[0257] At operation 1750, the transmitter stores the interleaved bit sequence in a buffer.

[0258] At operation 1755, the transmitter loads M bits to be transmitted through the channel from the buffer. Thereafter, after performing channel interleaving, modulation, etc., the bits are transmitted through the channel.

[0259] Depending on various embodiments, the subchannel allocation adjustment of operation 1730 and the bit interleaving within the subblock of operation 1745 may be selectively performed or omitted.

[0260] Figure 18 is a block diagram illustrating a transmitter according to an embodiment of the present disclosure.

[0261] refer to Figure 18 , the transmitter may include a transceiver 1805, a controller 1810, and a storage 1815. In the present disclosure, the controller 1810 may be defined as a circuit, an application-specific integrated circuit (ASIC), or at least one processor.

[0262] The transceiver 1805 can transmit and receive signals with other devices. When the transmitter is implemented in a terminal, the transceiver 1805 can, for example, receive system information and synchronization signals or reference signals from a base station, and also transmit a bit sequence to the base station.

[0263] According to various embodiments of the present disclosure, the controller 1810 may control the overall operation of the transmitter. For example, the controller 1810 may control the signal flow between the various blocks to perform the above-mentioned operations. Specifically, the controller 1810 may control the transmitter to encode the information bits as described in the various embodiments above.

[0264] The storage 1815 may store at least one of information transmitted or received through the transceiver 1805 and information generated by the controller 1810 .

[0265] Figure 19 is a block diagram illustrating a receiver according to an embodiment of the present disclosure.

[0266] refer to Figure 19 , the receiver may include a transceiver 1905, a controller 1910, and a storage 1915. In the present disclosure, the controller 1910 may be defined as a circuit, an application specific integrated circuit (ASIC), or at least one processor.

[0267] The transceiver 1905 can transmit and receive signals with other devices. When the receiver is implemented in a terminal, the transceiver 1905 can receive a coded bit sequence from a base station, for example.

[0268] According to various embodiments of the present disclosure, the controller 1910 can control the overall operation of the receiver. For example, the controller 1910 can control the signal flow between the various blocks to perform the above-mentioned operations. Specifically, the controller 1910 can control the receiver to decode the encoded information bits as described above in various embodiments.

[0269] The storage 1915 may store at least one of information transmitted or received through the transceiver 1905 and information generated by the controller 1910 .

[0270] According to an embodiment of the present disclosure, a polar code-based coding and rate matching method for a communication system may include the following operations: determining the size of a mother code to be used for encoding and decoding a polar code based on the number of codeword bits and the code rate; identifying a polar code sequence indicating subchannel priority when information bits are allocated to a subchannel; determining one of puncturing, shortening, and repetition operations based on the number of codeword bits, the code rate, and the determined mother code size; determining a block permutation-based interleaver for rate matching based on the mother code size; determining the positions of a portion of frozen bits through puncturing / shortening based on the interleaver; encoding bits based on a determined frozen bit pattern and the reliability of the polar code sequence or polarized channel; interleaving the coded bits using the determined interleaver; and determining a transmission order of the interleaved bits based on the determined one of shortening, puncturing, and repetition operations.

[0271] A block permutation-based interleaver can be determined based solely on the size of the mother code, regardless of the puncturing, shortening, and repetition operations. Furthermore, the block permutation-based interleaver can be determined based on the number of subblocks and the interleaving order of the subblocks. The interleaving order can be to interleave the subblocks in the order of polar code sequences having the same length as the number of subblocks, or to interleave the subblocks in an arbitrary order that satisfies the partial order. In the case of shortening, the pattern of bits that are forcibly frozen among the encoded input bits can be the same as the pattern of bits that are shortened among the encoded output bits. In the case of puncturing, the pattern of bits that are forcibly frozen among the encoded input bits can be the same as or in the opposite order of the pattern of bits that are punctured among the encoded output bits. The transmission order of the interleaved bits can be determined differently depending on the puncturing, shortening, and repetition operations, or can be determined equally regardless of the puncturing, shortening, and repetition operations.

[0272] The number of subblocks in a block permutation-based interleaver can be determined based on the size of the mother code while keeping the subblock size fixed, based on the size of each mother code, or constant regardless of the size of the mother code. In subblock permutation, the interleaving order can be determined based on the number of subblocks or the size of the mother code. A block permutation-based interleaver can perform subblock permutation alone or in conjunction with at least one of subchannel allocation adjustment and intra-subblock bit interleaving.

[0273] While the present disclosure has been shown and described with reference to various embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made without departing from the spirit and scope of the present disclosure as defined by the appended claims and their equivalents.

Claims

1. A method performed by a transmitter in a communication system, the method comprising: Identifying a first bit sequence to be encoded, the first bit sequence comprising an information bit sequence and cyclic redundancy check (CRC) bits of the information bit sequence; identifying a second bit sequence by encoding the first bit sequence with a polar code; identifying a third bit sequence by performing interleaving on the second bit sequence based on an interleaving pattern; performing the rate matching on the third bit sequence by determining one of repetition, puncturing, or shortening as rate matching based on the length of the first bit sequence, the length of the second bit sequence, and the length of the rate matching output sequence; and By performing the rate matching to obtain the rate matching output sequence, The interleaving pattern corresponds to {0, 1, 2, 4, 3, 5, 6, 7, 8, 16, 9, 17, 10, 18, 11, 19, 12, 20, 13, 21, 14, 22, 15, 23, 24, 25, 26, 28, 27, 29, 30, 31}.

2. The method according to claim 1, in, The third bit sequence includes a plurality of sub-blocks of the second bit sequence, the plurality of sub-blocks being rearranged based on the interleaving pattern, and The number of the multiple sub-blocks is 32.

3. The method according to claim 1, wherein The interleaving pattern is determined based on a partial order.

4. The method according to claim 1, wherein The second bit sequence includes one or more bits set to 0 to be rate matched.

5. The method according to claim 1, in, In a case where the length of the rate matching output sequence is shorter than the length of the second bit sequence, one of puncturing or shortening is determined as the rate matching based on a code rate determined according to the length of the first bit sequence and the length of the rate matching output sequence, and Wherein, in a case where the length of the rate matching output sequence is longer than the length of the second bit sequence, repetition is determined as the rate matching.

6. The method according to claim 1, in, Performing the rate matching includes: storing the third bit sequence in a circular buffer; and Puncturing is performed on a first portion of bits in the third bit sequence, and The length of the first portion of bits is determined by subtracting the length of the rate matching output sequence from the length of the second bit sequence.

7. The method according to claim 1, in, Performing the rate matching includes: storing the third bit sequence in a circular buffer; and Shortening is performed on the latter part of the third bit sequence, and The length of the latter portion of bits is determined by subtracting the length of the rate matching output sequence from the length of the second bit sequence.

8. The method according to claim 1, in, Performing the rate matching includes: storing the third bit sequence in a circular buffer; and performing repetition on the bits in the third bit sequence, and The length of the bits to be repeated is determined by subtracting the length of the second bit sequence from the length of the rate matching output sequence.

9. A device in a communication system, the device comprising: transceiver; and a controller coupled with the transceiver and configured to: identifying a first bit sequence to be encoded, the first bit sequence comprising an information bit sequence and cyclic redundancy check (CRC) bits of the information bit sequence, identifying a second bit sequence by encoding the first bit sequence with a polar code, identifying a third bit sequence by performing interleaving on the second bit sequence based on an interleaving pattern, performing the rate matching on the third bit sequence by determining one of repetition, puncturing, or shortening as rate matching based on the length of the first bit sequence, the length of the second bit sequence, and the length of the rate matching output sequence, and By performing the rate matching to obtain the rate matching output sequence, The interleaving pattern corresponds to {0, 1, 2, 4, 3, 5, 6, 7, 8, 16, 9, 17, 10, 18, 11, 19, 12, 20, 13, 21, 14, 22, 15, 23, 24, 25, 26, 28, 27, 29, 30, 31}.

10. The device according to claim 9, in, The third bit sequence includes a plurality of sub-blocks of the second bit sequence, the plurality of sub-blocks being rearranged based on the interleaving pattern, and The number of the multiple sub-blocks is 32.

11. The device according to claim 9, wherein The interleaving pattern is determined based on a partial order.

12. The device of claim 9, wherein: The second bit sequence includes one or more bits set to 0 to be rate matched.

13. The device according to claim 9, in, In a case where the length of the rate matching output sequence is shorter than the length of the second bit sequence, one of puncturing or shortening is determined as the rate matching based on a code rate determined according to the length of the first bit sequence and the length of the rate matching output sequence, and Wherein, in a case where the length of the rate matching output sequence is longer than the length of the second bit sequence, repetition is determined as the rate matching.

14. The device according to claim 9, in, In order to perform the rate matching, the controller is further configured to: storing the third bit sequence in a circular buffer, and Puncturing is performed on a first portion of bits in the third bit sequence, and The length of the first portion of bits is determined by subtracting the length of the rate matching output sequence from the length of the second bit sequence.

15. The device according to claim 9, in, In order to perform the rate matching, the controller is further configured to: storing the third bit sequence in a circular buffer, and Shortening is performed on the latter part of the third bit sequence, and The length of the latter portion of bits is determined by subtracting the length of the rate matching output sequence from the length of the second bit sequence.

16. The device according to claim 9, in, To perform rate matching, the controller is further configured to: storing the third bit sequence in a circular buffer, and performing repetition on the bits in the third bit sequence, and The length of the bits to be repeated is determined by subtracting the length of the second bit sequence from the length of the rate matching output sequence.

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