Semiconductor device and method of forming the same
By designing a U-shaped channel and a low dielectric constant isolation structure, the problem of large area occupied by IGZO transistors is solved, the integration density and performance stability of DRAM are improved, parasitic capacitance is reduced, and performance degradation is prevented.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- RUILI INTEGRATED CIRCUIT CO LTD
- Filing Date
- 2023-07-20
- Publication Date
- 2026-07-24
AI Technical Summary
Existing capacitorless DRAMs composed of IGZO transistors are arranged side by side on a plane, which makes it difficult to reduce the device size and occupies a large area. In addition, IGZO is sensitive to water and oxygen in the air, which leads to performance degradation and coupling.
The device employs a U-shaped channel first transistor and a second transistor located inside it, combined with an isolation structure made of low dielectric constant material, to reduce the device's footprint and volume, and to isolate the transistor from water and oxygen in the air.
It improves the integration of semiconductor devices, enhances performance stability, reduces parasitic capacitance, and prevents performance degradation.
Smart Images
Figure CN116685145B_ABST
Abstract
Description
Technical Field
[0001] This disclosure relates to the field of semiconductor technology, and to, but is not limited to, a semiconductor device and a method for forming the same. Background Technology
[0002] Because indium gallium zinc oxide thin-film transistors (IGZO-TFTs) have a very low cutoff current compared to silicon transistors, using IGZO-TFTs to form semiconductor devices can improve the data retention capability of memory cells (e.g., dynamic random access memory cells).
[0003] However, in related technologies, capacitor-free dynamic random access memory (DRAM) composed of IGZO transistors is usually arranged in parallel on a plane, thus occupying a large area and making it difficult to reduce the device size. Summary of the Invention
[0004] In view of this, embodiments of the present disclosure provide a semiconductor device and a method for forming the same.
[0005] In a first aspect, embodiments of this disclosure provide a semiconductor device, including:
[0006] Substrate:
[0007] A first transistor located in the substrate; wherein the first transistor includes at least a U-shaped first channel and a first gate located on the surface of the first channel; the U-shaped opening of the first channel faces a first direction and is away from the substrate; the first direction is the thickness direction of the substrate;
[0008] A second transistor located within the U-shaped opening on the surface of the first transistor; wherein the second transistor includes at least a second drain, the second drain being connected to the first gate.
[0009] In some embodiments, the second transistor further includes a second channel;
[0010] The second channel extends along the first direction;
[0011] Alternatively, the extension direction of the second channel is perpendicular to the first direction;
[0012] Alternatively, the second channel may be U-shaped, with the U-shaped opening of the second channel facing the first direction.
[0013] In some embodiments, the second transistor further includes a second source and a second gate located on the surface of the second channel;
[0014] The second source and the second drain are located at opposite ends of the second channel.
[0015] In some embodiments, it further includes: a first isolation structure;
[0016] The first isolation structure is located between the first gate and the second gate.
[0017] In some embodiments, the material of the first isolation structure includes a low dielectric constant material.
[0018] In some embodiments, the first transistor further includes a first source and a first drain;
[0019] The first source and the first drain are located on the substrate surfaces at both ends of the first channel.
[0020] Secondly, embodiments of this disclosure provide a method for forming a semiconductor device, comprising:
[0021] Provide substrate;
[0022] A first transistor is formed in the substrate; wherein the first transistor includes at least a U-shaped first channel and a first gate located on the surface of the first channel; the U-shaped opening of the first channel faces a first direction and is away from the substrate; the first direction is the thickness direction of the substrate;
[0023] A second transistor is formed within the U-shaped opening on the surface of the first transistor; wherein the second transistor includes at least a second drain, the second drain being connected to the first gate.
[0024] In some embodiments, the first transistor further includes a first source and a first drain located at both ends of the first channel; forming the first transistor in the substrate includes:
[0025] The substrate is etched to form a first trench;
[0026] A first semiconductor layer is formed on the substrate surface and the inner surface of the first trench; wherein the first semiconductor layer located on the inner surface of the first trench constitutes the first channel, and the first semiconductor layers located on the substrate surfaces at both ends of the first trench constitute the first source and the first drain, respectively.
[0027] The first gate is formed on the surface of the first channel.
[0028] In some embodiments, the second transistor further includes a second gate and a second source; forming the second transistor within the U-shaped opening on the surface of the first transistor includes:
[0029] A first initial isolation structure is formed in the first trench;
[0030] The first initial isolation structure is patterned to form a first isolation structure and a second trench located between the first isolation structures; wherein the second trench exposes the first gate.
[0031] A second semiconductor layer extending along the first direction is formed in the second trench, and a second gate is located on the middle sidewall of the second semiconductor layer along the first direction; the top surface of the second semiconductor layer is flush with the top surface of the first gate.
[0032] Wherein, the portion of the second semiconductor layer covered by the second gate forms the second channel, and the second semiconductor layers located at the bottom and top of the second channel form the second drain and the second source, respectively.
[0033] In some embodiments, forming a second semiconductor layer extending along the first direction and a second gate located on a middle sidewall of the second semiconductor layer along the first direction in the second trench includes:
[0034] The second semiconductor layer and the second initial isolation structure located on the sidewall of the second semiconductor layer are formed in the second trench;
[0035] The second initial isolation structure is re-etched to expose the second channel and the second source.
[0036] The second gate is formed on the surface of the second channel.
[0037] The semiconductor device and its formation method provided in this disclosure include: a substrate; a first transistor located in the substrate; wherein the first transistor includes at least a U-shaped first channel and a first gate located on the surface of the first channel; the U-shaped opening of the first channel faces a first direction and is away from the substrate; the first direction is the thickness direction of the substrate; a second transistor located within the U-shaped opening on the surface of the first transistor; wherein the second transistor includes at least a second drain, and the second drain is connected to the first gate. Because the first transistor has a U-shaped first channel (i.e., the first transistor has a U-shaped opening), and the second transistor is located inside the U-shaped opening, the occupied area and volume of the semiconductor device composed of the first transistor and the second transistor can be reduced, thereby improving the integration density of the semiconductor device. Attached Figure Description
[0038] In the accompanying drawings (which are not necessarily drawn to scale), similar reference numerals may describe similar parts in different views. Similar reference numerals with different letter suffixes may indicate different examples of similar parts. The drawings illustrate, by way of example and not limitation, the various embodiments discussed herein.
[0039] Figure 1 This is a schematic diagram of the circuit structure of a semiconductor device in the related technology;
[0040] Figures 2 to 7 This is a schematic diagram of the structure of a semiconductor device provided in an embodiment of this disclosure;
[0041] Figure 8 Equivalent circuit diagram of a semiconductor device provided in the embodiments of this disclosure;
[0042] Figure 9 A schematic flowchart of a semiconductor device formation method provided in an embodiment of this disclosure;
[0043] Figures 10 to 26 These are schematic diagrams of various structures in the semiconductor device formation process provided in the embodiments of this disclosure. Detailed Implementation
[0044] Exemplary embodiments of the present disclosure will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be implemented in various forms and should not be limited to the specific embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.
[0045] In the following description, numerous details are set forth in order to provide a more thorough understanding of this disclosure. However, it will be apparent to those skilled in the art that this disclosure may be practiced without one or more of these details. In other instances, to avoid confusion with this disclosure, some technical features well-known in the art have not been described; that is, not all features of actual embodiments are described herein, nor are well-known functions and structures described in detail.
[0046] In the accompanying drawings, for clarity, the dimensions of layers, areas, and elements, as well as their relative dimensions, may be exaggerated. The same reference numerals denote the same elements throughout.
[0047] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this disclosure, the first element, component, area, layer, or portion discussed below may be referred to as a second element, component, area, layer, or portion. And the discussion of a second element, component, area, layer, or portion does not imply that the first element, component, area, layer, or portion necessarily exists in this disclosure.
[0048] The terminology used herein is intended only to describe particular embodiments and is not intended to limit this disclosure. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprise” and / or “comprising,” when used in this specification, identify the presence of said features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.
[0049] Because indium gallium zinc oxide thin-film transistors have a very low cutoff current compared to silicon transistors, using indium gallium zinc oxide thin-film transistors to form semiconductor devices can improve the data retention capability of memory cells.
[0050] Figure 1 This is a schematic diagram of the circuit structure of a semiconductor device in the related technology, such as... Figure 1As shown, the semiconductor device in the related technology includes two IGZO transistors (i.e., a write transistor 10a and a read transistor 10b). The gate of the write transistor 10a is connected to the write word line (WWL), the source (or drain) of the write transistor 10a is connected to the write bit line (WBL), and the drain (or source) of the write transistor 10a is connected to the gate of the read transistor 10b through a storage node contact (SN). The source and drain of the read transistor 10b are connected to the read bit line (RBL) and the read word line (RWL), respectively.
[0051] In related technologies, the write transistor 10a and read transistor 10b are usually arranged horizontally or stacked vertically, resulting in a large area or volume occupied by the semiconductor device. In addition, because IGZO is sensitive to water and oxygen in the air, the performance of the semiconductor device gradually degrades.
[0052] Furthermore, the close proximity between the write transistor 10a and the read transistor 10b makes them prone to coupling, which further degrades the performance of the semiconductor device.
[0053] Based on this, the semiconductor device and its formation method provided in this disclosure include: a substrate; a first transistor located in the substrate; wherein the first transistor includes at least a U-shaped first channel and a first gate located on the surface of the first channel; the U-shaped opening of the first channel faces a first direction and is away from the substrate; the first direction is the thickness direction of the substrate; a second transistor located within the U-shaped opening on the surface of the first transistor; wherein the second transistor includes at least a second drain, and the second drain is connected to the first gate. Since the first transistor has a U-shaped first channel (i.e., the first transistor has a U-shaped opening), and the second transistor is located inside the U-shaped opening, the occupied area and volume of the semiconductor device composed of the first transistor and the second transistor can be reduced, thereby improving the integration density of the semiconductor device.
[0054] The semiconductor devices and their formation methods in the embodiments of this disclosure will now be described in detail with reference to the accompanying drawings.
[0055] Figures 2 to 7 This is a schematic diagram of the structure of a semiconductor device provided in an embodiment of this disclosure, such as... Figures 2 to 7 As shown, the semiconductor device 20 includes:
[0056] Substrate 201;
[0057] A first transistor located in a substrate 201; wherein the first transistor includes at least a U-shaped first channel 301 and a first gate 302 located on the surface of the first channel 301; the U-shaped opening of the first channel 301 faces a first direction and is away from the substrate 201;
[0058] A second transistor is located within a U-shaped opening on the surface of the first transistor; wherein the second transistor includes at least a second drain 401, and the second drain 401 is connected to the first gate 302.
[0059] Here, substrate 201 can be a silicon substrate, germanium substrate, silicon germanide substrate, silicon-on-insulator (SOI) substrate, or germanium-on-insulator (GOI) substrate, etc.; substrate 201 may also include other elemental semiconductors or compound semiconductors, such as gallium arsenide, indium phosphide, or silicon carbide, etc. In other embodiments, substrate 201 may also be an ion-doped substrate, such as a p-type doped substrate or an n-type doped substrate.
[0060] It should be noted that the first direction is the thickness direction of the substrate 201 (as shown by the Z-axis direction in the figure).
[0061] It should also be noted that since the semiconductor device 20 includes two transistors, the semiconductor device 20 in this embodiment of the present disclosure can be a 2T0C DRAM cell.
[0062] In this embodiment, the material of the first channel 301 can be a metal oxide, such as IGZO; that is, the first transistor can be an IGZO thin-film transistor. In other embodiments, the first transistor can also be a conventional silicon-based transistor or other types of transistors.
[0063] In this embodiment, the first channel 301 and the first gate 302 are U-shaped, that is, the first transistor is recessed into the substrate 201 to form a trench-type transistor; the second transistor is located inside the U-shaped opening of the first transistor, that is, the second transistor is located in the trench of the first transistor. In this way, the occupied area and volume of the semiconductor device composed of the first transistor and the second transistor can be reduced, thereby improving the integration of the semiconductor device.
[0064] In some embodiments, please continue to see Figures 2 to 7 The first gate 302 includes a first gate dielectric layer 3021 and a first gate conductive layer 3022 located on the surface of the first gate dielectric layer 3021.
[0065] The first gate dielectric layer 3021 can be made of a high dielectric constant (HK) material or other suitable materials such as silicon dioxide. For example, the high dielectric constant (HK) material can include hafnium oxide (HfO2), hafnium silicon oxide (HfSiO2), zirconium oxide (ZrO2), and aluminum oxide (Al2O3). The first gate conductive layer 3022 can be made of any material with good conductivity, such as any one of titanium (Ti), titanium nitride (TiN), tungsten nitride (WN), tungsten (W), cobalt (Co), platinum (Pt), palladium (Pd), ruthenium (Ru), and copper (Cu).
[0066] It is worth noting that the connection between the second drain 401 and the first gate 302 means that the second drain 401 is connected to the first gate conductive layer 3022 in the first gate 302.
[0067] In some embodiments, please continue to see Figures 2 to 7 The first transistor further includes a first source 303 and a first drain 304; the first source 303 and the first drain 304 are respectively located on the substrate 201 surface at both ends of the first channel 301.
[0068] In some embodiments, please continue to see Figures 2 to 7 The second transistor also includes a second channel 402 and a second gate 404 located on the surface of the second channel 402.
[0069] It should be noted that in this embodiment, the material of the second channel 402 can be a metal oxide, such as IGZO; that is, the second transistor can be an IGZO thin-film transistor. In other embodiments, the second transistor can also be a conventional silicon-based transistor or other types of transistors.
[0070] In some embodiments, please continue to see Figure 2 , Figure 5 , Figure 6 , Figure 7 The second channel 402 extends along the Z-axis, meaning the second transistor is a vertical channel transistor (i.e., a vertical transistor). In this case, the second gate 404 can be a dual-gate structure, a full-ring gate structure, or a single-gate structure.
[0071] In some embodiments, in order to improve the gate control capability of the second transistor, the second gate 404 is typically configured as a dual-gate structure or a full-ring gate structure.
[0072] In some embodiments, please continue to see Figure 3 The extension direction of the second channel 402 is perpendicular to the first direction, that is, the extension direction of the second channel 402 is parallel to the plane where the substrate 201 is located, that is, the second channel 402 extends in the horizontal direction, and the second transistor is a planar transistor.
[0073] In some embodiments, please continue to see Figure 4 The second channel 402 is U-shaped, and the U-shaped opening of the second channel 402 faces the Z-axis direction. Specifically, the extension direction of the second channel 402 can be towards the substrate 201 or away from the substrate 201 (e.g., Figure 4 (As shown). When the second channel 402 is U-shaped, the second gate 404 is also U-shaped, which can form a trench-type second transistor. The trench-type second transistor has a larger channel and stronger control capability.
[0074] In some embodiments, please continue to see Figures 2 to 7 The second gate 404 includes a second gate dielectric layer 4041 and a second gate conductive layer 4042 located on the surface of the second gate dielectric layer 4041. The second gate dielectric layer 4041 may be similar to the first gate dielectric layer 3021, and the material of the second gate conductive layer 4042 may be similar to that of the first gate conductive layer 3022.
[0075] In some embodiments, please continue to see Figures 2 to 7 The second transistor also includes a second source 403; the second source 403 and the second drain 401 are located at the two ends of the second channel 402, respectively.
[0076] In some embodiments, the extending direction of the first source 403 or the second drain 401 may be consistent with the extending direction of the second channel 402, or it may be perpendicular to the extending direction of the second channel 402. That is, when the second channel 402 extends along the Z-axis direction, the second drain 401, the second channel 402, and the second source 403 can form as follows: Figure 5 The L-type transistor shown can also be formed as follows: Figure 6 The T-type transistor shown or formed as Figure 7 The diagram shows an inverted T-type transistor. When the second channel 402 extends in a horizontal direction perpendicular to the Z-axis, the second drain 401, the second channel 402, and the second source 403 can form an L-type transistor or a T-type transistor. When the second drain 401, the second channel 402, and the second source 403 constitute an L-type transistor, a T-type transistor, or an inverted T-type transistor, the second gate 404 has a single-gate structure.
[0077] In some embodiments, please continue to see Figure 2 The semiconductor device 20 further includes a first isolation structure 21; the first isolation structure 21 is located between the first gate 302 and the second gate 404. The bottom surface of the first isolation structure 21 is in contact with the first gate 302, and the top surface of the first isolation structure 21 is flush with the top surface of the first gate 302.
[0078] It should be noted that the material of the first isolation structure 21 includes a low dielectric constant material.
[0079] In this embodiment of the present disclosure, by providing a first isolation structure 21 formed of a low dielectric constant between the first gate 302 and the second gate 404, the coupling effect between the first gate 302 and the second gate 404 can be reduced, that is, the parasitic capacitance between the first gate 302 and the second gate 404 can be reduced, thereby improving the performance of the semiconductor device.
[0080] In some embodiments, please continue to see Figure 2 The semiconductor device 20 further includes a second isolation structure 22 and a third isolation structure 23. The second isolation structure 22 is located on the sidewall of the second drain 401 and between the first gate 302 and the second gate 404; the third isolation structure 23 is located on the sidewall of the second source 403 and on the surface of the second gate 404, and the top surface of the third isolation structure 23 is flush with the top surface of the first gate 302.
[0081] It should be noted that the second isolation structure 22 includes a first sub-isolation structure 202 located between the second gate conductive layer 4022 and the first gate 302, and a second sub-isolation structure 203 located between the second gate dielectric layer 4021 and the first gate 302.
[0082] The materials of the first sub-isolation structure 202 and the third isolation structure 23 can be silicon nitride, silicon oxide, or silicon carbonitride, while the material of the second sub-isolation structure 203 can be any one of silicon nitride, silicon oxide, silicon carbonitride, or a low dielectric constant material. The materials of the first sub-isolation structure 202 and the second sub-isolation structure 203 can be the same or different.
[0083] In this embodiment of the disclosure, the first isolation structure 21, the second isolation structure 22 and the third isolation structure 23 are used to isolate the first transistor and the second transistor, and can isolate the first transistor and the second transistor from water and oxygen in the air, thereby improving the performance of the semiconductor device.
[0084] In some embodiments, please continue to see Figures 3 to 7 The semiconductor device also includes a fourth isolation structure 24 located between the first transistor and the second transistor. The material of the fourth isolation structure 24 may include any one of silicon nitride, silicon oxide, silicon carbonitride, or a low dielectric constant material. The fourth isolation structure 24 is used at least to isolate the first transistor and the second transistor to prevent short circuits between the first transistor and the second transistor.
[0085] In some embodiments, the semiconductor device 20 further includes a first conductive line, a second conductive line, a third conductive line, and a fourth conductive line; wherein the first conductive line is connected to the first source 303, the second conductive line is connected to the first drain 304, the third conductive line is connected to the second gate 404, and the fourth conductive line is connected to the second source 403. Understandably, the first conductive line is the read bit line (RBL) of the semiconductor device 20, the second conductive line is the read word line (RWL) of the semiconductor device 20, the third conductive line is the write word line (WWL) of the semiconductor device 20, and the fourth conductive line is the write bit line (WBL) of the semiconductor device 20.
[0086] Figure 8 The equivalent circuit diagram of the semiconductor device 20 provided in the embodiments of this disclosure is as follows: Figure 8 As shown, the semiconductor device 20 includes a first transistor 20a and a second transistor 20b, wherein the first transistor 20a is a read transistor and the second transistor 20b is a write transistor.
[0087] Below, for reference Figure 8 This invention explains the working principle of the semiconductor device 20 (2T0C DRAM memory cell) provided in the embodiments of this disclosure.
[0088] During the writing "1" process, a positive voltage is applied to the second gate (i.e., the write word line WWL) of the second transistor 20b. This positive voltage must be greater than the threshold voltage of the second transistor 20b to turn it on. A positive voltage is then applied to the second drain (i.e., the write bit line WBL) of the second transistor 20b to inject charge into the first gate capacitance of the first transistor 20a. After charge injection, the gate and drain voltages of the second transistor 20b are removed, preserving the "1" state.
[0089] In the process of reading "1", a reading voltage is applied to the first source of the first transistor 20a (i.e., the read word line RBL). Since there is a certain charge in the first gate capacitor, the first transistor 20a is in a low resistance state and obtains a large current. The reading of "1" is then completed by the amplification and recognition by the external circuit.
[0090] During the writing "0" process, a positive voltage is applied to the second gate (i.e., the write word line WWL) of the second transistor 20b. This positive voltage must be greater than the threshold voltage of the second transistor 20b to turn it on. A negative voltage is applied to the second drain (i.e., the write bit line WBL) of the second transistor 20b to draw charge from the first gate capacitance of the first transistor 20a. After the charge is drawn, the gate and drain voltages of the second transistor 20b are removed, and the "0" state is retained.
[0091] During the process of reading "0", a reading voltage is applied to the first source of the first transistor 20a (i.e., the read bit line RBL). Since there is no charge in the first gate capacitor, the first transistor 20a is in a high resistance state and obtains a small current. This current is then amplified and identified by the external circuit to complete the process of reading "0".
[0092] In another embodiment of this disclosure, Figure 9 This is a schematic flowchart of a semiconductor device formation method provided in an embodiment of this disclosure. Figures 10 to 26 The following are schematic diagrams of various structures in the semiconductor device formation process provided in the embodiments of this disclosure. Figures 10 to 26 The process of forming semiconductor devices is explained in detail.
[0093] like Figure 9 As shown, the method for fabricating a semiconductor device includes the following steps S601 to S603.
[0094] First, refer to Figures 9 to 11 Step S601 is executed to provide substrate 201.
[0095] Here, substrate 201 can be a silicon substrate, or substrate 201 can include other semiconductor elements, such as germanium, or include semiconductor compounds, such as silicon carbide, gallium arsenide, or include other semiconductor alloys, such as silicon germanium, gallium arsenide phosphide.
[0096] Next, continue to refer to Figures 9 to 16 Step S602 is executed to form a first transistor in the substrate 201; wherein the first transistor includes at least a U-shaped first channel 301 and a first gate 302 located on the surface of the first channel 301; the U-shaped opening of the first channel 301 faces a first direction and is away from the substrate 201.
[0097] In some embodiments, the first transistor further includes a first source 303 and a first drain 304 located on the surface of the substrate 201 at both ends of the first channel 301.
[0098] In some embodiments, step S601 may include the following steps:
[0099] S6011, etching substrate 201 to form first trench 702;
[0100] In implementation, a photoresist layer 701 with a predetermined pattern is formed on the surface of the substrate 201. The photoresist layer 701 can be a positive photoresist (such as...). Figure 10 (As shown) can also be negative photoresist (such as...) Figure 11 (As shown).
[0101] In some embodiments, when the photoresist layer 701 is a positive photoresist, the photoresist layer 701 exposes a portion of the surface of the substrate 201. The exposed portion of the substrate 201 is removed by etching, forming a structure as shown below. Figure 12 The first groove 702 is shown.
[0102] In some embodiments, when the photoresist layer 701 is a negative photoresist, the photoresist layer 701 covers the surface of the substrate 201 to be etched, and after exposure and development... Figure 11 The negative photoresist shown is removed, exposing the substrate 201 that needs to be etched. Subsequently, an etching step is performed to form the substrate 201 shown. Figure 12 The first trench 702.
[0103] S6012, A first semiconductor layer 703 is formed on the surface of the substrate 201 and the inner surface of the first trench 702; wherein, the first semiconductor layer 703 located on the inner surface of the first trench 702 constitutes the first channel 301, and the first semiconductor layer 703 located on the surface of the substrate 201 at both ends of the first trench 702 constitutes the first source 303 and the first drain 304, respectively.
[0104] During implementation, a first semiconductor material is deposited on the surface of the substrate 201 and the inner surface of the first trench 702 to form a structure such as... Figure 13 The first semiconductor layer 703 is shown. Here, the first semiconductor material can be a metal oxide material, such as IGZO. In other embodiments, the first semiconductor material can also be a semiconductor material such as silicon or germanium.
[0105] In this embodiment of the disclosure, the first semiconductor layer 703 can be formed by chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), spin coating, coating, or thin film processing.
[0106] S6013, A first gate 302 is formed on the surface of the first channel 301.
[0107] During implementation, a first gate dielectric material is deposited on the surface of the first semiconductor layer 703 to form a structure such as... Figure 14 The first gate dielectric layer 3021 is shown. Next, a first gate conductive material is deposited on the surface of the first gate dielectric layer 3021 to form a... Figure 15 The first gate conductive layer 3022 is shown. Here, the first gate dielectric material can be HK material or silicon dioxide, and the first gate conductive material can be titanium nitride or tungsten metal.
[0108] Next, please refer to Figure 16 The first gate conductive layer 3022 and the first gate dielectric layer 3021 located on the surfaces of the first source 303 and the first drain 304 are removed by chemical mechanical polishing (CMP) technology. The remaining first gate conductive layer 3022 and the first gate dielectric layer 3021 located on the surface of the first channel 301 constitute the first gate 302.
[0109] Finally, continue to refer to Figure 9 ,as well as Figures 17 to 26 Step S603 is executed to form a second transistor in the U-shaped opening on the surface of the first transistor; wherein the second transistor includes at least a second drain 401, and the second drain 401 is connected to the first gate 302.
[0110] In some embodiments, the second transistor further includes a second channel 402, a second gate 404, and a second source 403. The second channel 402 extends along the X-axis direction; or, the extension direction of the second channel 402 is perpendicular to the Z-axis direction; or, the second channel 402 is U-shaped, and the U-shaped opening of the second channel 402 faces the Z-axis direction.
[0111] It should be noted that when the second channel 402 extends along the X-axis, a vertical channel type second transistor can be formed; when the extension direction of the second channel 402 is perpendicular to the Z-axis, a planar type transistor can be formed; and when the second channel 402 is U-shaped, a trench type second transistor can be formed.
[0112] Below, taking the second channel 402 extending along the Z-axis as an example, combined with... Figures 17 to 26 This describes the specific process of forming a vertical channel type second transistor. In some embodiments, step S603 may include the following steps:
[0113] S6031, A first initial isolation structure 21a is formed in the first trench 702;
[0114] During implementation, a first isolation material is deposited in the first trench 702, forming a structure like... Figure 17 The first initial isolation structure 21a shown has its top surface flush with the top surface of the first gate 302. The first isolation material can be a low dielectric constant material.
[0115] S6032, pattern the first initial isolation structure 21a to form the first isolation structure 21 and the second trench 704 located between the first isolation structures 21; wherein the second trench 704 exposes the first gate 302;
[0116] In implementation, for example, a photoresist layer with a preset pattern can be formed on the surface of the first initial isolation structure 21a, exposing the middle portion of the surface of the first initial isolation structure 21a. The exposed first initial isolation structure 21a is then removed by etching the photoresist layer, forming a structure as shown below. Figure 18 The second trench 704 shown, the remaining first initial isolation structure 21a constitutes as follows Figure 18 The first isolation structure 21 is shown.
[0117] S6033, A second semiconductor layer 705 extending in a first direction is formed in the second trench 704, and a second gate 404 is located on the middle sidewall of the second semiconductor layer 705 in the first direction; the top surface of the second semiconductor layer 705 is flush with the top surface of the first gate 302.
[0118] It should be noted that the portion of the second semiconductor layer 705 covered by the second gate 404 constitutes the second channel 402, and the second semiconductor layers 705 located at the bottom and top of the second channel 402 respectively constitute the second drain 401 and the second source 403.
[0119] In some embodiments, step S6033 may include the following steps:
[0120] A second semiconductor layer 705 and a second initial isolation structure 706 located on the sidewall of the second semiconductor layer 705 are formed in the second trench 704.
[0121] In implementation, a second isolation material is deposited in the second trench 704 to form an isolation strip (not shown). The patterned isolation strip forms a third trench (not shown) extending along the Z-axis direction. The third trench exposes the first gate 302. The third trench is filled with a second semiconductor material to form a... Figure 19 The second semiconductor layer 705 shown has the remaining isolation strips arranged as follows: Figure 19 The second initial isolation structure 706 is shown.
[0122] The second initial isolation structure 706 is re-etched, exposing the second channel 402 and the second source electrode 403;
[0123] During implementation, a dry etching technique (such as plasma etching) can be used to etch away part of the second initial isolation structure 706, exposing the second channel 402 and the second source 403, forming a structure as shown in the figure. Figure 20 The fourth groove 707 is shown.
[0124] A second gate 404 is formed on the surface of the second channel 402.
[0125] In implementation, firstly, a second gate dielectric material and a second gate conductive material are sequentially deposited on the surfaces of the second channel 402 and the second source 403 in the fourth trench 707, forming a structure located on the surfaces of the second channel 402 and the second source 403. Figure 21 The second initial gate dielectric layer 4041a and the second initial gate conductive layer 4042a are shown; next, the second initial gate dielectric layer 4041a and the second initial gate conductive layer 4042a are etched back until the second source 403 is exposed, forming as shown. Figure 22 The fifth trench 708 is shown; the remaining second initial gate dielectric layer 4041a and the second initial gate conductive layer 4042a constitute the second gate 404.
[0126] In some embodiments, after forming the second gate 404, the method for forming the semiconductor device further includes: depositing a third isolation material in the fifth trench 708 to form a third isolation structure 23, thereby forming a structure as described above. Figure 23 The semiconductor structure 20 is shown. The top surface of the third isolation structure 23 is flush with the top surface of the first gate 302.
[0127] In some embodiments, step S6033 may further include the following steps:
[0128] A first sub-isolating material is deposited in the second trench 704 to form a first sub-isolating strip (not shown). The first sub-isolating strip is patterned to form a sixth trench (not shown) extending along the Z-axis direction. The remaining first sub-isolating strips are formed as shown in the figure. Figure 24 The first initial sub-isolation structure 202a shown has a sixth trench exposing a first gate 302; a second sub-isolation material is filled in the sixth trench to form a second sub-isolation strip (not shown); the second sub-isolation strip is patterned to form a seventh trench (not shown) extending along the Z-axis direction; the remaining second sub-isolation strips are formed as shown in the figure. Figure 24 The second initial sub-isolation structure 203a shown has a seventh trench exposing a first gate 302; a second semiconductor material is deposited in the seventh trench to form a structure as shown in the diagram. Figure 24 The second semiconductor layer 705 is shown. Here, the first sub-isolation material can be silicon nitride, silicon carbonitride, silicon oxide, or silicon oxynitride; the second sub-isolation material can be the same as the first isolation material, for example, both being low dielectric constant materials. The second semiconductor material can be a metal oxide material, such as IGZO.
[0129] Next, the first initial sub-isolation structure 202a and the second initial sub-isolation structure 203a are etched back, exposing the second channel 402 and the second source 403, forming as shown in the figure. Figure 25 The fourth groove 707 is shown.
[0130] Next, a second gate dielectric material and a second gate conductive material are sequentially deposited on the surfaces of the second channel 402 and the second source 403 in the fourth trench 707, forming a structure located on the surfaces of the second channel 402 and the second source 403. Figure 26 The second initial gate dielectric layer 4041a and the second initial gate conductive layer 4042a are shown; the second initial gate dielectric layer 4041a and the second initial gate conductive layer 4042a are etched back until the second source 403 is exposed, and the remaining second initial gate dielectric layer 4041a and the second initial gate conductive layer 4042a are the second gate 404.
[0131] Finally, a third isolation structure 23 is formed on the top surface of the second gate 404, thereby forming such a Figure 2 The semiconductor device 20 shown.
[0132] The semiconductor device formed by the method for forming a semiconductor device provided in this disclosure includes a first transistor and a second transistor. Since the first transistor is a trench type and the second transistor is located in the trench of the first transistor, the occupied area and volume of the semiconductor device composed of the first transistor and the second transistor can be reduced, thereby improving the integration density of the semiconductor device.
[0133] It should be noted that the semiconductor device formed in this embodiment is similar to the semiconductor device in the above embodiments. For technical features not disclosed in detail in this embodiment, please refer to the above embodiments for understanding. Here, they will not be repeated.
[0134] Another embodiment of this disclosure also provides a method such as Figure 3 The method for forming the semiconductor device 20 shown is specifically as follows: Figure 3 The method for forming the semiconductor device 20 shown includes the following steps:
[0135] Provide substrate;
[0136] A trench-type first transistor is formed in the substrate;
[0137] It should be noted that the formation process of the first transistor can be understood by referring to the above embodiments, and will not be repeated here.
[0138] A planar second transistor is formed in the trench of the first transistor.
[0139] Specifically, in the trench of the first transistor (i.e. Figure 16 A first isolation layer is formed at the bottom of the second trench 702 shown; the first isolation layer is etched until the first gate 302 is exposed, forming a first etch trench extending along the Z-axis; a first etch trench is formed in the first etch trench as shown. Figure 3The second drain 401 shown is connected to the first gate 302; a structure is formed on the surface of the second drain 401 and the first isolation layer as shown. Figure 3 The second channel 402 shown; a surface of the second channel 402 is formed as shown Figure 3 The second gate dielectric layer 4041 and the second gate conductive layer 4042 are shown, and the second gate dielectric layer 4041 and the second gate conductive layer 4042 constitute the second gate 404; next, a second isolation layer covering the second gate 404 and the second channel 402 is formed in the second trench 702, and the top surface of the second isolation layer is flush with the top surface of the first gate 302; the second isolation layer is etched until the second channel 402 is exposed, forming a second etched trench extending along the Z-axis direction, and a second etched trench is formed in the second etched trench as shown in the figure. Figure 3 The second source 403 shown, the remaining second isolation layer and the first isolation layer constitute the fourth isolation structure 24.
[0140] Another embodiment of this disclosure also provides, as Figure 4 The method for forming the semiconductor device 20 shown is specifically as follows: Figure 4 The method for forming the semiconductor device 20 shown includes the following steps:
[0141] Provide substrate;
[0142] A trench-type first transistor is formed in the substrate;
[0143] It should be noted that the formation process of the first transistor can be understood by referring to the above embodiments, and will not be repeated here.
[0144] A trench-type second transistor is formed in the trench of the first transistor.
[0145] Specifically, in the trench of the first transistor (i.e. Figure 16 A third isolation layer is formed in the second trench 702 shown; the top surface of the third isolation layer is lower than the top surface of the first gate 302; the third isolation layer is etched to form a third etched trench extending along the Z-axis direction; the bottom of the third etched trench extends beyond the bottom of the first gate 302; a third etched trench is formed in the third etched trench as shown. Figure 4 The second channel 402 and the second gate 404 are shown, and a second drain 401 and a second source 403 are formed on the surface of the third isolation layer at both ends of the third etch trench; wherein the second drain 401 is connected to the first gate 302; a fourth isolation layer is formed in the third etch trench and the remaining second trench 702; the fourth isolation layer and the remaining third isolation layer constitute the fourth isolation structure 24.
[0146] It should be noted that the specific formation process of the trench-type second transistor is similar to that of the trench-type first transistor, and will not be explained in more detail here.
[0147] Another embodiment of this disclosure also provides, as Figure 5 The method for forming the semiconductor device 20 shown is specifically as follows: Figure 5 The method for forming the semiconductor device 20 shown includes the following steps:
[0148] Provide substrate;
[0149] A trench-type first transistor is formed in the substrate;
[0150] It should be noted that the formation process of the first transistor can be understood by referring to the above embodiments, and will not be repeated here.
[0151] An L-shaped second transistor is formed in the trench of the first transistor.
[0152] Specifically, in the trench of the first transistor (i.e. Figure 16 A fifth isolation layer is formed in the second trench 702 shown; the fifth isolation layer is etched to form a fourth etch trench extending along the Z-axis; the fourth etch trench exposes the bottom of the first gate 302; a structure is formed in the fourth etch trench as shown. Figure 5 The diagram shows a second drain 401, a second channel 402, and a second source 403, and forms a second gate 404 on the surface of the second channel 402; wherein the second drain 401 is connected to the first gate 302; a sixth isolation layer is formed in the remaining fourth etch trench; the sixth isolation layer and the remaining fifth isolation layer constitute a fourth isolation structure 24.
[0153] Another embodiment of this disclosure also provides, as Figure 6 The method for forming the semiconductor device 20 shown is specifically as follows: Figure 6 The method for forming the semiconductor device 20 shown includes the following steps:
[0154] Provide substrate;
[0155] A trench-type first transistor is formed in the substrate;
[0156] It should be noted that the formation process of the first transistor can be understood by referring to the above embodiments, and will not be repeated here.
[0157] A T-shaped second transistor is formed in the trench of the first transistor.
[0158] Specifically, in the trench of the first transistor (i.e. Figure 16A seventh isolation layer is formed in the second trench 702 shown; the seventh isolation layer is etched to form a fifth etch trench extending along the Z-axis; the fifth etch trench exposes the bottom of the first gate 302; a structure is formed in the fifth etch trench as shown. Figure 6 The second drain 401, the second channel 402, and the second source 403 are shown, and a second gate 404 is formed on the surface of the second channel 402; wherein the second drain 401 is connected to the first gate 302; an eighth isolation layer is formed in the remaining fifth etch trench; the eighth isolation layer and the remaining seventh isolation layer constitute a fourth isolation structure 24.
[0159] Another embodiment of this disclosure also provides, as Figure 7 The method for forming the semiconductor device 20 shown is specifically as follows: Figure 7 The method for forming the semiconductor device 20 shown includes the following steps:
[0160] Provide substrate;
[0161] A trench-type first transistor is formed in the substrate;
[0162] It should be noted that the formation process of the first transistor can be understood by referring to the above embodiments, and will not be repeated here.
[0163] An inverted T-shaped second transistor is formed in the trench of the first transistor.
[0164] Specifically, in the trench of the first transistor (i.e. Figure 16 A ninth isolation layer is formed in the second trench 702 shown; the ninth isolation layer is etched to form an inverted T-shaped sixth etch trench; the sixth etch trench exposes the bottom of the first gate 302; a structure is formed in the sixth etch trench as shown. Figure 6 The second drain 401, the second channel 402, and the second source 403 are shown, and a second gate 404 is formed on the surface of the second channel 402; wherein the second drain 401 is connected to the first gate 302; the remaining ninth isolation layer constitutes the fourth isolation structure 24.
[0165] In this embodiment of the present disclosure, regardless of whether the second transistor is trench type, vertical type or planar type, it is located in the trench of the first transistor, thus enabling miniaturization.
[0166] In the several embodiments provided in this disclosure, it should be understood that the disclosed structures and methods can be implemented in a non-target manner. The structural embodiments described above are merely illustrative. For example, the division of units is only a logical functional division, and in actual implementation, there may be other division methods, such as: multiple units or components can be combined, or integrated into another system, or some features can be ignored or not executed. In addition, the various components shown or discussed are coupled to each other or directly coupled.
[0167] The features disclosed in the several method or structural embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new method or structural embodiments.
[0168] The above are merely some embodiments of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.
Claims
1. A semiconductor device, characterized in that, include: Substrate: A first transistor located in the substrate; wherein the first transistor includes at least a U-shaped first channel and a first gate located on the surface of the first channel; the U-shaped opening of the first channel faces a first direction and is away from the substrate; the first direction is the thickness direction of the substrate; A second transistor located within the U-shaped opening on the surface of the first transistor; wherein the second transistor includes at least a second drain, the second drain being connected to the first gate.
2. The semiconductor device according to claim 1, characterized in that, The second transistor also includes a second channel; The second channel extends along the first direction; Alternatively, the extension direction of the second channel is perpendicular to the first direction; Alternatively, the second channel may be U-shaped, with the U-shaped opening of the second channel facing the first direction.
3. The semiconductor device according to claim 2, characterized in that, The second transistor further includes a second source and a second gate located on the surface of the second channel; The second source and the second drain are located at opposite ends of the second channel.
4. The semiconductor device according to claim 3, characterized in that, Also includes: First isolation structure; The first isolation structure is located between the first gate and the second gate.
5. The semiconductor device according to claim 4, characterized in that, The material of the first isolation structure includes a low dielectric constant material.
6. The semiconductor device according to claim 3, characterized in that, The first transistor further includes: a first source and a first drain; The first source and the first drain are located on the substrate surfaces at both ends of the first channel.
7. A method for forming a semiconductor device, characterized in that, The method includes: Provide substrate; A first transistor is formed in the substrate; wherein the first transistor includes at least a U-shaped first channel and a first gate located on the surface of the first channel; the U-shaped opening of the first channel faces a first direction and is away from the substrate; the first direction is the thickness direction of the substrate; A second transistor is formed within the U-shaped opening on the surface of the first transistor; wherein the second transistor includes at least a second drain, the second drain being connected to the first gate.
8. The method according to claim 7, characterized in that, The first transistor further includes a first source and a first drain located at both ends of the first channel; forming the first transistor in the substrate includes: The substrate is etched to form a first trench; A first semiconductor layer is formed on the substrate surface and the inner surface of the first trench; wherein the first semiconductor layer located on the inner surface of the first trench constitutes the first channel, and the first semiconductor layers located on the substrate surfaces at both ends of the first trench constitute the first source and the first drain, respectively. The first gate is formed on the surface of the first channel.
9. The method according to claim 8, characterized in that, The second transistor further includes a second gate and a second source; the second transistor is formed within the U-shaped opening on the surface of the first transistor, including: A first initial isolation structure is formed in the first trench; The first initial isolation structure is patterned to form a first isolation structure and a second trench located between the first isolation structures; wherein the second trench exposes the first gate. A second semiconductor layer extending along the first direction is formed in the second trench, and a second gate is located on the middle sidewall of the second semiconductor layer along the first direction; the top surface of the second semiconductor layer is flush with the top surface of the first gate. Wherein, the portion of the second semiconductor layer covered by the second gate forms the second channel, and the second semiconductor layers located at the bottom and top of the second channel form the second drain and the second source, respectively.
10. The method according to claim 9, characterized in that, Forming a second semiconductor layer extending along the first direction in the second trench, and a second gate located on the middle sidewall of the second semiconductor layer along the first direction, includes: The second semiconductor layer and the second initial isolation structure located on the sidewall of the second semiconductor layer are formed in the second trench; The second initial isolation structure is re-etched to expose the second channel and the second source. The second gate is formed on the surface of the second channel.