Display substrate, display panel and display device

Abstract

The present disclosure provides a display substrate, a display panel and a display device. The display substrate comprises: a substrate; a plurality of signal lines, the plurality of signal lines are located on one side of the substrate and arranged along a first direction, and the orthographic projection shape of the signal lines on the substrate is a zigzag shape; a plurality of common electrode strips, the plurality of common electrode strips and the signal lines are located on the same side of the substrate, and the two are insulated from each other; the plurality of common electrode strips extend along the first direction and are arranged along a second direction, the common electrode strips comprise a plurality of common electrode blocks arranged in sequence along the first direction, a first slit is provided between adjacent common electrode blocks, and at least part of the orthographic projections of the signal lines on the substrate are located within the orthographic projections of the first slits on the substrate.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to the Chinese patent application filed with the China Patent Office on December 29, 2021, with application number PCT / CN2021 / 142652 and application name “Display Device”, the entire contents of which are incorporated by reference into this application. Technical Field

[0003] The present disclosure relates to the field of semiconductor technology, and in particular to a display substrate, a display panel and a display device. Background Art

[0004] In recent years, the field of 3D display has developed rapidly. Among them, grating type 3D display devices have attracted much attention due to their advantages such as simple process and low crosstalk. Generally, grating type 3D display devices include a display panel and a grating. The left eye and right eye of the viewer obtain the left eye view and right eye view displayed by the display panel through the grating respectively to form a 3D display image. Summary of the invention

[0005] The present disclosure provides a display substrate, a display panel and a display device. The display substrate comprises:

[0006] substrate;

[0007] A plurality of signal lines, wherein the plurality of signal lines are located on one side of the substrate and arranged along a first direction, and the orthographic projection shape of the signal lines on the substrate is a folded line;

[0008] A plurality of common electrode strips, wherein the plurality of common electrode strips and the signal lines are located on the same side of the substrate and are insulated from each other; the plurality of common electrode strips extend along the first direction and are arranged along the second direction, the common electrode strips include a plurality of common electrode blocks arranged in sequence along the first direction, a first slit is provided between adjacent common electrode blocks, and at least a portion of the signal lines have their orthographic projections on the substrate located within the orthographic projections of the first slit on the substrate.

[0009] In a possible implementation manner, the signal line includes a first signal line portion and a second signal line portion; the orthographic projection of the first signal line portion on the substrate is located in the region where the orthographic projection of the first slit on the substrate is located, and the orthographic projection of the second signal line portion on the substrate is located in the gap region between two adjacent common electrode strips;

[0010] The orthographic projection shape of the first signal line portion on the substrate is a zigzag shape; the orthographic projection shape of the first slit on the substrate is similar to the orthographic projection shape of the first signal line portion on the substrate.

[0011] In a possible implementation manner, in a direction perpendicular to an extension direction of the first signal line portion, a width of the first slit is greater than a width of the first signal line portion.

[0012] In a possible implementation, the display substrate further includes a data line layer located on a side of the common electrode strip away from the substrate; the data line layer includes a plurality of data lines extending along the second direction;

[0013] The signal line includes the data line.

[0014] In a possible implementation manner, the data line layer further includes a plurality of first connection lines extending along the second direction, and two adjacent common electrode strips are electrically connected via the first connection lines;

[0015] The signal line further includes the first connecting line.

[0016] In a possible implementation manner, the common electrode strip is provided with the first slit only in the area where the data line is located.

[0017] In a possible implementation manner, the common electrode strip is provided with the first slit in the area where the data line and the first connecting line are located.

[0018] In a possible implementation, in the first direction, the data lines and the first connection lines are arranged alternately.

[0019] In a possible implementation, the display substrate further includes a plurality of second connection lines extending along the first direction, and each of the common electrode blocks of the same common electrode bar is electrically connected to the same second connection line.

[0020] In a possible implementation, the display substrate further includes a gate layer located between the common electrode layer and the data line layer, and the gate layer includes a plurality of gate lines extending along the second direction;

[0021] The second connection line is located in the gate layer.

[0022] In a possible implementation, the display substrate further includes a light shielding strip located on a side of the common electrode strip facing away from the substrate, and the light shielding strip's orthographic projection on the substrate covers a region of the common electrode block close to the first slit.

[0023] In a possible implementation manner, an orthographic projection of the light-shielding strip on the substrate and an orthographic projection of the first slit on the substrate do not overlap with each other.

[0024] In a possible implementation manner, an orthographic projection shape of the light shielding strip on the substrate is similar to an orthographic projection shape of the first slit on the substrate.

[0025] In a possible implementation manner, in the second direction, the length of the light shielding strip is substantially the same as the length of the first signal line portion.

[0026] In a possible implementation manner, the light shielding strip is located on the gate layer.

[0027] In a possible implementation manner, the display substrate further includes a plurality of pixel electrodes located on a side of the data line layer away from the substrate;

[0028] The pixel electrode includes: two sub-pixel electrode portions arranged along the first direction, and a bridge portion connecting the two sub-pixel electrode portions; a second slit is provided between the two sub-pixel electrode portions.

[0029] In a possible implementation manner, an orthographic projection of the signal line on the substrate is located within an orthographic projection of the second slit on the substrate.

[0030] In a possible implementation manner, the orthographic projection of the first slit on the substrate is located within the orthographic projection of the second slit on the substrate.

[0031] In a possible embodiment, the sub-pixel electrode portion includes: a skeleton portion, and a plurality of branch groups, the skeleton portion is in a zigzag shape with the main direction extending along the second direction, the plurality of branch groups extend from the skeleton portion to a side away from the second slit, and the outer edges of adjacent branch groups connected to the same skeleton portion are alternately convex.

[0032] In a possible implementation, the plurality of branch groups include a first branch group and a second branch group; and among the plurality of branch groups connected to the same skeleton portion, the first branch group and the second branch group are arranged alternately.

[0033] In a possible implementation manner, the convex dimensions of each of the first branch groups relative to each of the second branch groups are substantially the same.

[0034] In a possible implementation manner, the protrusion dimension of each of the first branch groups relative to each of the second branch groups is 2-5 times the spacing between adjacent pixel electrodes.

[0035] In a possible implementation manner, the number of the first branch groups connected to the same skeleton portion is substantially the same as the number of the second branch groups.

[0036] In a possible implementation, the first branch groups of different sub-pixel electrode portions within the same pixel electrode are staggered in an extension direction parallel to the first branch groups; and the second branch groups of different sub-pixel electrode portions within the same pixel electrode are staggered in an extension direction parallel to the first branch groups.

[0037] In a possible implementation manner, the branch group includes: a plurality of branches extending from the skeleton portion to a side away from the second slit; within the same branch group, a third slit is provided between adjacent branches;

[0038] The outer edges of the plurality of branches in the same branch group away from the second slit are substantially flush.

[0039] In a possible implementation, in the same sub-pixel electrode portion, outer edges of the branches of each of the first branch groups are flush; in the same sub-pixel electrode portion, outer edges of the branches of each of the second branch groups are substantially flush.

[0040] In a possible implementation manner, the number of the branches included in at least part of the first branch group is substantially the same as the number of the branches included in at least part of the second branch group.

[0041] In a possible implementation manner, outer edge patterns of the branch groups of adjacent pixel electrodes are complementary.

[0042] In a possible implementation manner, the first branch group of the pixel electrodes is arranged opposite to the second branch group of the adjacent pixel electrodes.

[0043] In a possible implementation manner, the line width of the first connecting line is smaller than the line width of the data line; and the distance between the first connecting line and the second slit is smaller than the distance between the data line and the second slit.

[0044] In a possible implementation manner, the data line layer further includes a first electrode electrically connected to the data line, and a second electrode separated from the first electrode;

[0045] The pixel electrode includes a first type of pixel electrode and a second type of pixel electrode alternately arranged along the first direction, wherein the first type of pixel electrode includes: a first transition portion, and a first connecting portion; the first connecting portion connects the first transition portion and one of the sub-pixel electrode portions across the first connecting line; the orthographic projection of the first transition portion on the substrate and the orthographic projection of the second pole on the substrate have an overlapping area; the second type of pixel electrode includes: a second transition portion directly connected to one of the sub-pixel electrode portions, and the orthographic projection of the second transition portion on the substrate and the orthographic projection of the second pole on the substrate have an overlapping area.

[0046] In a possible implementation, the second type of pixel electrode further includes: a compensation portion extending from the second adapter portion along the first direction away from the data line, wherein an orthographic projection of the compensation portion on the substrate overlaps with an orthographic projection of the first connecting line on the substrate.

[0047] In a possible implementation, an overlapping area formed by an orthographic projection of the compensation portion on the substrate and an orthographic projection of the first connecting line on the substrate is substantially equal to an overlapping area formed by an orthographic projection of the first connecting portion on the substrate and an orthographic projection of the first connecting line on the substrate.

[0048] In a possible implementation manner, a shape of an orthographic projection of the compensation portion on the substrate is similar to a shape of an orthographic projection of the first connection portion on the substrate.

[0049] In a possible implementation manner, the compensation portion and the second transition portion are located on the same layer.

[0050] In a possible implementation manner, the sub-pixel electrode portion, the bridge portion, the first transfer portion, and the first connection portion of the same pixel electrode are located in the same layer.

[0051] The embodiment of the present disclosure further provides a display panel, which includes the display substrate provided in the embodiment of the present disclosure.

[0052] In a possible implementation, the display panel further includes an opposing substrate disposed opposite to the display substrate;

[0053] The opposite substrate includes a black matrix, the black matrix includes a first black matrix portion arranged corresponding to the first slit area, and the orthographic projection of the first black matrix portion on the substrate covers the orthographic projection of the first slit on the substrate.

[0054] In a possible implementation manner, an outer edge of the first black matrix portion is substantially flush with an outer edge of the light shielding strip away from the first slit.

[0055] In a possible embodiment, the first black matrix portion has a first sub-black matrix portion, and second sub-black matrix portions located on both sides of the first sub-black matrix portion; wherein the orthographic projection of the first sub-black matrix portion on the substrate coincides with the orthographic projection of the first slit on the substrate, and the orthographic projection of the second sub-black matrix portion on the substrate coincides with the orthographic projection of the shading strip on the substrate.

[0056] In a possible implementation manner, a width of the first sub-black matrix portion covering the first connecting line in an orthographic projection of the substrate is less than or equal to a width of the first sub-black matrix portion covering the data line.

[0057] An embodiment of the present disclosure further provides a display device, which includes the display panel provided by the embodiment of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0058] Figure 1 It is a structural schematic diagram of a 3D display device;

[0059] Figure 2 Schematic diagram of ideal display dark area for naked-eye 3D products;

[0060] Figure 3A One of the schematic diagrams of a display substrate provided in an embodiment of the present disclosure;

[0061] Figure 3B for Figure 3A Schematic diagram of a single film layer of the common electrode layer;

[0062] Figure 3C for Figure 3A Schematic diagram of a single film layer where the signal line is located;

[0063] Figure 3D for Figure 3A Schematic diagram of the cross section along the dotted line EF;

[0064] Figure 3E exist Figure 3A Schematic diagram of a display substrate after superimposing a gate layer;

[0065] Figure 3F for Figure 3E Schematic diagram of a single film layer of the gate layer in FIG.

[0066] Figure 3G For Figure 3E A schematic cross-sectional view corresponding to the dashed line GH;

[0067] Figure 4A A second schematic diagram of a display substrate provided in an embodiment of the present disclosure;

[0068] Figure 4B for Figure 4A Schematic diagram of a single film layer of the common electrode layer;

[0069] Figure 4C for Figure 4A Schematic diagram of a single film layer where the signal line is located;

[0070] Figure 4D for Figure 4A Schematic diagram of the cross section along the dotted line EF;

[0071] Figure 4E For Figure 4A Schematic diagram of a display substrate after superimposing a gate layer;

[0072] Figure 4F for Figure 4E Schematic diagram of a single film layer of the gate layer in FIG.

[0073] Figure 4G For Figure 4E A schematic cross-sectional view corresponding to the dashed line GH;

[0074] Figure 5A A schematic diagram of testing light leakage of a display product without a shading strip;

[0075] Figure 5B A schematic diagram of testing light leakage of a display product provided with a shading strip;

[0076] Fig. 6A For Figure 3E Schematic diagram of the film layer after superimposing the pixel electrode layer;

[0077] Figure 6B for Fig. 6A A schematic cross-sectional view corresponding to the dashed line GH;

[0078] Figure 6C is a schematic diagram of the stacking of a pixel electrode layer and a data line layer;

[0079] Fig.6D is a schematic diagram of a single film layer of a pixel electrode layer;

[0080] Fig. 6E is a schematic diagram of a pixel electrode;

[0081] Fig. 6F is another schematic diagram of a pixel electrode;

[0082] Figure 7 A schematic diagram of another pixel electrode provided by an embodiment of the present disclosure;

[0083] Figure 8 A schematic diagram of another pixel electrode provided in an embodiment of the present disclosure;

[0084] Fig.9A A display substrate with a single-gate structure includes a stacked schematic diagram of a common electrode layer, a data line layer, a gate layer, and a pixel electrode layer;

[0085] Fig. 9B A display substrate with a single-gate structure includes a stacked schematic diagram of a common electrode layer, a data line layer and a gate layer;

[0086] Fig. 9C for Fig. 9B Schematic diagram of the film layers of a single gate layer in the middle;

[0087] Fig. 10A A schematic diagram of forming a common electrode layer for a dual-gate structure display substrate;

[0088] Fig. 10B A schematic diagram of forming a gate layer for a dual-gate structure display substrate;

[0089] Fig. 10C A schematic diagram of forming an active layer for a dual-gate structure display substrate;

[0090] Fig. 10D A schematic diagram of forming a common electrode layer for a dual-gate structure display substrate;

[0091] Fig.10E A schematic diagram of forming a pixel electrode layer for a dual-gate structure display substrate;

[0092] Fig.10F A schematic diagram of forming a black matrix for a dual-gate structure display substrate;

[0093] Figure 10G Schematic diagram of a single black matrix film layer;

[0094] Fig.11A A schematic diagram of forming a common electrode layer on a single-gate structure display substrate;

[0095] Fig. 11B A schematic diagram showing a gate layer formed on a substrate for a single-gate structure;

[0096] Fig. 11C A schematic diagram of forming an active layer for a single-gate structure display substrate;

[0097] Fig.11D A schematic diagram of forming a common electrode layer on a single-gate structure display substrate;

[0098] Fig.11E A schematic diagram of forming a pixel electrode layer for a single-gate structure display substrate;

[0099] Fig.11F A schematic diagram of forming a black matrix on a single-gate structure display substrate;

[0100] Fig.11G Schematic diagram of a black matrix single film layer;

[0101] Fig. 12A A schematic diagram of forming a common electrode layer on a display substrate in which a common electrode strip is provided with a first slit only at a data line;

[0102] Fig. 12B A schematic diagram of forming a gate layer on a display substrate in which a common electrode strip is provided with a first slit only at a data line;

[0103] Fig. 12C A schematic diagram of forming an active layer on a display substrate in which a common electrode strip is provided with a first slit only at a data line;

[0104] Fig.12D A schematic diagram of forming a common electrode layer on a display substrate in which a common electrode strip is provided with a first slit only at a data line;

[0105] Fig.12E A schematic diagram of forming a pixel electrode layer on a display substrate in which a common electrode strip is provided with a first slit only at a data line;

[0106] Fig.12F A schematic diagram of forming a black matrix on a display substrate in which a common electrode strip is provided with first slits only at data lines;

[0107] Figure 12G for Fig.12F A schematic cross-sectional view at the dashed line EF;

[0108] Fig.12H Schematic diagram of a single black matrix film layer. DETAILED DESCRIPTION

[0109] In order to make the purpose, technical solution and advantages of the embodiments of the present disclosure clearer, the technical solution of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0110] Unless otherwise defined, the technical terms or scientific terms used in the present disclosure should be understood by people with ordinary skills in the field to which the present disclosure belongs. The "first", "second" and similar words used in the present disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. "Include" or "comprise" and similar words mean that the elements or objects appearing before the word cover the elements or objects listed after the word and their equivalents, without excluding other elements or objects. "Connect" or "connected" and similar words are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0111] As used herein, "approximately" or "substantially the same" includes the stated value and means within an acceptable range of deviation for the particular value as determined by one of ordinary skill in the art taking into account the measurement in question and the errors associated with the measurement of the particular quantity (i.e., the limitations of the measurement system). For example, "substantially the same" may mean that the difference relative to the stated value is within one or more standard deviations, or within ±30%, 20%, 10%, 5%.

[0112] In the accompanying drawings, the thickness of layers, films, panels, regions, etc., is exaggerated for clarity. Exemplary embodiments are described herein with reference to cross-sectional views as schematic diagrams of idealized embodiments. In this way, deviations from the shapes of the figures as a result of, for example, manufacturing techniques and / or tolerances will be expected. Thus, the embodiments described herein should not be interpreted as being limited to the specific shapes of the regions as shown herein, but include deviations in shape caused by, for example, manufacturing. For example, a region illustrated or described as flat may typically have rough and / or nonlinear features. In addition, the illustrated sharp corners may be rounded. Thus, the regions shown in the figures are schematic in nature, and their shapes are not intended to illustrate the precise shapes of the regions, and are not intended to limit the scope of the claims.

[0113] In order to keep the following description of the embodiments of the present disclosure clear and concise, the present disclosure omits detailed descriptions of well-known functions and well-known components.

[0114] See also Figure 1 As shown, it is a schematic diagram of the structure of naked-eye 3D, including a light source 01, a display panel 02, a flat glass 04, a lenticular layer 03, and a protective layer 05 (specifically, a resin layer) arranged in sequence, wherein the display panel 02 receives external signals and displays a two-dimensional picture; and then refracts through the lenticular layer 03 in front of the screen to achieve parallax, form a three-dimensional effect, and allow the viewer to see a 3D image.

[0115] In order to improve the moiré defect of naked-eye 3D products, the vertical dark area of ​​the pixels in the display panel should be as small as possible, otherwise the wider dark area will form thick moiré fringes after being imaged by the lenticular lens. Figure 2 As shown, Figure 2 Schematic diagram of the ideal display dark area of ​​naked-eye 3D products. The pixel design in the display panel must meet the following two rules: ① The vertical data line at the position is an opaque metal line, which must be bent and routed to achieve the diagonal dark area; ② The adjacent pixels at the position are not ideal zero-pitch displays, so the distance between adjacent pixel electrodes must be reduced as much as possible, reducing the width of the non-display area, while improving the light efficiency of the pixel edge to minimize the width of the vertical dark area.

[0116] The naked-eye 3D pixel design that uses the High Advanced Super Dimension Switch (HADS) display mode and sets a thicker organic film (ORG) between the data line and the common electrode layer and the pixel electrode layer is more suitable for smaller products. When the product size is larger, on the one hand, the corresponding vertical data line path is longer; on the other hand, the product is difficult to charge, and in order to increase the charging rate, the data line width must increase. Both will cause the overlap area between the data signal and the common (Com) electrode and pixel (Pixel) electrode above to increase, and the coupling capacitance will increase significantly. Even if the organic film process is used, this problem cannot be solved, which is why large-size products cannot be made into HADS mode. Therefore, the mass production of the above-mentioned HADS ORG process is limited to small-size products, and the organic film has a great impact on production capacity and high cost, which is not conducive to the mass production application of 3D.

[0117] In view of this, see Figure 3A-3D , Figure 4A-4D As shown, Figure 3B for Figure 3A Schematic diagram of a single film layer of the common electrode layer. Figure 3C for Figure 3A Schematic diagram of a single film layer where the signal line is located. Figure 3D for Figure 3A Schematic diagram of the cross section along the dotted line EF, Figure 4B for Figure 4A Schematic diagram of a single film layer of the common electrode layer. Figure 4C for Figure 4A Schematic diagram of a single film layer where the signal line is located. Figure 4D for Figure 4A A cross-sectional schematic diagram along the dotted line EF shows that an embodiment of the present disclosure provides a display substrate, which includes:

[0118] Substrate 1;

[0119] A plurality of signal lines 2, the plurality of signal lines 2 are located on one side of the substrate 1 and arranged along the first direction X, and the orthographic projection shape of the signal lines on the substrate 1 is a folded line shape; specifically, the main direction of the signal lines 2 can extend along the second direction Y;

[0120] A plurality of common electrode strips 3, the plurality of common electrode strips 3 and the signal line 2 are located on the same side of the substrate 1, and the two are insulated from each other; the plurality of common electrode strips 3 extend along the first direction X and are arranged along the second direction Y, the common electrode strips 3 include a plurality of common electrode blocks 31 arranged in sequence along the first direction X, a first slit 30 is provided between adjacent common electrode blocks 31, and at least a portion of the signal line 2 is located within the orthographic projection of the first slit 30 on the substrate 1. Specifically, one common electrode strip 3 may correspond to a row of pixel electrodes.

[0121] In the embodiment of the present disclosure, the common electrode strip 3 includes a plurality of common electrode blocks 31 arranged in sequence along a first direction X, and a first slit 30 is provided between adjacent common electrode blocks 31. The orthographic projection of the signal line 2 on the substrate 1 is located within the orthographic projection of the first slit 30 on the substrate 1. By designing the common electrode strip 3 in blocks, each common electrode block 31 is arranged with the bent signal line 2 as a dividing line to avoid large-area vertical overlap of the common electrode strip 3 and the signal line 2, thereby reducing the coupling capacitance between the common electrode strip 3 and the signal line 2. Moreover, compared with the related art that reduces the coupling capacitance between the common electrode strip 3 and the signal line 2 by setting a thicker organic film, the embodiment of the present disclosure can reduce the coupling capacitance without setting an organic film, and can be suitable for large-size display products, with a low production cost, which is conducive to the mass production application of 3D display products.

[0122] In one possible implementation, combining Figure 3A-3D , Figure 4A-4D As shown, the signal line 2 includes a first signal line portion 201 and a second signal line portion 202; the orthographic projection of the first signal line portion 201 on the substrate 1 is located in the area where the orthographic projection of the first slit 30 on the substrate 1 is located, and the orthographic projection of the second signal line portion 202 on the substrate 1 is located in the gap area between two adjacent common electrode strips 3; the orthographic projection shape of the first signal line portion 201 on the substrate 1 is a zigzag shape; the orthographic projection of the first slit 30 on the substrate 1 is similar to the orthographic projection shape of the first signal line portion 201 on the substrate 1. In this way, the first signal line portion 201 is located in the first slit 30 between adjacent common electrode blocks 31, avoiding vertical overlap between the common electrode strips 3 and the signal line 2. In addition, the orthographic projection shape of the first signal line portion 201 on the substrate 1 is a zigzag shape, which can realize the oblique line of the dark area, eliminate the moiré pattern in the display image, and improve the display effect.

[0123] In one possible implementation, combining Figure 3A-3D As shown, in a direction perpendicular to the extension direction of the first signal line portion 201 , a width k1 of the first slit 30 is greater than a width k2 of the first signal line portion 201 .

[0124] In one possible implementation, combining Figure 3A-3D , Figure 4A-4D As shown, the display substrate further includes a data line layer 2 located on the side of the common electrode strip 3 away from the substrate 1 ; the data line layer 2 includes a plurality of data lines 21 extending along the second direction Y; and the signal line 2 includes the data line 21 .

[0125] In one possible implementation, combining Figure 3A-3D , Figure 4A-4D As shown, the data line layer further includes a plurality of first connection lines 22 extending along the second direction Y, and two adjacent common electrode strips 3 can be electrically connected via the first connection lines 22 ; the signal line 2 also includes the first connection lines 22 .

[0126] In a specific implementation, the common electrode strip 3 may be provided with the first slit 30 in the area where each signal line 2 is located, or may be provided with the first slit 30 only in the area where some signal lines 2 are located, which is specifically described below with examples.

[0127] For example, in one possible embodiment, combining Figure 3A-3D The common electrode strips 3 are provided with first slits 30 in the areas where the data lines 21 and the first connecting lines 22 are located. In the disclosed embodiment, the common electrode strips 3 are provided with first slits 30 in the areas where the data lines 21 and the first connecting lines 22 are located. The common electrode strips 3 are designed in blocks and arranged with the bent signal lines 2 as the dividing lines to avoid large-area vertical overlap of the common electrode strips 3 and the signal lines 2.

[0128] For example, in another possible implementation, in combination Figure 4A-4D As shown, the common electrode strip 3 is provided with the first slit 30 only in the area where the data line 21 is located. In the disclosed embodiment, the common electrode strip 3 is provided with the first slit 30 only in the area where the data line 21 is located, that is, the common electrode strip 3 is a complete surface under the first connecting line 22, there is no coupling capacitor, and it has an electric field shielding effect.

[0129] In one possible implementation, combining Figure 3A-3D , Figure 4A-4D As shown, in the first direction X, the data lines 21 and the first connection lines 22 are arranged alternately.

[0130] In one possible implementation, combining Figure 3E-3G , Figure 4E-Figure 4G As shown, Figure 3F for Figure 3E Schematic diagram of the film layers of the gate layer and the common electrode layer in FIG. Figure 3G For Figure 3E Schematic diagram of a single film layer in the middle gate layer. Figure 4F for Figure 4E Schematic diagram of the film layers of the gate layer and the common electrode layer in FIG. Figure 4G For Figure 4E A schematic diagram of a single film layer of the gate layer shows that the substrate further includes a plurality of second connection lines 41 extending along the first direction X, and each common electrode block 31 of the same common electrode strip 3 can be electrically connected to the same second connection line 41 .

[0131] In one possible implementation, see Figure 3E-3G , Figure 4E-Figure 4G As shown, the display substrate further includes a gate layer 4 located between the common electrode layer and the data line layer 2 , the gate layer 4 includes a plurality of gate lines 42 extending along the second direction Y; the second connection line 41 is located in the gate layer 4 .

[0132] Specific, combined Figure 3D , Figure 4D As shown, a first insulating layer 61 may be disposed between the common electrode strip 3 and the data line layer 2, and a second insulating layer 62 may be disposed on the side of the data line layer 2 away from the first insulating layer 61. Figure 3E-3G , Figure 4E-Figure 4G As shown, each common electrode block 31 of the same common electrode strip 3 is electrically connected to the same second connecting line 41. Specifically, the second connecting line 41 and the common electrode strip 3 can be located in adjacent layers, and the second connecting line 41 and the common electrode strip 3 can be electrically connected through direct contact; the first connecting line 22 and the common electrode strip 3 can be located in a different layer, and the first connecting line 22 can be electrically connected to the second connecting line 41 through a via hole penetrating the first insulating layer 61, thereby further realizing electrical connection with the common electrode strip 3.

[0133] In one possible implementation, combining Figure 3D-Figure 3G , Figure 4E-Figure 4G As shown, the display substrate also includes a light shielding strip 43 located on the side of the common electrode strip 3 facing away from the substrate 1, and the orthographic projection of the light shielding strip 43 on the substrate 1 covers the area of ​​the common electrode block 31 near the first slit 30. In the embodiment of the present disclosure, since the common electrode strip 3 does not cover the data line 21, it is unable to shield the electric field generated by the changing data line 21, and the electric field between the bent data line 21 and the comb-shaped pixel electrode 5 is not perpendicular, the liquid crystal deflection causes regional light leakage. Therefore, compared with the display product in the related art where the data line 21 is a straight line, a very wide black matrix is ​​required to cover the data line 21, thereby causing a large aperture loss. In order to improve the aperture, further, in the embodiment of the present disclosure, along the bent data line 21, above the edge of the common electrode block 31, a light shielding strip 43 is added for light shielding, which can reduce the light leakage area, reduce the black matrix width, and improve the aperture. Specifically, by taking the display products without and with light shielding strips as examples for testing, see FIG. Figure 5A and Figure 5B As shown, Figure 5A Schematic diagram of light leakage of a display product without a shading strip, where Figure 5B Schematic diagram of light leakage of display products with shading strips. The light leakage area is Figure 5A The 22.9 μm in Figure 5B The black matrix coverage width can be reduced from 32.9μm to 24.5μm, and the aperture ratio is increased from 42% to 50.9%, which is comparable to display products with traditional data lines 21 in a straight line.

[0134] In one possible implementation, combining Figure 3D As shown, the orthographic projection of the light shielding strip 43 on the substrate 1 and the orthographic projection of the first slit 30 on the substrate 1 do not overlap each other.

[0135] In one possible implementation, see Figure 3A-3G , Figure 4A-4G As shown, the orthographic projection shape of the light shielding strip 43 on the substrate 1 is similar to the orthographic projection shape of the first slit 30 on the substrate 4. In this way, the light leakage at the first slit 30 can be well shielded.

[0136] In one possible implementation, see Figure 3E and Figure 4E As shown, in the second direction Y, the length k3 of the light shielding strip 43 is substantially the same as the length k4 of the first signal line portion 201 .

[0137] In one possible implementation, see Figure 3G , Figure 4G , Figure 3D As shown, the light shielding strip 43 is located at the gate layer 4. In the disclosed embodiment, the light shielding strip 43 is located at the gate layer 4, which can achieve better shielding of light leakage at the first slit 30 without increasing the display substrate process, thereby improving the aperture ratio of the display substrate.

[0138] In one possible implementation, see Figure 6A-6F , Figure 7 and Figure 8 As shown, Figure 6B for Fig. 6A The cross-sectional view corresponding to the dashed line GH is shown below: Figure 6C for Fig. 6A Schematic diagram of the stacking of the pixel electrode layer and the data line layer, Fig.6D for Fig. 6A Schematic diagram of a single film layer of the pixel electrode layer. Fig. 6E is a schematic diagram of a pixel electrode, Fig. 6F Another schematic diagram of a pixel electrode, the display substrate further includes a plurality of pixel electrodes 5 located on the side of the data line layer 2 away from the substrate 1; the pixel electrode 5 includes: two sub-pixel electrode portions 51 arranged along the first direction X, and a bridge portion 53 connecting the two sub-pixel electrode portions 51; a second slit 50 is provided between the two sub-pixel electrode portions 51. In the disclosed embodiment, considering that the data line 21 must be bent, the overlapping portion of the pixel electrode 5 and the bent data line 21 is hollowed out and divided into two, which are separated on both sides of the data line 21. The skeletons of the left and right half electrodes are arranged along the bent data line 21, and are connected at the corners of the data line 21 to form a whole. The edge adopts an open slit structure to improve the light effect and reduce the dark area. This pixel design can greatly reduce the overlapping capacitance of the data line 21 and the pixel electrode 5 and the common electrode strip 3, and can be applied to products of different sizes, especially suitable for large-size products.

[0139] Specifically, along the second direction Y, the width of the bridge portion 53 may be about 5 μm to 6 μm, so as to avoid the problem that a too wide width may increase the overlapping capacitance with the data line 21 , and a too narrow width may easily cause breakage and poor connection and conduction effects.

[0140] In one possible implementation, see Figure 6A-6C As shown, the orthographic projection of the signal line 2 on the substrate 1 is located within the orthographic projection of the second slit 50 on the substrate 1 .

[0141] In one possible implementation, see Figure 6B As shown, the orthographic projection of the first slit 30 on the substrate 1 is located within the orthographic projection of the second slit 50 on the substrate 1 .

[0142] In one possible implementation, see Figure 6A-6F , Figure 7 and Figure 8 As shown, the sub-pixel electrode portion 51 includes: a skeleton portion 511, and a plurality of branch groups 512. The skeleton portion 511 is a zigzag shape with the main direction extending along the second direction Y. The plurality of branch groups 512 extend from the skeleton portion 511 to a side away from the second slit 50, and the outer edges of adjacent branch groups 512 connected to the same skeleton portion 511 are alternately convex. In the embodiment of the present disclosure, the pixel electrode 5 is bent, that is, the dark area between adjacent pixel electrodes 5 is divided into left and right sections, so that the dark area is staggered and obliquely formed. Figure 6C As shown in the figure as an example, each sub-pixel electrode portion 51 is divided into two sections, the upper section is horizontally shifted to the left, and the lower section is horizontally shifted to the right, which can further achieve moiré avoidance.

[0143] In one possible implementation, see Figure 6A-6F , Figure 7 and Figure 8 As shown, the multiple branch groups 512 include a first branch group 5121 and a second branch group 5122; among the multiple branch groups 512 connected to the same skeleton portion 511, the first branch groups 5121 and the second branch groups 5122 are arranged alternately, and the outer edge of the first branch group 5121 is convex relative to the outer edge of the second branch group 5122.

[0144] In one possible implementation, see Figure 6A-6F , Figure 7 and Figure 8 As shown, the outer projection dimensions of each first branch group 5121 relative to each second branch group 5122 are substantially the same. Figure 8As shown, the outer projection dimension b1 of the first first branch group 5121 from top to bottom relative to the first second branch group 5122 of the right sub-pixel electrode portion 51 is substantially the same as the outer projection dimension b2 of the second first branch group 5121 relative to the second second branch group 5122. This is beneficial to simplify the manufacturing process of the pixel electrode 5. Of course, in a specific implementation, the outer projection dimensions of different first branch groups 5121 relative to the second branch group 5122 may also be different, so that the dark area between adjacent pixel electrodes 5 can be further weakened.

[0145] It should be noted that, due to the limited actual process accuracy, it is difficult to require that the convex dimensions of each first branch group 5121 relative to each second branch group 5122 are exactly the same. In the embodiment of the present disclosure, the convex dimensions of each first branch group 5121 relative to each second branch group 5122 are roughly the same. It can be understood that the difference in the convex dimensions of each first branch group 5121 relative to each second branch group 5122 is less than 10% of the ratio of any one of them.

[0146] In one possible implementation, see Figure 6A-6F , Figure 7 and Figure 8 As shown, the outer protrusion dimension b of each first branch group 5121 relative to each second branch group 5122 is 2-5 times the spacing c between adjacent pixel electrodes 5. In this way, without affecting the normal display of the pixel electrodes 5 of the display substrate, a better effect of weakening the dark area between adjacent pixel electrodes 5 is achieved to avoid excessive bending, which will cause a heavier color mixing effect, and too small bending, which will make the dark area fold line inconspicuous.

[0147] Specifically, for example, the outer protrusion dimension b of each first branch group 5121 relative to each second branch group 5122 is 2 times, 3 times, 4 times or 5 times the spacing c of adjacent pixel electrodes 5. For example, the spacing c of adjacent pixel electrodes 5 is 3μm, and the outer protrusion dimension b of each first branch group 5121 relative to each second branch group 5122 is 6μm. The spacing c of adjacent pixel electrodes 5 can also be 3.5μm, or it can be further reduced to less than 3μm according to the accuracy of the exposure machine while avoiding poor process; the outer protrusion dimension b of each first branch group 5121 relative to each second branch group 5122 can also be reduced to 1μm, 2μm, 3μm, 4μm or 5μm. Specifically, considering that the position accuracy of the color film exposure machine is ±3um, the maximum offset of the adjacent pixel electrode 5 pattern can be 6um to avoid excessive bending, which will cause a heavier color mixing effect, and too small bending, which will cause the dark area fold line to be insignificant.

[0148] In one possible implementation, see Figure 6A-6F , Figure 7 and Figure 8As shown in FIG. 5 , the number of the first branch groups 5121 and the number of the second branch groups 5122 connected to the same skeleton portion 511 are substantially the same. This is advantageous in simplifying the manufacturing process of the pixel electrode 5. Specifically, for example, Fig. 6F In the right sub-pixel electrode portion 51, the number of the first sub-group 5121 connected to the same skeleton portion 511 is 1, and the number of the second sub-group 5122 is 1; for another example, Figure 7 In the right sub-pixel electrode portion 51, the number of the first sub-group 5121 is 2, and the number of the second sub-group 5122 is 2; for another example, Figure 8 In the right sub-pixel electrode portion 51, the number of the first sub-groups 5121 is 4, and the number of the second sub-groups 5122 is 4. Of course, in a specific implementation, the number of the first sub-groups 5121 and the number of the second sub-groups 5122 connected to the same skeleton portion 511 may also be different, so that the dark area between adjacent pixel electrodes 5 can be further weakened.

[0149] In one possible implementation, see Figure 6A-6F , Figure 7 and Figure 8 As shown, the first branch groups 5121 of different sub-pixel electrode parts 51 in the same pixel electrode 5 are staggered in the extension direction Z parallel to the first branch group 5121; the second branch groups 5122 of different sub-pixel electrode parts 51 in the same pixel electrode 5 are staggered in the extension direction Z parallel to the first branch group 5121. Specifically, for example, Figure 8 In the figure, the second first branch group 5121 from top to bottom of the right sub-pixel electrode portion 51 in the right pixel electrode 5 is staggered with the second first branch group 5121 from top to bottom of the left sub-pixel electrode portion 51 in the right pixel electrode 5, that is, the starting position of the second first branch group 5121 from top to bottom of the right sub-pixel electrode portion 51 in the right pixel electrode 5 corresponds to the middle position of the second first branch group 5121 from top to bottom of the left sub-pixel electrode portion 51 in the right pixel electrode 5, as shown in FIG. Figure 8 As shown by the middle dotted line Z. In the disclosed embodiment, the first branch groups 5121 of different sub-pixel electrode parts 51 in the same pixel electrode 5 are staggered in the extension direction Z parallel to the first branch group 5121; the second branch groups 5122 of different sub-pixel electrode parts 51 in the same pixel electrode 5 are staggered in the extension direction parallel to the first branch group 5121, which can make the edge of the pixel electrode 5 asymmetric as a whole, and better weaken the dark area at the edge of the pixel electrode 5.

[0150] In one possible implementation, see Figure 6A-6F , Figure 7 and Figure 8As shown, each branch group 512 may include: a plurality of branches 5120 extending from the skeleton portion 511 to a side away from the second slit 50; within the same branch group 512, a third slit 500 is provided between adjacent branches 5120; and the outer edges of the plurality of branches 5120 of the same branch group 512 away from the second slit 50 are roughly flush.

[0151] In one possible implementation, see Figure 6A-6F , Figure 7 and Figure 8 As shown, in the same sub-pixel electrode portion 51, the outer edges of the branches 5120 of each first branch group 5121 are roughly flush; in the same sub-pixel electrode portion 51, the outer edges of the branches 5120 of each second branch group 5122 are roughly flush. In this way, it is helpful to simplify the manufacturing process of the pixel electrode 5. Of course, in the specific implementation, in the same sub-pixel electrode portion 51, the outer edges of the branches 5120 of each first branch group 5121 may not be flush; in the same sub-pixel electrode portion 51, the outer edges of the branches 5120 of each second branch group 5122 may not be flush, so that the dark area between adjacent pixel electrodes 5 can be further weakened.

[0152] In one possible implementation, see Figure 6A-6F , Figure 7 and Figure 8 As shown, the number of branches 5120 included in at least part of the first branch group 5121 is substantially the same as the number of branches 5120 included in at least part of the second branch group 5122. Specifically, for example, Figure 8 In the figure, the first second branch group 5122 from top to bottom of the right sub-pixel electrode portion 51 includes 4 branches 5120, and the second first branch group 5121 from top to bottom of the right sub-pixel electrode portion 51 includes 4 branches 5120, and the two are the same in number. In this way, it is helpful to simplify the manufacturing process of the pixel electrode 5. Of course, in the specific implementation, the number of branches 5120 included in the first branch group 5121 may be the same as or different from the number of branches 5120 included in the second branch group 5122, so that the dark area between adjacent pixel electrodes 5 can be further weakened.

[0153] In one possible implementation, see Figure 6A-6F , Figure 7 and Figure 8 As shown, the patterns of the outer edges of the branch groups 512 of adjacent pixel electrodes are complementary. Specifically, the first branch group 5121 of the pixel electrode 5 is arranged opposite to the second branch group 5122 of the adjacent pixel electrode 5. Specifically, for example, Figure 8In the figure, the first branch group 5121 of the sub-pixel electrode portion 51 on the left side of the right pixel electrode 5 is convex, and the second branch group 5122 of the sub-pixel electrode portion 51 on the right side of the left pixel electrode 5 is concave, so as to better weaken the dark area between adjacent pixel electrodes 5.

[0154] In one possible implementation, see Figure 6C As shown, the data line layer 2 further includes a first electrode 211 electrically connected to the data line 21, and a second electrode 212 separated from the first electrode 211; see Figure 6A-6F As shown, the pixel electrode 5 includes a first type of pixel electrode P1 and a second type of pixel electrode P2 alternately arranged along the first direction X, wherein the first type of pixel electrode P1 includes: a first adapter portion P11, and a first connecting portion P12; the first connecting portion P12 crosses the first connecting line 22 to connect the first adapter portion P11 and one of the sub-pixel electrode portions 51; the orthographic projection of the first adapter portion P11 on the substrate 1 and the orthographic projection of the second pole 212 on the substrate 1 have an overlapping area; the second type of pixel electrode P2 includes: a second adapter portion P21 directly connected to one of the sub-pixel electrode portions 51, and the orthographic projection of the second adapter portion P21 on the substrate 1 and the orthographic projection of the second pole 212 on the substrate 1 have an overlapping area; the second type of pixel electrode P2 also includes: a compensation portion P22 extending from the second adapter portion P21 along the first direction X away from the data line 21, and the orthographic projection of the compensation portion P22 on the substrate 1 overlaps with the orthographic projection of the first connecting line 22 on the substrate. In specific implementation, since large-size display products are difficult to charge, in order to reduce the number of source driver chip (Source IC) pins and reduce costs, when a dual gate design is adopted, the charging rate is lower and the picture quality is prone to poor. In conventional dual gate products, half of the pixel electrodes 5 are bridged by the vertical first connecting line 22, while the other half of the pixel electrodes 5 do not. In order to obtain better picture quality, the smaller the design difference between different pixel electrodes 5, the better the picture uniformity. Furthermore, in the embodiment of the present disclosure, the second type of pixel electrode P2 also includes a compensation part P22, and the positive projection of the compensation part P22 on the substrate 1 overlaps with the positive projection of the first connecting line 22 on the substrate, that is, a capacitance compensation method is adopted, and for the second type of pixel electrode P2 without bridge, an additional bridge path compensation part P22 (i.e. Figure 6C The width of the compensation portion P22 and the distance from other structures are equal to the first connection portion P12 (i.e. Figure 6C The dotted circle Q1 ensures that the capacitance difference between each pixel electrode 5 and the common electrode strip 3, the gate line 42 and other signals is minimized.

[0155] Specifically, in a possible implementation, the first type of pixel electrode P1 may be, for example, a pixel electrode 5 corresponding to a pixel emitting red light, and the second type of pixel electrode P2 may be a pixel electrode 5 corresponding to a pixel emitting green light.

[0156] In one possible implementation, see Figure 6A-6F , Figure 7 and Figure 8 As shown, the overlapping area formed by the orthographic projection of the compensation portion P22 on the substrate 1 and the orthographic projection of the first connecting line 22 on the substrate 1 is substantially equal to the overlapping area formed by the orthographic projection of the first connecting portion P12 on the substrate 1 and the orthographic projection of the first connecting line 22 on the substrate 1 .

[0157] In one possible implementation, see Figure 6A-6F , Figure 7 and Figure 8 As shown, the orthographic projection shape of the compensation portion P22 on the substrate 1 is similar to the orthographic projection shape of the first connection portion P12 on the substrate 1 .

[0158] In one possible implementation, see Figure 6A-6F , Figure 7 and Figure 8 As shown, the compensation portion P22 and the second transfer portion P21 are located in the same layer, thereby simplifying the manufacturing process of the display substrate.

[0159] In one possible implementation, see Figure 6A-6F , Figure 7 and Figure 8 As shown, the sub-pixel electrode portion 51, the bridge portion 53, the first transfer portion P11, and the first connection portion P12 of the same pixel electrode 5 are located in the same layer, so as to further simplify the manufacturing process of the display substrate.

[0160] In a conventional pixel electrode structure, a circle around the edge of the pixel electrode is a closed electrode skeleton (for transmitting signals), and a plurality of transverse slits are provided inside the pixel electrode, and liquid crystals are arranged along the slits; however, when the pixel electrode reaches a circle around the edge, the liquid crystals at the edge of the pixel electrode are arranged disorderly due to the structure of the electrode skeleton, forming a display dark area; therefore, a large display dark area exists between adjacent sub-pixels, which is not conducive to eliminating moiré patterns; the above-mentioned display substrate provided by the embodiment of the present disclosure, by setting the pixel electrode to include: two sub-pixel electrode portions 51, each sub-pixel electrode portion 51 includes a skeleton portion 511 and a comb-like structure connected to one side of the skeleton portion 511, and the comb-like structure is composed of a plurality of branches 5120 and a plurality of third slits 500 arranged alternately, so that there is no electrode skeleton at the edge of the pixel electrode structure provided by the present disclosure, but the electrode skeleton is moved to the inside of the sub-pixel, that is, the edge of the pixel electrode structure is an open comb-like structure, so that the liquid crystal at the edge of the pixel electrode can be arranged in an orderly manner, so that the display dark area between the pixel electrodes can be reduced, and when the display substrate provided by the embodiment of the present disclosure is applied to a 3D display device, the moiré patterns can be improved and the display effect can be improved.

[0161] In a specific implementation, in the above-mentioned display panel provided in the embodiment of the present disclosure, the shape of the skeleton portion 511 is a zigzag shape. The zigzag-shaped skeleton portion 511 can avoid the moiré caused by interference with the grating of the 3D display device, and can further eliminate the moiré in the display image, thereby improving the display effect.

[0162] In specific implementation, in the above display panel provided in the embodiment of the present disclosure, combined with Fig. 6F As shown, in each sub-pixel electrode portion 51, the skeleton portion 511 can be divided into a first sub-skeleton portion 5111 and a second sub-skeleton portion 5112 along the bending point A; in the same pixel electrode 5, the branches 5120 on both sides of the two first sub-skeleton portions 5111 extending in the same direction correspond to each other and are located on the same straight line, and the branches 5120 on both sides of the two second sub-skeleton portions 5112 extending in the same direction correspond to each other and are located on the same straight line. This is conducive to the regular arrangement of liquid crystal molecules and improves the display effect.

[0163] In specific implementation, in the above display panel provided in the embodiment of the present disclosure, combined with Fig. 6F As shown, the branches 5120 connected to the first sub-framework 5111 are substantially parallel, and the branches 5120 connected to the second sub-framework 5112 are substantially parallel. In this way, when the liquid crystal display panel is displaying, all liquid crystal molecules can be arranged regularly to improve the display effect.

[0164] In a specific implementation, in the above display panel provided in the embodiment of the present disclosure, if Fig. 6FAs shown, the branch 5120 connected to the second sub-frame portion 5112 has a first inclination angle α1 with the first direction X, and the branch 5120 connected to the first sub-frame portion 5111 has a second inclination angle α2 with the first direction X, and the first inclination angle α1 and the second inclination angle α2 are complementary. The same pixel electrode 5 has branches 5120 with complementary inclination angles. Under this arrangement, the brightness of the same pixel electrode 5 can be complementary, thereby avoiding the appearance of horizontal stripes.

[0165] In a specific implementation, in the above-mentioned display substrate provided in the embodiment of the present disclosure, if Fig. 6F As shown, the pixel electrode 5 has a center line L extending along the first direction X, and the bending point A is approximately located on the center line L. Due to the influence of the manufacturing process, the position of the bending point A and the center line L may have a certain error. This structure can improve the moiré defect to the greatest extent.

[0166] In a specific implementation, in the above-mentioned display substrate provided in the embodiment of the present disclosure, if Fig. 6F As shown, the skeleton part 511 has a bending angle β at the position corresponding to the bending point A. On one side of the bending angle β and at a position close to the bending point A (at the elliptical dotted frame T1), the first sub-skeleton part 5111 and the second sub-skeleton part 5112 are electrically connected to the corresponding multiple branches 5120; on the opposite side of the bending angle β and at the edges on both sides away from the bending point A (at the elliptical dotted frame T2), the first sub-skeleton part 5111 is electrically connected to the corresponding multiple branches 5120, and the second sub-skeleton part 511 is electrically connected to the corresponding multiple branches 5120; the ends of the branches 5120 at the remaining positions away from the skeleton part 511 are independent of each other, that is, the edge of the pixel electrode structure is set to an open comb structure, so that the liquid crystal at the edge of the pixel electrode can be arranged in an orderly manner, the dark area between the sub-pixels can be reduced, the moiré pattern can be improved, and the display effect can be improved. Specifically, the bending angle β can be greater than 90° and less than 180°. Exemplarily, the bending angle β can be set to 114°. Of course, in practical applications, the specific value of β can be designed according to the needs of the practical application and is not limited here.

[0167] It should be noted that Figure 3A-Figure 8 The example shown is a dual-gate structure of the display panel. Figure 3E and Fig. 6AAs shown, the gate line 42 may include a first gate line 421 and a second gate line 422, and the orthographic projections of the first gate line 421 and the second gate line 422 on the substrate 1 are located at the gap between the orthographic projections of the two adjacent rows of pixel electrodes 5 on the substrate 1. In addition, the two gate lines (the first gate line 421 and the second gate line 422) corresponding to the same row of pixel electrodes 5 are respectively located on both sides of the corresponding row of pixel electrodes 5. For example, the first gate line 421 of the two gate lines corresponding to the same row of pixel electrodes 5 is electrically connected to the thin film transistors in the odd-numbered columns of the row, and the other gate line (such as the second gate line 422) is electrically connected to the thin film transistors in the even-numbered columns of the row. The gate line (such as the first gate line 421) electrically connected to the thin film transistors in the odd-numbered columns of the row can be arranged above the row, and the gate line (such as the second gate line 422) electrically connected to the thin film transistors in the even-numbered columns of the row can be arranged below the row.

[0168] In a possible implementation manner, the display substrate provided in the embodiment of the present disclosure may also be a single-gate structure. Specifically, Figure 9A-9C As shown, Fig.9A is a schematic diagram of a stack including a common electrode layer, a data line layer, a gate layer, and a pixel electrode layer. Fig. 9B is a schematic diagram of a stack including a common electrode layer, a data line layer and a gate layer, Fig. 9C for Fig. 9B Schematic diagram of the film layer of a single gate layer, the gate line 42 extends along the row direction of the pixel electrodes 5, and one row of pixel electrodes 5 corresponds to one gate line 42.

[0169] Based on the same inventive concept, an embodiment of the present disclosure further provides a display panel, which includes a display substrate provided by the embodiment of the present disclosure.

[0170] In a possible implementation manner, the display panel further includes an opposing substrate disposed opposite to the display substrate; the opposing substrate includes a black matrix. Figure 6B as well as Figure 10G As shown, the black matrix includes a first black matrix portion 7 arranged corresponding to the first slit 30 area, the orthographic projection of the first black matrix portion 7 on the substrate 1 covers the orthographic projection of the first slit 30 on the substrate 1, and the outer edge of the first black matrix portion 7 is roughly flush with the outer edge of the shading strip 43 away from the first slit 30.

[0171] In one possible implementation, combining Figure 6B As shown, the first black matrix portion 7 has a first sub-black matrix portion 71, and a second sub-black matrix portion 72 located on both sides of the first sub-black matrix portion 71, wherein the orthographic projection of the first sub-black matrix portion 71 on the substrate 1 coincides with the orthographic projection of the first slit 30 on the substrate 1, and the orthographic projection of the second sub-black matrix portion 72 on the substrate 1 coincides with the orthographic projection of the shading strip 43 on the substrate 1.

[0172] Specific, combined Figure 6B and Figure 12G As shown, Figure 6B It can be a cross-sectional schematic diagram at the location of the data line 21, Figure 12G It can be a cross-sectional schematic diagram of the first connection line 22, and the line width d2 of the first connection line 22 can be equal to the line width d1 of the data line 21, or it can be less than the line width d1 of the data line 21; at the same time, the spacing a2' between the first connection line 22 and the second slit 50 can be equal to the spacing a2 between the data line 21 and the second slit 50, or it can be less than the spacing a2 between the data line 21 and the second slit 50. In some embodiments, the line width d2 of the first connection line 22 is less than the line width d1 of the data line 21, and / or the spacing a2' between the first connection line 22 and the second slit 50 is less than the spacing a2 between the data line 21 and the second slit 50, which can further increase the aperture ratio and transmittance. Specifically, the line width of the data line 21 can be 5.5μm to 9.5μm, specifically, for example, it can be 7.5μm; the line width of the first connection line 22 can be 2μm to 8.5μm, specifically, for example, it can be 3μm or 5μm, 7.5um.

[0173] Specifically, the distance a2 ′ between the first connection line 22 and the second slit 50 may be 2.5-5.5 μm, such as 3 μm or 5 μm, and the distance a2 between the data line 21 and the second slit 50 may be 4.5-5.5 μm, such as 5 μm.

[0174] Of course, the difference between the line width d1 of the data line 21 and the line width d2 of the first connection line 22 should not be too large, so that the entire pixel area can maintain uniform display on the basis of improving the aperture ratio and transmittance, and avoid the occurrence of dark lines or horizontal lines. In some embodiments, the difference between the line width d1 of the data line 21 and the line width d2 of the first connection line 22 is less than 6um.

[0175] In a possible implementation manner, the width of the first sub-black matrix portion 7 covering the first connecting line 21 in the orthographic projection of the substrate 1 is less than or equal to the width of the first sub-black matrix portion 7 covering the data line 22. Figure 6B and Figure 12G As shown, the line width a6 of the first black matrix portion 7 corresponding to the data line 21 may be greater than or equal to the line width a6' of the first black matrix portion 7 corresponding to the first connection line 21. Specifically, for example, the line width a6 of the first black matrix portion 7 corresponding to the data line 21 may be 23-25 ​​μm, and the line width a6' of the first black matrix portion 7 corresponding to the first connection line 21 may be 17-18.5 μm.

[0176] Specific, combined Figure 6BAs shown, in the embodiment of the present disclosure, in the extension direction perpendicular to the first slit 30, there can be a first spacing a1 between the data line 21 and the first slit 30 to ensure that the data line 21 can still be located in the area where the first slit 30 is located in the case of process errors. Specifically, the size of the first spacing a1 can be determined according to the manufacturing process accuracy in the actual process. For example, the first spacing a1 can be specifically 3μm~4μm; specifically, the first spacing a1 can be specifically 3.5μm.

[0177] Specific, combined Figure 6B As shown, in the extending direction perpendicular to the first slit 30, the width a3 of the light shielding strip 43 may be 4 μm to 7 μm, and specifically, the width a3 of the light shielding strip 43 may be 4 μm, 5 μm, 6 μm or 7 μm. Specifically, the width a3 of the light shielding strip 43 may be 5 μm.

[0178] Specific, combined Figure 6B As shown, in the extension direction perpendicular to the first slit 30, there may be a second spacing a2 between the data line 21 and the second slit 50. Specifically, the second spacing a2 may be 3μm to 7μm; specifically, the second spacing a2 may be 3μm, 4μm, 5μm, 6μm, or 7μm.

[0179] Specific, combined Figure 6B As shown, in the extension direction perpendicular to the branch 5120, the width a4 of the branch 5120 may be 2 μm to 4 μm, specifically, the width a4 of the branch 5120 may be 2.2 μm; in the extension direction perpendicular to the branch 5120, the width a5 of the third slit 500 may be 4 μm to 5 μm, specifically, the width a5 of the third slit 500 may be 4.4 μm.

[0180] Specific, combined Figure 6B As shown, in the extending direction perpendicular to the first slit 30, the width a6 of the first black matrix portion 7 may be 20 μm to 28 μm. Specifically, the width a6 of the first black matrix portion 7 may be 20 μm, 21 μm, 22 μm, 23 μm, 24 μm, 25 μm, 26 μm, 27 μm or 28 μm. Specifically, the width a6 of the first black matrix portion 7 may be 24.5 μm.

[0181] Liquid Crystal Display (LCD) panels have the characteristics of being thin and light, power-saving, and radiation-free, and are widely used. The working principle of the LCD panel is to change the arrangement state of the liquid crystal molecules in the liquid crystal layer by changing the voltage difference across the liquid crystal layer, so as to change the light transmittance of the liquid crystal layer to display images. In specific implementation, the display panel in the embodiment of the present disclosure may be a liquid crystal display panel.

[0182] In order to more clearly understand the display panel structure provided by the embodiment of the present disclosure, the process of manufacturing different display panel structures is described as follows:

[0183] Embodiment 1: For example, the display panel has a dual-gate structure, and the manufacturing process may be specifically as follows:

[0184] Step 1: forming a common electrode layer on one side of the substrate 1, such as Fig. 10A As shown, the common electrode layer includes: a plurality of common electrode strips 3, the plurality of common electrode strips 3 extend along a first direction X and are arranged along a second direction Y, the common electrode strips 3 include a plurality of common electrode blocks 31 sequentially arranged along the first direction X, and a first slit 30 is provided between adjacent common electrode blocks 31;

[0185] Step 2: forming a gate layer on the side of the common electrode layer facing away from the substrate 1, such as Fig. 10B As shown, the gate layer includes a plurality of gate lines 42 extending along the second direction Y, and the gate lines 42 may include a first gate line 421 and a second gate line 422, and the orthographic projections of the first gate line 421 and the second gate line 422 on the substrate 1 are located at the gap between the orthographic projections of two adjacent rows of pixel electrodes 5 on the substrate 1; the gate layer also includes a plurality of second connecting lines 41 extending along the first direction X, and each common electrode block 31 of the same common electrode strip 3 is electrically connected to the same second connecting line 41; the gate layer also includes a shading strip 43 extending in the main direction along the second direction Y, and the orthographic projection of the shading strip 43 on the substrate 1 covers the area of ​​the common electrode block 31 close to the first slit 30;

[0186] Step 3: forming an active layer 8 on the side of the gate layer away from the common electrode layer, such as Fig. 10C As shown;

[0187] Step 4: forming a data line layer on the side of the active layer 8 away from the gate layer, such as Fig. 10D As shown, the data line layer includes a plurality of data lines 21 extending along the second direction Y, and first connection lines 22. In the first direction X, the data lines 21 and the first connection lines 22 are arranged alternately;

[0188] Step 5: forming a pixel electrode layer on the side of the data line layer away from the active layer, such as Fig.10E As shown, the pixel electrode layer includes a plurality of pixel electrodes 5; each pixel electrode 5 includes: two sub-pixel electrode portions 51 arranged along the first direction X, and a bridge portion 53 connecting the two sub-pixel electrode portions 51; and a second slit 50 is provided between the two sub-pixel electrode portions 51;

[0189] Step 6: Form a second insulating layer 62 on the side of the pixel electrode layer away from the data layer, and combine Figure 6B As shown;

[0190] Step 7: forming a counter substrate on the side of the second insulating layer 62 away from the pixel electrode layer, wherein the counter substrate includes a black matrix, such as Fig.10F and 10G As shown, Figure 10G Schematic diagram of a single film layer of a black matrix, the black matrix includes a first black matrix portion 7 arranged corresponding to the first slit 30 area, and the orthographic projection of the first black matrix portion 7 on the substrate 1 covers the orthographic projection of the first slit 30 on the substrate 1.

[0191] Embodiment 2: For another example, taking the display panel as a single-grid structure, the manufacturing process may be as follows:

[0192] Step 1: forming a common electrode layer on one side of the substrate 1, such as Fig.11A As shown, the common electrode layer includes: a plurality of common electrode strips 3, the plurality of common electrode strips 3 extend along a first direction X and are arranged along a second direction Y, the common electrode strips 3 include a plurality of common electrode blocks 31 sequentially arranged along the first direction X, and a first slit 30 is provided between adjacent common electrode blocks 31;

[0193] Step 2: forming a gate layer on the side of the common electrode layer facing away from the substrate 1, such as Fig. 11B As shown, the gate layer includes a plurality of gate lines 42 extending along the second direction Y; the gate layer also includes a plurality of second connecting lines 41 extending along the first direction X, and each common electrode block 31 of the same common electrode strip 3 is electrically connected to the same second connecting line 41. Specifically, the second connecting line 41 can be located below the connected common electrode strip 3; the gate layer also includes a shading strip 43 extending in the main direction along the second direction Y, and the orthographic projection of the shading strip 43 on the substrate 1 covers the area of ​​the common electrode block 31 close to the first slit 30;

[0194] Step 3: forming an active layer 8 on the side of the gate layer away from the common electrode layer, such as Fig. 11C As shown;

[0195] Step 4: forming a data line layer on the side of the active layer 8 away from the gate layer, such as Fig.11D As shown, the data line layer includes a plurality of data lines 21 that extend along the second direction Y;

[0196] Step 5: forming a pixel electrode layer on the side of the data line layer away from the active layer, such as Fig.11E As shown, the pixel electrode layer includes a plurality of pixel electrodes 5; each pixel electrode 5 includes: two sub-pixel electrode portions 51 arranged along the first direction X, and a bridge portion 53 connecting the two sub-pixel electrode portions 51; and a second slit 50 is provided between the two sub-pixel electrode portions 51;

[0197] Step 6: Form a second insulating layer 62 on the side of the pixel electrode layer away from the data layer, and combine Figure 6B As shown;

[0198] Step 7: forming a counter substrate on the side of the second insulating layer 62 away from the pixel electrode layer, wherein the counter substrate includes a black matrix, such as Fig.11F and 11G As shown, Fig.11G Schematic diagram of a single film layer of a black matrix, the black matrix includes a first black matrix portion 7 arranged corresponding to the first slit 30 area, and the orthographic projection of the first black matrix portion 7 on the substrate 1 covers the orthographic projection of the first slit 30 on the substrate 1.

[0199] Embodiment 3: For another example, taking the display panel as an example, only the first slit 30 is provided at the location of the data line 21, the manufacturing process may be specifically as follows:

[0200] Step 1: forming a common electrode layer on one side of the substrate 1, such as Fig. 12A As shown, the common electrode layer includes: a plurality of common electrode strips 3, the plurality of common electrode strips 3 extend along a first direction X and are arranged along a second direction Y, the common electrode strips 3 include a plurality of common electrode blocks 31 sequentially arranged along the first direction X, and a first slit 30 is provided between adjacent common electrode blocks 31; the common electrode blocks 31 are provided with the first slit 30 only at the data lines 21;

[0201] Step 2: forming a gate layer on the side of the common electrode layer facing away from the substrate 1, such as Fig. 12B As shown, the gate layer includes a plurality of gate lines 42 extending along the second direction Y, and the gate lines 42 may include a first gate line 421 and a second gate line 422, and the orthographic projections of the first gate line 421 and the second gate line 422 on the substrate 1 are located at the gap between the orthographic projections of two adjacent rows of pixel electrodes 5 on the substrate 1; the gate layer also includes a plurality of second connecting lines 41 extending along the first direction X, and each common electrode block 31 of the same common electrode strip 3 is electrically connected to the same second connecting line 41; the gate layer also includes a shading strip 43 extending in the main direction along the second direction Y, and the orthographic projection of the shading strip 43 on the substrate 1 covers the area of ​​the common electrode block 31 close to the first slit 30;

[0202] Step 3: forming an active layer 8 on the side of the gate layer away from the common electrode layer, such as Fig. 12C As shown;

[0203] Step 4: forming a data line layer on the side of the active layer 8 away from the gate layer, such as Fig.12D As shown, the data line layer includes a plurality of data lines 21 extending along the second direction Y, and first connection lines 22. In the first direction X, the data lines 21 and the first connection lines 22 are arranged alternately;

[0204] Step 5: forming a pixel electrode layer on the side of the data line layer away from the active layer, such as Fig.12EAs shown, the pixel electrode layer includes a plurality of pixel electrodes 5; each pixel electrode 5 includes: two sub-pixel electrode portions 51 arranged along a first direction X, and a bridge portion 52 connecting the two sub-pixel electrode portions 51; and a second slit 50 is provided between the two sub-pixel electrode portions 51;

[0205] Step 6: Form a second insulating layer 62 on the side of the pixel electrode layer away from the data layer, and combine Figure 6B As shown;

[0206] Step 7: forming a counter substrate on the side of the second insulating layer 62 away from the pixel electrode layer, wherein the counter substrate includes a black matrix, such as Fig.12F and 12G As shown, Fig.12H Schematic diagram of a single film layer of a black matrix, the black matrix includes a first black matrix portion 7 arranged corresponding to the first slit 30 area, and the orthographic projection of the first black matrix portion 7 on the substrate 1 covers the orthographic projection of the first slit 30 on the substrate 1.

[0207] Based on the same inventive concept, an embodiment of the present disclosure further provides a display device, which includes the display panel provided by the embodiment of the present disclosure.

[0208] In the embodiment of the present disclosure, the common electrode strip 3 includes a plurality of common electrode blocks 31 arranged in sequence along a first direction X, and a first slit 30 is provided between adjacent common electrode blocks 31. The orthographic projection of the signal line 2 on the substrate 1 is located within the orthographic projection of the first slit 30 on the substrate 1. By designing the common electrode strip 3 in blocks, each common electrode block 31 is arranged with the bent signal line 2 as a dividing line to avoid large-area vertical overlap between the common electrode strip 3 and the signal line 2, thereby reducing the coupling capacitance between the common electrode strip 3 and the signal line 2. Moreover, compared with the related art in which a thicker organic film is provided to reduce the coupling capacitance between the common electrode strip 3 and the signal line 2, the embodiment of the present disclosure can be applied to large-size display products, has a lower production cost, and is conducive to the mass production application of 3D display products.

[0209] The display device provided in the embodiments of the present disclosure is any product or component with a display function, such as a mobile phone, a tablet computer, a television, a display, a laptop computer, a digital photo frame, a navigator, etc. Other essential components of the display device are well understood by those skilled in the art, and are not described in detail here, nor should they be used as limitations to the present disclosure.

[0210] Although the preferred embodiments of the present invention have been described, those skilled in the art may make other changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the present invention.

[0211] Obviously, those skilled in the art can make various changes and modifications to the embodiments of the present invention without departing from the spirit and scope of the embodiments of the present invention. Thus, if these modifications and variations of the embodiments of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include these modifications and variations.

Claims

1. A display substrate, wherein: include: substrate; A plurality of signal lines, wherein the plurality of signal lines are located on one side of the substrate and arranged along a first direction, and the orthographic projection shape of the signal lines on the substrate is a folded line; A plurality of common electrode strips, wherein the plurality of common electrode strips and the signal line are located on the same side of the substrate and are insulated from each other; the plurality of common electrode strips extend along the first direction and are arranged along the second direction, the common electrode strips include a plurality of common electrode blocks arranged in sequence along the first direction, a first slit is provided between adjacent common electrode blocks, and at least a portion of the signal line's orthographic projection on the substrate is located within the orthographic projection of the first slit on the substrate; A data line layer, located on a side of the common electrode strip away from the substrate; A plurality of pixel electrodes are located on a side of the data line layer away from the substrate; Wherein, the pixel electrode comprises: two sub-pixel electrode parts arranged along the first direction, and a bridge part connecting the two sub-pixel electrode parts; a second slit is provided between the two sub-pixel electrode parts; The orthographic projection of the signal line on the substrate is located within the orthographic projection of the second slit on the substrate.

2. The display substrate according to claim 1, wherein: The signal line includes a first signal line portion and a second signal line portion; the orthographic projection of the first signal line portion on the substrate is located in the region where the orthographic projection of the first slit on the substrate is located, and the orthographic projection of the second signal line portion on the substrate is located in the gap region between two adjacent common electrode strips; The orthographic projection shape of the first signal line portion on the substrate is a zigzag shape; The orthographic projection of the first slit on the substrate has a shape similar to the orthographic projection of the first signal line portion on the substrate.

3. The display substrate according to claim 2, wherein: In a direction perpendicular to an extension direction of the first signal line portion, a width of the first slit is greater than a width of the first signal line portion.

4. The display substrate according to claim 1, wherein: The data line layer includes a plurality of data lines extending along the second direction; The signal line includes the data line.

5. The display substrate according to claim 4, wherein: The data line layer further comprises a plurality of first connection lines extending along the second direction, and two adjacent common electrode strips are electrically connected via the first connection lines; The signal line further includes the first connecting line.

6. The display substrate according to claim 5, wherein: The common electrode strip is provided with the first slit only in the area where the data line is located.

7. The display substrate according to claim 5, wherein: The common electrode strip is provided with the first slit in the area where the data line and the first connecting line are located.

8. The display substrate according to claim 5, wherein: In the first direction, the data lines and the first connection lines are arranged alternately.

9. The display substrate according to any one of claims 4 to 8, wherein: The display substrate further includes a plurality of second connection lines extending along the first direction, and each of the common electrode blocks of the same common electrode bar is electrically connected to the same second connection line.

10. The display substrate according to claim 9, wherein: The display substrate further comprises a gate layer located between the common electrode layer and the data line layer, wherein the gate layer comprises a plurality of gate lines extending along the second direction; The second connection line is located in the gate layer.

11. The display substrate according to claim 10, wherein: The display substrate further comprises a light shielding strip located on a side of the common electrode strip away from the substrate, wherein the light shielding strip has an orthographic projection on the substrate covering a region of the common electrode block close to the first slit.

12. The display substrate according to claim 11, wherein: The orthographic projection of the light shielding strip on the substrate and the orthographic projection of the first slit on the substrate do not overlap each other.

13. The display substrate according to claim 12, wherein: The orthographic projection shape of the light shielding strip on the substrate is similar to the orthographic projection shape of the first slit on the substrate.

14. The display substrate according to claim 13, wherein: The light shielding strip is located on the gate layer.

15. The display substrate according to claim 1, wherein: The orthographic projection of the first slit on the substrate is located within the orthographic projection of the second slit on the substrate.

16. The display substrate according to claim 15, wherein: The sub-pixel electrode portion includes a skeleton portion and a plurality of branch groups. The skeleton portion is in a zigzag shape with a main direction extending along the second direction. The plurality of branch groups extend from the skeleton portion to a side away from the second slit.

17. The display substrate according to claim 16, wherein: The multiple branch groups include a first branch group and a second branch group; among the multiple branch groups connected to the same skeleton part, the first branch group and the second branch group are arranged alternately, and the outer edge of the first branch group is convex relative to the outer edge of the second branch group.

18. The display substrate according to claim 17, wherein: The ratio range of the difference in the convex dimensions of each of the first branch groups relative to each of the second branch groups to any one of them is less than 10%.

19. The display substrate according to claim 17, wherein: The protruding dimension of each of the first branch groups relative to each of the second branch groups is 2-5 times the spacing between adjacent pixel electrodes.

20. The display substrate according to any one of claims 16 to 19, wherein: The number of the first branch groups and the number of the second branch groups connected to the same skeleton portion are both 1, or, The number of the first branch groups and the number of the second branch groups connected to the same skeleton portion are both 2; or, The number of the first branch groups and the number of the second branch groups connected to the same skeleton portion are both four.

21. The display substrate according to any one of claims 16 to 19, wherein: The first branch groups of different sub-pixel electrode parts in the same pixel electrode are staggered and distributed in a direction parallel to the extension of the first branch groups; the second branch groups of different sub-pixel electrode parts in the same pixel electrode are staggered and distributed in a direction parallel to the extension of the first branch groups.

22. The display substrate according to claim 21, wherein: The branch group includes: a plurality of branches extending from the frame portion to a side away from the second slit; within the same branch group, a third slit is provided between adjacent branches; The outer edges of the plurality of branches in the same branch group away from the second slit are substantially flush.

23. The display substrate according to claim 22, wherein: In the same sub-pixel electrode portion, outer edges of the branches of each of the first branch groups are substantially flush with each other; in the same sub-pixel electrode portion, outer edges of the branches of each of the second branch groups are substantially flush with each other.

24. The display substrate according to claim 23, wherein: At least part of the first branch group includes four of the branches, and at least part of the second branch group includes four of the branches.

25. The display substrate according to claim 22, wherein: The outer edge patterns of the branch groups of adjacent pixel electrodes are complementary.

26. The display substrate according to claim 25, wherein: The first branch group of the pixel electrodes is arranged opposite to the second branch group of the adjacent pixel electrodes.

27. The display substrate according to claim 26, wherein: The line width of the first connecting line is smaller than or equal to the line width of the data line; the distance between the first connecting line and the second slit is smaller than or equal to the distance between the data line and the second slit.

28. The display substrate according to claim 27, wherein: The data line layer further includes a first electrode electrically connected to the data line, and a second electrode spaced apart from the first electrode; The pixel electrode includes a first type of pixel electrode and a second type of pixel electrode alternately arranged along the first direction, wherein the first type of pixel electrode includes: a first transition portion, and a first connecting portion; the first connecting portion connects the first transition portion and one of the sub-pixel electrode portions across the first connecting line; the orthographic projection of the first transition portion on the substrate and the orthographic projection of the second pole on the substrate have an overlapping area; the second type of pixel electrode includes: a second transition portion directly connected to one of the sub-pixel electrode portions, and the orthographic projection of the second transition portion on the substrate and the orthographic projection of the second pole on the substrate have an overlapping area.

29. The display substrate according to claim 28, wherein: The second type pixel electrode further includes: a compensation portion extending from the second transfer portion along the first direction away from the data line, wherein an orthographic projection of the compensation portion on the substrate overlaps an orthographic projection of the first connection line on the substrate.

30. The display substrate according to claim 28, wherein: The orthographic projection shape of the compensation portion on the substrate is similar to the orthographic projection shape of the first connecting portion on the substrate.

31. The display substrate according to claim 30, wherein: The compensation portion and the second transfer portion are located on the same layer.

32. The display substrate according to claim 31, wherein: The sub-pixel electrode portion, the bridge portion, the first transfer portion, and the first connection portion of the same pixel electrode are located in the same layer.

33. A display panel, wherein: Comprising a display substrate as described in any one of claims 1-32.

34. The display panel according to claim 33, wherein: The display panel further includes an opposing substrate disposed opposite to the display substrate; The opposite substrate includes a black matrix, the black matrix includes a first black matrix portion arranged corresponding to the first slit area, and the orthographic projection of the first black matrix portion on the substrate covers the orthographic projection of the first slit on the substrate.

35. The display panel according to claim 34, wherein: The first black matrix portion has a first sub-black matrix portion and a second sub-black matrix portion located on both sides of the first sub-black matrix portion; wherein the orthographic projection of the first sub-black matrix portion on the substrate coincides with the orthographic projection of the first slit on the substrate, and the orthographic projection of the second sub-black matrix portion on the substrate coincides with the orthographic projection of the shading strip on the substrate. 36 . The display panel as claimed in claim 35 , wherein a width of the first sub-black matrix portion covering the first connecting line in an orthographic projection of the substrate is less than or equal to a width of the first sub-black matrix portion covering the data line.

37. A display device, wherein: Comprising a display panel as described in any one of claims 33-36.

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