Uninterruptible power supply device

Abstract

The main controller (22) includes a first programmable device (40), a device (42), and a first selector (44). Each controller (66) includes a second programmable device (50) and a second selector (52). The second programmable device (50) includes a memory (502) and a processor (500). The first selector (44) connects the first programmable device (40) to the serial communication line (15) while the uninterruptible power supply unit is operating, and connects the device (42) to the serial communication line in response to the device (42) receiving an execution instruction for an update process. The second selector (52) connects the processor (500) to the serial communication line (15) while the uninterruptible power supply unit is operating, and connects the memory (502) to the serial communication line (15) in response to the processor (500) receiving an execution instruction from the first programmable device (40) while the uninterruptible power supply unit is operating.

Description

Technical Field

[0001] This disclosure relates to uninterruptible power supply devices. Background Technology

[0002] Japanese Patent Application Publication No. 2018-182872 (Patent Document 1) discloses a power supply system comprising: multiple power supply devices each having a slave control unit, and a master control unit that provides instructions to the slave control circuits of each of the multiple power supply devices. In this power supply system, each slave control unit is configured as a programmable device, including a high-speed serial communication unit connected to the master control unit. Each slave control unit receives instruction values, etc., from the master control unit via the high-speed serial communication unit and transmits the operating status of the power supply device to the master control unit.

[0003] Existing technical documents

[0004] Patent documents

[0005] Patent Document 1: Japanese Patent Application Publication No. 2018-182872 Summary of the Invention

[0006] The problem that the invention aims to solve

[0007] In the aforementioned power supply system, by employing serial communication in the data exchange between the master control device and multiple slave control devices, the number of wiring connections between the master control device and multiple slave control devices can be reduced.

[0008] However, when updating the software (program) of the programmable device installed on each slave control device, it is necessary to connect each slave control device to the computer via a programming cable and download the update data from the computer to the programmable device.

[0009] Therefore, in power supply devices with large-scale and complex structures, the configuration of the control board carrying programmable devices needs to be designed to facilitate the execution of update processes. Furthermore, as the number of power supply devices mounted in uninterruptible power supplies increases, update processes can become extremely time-consuming and labor-intensive.

[0010] Therefore, the main objective of this disclosure is to provide an uninterruptible power supply device capable of efficiently performing program updates with a simplified structure.

[0011] Methods for solving problems

[0012] One aspect of this disclosure provides an uninterruptible power supply (UPS) device comprising multiple modules, a main controller, multiple controllers, and a serial communication line. The main controller includes a first programmable device that controls the multiple modules. Each of the multiple controllers includes a second programmable device that drives the multiple modules respectively through communication with the main controller. The serial communication line provides a communication connection between the main controller and the multiple controllers. The main controller also includes a device and a first selector. The device performs update processes for both the first and second programmable devices. The first selector connects the first programmable device and one of the devices to the serial communication line. The second programmable device includes a memory storing a program, and a processor that drives the corresponding module by executing the program stored in the memory. Each of the multiple controllers also includes a second selector. The second selector connects the processor and the memory to the serial communication line. The first selector connects the first programmable device to the serial communication line when the UPS is operating. The first selector connects the device to the serial communication line in response to the device receiving an execution instruction for update processing. The second selector connects the processor to the serial communication line when the UPS is operating. In response to the processor receiving an execution instruction from the first programmable device during the operation of the uninterruptible power supply, the second selector connects the memory to the serial communication line.

[0013] Invention Effects

[0014] According to this disclosure, an uninterruptible power supply device can be provided that can efficiently perform program updates with a simplified structure. Attached Figure Description

[0015] Figure 1 This is a circuit block diagram showing the structure of the uninterruptible power supply device according to Embodiment 1.

[0016] Figure 2 This is a block diagram showing the structure of the main controller and gate drivers.

[0017] Figure 3 This is a diagram illustrating bidirectional communication under normal communication mode.

[0018] Figure 4 This is a diagram illustrating bidirectional communication in update mode.

[0019] Figure 5 This is a flowchart illustrating the steps involved in processing a programmable device that updates the main controller and gate drivers.

[0020] Figure 6 This is a circuit block diagram showing the structure of the uninterruptible power supply device according to Embodiment 2.

[0021] Figure 7 It means Figure 6 The circuit block diagram shown illustrates the structure of the bypass module and the power module.

[0022] Figure 8 It is a block diagram representing the structure of the main controller and the controller.

[0023] Figure 9 This is a diagram illustrating bidirectional communication under normal communication mode.

[0024] Figure 10 This is a diagram illustrating bidirectional communication in update mode. Detailed Implementation

[0025] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. Furthermore, the same or equivalent parts in the drawings will be labeled with the same reference numerals, and their descriptions will generally not be repeated.

[0026] [Implementation Method 1]

[0027] Figure 1 This is a circuit block diagram illustrating the structure of the uninterruptible power supply (UPS) device according to Embodiment 1. The UPS device 100 of Embodiment 1 first converts three-phase AC power supplied from a commercial AC power source 30 into DC power, and then converts the DC power back into three-phase AC power and supplies it to the load 31. Figure 1 In order to simplify the accompanying drawings and descriptions, only the part of the circuit corresponding to one of the three phases (U phase, V phase, W phase) (e.g., U phase) is shown.

[0028] Reference Figure 1 The uninterruptible power supply (UPS) 100 has an AC input terminal T11, a battery terminal T12, an AC output terminal T13, and a bypass input terminal T14. The AC input terminal T11 receives commercial frequency AC power from a commercial AC power source 30. The bypass input terminal T14 receives commercial frequency AC power from a bypass AC power source 33. The bypass AC power source 33 can be a commercial AC power source or a generator.

[0029] Battery terminal T12 is connected to battery 32. Battery 32 stores DC power. Battery 32 corresponds to one embodiment of a "power storage device". A capacitor may also be connected instead of battery 32. AC output terminal T13 is connected to load 31. Load 31 is driven by AC power.

[0030] The uninterruptible power supply device 100 also includes electromagnetic contactors S1, S2, S3, S4, current detectors 12, 13, capacitors 1, 5, 10, reactors 2, 9, converter 4, bidirectional chopper 7, inverter 8, semiconductor switch 20, detectors 60, 62, 64, gate drivers 66, 68, 70, switch interface (I / F) 72, operation unit 24, and main controller 22.

[0031] Electromagnetic contactors S1, S2, S3, S4, current detectors 12, 13, capacitors 1, 5, 10, reactors 2 and 9, converter 4, bidirectional chopper 7, inverter 8, and semiconductor switch 20 each correspond to one embodiment of the "module". Detectors 60, 62, 64, gate drivers 66, 68, 70, and switch I / F 72 each correspond to one embodiment of the "controller".

[0032] The first terminal of electromagnetic contactor S1 is connected to AC input terminal T11, and the second terminal (node ​​N1) of electromagnetic contactor S1 is connected to the first terminal of reactor 2. The second terminal of reactor 2 is connected to AC terminal 4a of converter 4. Capacitor 1 is connected between node N1 and neutral point NP. Neutral point NP receives, for example, ground voltage. Electromagnetic contactor S1 is turned on when the uninterruptible power supply 100 is in use, and turned off, for example, during maintenance of the uninterruptible power supply 100.

[0033] The instantaneous value of the AC input voltage Vi appearing at node N1 is detected by detector 60. Current detector 12 detects the AC input current Ii flowing through node N1 and outputs a signal Iif representing the detected value to detector 60. Detector 60 is connected to the main controller 22 via communication line 15. Communication line 15 is configured for bidirectional data transmission via serial communication. Communication line 15 corresponds to one embodiment of a "serial communication line". Detector 60 provides the main controller 22 with a signal representing the detected value of the instantaneous AC input voltage Vi and a signal Iif representing the detected value of the AC input current Ii via communication line 15.

[0034] Capacitor 1 and reactor 2 constitute AC filter 3, which allows commercial frequency AC power to pass through and prevents the switching frequency current generated by converter 4 from passing through commercial AC power supply 30.

[0035] Converter 4, controlled by main controller 22, converts AC power to DC power and outputs it to DC line 6 during normal operation when AC power is supplied from commercial AC power source 30. When AC power is no longer supplied normally from commercial AC power source 30 (during a power outage), converter 4 stops operating. The output voltage of converter 4 can be controlled to a desired value.

[0036] Specifically, converter 4 has multiple switching elements (not shown). These switching elements are connected to a gate driver (GD) 66. The gate driver 66 is connected to a main controller 22 via a communication line 15 and drives the multiple switching elements according to gate signals provided from the main controller 22.

[0037] Capacitor 5 is connected to DC line 6 to smooth the voltage of DC line 6. The instantaneous value of the DC voltage VD appearing on DC line 6 is detected by detector 62. DC line 6 is connected to the high-voltage side node of bidirectional chopper 7, and the low-voltage side node of bidirectional chopper 7 is connected to battery terminal T12 via electromagnetic contactor S2.

[0038] Electromagnetic contactor S2 is turned on when the uninterruptible power supply 100 is in use, and turned off, for example, during maintenance of the uninterruptible power supply 100 and battery 32. The instantaneous value of the inter-terminal voltage VB of battery 32 appearing at battery terminal T12 is detected by detector 62. Detector 62 is connected to main controller 22 via communication line 15. Detector 62 provides signals representing the detected instantaneous values ​​of DC voltage VD and the inter-terminal voltage VB of battery 32 to main controller 22 via communication line 15.

[0039] The bidirectional chopper 7 is controlled by the main controller 22. During normal operation, it stores the DC power generated by the converter 4 into the battery 32. When the commercial AC power supply 30 fails, it supplies the DC power of the battery 32 to the inverter 8 via the DC line 6.

[0040] When storing DC power in battery 32, the bidirectional chopper 7 steps down the DC voltage VD of DC line 6 and supplies it to battery 32. Additionally, when supplying DC power from battery 32 to inverter 8, the bidirectional chopper 7 boosts the inter-terminal voltage VB of battery 32 and outputs it to DC line 6. DC line 6 is connected to the input node of inverter 8.

[0041] Specifically, the bidirectional chopper 7 has multiple switching elements (not shown). These switching elements are connected to a gate driver (GD) 68. The gate driver 68 is connected to a main controller 22 via a communication line 15 and drives the multiple switching elements according to gate signals provided from the main controller 22.

[0042] Inverter 8, controlled by main controller 22, converts the DC power supplied from converter 4 or bidirectional chopper 7 via DC line 6 into commercial frequency AC power and outputs it. Specifically, during normal operation, inverter 8 converts the DC power supplied from converter 4 via DC line 6 into AC power; when the commercial AC power supply 30 fails, it converts the DC power supplied from battery 32 via bidirectional chopper 7 into AC power. The output voltage of inverter 8 can be controlled to a desired value.

[0043] Specifically, inverter 8 has multiple switching elements (not shown). These switching elements are connected to a gate driver (GD) 70. The gate driver 70 is connected to a main controller 22 via communication line 15 and drives the multiple switching elements according to gate signals provided from the main controller 22.

[0044] The AC terminal 8a of inverter 8 is connected to the first terminal of reactor 9, the second terminal of reactor 9 (node ​​N2) is connected to the first terminal of electromagnetic contactor S3, and the second terminal of electromagnetic contactor S3 (node ​​N3) is connected to AC output terminal T13. Capacitor 10 is connected between node N2 and neutral point NP. Neutral point NP receives, for example, ground voltage.

[0045] Current detector 13 detects the instantaneous value of the output current Io of inverter 8 and provides a signal Iof representing this detected value to detector 64. The instantaneous value of the AC output voltage Vo appearing at node N2 is detected by detector 64.

[0046] Detector 64 is connected to main controller 22 via communication line 15. Detector 64 provides the main controller 22 with a signal representing the instantaneous value of the AC output voltage Vo and a signal Iof representing the instantaneous value of the output current Io via communication line 15.

[0047] The reactor 9 and the capacitor 10 constitute an AC filter 11, which allows the commercial frequency AC power generated by the inverter 8 to pass through the AC output terminal T13, and prevents the switching frequency current generated by the inverter 8 from passing through the AC output terminal T13.

[0048] Electromagnetic contactor S3 is controlled by main controller 22. It is turned on in inverter power supply mode when AC power generated by inverter 8 is supplied to load 31, and turned off in bypass power supply mode when AC power from bypass AC power supply 33 is supplied to load 31.

[0049] Semiconductor switch 20 includes a pair of thyristors connected in parallel with opposite polarities, connected between bypass input terminal T14 and node N3. Electromagnetic contactor S4 is connected in parallel with semiconductor switch 20. Semiconductor switch 20 is controlled by main controller 22, normally open, and momentarily closed in the event of a fault in inverter 8, supplying AC power from bypass AC power supply 33 to load 31. Semiconductor switch 20 is closed after a predetermined time from being closed.

[0050] The electromagnetic contactor S4 is disconnected in inverter power supply mode when supplying AC power generated by inverter 8 to load 31, and connected in bypass power supply mode when supplying AC power from bypass AC power source 33 to load 31.

[0051] Additionally, in the event of a fault in inverter 8, electromagnetic contactor S4 is activated to supply AC power from bypass AC power supply 33 to load 31. That is, in the event of a fault in inverter 8, semiconductor switch 20 is activated momentarily for a predetermined time, and electromagnetic contactor S4 is also activated. This is to prevent semiconductor switch 20 from overheating and being damaged.

[0052] Specifically, a switch I / F 72 is connected to the electromagnetic contactors S3 and S4 and the semiconductor switch 20. The switch I / F 72 is connected to the main controller 22 via the communication line 15. The switch I / F 72 turns the electromagnetic contactors S3 and S4 and the semiconductor switch 20 on or off according to the on or off command provided by the main controller 22.

[0053] The operation unit 24 includes multiple buttons operated by the user of the uninterruptible power supply device 100, a display showing various information, etc. By operating the operation unit 24, the user can turn the power supply of the uninterruptible power supply device 100 on and off, or select either the bypass power supply mode or the inverter power supply mode.

[0054] In addition, the operation unit 24 is connected to the communication network NW, and can exchange data with the external device 35 of the uninterruptible power supply device 100 via the communication network NW (see reference). Figure 2 External device 35 may include, for example, a PC (Personal Computer) or a server. Operation unit 24 may also have a USB connector. In this case, operation unit 24 exchanges data with external device 35 via the USB connector.

[0055] By directly operating the operation unit 24 or by remotely operating the operation unit 24 using an external device 35, updates to the programs installed on the main controller 22, detectors 60, 62, 64, gate drivers 66, 68, 70, and switch I / F 72 can be performed. Details of the program update process will be explained later.

[0056] The main controller 22 controls the uninterruptible power supply device 100 as a whole based on signals from the operation unit 24 and signals from detectors 60, 62, and 64. That is, the main controller 22 detects whether a power outage has occurred based on the detected value of the AC input voltage Vi, and controls the converter 4 and inverter 8 in phase synchronization with the AC input voltage Vi.

[0057] In addition, the main controller 22 controls the converter 4 based on the AC input voltage Vi, the AC input current Ii, and the DC voltage VD. During normal operation, the main controller 22 controls the converter 4 so that the DC voltage VD becomes the desired target voltage VDT. When the commercial AC power supply 30 fails, the converter 4 stops operating.

[0058] In addition, the main controller 22 controls the bidirectional chopper 7 based on the DC voltage VD and the battery voltage VB. During normal operation, the main controller 22 controls the bidirectional chopper 7 such that the battery voltage VB becomes the desired target battery voltage VBT. When the commercial AC power supply 30 fails, the main controller 22 controls the bidirectional chopper 7 such that the DC voltage VD becomes the desired target voltage VDT.

[0059] In addition, the main controller 22 controls the inverter 8 based on the AC output current Io and the AC output voltage Vo, so that the AC output voltage Vo becomes the desired target voltage VoT.

[0060] The control of the converter 4, bidirectional chopper 7 and inverter 8 mentioned above is achieved by the main controller 22 and detectors 60, 62, 64, gate drivers 66, 68, 70 and switch I / F 72 each executing pre-installed programs and exchanging data with each other via communication line 15.

[0061] That is, detectors 60, 62, 64, gate drivers 66, 68, 70, and switch I / F 72 each correspond to an embodiment of a "controller" that controls the operation of each module of the uninterruptible power supply 100 under the control of the main controller 22, which controls the overall uninterruptible power supply 100. In this embodiment, data can be exchanged between the main controller and each controller via serial communication. Therefore, even if the number of modules increases, the increase in the number of wiring connected to the main controller 22 can be suppressed.

[0062] Next, the structures of the main controller 22, detectors 60, 62, 64, gate drivers 66, 68, 70, and switch I / F 72 will be described. Since the basic structures of detectors 60, 62, 64, gate drivers 66, 68, 70, and switch I / F 72 are the same, the structure of gate driver 66 will be shown as an example in the following description.

[0063] Figure 2 This is a block diagram showing the structure of the main controller 22 and the gate driver 66.

[0064] Reference Figure 2 The main controller 22 and the gate driver 66 are bidirectionally connected via communication line 15. Communication line 15 is configured to transmit data bidirectionally via serial communication. Communication line 15 includes communication line 15A for transmitting data from the main controller 22 to the gate driver 66 and communication line 15B for transmitting data from the gate driver 66 to the main controller 22.

[0065] The main controller 22 and the gate driver 66 cooperate to control the converter 4 by executing a program pre-stored in the memory. The main controller 22 and the gate driver 66 have two communication modes: a "normal communication mode" for bidirectional communication in the operation of the uninterruptible power supply device 100, and an "update mode" for bidirectional communication to update the programs stored in the respective storage devices.

[0066] Furthermore, the default communication mode is normal communication mode. Upon receiving an updated execution instruction from the operation unit 24, the main controller 22 and the gate driver 66 respectively switch the communication mode from normal communication mode to update mode.

[0067] The main controller 22 includes a programmable device 40, an update device 42, a selector 44, and a serial communication I / F 46.

[0068] The programmable device 40 includes a processor 400, a memory 402, an input / output (I / O) circuit 404, and a communication I / F 406. The processor 400, memory 402, I / O circuit 404, and communication I / F 406 can send and receive signals to each other via a bus (not shown). The programmable device 40 can also be implemented as a control board including the processor 400. The programmable device 40 corresponds to one embodiment of the "first programmable device".

[0069] The processor 400 is composed of at least one integrated circuit. The integrated circuit may be composed of at least one CPU (Central Processing Unit), at least one MPU (Micro Processing Unit), at least one FPGA (Field Programmable Gate Array), or a combination thereof.

[0070] The memory 402 includes ROM (Read Only Memory), RAM (Random Access Memory), and non-volatile storage devices. The processor 400 controls the operation of the uninterruptible power supply device 100 by executing various programs. The processor 400 reads programs from the non-volatile storage devices to the ROM. The RAM functions as working memory, temporarily storing various data required for program execution. The I / O circuit 404 is connected to the operation unit 24 and the update device 42, and is capable of exchanging signals with the operation unit 24 and the update device 42.

[0071] The communication I / F 406 is an interface used to exchange data with the gate driver 66 in normal communication mode.

[0072] In normal communication mode, programmable device 40 generates a transmit signal T1 and outputs the generated transmit signal T1 to the first input terminal of selector 44. Programmable device 40 has a parallel / serial converter that converts the transmit signal T1, which is parallel data, into serial data.

[0073] The update device (hereinafter also simply referred to as the device) 42 is used to update the programmable devices 40 and 50, respectively included in the main controller 22 and the gate driver 66. The device 42 operates upon receiving an update execution instruction from the operation unit 24, performing the process of updating the programmable devices 40 and 50. The device 42 may be integrally configured with the programmable device 40, or it may be configured as a separate device from the programmable device 40. The device 42 corresponds to one embodiment of the term "device".

[0074] Device 42 includes I / O circuitry 420 and communication I / F 422. I / O circuitry 420 and communication I / F 422 are capable of sending and receiving signals to each other via a bus (not shown).

[0075] I / O circuit 420 is connected to programmable device 40 and operation unit 24, and is capable of sending and receiving signals between programmable device 40 and operation unit 24. Communication I / O circuit 422 is an interface for exchanging data between device 42 and gate driver 66 in update mode.

[0076] In update mode, device 42 receives data required for update processing from operation unit 24 via I / O circuit 420. Using the data provided from operation unit 24, device 42 generates a transmission signal Tu1 for updating programmable device 50, and outputs the generated transmission signal Tu1 to the second input terminal of selector 44. Device 42 has a parallel / serial converter that converts the transmission signal Tu1, which is parallel data, into serial data.

[0077] Additionally, device 42 receives an update mode transfer flag Fu indicating an updated execution instruction from operation unit 24 via I / O circuit 420. The update mode transfer flag Fu is set to a closed state in normal communication mode and is set to an open state corresponding to the updated execution instruction.

[0078] When the update mode transition flag Fu is in the enabled state, device 42 generates an output signal UO2 with an activation level of H (logic high) and outputs the generated output signal UO2 to selector 44. When the update mode transition flag Fu is in the disabled state, device 42 outputs the output signal UO2 with an activation level of L (logic low) to selector 44.

[0079] Selector 44 receives a normal communication transmit signal T1 output from programmable device 40 to the first input terminal, and an update transmit signal Tu1 output from device 42 to the second input terminal. Selector 44 selects one of the two input signals based on the output signal UO2 provided by device 42 and outputs it to driver 460 within serial communication I / F 46. Specifically, when output signal UO2 is at a low level (L), selector 44 selects the transmit signal T1 from programmable device 40 and outputs it to driver 460. Conversely, when output signal UO2 is at a high level (H), selector 44 selects the transmit signal Tu1 from device 42 and outputs it to driver 460. Selector 44 corresponds to one embodiment of the "first selector".

[0080] The serial communication I / F 46 is a communication interface used to exchange various data between the main controller 22 and the gate driver 66 via serial communication using communication line 15. The serial communication I / F 46 has a driver 460 and a receiver 462.

[0081] The transmit signal output from selector 44 is provided to driver 460. Driver 460 transmits the data corresponding to the transmit signal to controller 14 via communication line 15A.

[0082] Receiver 462 receives data transmitted from gate driver 66 via communication line 15B and outputs it as a receive signal to programmable device 40 or device 42. In normal communication mode, receiver 462 outputs data from gate driver 66 as a normal communication receive signal R1 to programmable device 40. In update mode, receiver 462 outputs data from gate driver 66 as an update receive signal Ru1 to device 42.

[0083] The programmable device 40 receives a received signal R1 output from the receiver 462 and performs prescribed processing based on the input received signal R1. The programmable device 40 has a serial / parallel converter that converts serial data, i.e., the received signal R1, into parallel data.

[0084] Device 42 receives an update receive signal Ru1 output from receiver 462 and performs prescribed processing based on the input receive signal Ru1. Device 42 has a serial / parallel converter that converts serial data, i.e., the receive signal Ru1, into parallel data.

[0085] The gate driver 66 includes a programmable device 50, a selector 52, a latch circuit 54, and a serial communication I / F 56.

[0086] The programmable device 50 includes a processor 500, a ROM 502, a RAM 504, a buffer circuit 506, a receiving terminal 508 for updating, and a transmitting terminal 510 for updating. These components are capable of transmitting and receiving signals to each other via a bus (not shown). The programmable device 50 can be implemented as a control board including the processor 500. The programmable device 50 corresponds to one embodiment of a "second programmable device".

[0087] The processor 500 is composed of at least one integrated circuit. The integrated circuit may be, for example, at least one CPU, at least one MPU, at least one FPGA, or a combination thereof.

[0088] The processor 500 drives the switching elements constituting the converter 4 by executing various programs. The processor 500 expands and executes the program stored in ROM 502 in RAM 504. The program stored in ROM 502 records various processes executed by the processor 500. RAM 504 functions as working memory and temporarily stores various data required for program execution.

[0089] In normal communication mode, programmable device 50 generates a transmit signal T2 for normal communication and outputs the generated transmit signal T2 to buffer circuit 506. Programmable device 50 has a parallel / serial converter that converts the transmit signal T2, which is parallel data, into serial data.

[0090] The buffer circuit 506 includes a transmit buffer Bt, a receive buffer Br, and an output buffer Bo. The transmit buffer Bt is connected to the first input terminal of the selector 52. The transmit buffer Bt temporarily stores the transmit signal T2 output from the processor 500.

[0091] The receive buffer Br temporarily stores the receive signal R2 input to the processor 500 for normal communication. Furthermore, in normal communication mode, when the main controller 22 receives the update mode transfer flag Fu from the operation unit 24, the processor 500 receives the update mode transfer flag Fu transmitted from the main controller 22 via the receive buffer Br.

[0092] If the processor 500 receives the update mode transition flag Fu, it generates an output signal UO1 activated at level H and outputs the generated output signal UO1 to the selector 52. If the update mode transition flag Fu is not received, the processor 500 outputs the output signal UO1 at level L to the selector 52. The output buffer Bo temporarily stores the output signal UO1 output from the processor 500. A latch circuit 54 is disposed between the output buffer Bo and the selector 52 to latch the output signal UO1 output from the output buffer Bo.

[0093] The output buffer Bo also outputs the output signal UO1 to the ROM 502. The ROM 502 determines the communication mode between the main controller 22 and the gate driver 66 based on the output signal UO1 provided by the output buffer Bo. Specifically, when the output signal UO1 is at a low level, the ROM 502 determines that the communication mode is the normal communication mode. When the output signal UO1 is at a high level, the ROM 502 determines that the communication mode is the update mode.

[0094] The receive terminal 508 and the transmit terminal 510 are connected to the ROM 502. The receive terminal 508 and the transmit terminal 510 are used for transmitting and receiving data to update the program stored in the ROM 502. The receive terminal 508 is connected to the receiver 560 within the serial communication I / F 56, and inputs the receive signal Ru2 output from the receiver 560 to the ROM 502. The transmit terminal 510 is connected to the second input terminal of the selector 52, and inputs the transmit signal Tu2 generated by the ROM 502 to the second input terminal of the selector 52.

[0095] Selector 52 receives a normal communication transmit signal T2 output from processor 500 to the first input terminal, and an update transmit signal Tu2 output from ROM 502 to the second input terminal. Selector 52 selects one of the two input signals based on the output signal UO1 provided by processor 500 and outputs it to driver 562 within serial communication I / F 56. When output signal UO1 is at a low level (L), selector 52 selects the transmit signal T2 from processor 500 and outputs it to driver 562. Conversely, when output signal UO1 is at a high level (H), selector 52 selects the transmit signal Tu2 from ROM 502 and outputs it to driver 562. Selector 52 corresponds to one embodiment of the "second selector".

[0096] The serial communication I / F 56 is a communication interface used to exchange various data between the gate driver 66 and the main controller 22 via serial communication using communication line 15. The serial communication I / F 56 has a receiver 560 and a driver 562.

[0097] Receiver 560 receives data sent from main controller 22 via communication line 15A and outputs it as a receive signal to processor 500 or ROM 502. In normal communication mode, receiver 560 outputs data from autonomous controller 22 as a receive signal R2 for normal communication to processor 500. In update mode, receiver 560 outputs data from autonomous controller 22 as an update receive signal Ru2 to ROM 502.

[0098] Processor 500 receives the received signal R2 output from receiver 560 and performs prescribed processing based on the input received signal R2. Processor 500 has a serial / parallel converter that converts the received signal R2, which is serial data, into parallel data.

[0099] ROM 502 receives the received signal Ru2 output from receiver 560 and performs update processing based on the input received signal Ru2. ROM 502 has a serial / parallel converter that converts the received signal Ru2, which is serial data, into parallel data.

[0100] The transmit signal output from selector 52 is provided to driver 562. Driver 562 transmits the data corresponding to the transmit signal to main controller 22 via communication line 15B.

[0101] Next, the bidirectional communication between the main controller 22 and the gate driver 66 in both normal communication mode and update mode will be described.

[0102] <Normal Communication Mode>

[0103] Figure 3 This is a diagram illustrating bidirectional communication under normal communication mode.

[0104] Reference Figure 3 In normal communication mode, the programmable device 40 of the main controller 22 and the programmable device 50 (processor 500) of the gate driver 66 exchange data via communication line 15.

[0105] Specifically, in normal communication mode, the update mode transition flag Fu is set to the off state. When the update mode transition flag Fu is off, device 42 outputs the L-level output signal UO2 to selector 44.

[0106] Selector 44 receives a transmit signal T1 output from programmable device 40 to the first input terminal and a transmit signal Tu1 output from device 42 to the second input terminal. When output signal UO2 is at level L, selector 44 selects the transmit signal T1 from programmable device 40 and outputs it to driver 460. The transmit signal T1 output from selector 44 is transmitted to gate driver 66 via communication line 15A.

[0107] In controller 14, receiver 560 receives transmit signal T1 via communication line 15A. In normal communication mode, receiver 560 outputs the received transmit signal T1 to receive buffer Br. Receiver buffer Br then outputs transmit signal T1 as receive signal R2 to processor 500.

[0108] The processor 500 outputs the low-level output signal UO1 to the selector 44. Then, the processor 500 transmits the low-level output signal UO1 to the ROM 502 via the output buffer Bo. Based on the low-level output signal UO1 provided from the output buffer Bo, the ROM 502 determines that the communication mode is the normal communication mode.

[0109] The output buffer Bo provides the L-level output signal UO1 to the selector 52 via the latch circuit 54. The latch circuit 54 latches the output signal UO1.

[0110] Selector 52 receives the transmit signal T2 output from processor 500 to the first input terminal and the transmit signal Tu2 output from ROM 502 to the second input terminal. When output signal UO1 is at level L, selector 52 selects the transmit signal T2 from processor 500 and outputs it to driver 562. The transmit signal T2 output from selector 52 is transmitted to main controller 22 via communication line 15B.

[0111] In the main controller 22, the receiver 462 receives the transmitted signal T2 via communication line 15B. In normal communication mode, the receiver 462 outputs the received transmitted signal T2 to the programmable device 40. The programmable device 40 receives the transmitted signal T2 as the received signal R1.

[0112] exist Figure 3 In the diagram, the communication path formed between the main controller 22 and the gate driver 66 during normal communication mode is indicated by thick lines. In normal communication mode, the selector 44 of the main controller 22 selects the transmit signal T1 of the programmable device 40 and transmits it to the gate driver 66. The selector 52 of the gate driver 66 selects the transmit signal T2 of the programmable device 50 and transmits it to the main controller 22. That is, a communication path is formed to enable communication between the programmable device 40 and the programmable device 50. In the application of the uninterruptible power supply device 100, data can be exchanged between the programmable device 40 and the programmable device 50 using this communication path, thereby controlling the converter 4.

[0113] <Update Mode>

[0114] Figure 4 This is a diagram illustrating bidirectional communication in update mode.

[0115] Reference Figure 4 In update mode, the ROM 502 of the main controller 22 device 42 and the gate driver 66 exchange data for updating the programmable device 50 via communication line 15.

[0116] Execute according to the update mode transfer flag Fu input from the operation unit 24. Figure 3The diagram shows the transition from normal communication mode to... Figure 4 The update mode transition is shown. Specifically, in normal communication mode, if an update execution instruction is received from the user or external device 35, the operation unit 24 sets the update mode transition flag Fu to the enabled state. The operation unit 24 outputs the enabled update mode transition flag Fu to the device 42.

[0117] Device 42 transmits the update mode transfer flag Fu received from operation unit 24 to programmable device 40. Furthermore, device 42 receives data from operation unit 24 for updating each of programmable devices 40 and 50.

[0118] If the programmable device 40 receives the update mode transfer flag Fu, it generates a transmit signal T1 containing the update mode transfer flag Fu and outputs it to the selector 44. In normal communication mode, the L-level output signal UO2 is input to the selector 44. Therefore, the selector 44 selects the transmit signal T1 (i.e., the update mode transfer flag Fu) from the programmable device 40 according to the L-level output signal UO2 and outputs it to the driver 460. The transmit signal T1 output from the selector 44 is transmitted to the controller 14 via the communication line 15A.

[0119] Device 42 transmits data provided by operation unit 24 for updating programmable device 40 to programmable device 40. In update mode, programmable device 40 updates the program stored in memory 402 according to the update data provided by device 42.

[0120] Additionally, in response to the update mode transfer flag Fu, device 42 activates the output signal UO2 to level H and outputs the output signal UO2 to selector 44. Furthermore, device 42 generates an update transmission signal Tu1 based on the data provided from operation unit 24 for updating programmable device 50.

[0121] If an H-level output signal UO2 is received, selector 44 selects the transmit signal Tu1 from device 42 and outputs it to driver 460. The transmit signal Tu1 output from selector 44 is transmitted to gate driver 66 via communication line 15A.

[0122] In gate driver 66, if a transmit signal T1 containing the update mode transfer flag Fu is received in normal communication mode, receiver 560 outputs the received transmit signal T1 to receive buffer Br. Receive buffer Br then outputs the transmit signal T1 as receive signal R2 to processor 500. Receive signal R2 contains the update mode transfer flag Fu, which is set to the enabled state.

[0123] If the update mode transition flag Fu is received, the processor 500 activates the output signal UO1 to level H and outputs the output signal UO1 to the selector 44. Furthermore, the processor 500 transmits the output signal UO1 to the ROM 502.

[0124] Furthermore, in response to receiving the update mode transition flag Fu, the processor 500 disables the buffer circuit 506. In update mode, by stopping data exchange by the processor 500, malfunctions by the processor 500 during update execution can be prevented.

[0125] The H-level output signal UO1 is input to the selector 52 via the output buffer Bo and the latch circuit 54. The latch circuit 54 latches the H-level output signal UO1. Thus, even when the buffer circuit 506 is disabled and the output buffer Bo cannot output the output signal UO1, the H-level output signal UO1 can still be continuously provided to the selector 52.

[0126] ROM 502 determines whether the normal mode is update mode based on the H-level output signal UO1 input from the output buffer Bo. In update mode, ROM 502 can replace processor 500 to exchange update data with main controller 22 (device 42).

[0127] Selector 52, corresponding to the H-level output signal UO1 input from latch circuit 54, selects the update transmission signal Tu2 from ROM 502 and outputs it to driver 562. The transmission signal Tu2 output from selector 52 is transmitted to main controller 22 via communication line 15B.

[0128] In the main controller 22, the receiver 462 receives the transmitted signal Tu2 via communication line 15B. In update mode, the receiver 462 outputs the received transmitted signal Tu2 to the device 42. The device 42 receives the transmitted signal Tu2 as the received signal Ru1 for update.

[0129] exist Figure 4 In the diagram, the communication path formed between the main controller 22 and the gate driver 66 during update mode is indicated by thick lines. In update mode, the selector 44 of the main controller 22 selects the update transmission signal Tu1 for the device 42 and sends it to the gate driver 66. The selector 52 of the gate driver 66 selects the update transmission signal Tu2 for the ROM 502 and sends it to the main controller 22. That is, a communication path is formed to enable communication between the device 42 and the ROM 502. In update mode, update data can be exchanged between the device 42 and the ROM 502 using this communication path, thereby updating the programmable device 50.

[0130] Here, the communication path in the normal communication mode described above (refer to...) Figure 3 ) and the communication path during update mode (refer to Figure 4 They share a common communication line 15. Therefore, without increasing the number of communication lines, the programmable device 50 of the gate driver 66 can be updated via the main controller 22. For example... Figure 1 As shown, the main controller 22 is connected to multiple controllers (detectors 60, 62, 64, gate drivers 66, 68, 70, and switch I / F 72) via communication line 15. Therefore, by using communication line 15 to form an update communication path between the main controller 22 and each controller, the main controller 22 can update all controllers.

[0131] Furthermore, as described above, if the update mode transition flag Fu is received from the main controller 22 in the gate driver 66, the programmable device 50 disables the buffer circuit 506 used for bidirectional communication in normal communication mode. Therefore, in update mode, the processor 500 cannot exchange data, and thus the output signal UO1 is also interrupted relative to the output of the selector 52. In this embodiment, by providing a latch circuit 54 that latches the output signal UO1 of the processor 500, a high-level output signal UO1 can be continuously provided to the selector 52. As a result, in update mode, bidirectional communication between the device 42 of the main controller 22 and the ROM 502 can be maintained, and the program stored in the ROM 502 can be updated.

[0132] If the update of programmable devices 40 and 50 is completed, the main controller 22 and the gate driver 66 respectively execute the initialization process of programmable devices 40 and 50. Through this initialization process, the communication mode is switched from the update mode to the normal communication mode. Specifically, in the main controller 22, device 42 outputs the L-level output signal UO2 to the selector 44. In the gate driver 66, the processor 500 outputs the L-level output signal UO1 to the selector 52 and restores the buffer circuit 506 to a usable state.

[0133] Figure 5 This is a flowchart illustrating the steps of processing the programmable device that updates the main controller 22 and the gate driver 66. The process executed by the main controller 22 is shown on the left, and the process executed by the gate driver 66 is shown on the right.

[0134] In normal communication mode, through step (hereinafter simply referred to as S)01, the main controller 22 and device 42 determine whether they have received the update mode transfer flag Fu from the operation unit 24. If the update mode transfer flag Fu is received from the operation unit 24 (when S01 determines "yes"), device 42 transmits the received update mode transfer flag Fu to programmable device 40.

[0135] In S02, the programmable device 40 generates a transmit signal T1 containing the update mode transfer flag Fu and outputs it to the selector 44. At this time, the selector 44 receives the L-level output signal UO2 from the device 42, and therefore selects the transmit signal T1 (update mode transfer flag Fu) and transmits it to the gate driver 66 via the communication line 15.

[0136] Device 42 outputs an H-level output signal UO2 to selector 44 via S03. Upon receiving the H-level output signal UO2, selector 44 selects the update transmission signal Tu1 from device 42 to replace the transmission signal T1 from programmable device 40 and outputs it to driver 460. This switches the communication mode from normal communication mode to update mode. According to S03, the communication path between main controller 22 and gate driver 66 is hardware-switched from the communication path between programmable device 40 and gate driver 66 to the communication path between device 42 and gate driver 66. Therefore, in update mode, programmable device 40 cannot exchange data with gate driver 66.

[0137] In step S04, programmable device 40 uses update data provided by slave device 42 to update the program stored in memory 402. After the update is completed, programmable device 40 enters a standby state until the update of programmable device 50 is completed.

[0138] In S05, device 42 updates the programmable device 50 of gate driver 66 by exchanging update data with gate driver 66.

[0139] In S06, device 42 determines whether the update of programmable devices 40 and 50 has been completed. In S06, device 42 determines whether the update of programmable device 40 has been completed based on the signal from programmable device 40. Additionally, device 42 determines whether the update of programmable device 50 has been completed based on the signal sent from gate driver 66. If the update of programmable device 50 has not been completed (when S06 determines "no"), device 42 continues the processing in S05.

[0140] If it is determined that the update of programmable devices 40 and 50 has been completed (when S06 determines "yes"), programmable device 40 initializes the main controller 22 in S07. Through initialization, in S08, device 42 outputs a deactivated L-level output signal UO2 to selector 44. By receiving the L-level output signal UO2, selector 44 selects the transmit signal T1 of programmable device 40 and outputs it to driver 460. This changes the communication mode from update mode to normal communication mode. According to S08, the communication path between the main controller 22 and gate driver 66 is switched in hardware from the communication path between device 42 and gate driver 66 to the communication path between programmable device 40 and gate driver 66. Therefore, programmable device 40 exchanges data with gate driver 66 according to the updated program.

[0141] In the gate driver 66, during normal communication mode, the programmable device 50 determines whether it has received an update mode transfer flag Fu from the main controller 22 via S11. If the update mode transfer flag Fu is received from the main controller 22 (if S11 determines "yes"), the programmable device 50 outputs an output signal UO1 activated to the H level to the selector 52 in S12.

[0142] By receiving the H-level output signal UO1, selector 52 selects the update output signal Tu2 from ROM 502 to replace the send signal T2 from processor 500 and output it to driver 562. As a result, the communication path between main controller 22 and gate driver 66 is switched in hardware from the communication path between programmable device 40 and processor 500 to the communication path between device 42 and ROM 502.

[0143] Then, programmable device 50 disables buffer circuit 506 via S13. This changes the communication mode from normal communication mode to update mode. In update mode, programmable device 50 cannot exchange data with programmable device 40.

[0144] In S14, update data is exchanged between ROM 502 and device 42 via communication line 15, thereby updating the program stored in ROM 502. In S16, device 42 determines whether the update of programmable device 50 has been completed. In S16, programmable device 50 determines whether the update of programmable device 50 has been completed based on the signal from ROM 502. If the update of programmable device 50 has not been completed (when S16 determines "no"), programmable device 50 continues the processing of S14 and S15.

[0145] If it is determined that the update of the programmable device 50 has been completed (when S16 is determined to be "yes"), the programmable device 50 initializes the gate driver 66 in S17. Upon initialization, in S18, the programmable device 50 outputs a deactivated L-level output signal UO1 to the selector 52. By receiving the L-level output signal UO1, the selector 52 selects the processor 500's transmit signal T2 and outputs it to the driver 562.

[0146] According to S18, the communication path between the main controller 22 and the gate driver 66 is switched in hardware from the communication path between the device 42 and the ROM 502 to the communication path between the programmable device 40 and the processor 500. Therefore, the programmable device 50 exchanges data with the programmable device 40 of the main controller 22 according to the updated program.

[0147] Then, programmable device 50 activates buffer circuit 506 via S19. This transitions the communication mode from update mode to normal communication mode. Programmable device 50 returns to a state where it can exchange data with programmable device 40.

[0148] <Effects>

[0149] As explained above, according to the uninterruptible power supply device 100 of Embodiment 1, the main controller 22 and multiple controllers (e.g., gate drivers 66) are connected to each other via a serial communication line (communication line 15) to enable communication between them. The main controller 22 can use this serial communication line to update the programs installed on each controller. Therefore, it is not necessary to connect each controller to the computer via programming cables. Thus, all controllers can be updated efficiently with a simplified structure.

[0150] Furthermore, by configuring the operation unit 24 to be communicatively connected to the external device 35 and the main controller 22 to receive update data from the operation unit 24 and send it to each controller, the user can also remotely update each controller using the external device 35.

[0151] [Implementation Method 2]

[0152] Figure 6 This is a circuit block diagram showing the structure of the uninterruptible power supply device according to Embodiment 2.

[0153] Reference Figure 6 The uninterruptible power supply device 110 in Embodiment 2 includes a bypass module B0, multiple power modules P1 to Pn (n being an integer of 2 or more), a battery 32, and a communication line 15. The bypass module B0 and the power modules P1 to Pn are connected to each other via the communication line 15. The communication line 15 is configured to transmit data bidirectionally via serial communication.

[0154] The bypass module B0 has an AC input terminal T21, an AC output terminal T22, and a switch (not shown) connected between the AC input terminal T21 and the AC output terminal T22.

[0155] Power modules P1 through Pn are power conversion modules that include converters and inverters, respectively. In the following description, power modules P1 through Pn are sometimes collectively referred to as "power module P". Power module P has an AC input terminal T11, a battery terminal T12, and an AC output terminal T13.

[0156] The AC input terminal T21 of the bypass module B0 and the AC input terminals T11 of each power module P are connected to the commercial AC power supply 30. The AC input terminals T21 and T11 receive a commercial frequency AC voltage Vi supplied from the commercial AC power supply 30.

[0157] Each power module P's battery terminal T12 is connected to battery 32. Battery 32 stores DC power. Alternatively, a capacitor can be connected instead of battery 32.

[0158] The AC output terminal T22 of the bypass module B0 and the AC output terminal T13 of each power module P are connected to the load 31. That is, the bypass module B0 and the power modules P1 to Pn are connected in parallel between the commercial AC power supply 30 and the load 31. The load 31 is driven by AC power supplied from the bypass module B0 or ​​the power modules P.

[0159] Such an uninterruptible power supply (UPS) device is called a "modular UPS". A modular UPS internally constructs a parallel circuit of power modules corresponding to the UPS's capacity. When the UPS requires N power modules to supply power, redundancy is achieved by installing (N+1) power modules, improving power quality. This method of achieving redundancy on a module-by-module basis within a single UPS is also called "hot-swappable". Hot-swappable refers to a structure that allows power modules to be removed and inserted while the UPS is in operation. This allows power module P to be replaced while the UPS continues to supply power during faulty or inspected power modules.

[0160] The uninterruptible power supply (UPS) device 110 has an inverter power supply mode and a bypass power supply mode. In inverter power supply mode, AC power is supplied from the power module P to the load 31. In inverter power supply mode, AC power supplied from the commercial AC power source 30 is converted to DC power by the converter in the power module P, and this DC power is then converted back to AC power by the inverter and supplied to the load 31. Bypass power supply mode, AC power is supplied from the commercial AC power source 30 to the load 31 via the bypass module B0. In bypass power supply mode, AC power supplied from the commercial AC power source 30 is supplied to the load 31 without passing through the power module P.

[0161] Figure 7 It means Figure 6 The circuit block diagram shown illustrates the structure of the bypass module B0 and the power module P. The uninterruptible power supply (UPS) 110 converts three-phase AC power from a commercial AC power source 30 into DC power, then converts the DC power back into three-phase AC power and supplies it to the load 31. Figure 7 To simplify the accompanying drawings and descriptions, only the circuit portion corresponding to one of the three phases (U phase, V phase, W phase) is shown.

[0162] like Figure 7 As shown, the bypass module B0 includes a semiconductor switch 20, a main controller 80, and an operation unit 24. The semiconductor switch 20 is connected between the AC input terminal T21 and the AC output terminal T22. The semiconductor switch 20 is, for example, a thyristor switch with a pair of thyristors connected in reverse parallel. The semiconductor switch 20 is controlled by the main controller 80. The semiconductor switch 20 is open in inverter power supply mode and open in bypass power supply mode.

[0163] The operation unit 24 includes multiple buttons operated by the user of the uninterruptible power supply device 110, a display showing various information, etc. By operating the operation unit 24, the user can turn the power supply of the uninterruptible power supply device 110 on and off, or select either the bypass power supply mode or the inverter power supply mode.

[0164] In addition, the operation unit 24 is connected to the communication network NW, and can exchange data with the external device 35 of the uninterruptible power supply device 110 via the communication network NW (see reference). Figure 8 External device 35 may include, for example, a PC or server. Operation unit 24 may also have a USB connector. In this case, operation unit 24 exchanges data with external device 35 via the USB connector.

[0165] The uninterruptible power supply device 100 according to Embodiment 1 (see reference) Figure 1Similarly, in the uninterruptible power supply device 110, updates to the programs installed on the main controller 80 and the controller 82 of the power module P can be performed by the user directly operating the operation unit 24 or by the user remotely operating the operation unit 24 using an external device 35.

[0166] The power module P has electromagnetic contactors S1 to S3, capacitors 1, 5, and 10, reactor 2 and reactor 9, converter 4, DC line 6, bidirectional chopper 7, inverter 8, current detector 13, and controller 82.

[0167] Electromagnetic contactor S1 and reactor 2 are connected in series between AC input terminal T11 and the input node of converter 4. Capacitor 1 is connected at node N1 between electromagnetic contactor S1 and reactor 2. Electromagnetic contactor S1 is turned on when the corresponding power module P is in the operating state and turned off when the corresponding power module P is in the stopped state. The instantaneous value of AC input voltage Vi appearing at node N1 is detected by controller 82. The instantaneous value of AC input voltage Vi is used to determine whether a power outage has occurred.

[0168] Capacitor 1 and reactor 2 constitute AC filter 3. AC filter 3 is a low-pass filter that allows commercial frequency AC power from commercial AC power supply 30 to pass through converter 4, preventing the switching frequency signal generated by converter 4 from passing through commercial AC power supply 30.

[0169] Converter 4, controlled by controller 82, converts AC power to DC power and outputs it to DC line 6 during normal operation when AC power is supplied from commercial AC power source 30. When commercial AC power source 30 fails to supply power, converter 4 stops operating.

[0170] Capacitor 5 is connected to DC line 6 to smooth the voltage of DC line 6. The instantaneous value of the DC voltage VD appearing on DC line 6 is detected by controller 82. DC line 6 is connected to the high-voltage side node of bidirectional chopper 7, and the low-voltage side node of bidirectional chopper 7 is connected to battery terminal T12 via electromagnetic contactor S2.

[0171] Electromagnetic contactor S2 is turned on when the corresponding power module P is in use, and turned off when the corresponding power module P and the corresponding battery 32 are under maintenance. The instantaneous value of the inter-terminal voltage VB of battery 32 appearing at battery terminal T12 is detected by controller 82.

[0172] The bidirectional chopper 7 is controlled by the controller 82. During normal operation, it stores the DC power generated by the converter 4 in the battery 32. When the commercial AC power supply 30 fails, it supplies the DC power of the battery 32 to the inverter 8 via the DC line 6.

[0173] When storing DC power in battery 32, bidirectional chopper 7 steps down the DC voltage VD of DC line 6 and supplies it to battery 32. Conversely, when supplying DC power from battery 32 to inverter 8, bidirectional chopper 7 boosts the inter-terminal voltage VB of battery 32 and outputs it to DC line 6. DC line 6 is connected to the input node of inverter 8.

[0174] The output node of inverter 8 is connected to the first terminal of reactor 9, and the second terminal of reactor 9 (node ​​N2) is connected to AC output terminal T13 via electromagnetic contactor S3. Capacitor 10 is connected to node N2. The instantaneous value of the AC output voltage Vo appearing at node N2 is detected by controller 82. Current detector 13 detects the instantaneous value of the current Io flowing from node N2 to AC output terminal T13 (i.e., load 31) via electromagnetic contactor S3, and provides a signal Iof representing this detected value to controller 82.

[0175] Reactor 9 and capacitor 10 constitute AC filter 11. AC filter 11 is a low-pass filter that allows the commercial frequency AC power generated by inverter 8 to pass through AC output terminal T13, while preventing the switching frequency signal generated by inverter 8 from passing through AC output terminal T13. Electromagnetic contactor S3 is controlled by controller 82, and is turned on when the corresponding power module P is in the operating state, and turned off when the corresponding power module P is in the stopped state.

[0176] The controller 82 controls the corresponding power module P as a whole based on the AC input voltage Vi, DC voltage VD, terminal voltage VB of battery 32, AC output current Io, and AC output voltage Vo. That is, the controller 82 detects whether a power outage has occurred based on the detected value of AC input voltage Vi, and controls the converter 4 and inverter 8 in phase synchronization with the AC input voltage Vi.

[0177] In addition, when the controller 82 is working normally, it controls the converter 4 so that the DC voltage VD becomes the desired target voltage VDT. When the commercial AC power supply 30 fails, it stops the operation of the converter 4.

[0178] Furthermore, when the controller 82 is operating normally, it controls the bidirectional chopper 7 in a manner that makes the inter-terminal voltage VB of the battery 32 the desired target battery voltage VBT. When the commercial AC power supply 30 is interrupted, it controls the bidirectional chopper 7 in a manner that makes the DC voltage VD the desired target voltage VDT.

[0179] Furthermore, controller 82 is interconnected with main controller 80 and the controllers 82 of other power modules P via communication line 15, and transmits and receives information with main controller 80 and other controllers 82 via communication line 15. Serial communication is used as the communication method between main controller 80 and each controller 82. Controller 82 controls converter 4 and inverter 8 to ensure that the current shared by the multiple power modules P is equal.

[0180] The main controller 80 controls the uninterruptible power supply device 110 as a whole based on signals from multiple power modules P. Each controller 82 controls its corresponding power module P according to the control commands provided by the main controller 80.

[0181] Specifically, the main controller 80 calculates the sum of the output currents Io of the multiple power modules P, i.e., the load current IL, based on the output signals Iof of the multiple current detectors 13, and then calculates the reasonable number of power modules P required to supply this load current IL. Furthermore, the main controller 80 compares the calculated reasonable number of operating modules with the current number of operating modules, and based on the comparison result, determines whether to put each power module P into an operating state or a stopped state. The main controller 80 sends a signal indicating the determination result to each controller 82 via the communication line 15.

[0182] When the corresponding power module P is in a stopped state, the controller 82 disconnects the corresponding electromagnetic contactors S1 and S3, and stops the operation of the corresponding converter 4, bidirectional chopper 7, and inverter 8. Conversely, when the corresponding power module P is in an operating state, the controller 82 keeps the corresponding electromagnetic contactors S1 and S3 in a closed state, and continues the operation of the corresponding converter 4, bidirectional chopper 7, and inverter 8.

[0183] Figure 8 This is a block diagram showing the structure of the main controller 80 and the controller 82.

[0184] Reference Figure 8 The main controller 80 and multiple controllers 82 are bidirectionally connected via communication line 15. Communication line 15 is configured for bidirectional data transmission via serial communication. Figure 8 In this example, the main controller 80 and multiple controllers 82 are connected via a daisy chain. However, the connection method of the main controller 80 and multiple controllers 82 is not limited to a daisy chain.

[0185] The basic structure of the main controller 80 and Figure 2 The main controller 22 shown is the same. That is, the main controller 80 includes a programmable device 40, a device 42, a selector 44, and a communication I / F 44.

[0186] The basic structure of each of the multiple controllers 82 and Figure 2 The gate driver 66 shown is the same. That is, the controller 82 includes a programmable device 50, a selector 52, a latch circuit 54, and a communication I / F 56.

[0187] The main controller 80 and each controller 82 cooperate to control the corresponding power module P by executing programs pre-stored in the memory. The main controller 80 and each controller 82 have two communication modes: a "normal communication mode" for bidirectional communication during operation of the uninterruptible power supply device 110, and an "update mode" for bidirectional communication to update programs stored in each memory. The default communication mode is the normal communication mode. Upon receiving an update execution instruction from the operation unit 24, the main controller 80 and each controller 82 switch the communication mode from the normal communication mode to the update mode.

[0188] In Embodiment 2, similarly to Embodiment 1 described above, update data can be exchanged between the main controller 80 and each controller 82 using the communication line 15 used in normal communication mode, thereby updating the programmable device 40 of the main controller 80 and the programmable device 50 of each controller 82.

[0189] Figure 9 This is a diagram illustrating bidirectional communication under normal communication mode. For example... Figure 9 As shown, in normal communication mode, the selector 44 of the main controller 80 selects the normal communication transmission signal T1 output from the programmable device 40 and transmits it to each controller 82 via the communication line 15. The selector 52 of each controller 82 selects the normal communication transmission signal T2 output from the programmable device 50 and transmits it to the main controller 80 via the communication line 15. That is, a communication path is formed to enable communication between the programmable device 40 and the programmable device 50. In the application of the uninterruptible power supply device 110, data can be exchanged between the programmable device 40 and the programmable device 50 using this communication path, thereby controlling each power module P.

[0190] Figure 10 This diagram illustrates bidirectional communication in update mode. In update mode, the device 42 of the main controller 80 and the ROM (not shown) of the programmable device 50 of the controller 82 exchange data for updating the programmable device 50 via communication line 15. Furthermore, a transition from normal communication mode to update mode is performed in accordance with the update mode transition flag Fu input from the operation unit 24 to the main controller 80.

[0191] As described in Embodiment 1, when the main controller 80 receives the update mode transition flag Fu, the selector 44 selects the update transmission signal Tu1 output from the slave device 42 and transmits it to each controller 82 via the communication line 15. In each controller 82, when the programmable device 50 receives the update mode transition flag Fu in normal communication mode, the selector 52 selects the update transmission signal Tu2 output from the programmable device 50 and transmits it to the main controller 80 via the communication line 15.

[0192] Furthermore, in update mode, programmable device 50 disables the buffer circuit 506 used for normal communication. The H-level output signal UO1 input to selector 52 is latched by latch circuit 54.

[0193] That is, a communication path is formed to enable communication between device 42 and programmable device 50. By using this communication path, update data can be exchanged between device 42 and programmable device 50, thereby updating each programmable device 50.

[0194] <Effects>

[0195] As explained above, the modular uninterruptible power supply device 110 of Embodiment 2 also achieves the same effects as the uninterruptible power supply device 100 of Embodiment 1. That is, the main controller 80 can update the programs installed on each controller 82 using a serial communication line (communication line 15). Therefore, it is not necessary to connect each controller 82 to the computer via programming cables. Thus, all controllers 82 connected to the main controller 80 can be updated efficiently with a simplified structure.

[0196] Furthermore, by configuring the operation unit 24 to be communicatively connected to the external device 35 and the main controller 80 to receive update data from the operation unit and send it to each controller 82, the user can also use the external device 35 to remotely update each controller 82.

[0197] The embodiments disclosed herein should be considered illustrative in all respects and not restrictive. The scope of the invention is set forth in the claims, not the foregoing description, and is intended to include all modifications within the meaning and scope equivalent to the claims.

[0198] [Label Explanation]

[0199] 1, 5, 10 Capacitors; 2, 9 Reactors; 3, 11 AC Filters; 4 Converters; 6 DC Lines; 7 Bidirectional Choppers; 8 Inverters; 12, 13 Current Detectors; 14, 82 Controllers; 22, 80 Main Controllers; 15 Communication Lines; 20 Semiconductor Switches; 24 Operating Units; 30 Commercial AC Power Supplies; 31 Loads; 32 Batteries; 33 Bypass AC Power Supplies; 35 External Devices; 40, 50 Programmable Devices; 42 Devices; 44, 52 Selectors; 46, 56 Serial Communication I / O; 54 Latch Circuits; 60, 62, 64 Detectors; 66, 68, 70 Gate Drivers; 72 Switches. / F, 100, 110 uninterruptible power supply devices, 400, 500 processors, 402 memory, 460, 562 drivers, 406, 422 communication I / O, 404, 420 I / O circuits, 462, 560 receivers, 502 ROM, 504 RAM, 506 buffer circuit, Br receive buffer, Bo output buffer, Bt transmit buffer, B0 bypass module, P1~Pn power modules, S1~S4 electromagnetic contactors, Fu update mode transfer flag, T11, T21 AC input terminals, T12 battery terminal, T13, T22 AC output terminals, NW communication network.

Claims

1. An uninterruptible power supply device, comprising: Multiple modules; The main controller includes a first programmable device and controls the plurality of modules; Multiple controllers, each containing a second programmable device, drive the multiple modules respectively through communication with the main controller; and A serial communication line connects the main controller to the plurality of controllers for communication. The main controller further includes: The device performs update processes for both the first programmable device and the second programmable device; and A first selector is used to connect the first programmable device and one of the devices to the serial communication line. The second programmable device includes: Memory, stored program; as well as The processor drives the corresponding module by executing the program stored in the memory. Each of the plurality of controllers further includes a second selector, the second selector being used to connect one of the processor and the memory to the serial communication line. The first selector connects the first programmable device to the serial communication line when the uninterruptible power supply is operating, and connects the device to the serial communication line in response to the device receiving an execution instruction for the update process. The second selector connects the processor to the serial communication line when the uninterruptible power supply is in operation, and connects the memory to the serial communication line in response to the processor receiving the execution instruction from the first programmable device during the operation of the uninterruptible power supply.

2. The uninterruptible power supply device according to claim 1, wherein, In response to receiving the execution instruction, the device outputs a selection instruction to the first selector and update data for updating the second programmable device to the first selector. The memory obtains the update data via the serial communication line and updates the program, and outputs the data generated by the update to the second selector.

3. The uninterruptible power supply device according to claim 1 or 2, wherein, The second programmable device further includes a buffer circuit for temporarily storing data input to or output to the processor. In response to receiving the execution instruction, the processor outputs the memory selection instruction to the second selector via the buffer circuit and invalidates the buffer circuit. The controller also includes latching circuitry for latching the selection indication.

4. The uninterruptible power supply device according to claim 1 or 2, wherein, In response to receiving the execution instruction, the device also performs the update process of the first programmable device.

5. The uninterruptible power supply device according to claim 1 or 2, wherein, The plurality of modules includes: The converter converts AC power supplied by an AC power source into DC power. An inverter converts DC power supplied from the converter or power storage device into AC power and supplies it to the load; and A bidirectional chopper selectively performs charging and discharging operations. The charging operation stores a portion of the DC power generated by the converter in the power storage device, and the discharging operation supplies the DC power from the power storage device to the inverter. The plurality of controllers include a plurality of gate drivers that drive the converter, the inverter and the bidirectional chopper respectively.

6. The uninterruptible power supply device according to claim 1 or 2, wherein, The plurality of modules comprises a plurality of power conversion modules connected in parallel relative to the load.

7. The uninterruptible power supply device according to claim 6, wherein, The main controller and the plurality of controllers are connected in a daisy chain via the serial communication line.

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