Linear voltage stabilizing circuit for converting high voltage to low voltage and electronic device

Abstract

The application discloses a linear voltage stabilizing circuit for converting high voltage into low voltage and electronic equipment. The voltage stabilizing circuit comprises a power tube for outputting an output voltage of the linear voltage stabilizing circuit; a voltage dividing resistor string module for obtaining a divided voltage by dividing the output voltage of the linear voltage stabilizing circuit through a resistor string; an error amplifier module for amplifying a difference between the divided voltage and a reference voltage to obtain a difference amplified voltage; and a buffer module for driving a third MOS tube by the difference amplified voltage to transmit the difference amplified voltage to a gate of the power tube. The buffer module and the power tube obtain a supply voltage according to an input voltage. A first pre-stabilizer module generates a first bias voltage, and a second MOS tube obtains a first low voltage power supply rail under the drive of the first bias voltage to supply power for the error amplifier module. The error amplifier module can be realized by low-voltage 5V MOS tubes, so that the number of high-voltage MOS tubes can be reduced, the power consumption and the area of the voltage stabilizing circuit can be reduced, and the cost can be effectively reduced.

Description

Technical Field

[0001] This application belongs to the field of linear voltage regulator circuit technology and switching power supply technology, specifically relating to a high-voltage to low-voltage linear voltage regulator circuit and electronic equipment. Background Technology

[0002] High-voltage to low-voltage linear regulators are widely used in industrial and automotive electronics. Their main feature is that they can directly output 3.3V or 5V voltage within a wide input range (e.g., 8V-55V) to power other circuit modules, such as digital isolators and analog-to-digital converters.

[0003] Linear regulators require the use of some high-voltage devices (such as LDMOS), and considering cost, the number of high-voltage devices should be minimized as much as possible.

[0004] In existing technologies, such as the low-dropout linear regulator (LDO) and its power-on circuit disclosed in Chinese invention patent CN113568466A, which is resistant to high voltage, at least two high-voltage PMOS transistors and three high-voltage NMOS transistors are required for high-voltage applications, increasing circuit power consumption and area. Furthermore, this regulator structure lacks a buffer, which could lead to stability issues if a large external capacitor is connected to VOUT. Adding a buffer to this structure would require additional high-voltage transistors. Summary of the Invention

[0005] This application addresses the issue that existing voltage regulator circuits require a large number of high-voltage components, which increases the power consumption and area of ​​the driver chip and may also cause stability problems. It provides a high-voltage to low-voltage linear voltage regulator circuit and a switching power supply.

[0006] To achieve the above technical objectives, this application adopts the following technical solution.

[0007] On the one hand, this application provides a high-voltage to low-voltage linear voltage regulator circuit, comprising:

[0008] The power transistor M0 is used to output the output voltage VOUT of the linear voltage regulator circuit.

[0009] The voltage divider resistor string module is used to divide the output voltage VOUT through a resistor string to obtain the voltage divider VFB.

[0010] The error amplifier module is used to amplify the difference between the voltage divider VFB and the reference voltage VBG to obtain the difference amplification voltage VEA;

[0011] The buffer module includes a third MOS transistor M3. The buffer module is used to drive the third MOS transistor M3 with the differential amplification voltage VEA to transfer the differential amplification voltage VEA to the gate of the power transistor M0. The buffer module and the power transistor M0 obtain the supply voltage according to the input voltage VIN.

[0012] The first pre-regulator module includes a first bias unit and a second MOSFET M2. The first bias unit is used to generate a first bias voltage. The second MOSFET M2 obtains a first low-voltage power rail VINT5 under the drive of the first bias voltage. The first low-voltage power rail VINT5 is used to power the error amplifier module.

[0013] On the other hand, this application provides an electronic device, including: a high-voltage to low-voltage linear voltage regulator circuit as described above.

[0014] Compared with the prior art, the technical solution of this application has at least the following advantages:

[0015] The high-voltage to low-voltage linear regulator circuit provided in this application includes: a power transistor MOSFET, a voltage divider resistor series module, an error amplifier module, a buffer module, and a first pre-regulator module. The first pre-regulator module generates an internal low-voltage 5V first low-voltage power rail VINT5 to power the error amplifier module. Thus, the error amplifier module can be entirely implemented by low-voltage 5V MOSFETs, thereby reducing the number of high-voltage MOSFETs, reducing the power consumption and area of ​​the regulator circuit, and effectively reducing costs.

[0016] In addition, a second pre-regulator module was added to generate a 6V-8V second low-voltage power rail VINT6 to power the buffer module and power transistor M0. This allows both the power transistor M0 and the first PMOS transistor M1 in the buffer module to be implemented using only 5V low-voltage transistors. For example, if the output voltage VOUT normally outputs 5V, there will be no overvoltage between the ports of the power transistor M0.

[0017] Furthermore, a clamping circuit is added to clamp the second low-voltage power rail VINT6 at a preset potential when the second low-voltage power rail VINT6 is higher than the second bias voltage VB, so that overvoltage will not occur.

[0018] The voltage regulator circuit provided in this application also includes a power-on reset module and a tenth MOSFET M10, which can charge the output voltage VOUT to a steady-state voltage of 5V, and the power transistor M0 will not be over-voltaged during this process.

[0019] The electronic device provided in this application can reduce the number of high-voltage MOSFETs, thereby reducing the power consumption and area of ​​the voltage regulator circuit and effectively reducing costs. Attached Figure Description

[0020] The accompanying drawings described herein are for illustrative purposes only and are not intended to limit the scope of this application in any way. Furthermore, the shapes and scales of the components in the drawings are merely illustrative to aid in understanding this application and do not specifically limit the shapes and scales of the components. Those skilled in the art, guided by the teachings of this application, can select various possible shapes and scales to implement this application according to specific circumstances. In the drawings:

[0021] Figure 1 This is a schematic block diagram of the linear voltage regulator circuit provided in Embodiment 1 of this application;

[0022] Figure 2 This is a schematic block diagram of the linear voltage regulator circuit provided in Embodiment 2 of this application;

[0023] Figure 3 This is a schematic block diagram of the linear voltage regulator circuit provided in Embodiment 3 of this application;

[0024] Figure 4 This is a schematic block diagram of the linear voltage regulator circuit provided in Embodiment 4 of this application;

[0025] Figure 5 This is a schematic block diagram of the linear voltage regulator circuit provided in Embodiment 5 of this application;

[0026] Figure 6 This is a waveform diagram of the linear voltage regulator circuit provided in Embodiment 5 of this application;

[0027] Figure 7 This is a schematic diagram of the electronic device structure provided in Embodiment 6 of this application;

[0028] Reference numerals: 10-First pre-regulator module, 20-Second pre-regulator module, 30-Buffer module, 40-Error amplifier module, 50-Voltage divider resistor series module, 60-Power-on reset module, 100-Linear regulator circuit, 200-Electronic equipment. Detailed Implementation

[0029] To enable those skilled in the art to better understand the technical solutions in this application, the technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of this application.

[0030] In the description of this application, it should be noted that, unless otherwise expressly specified and limited, the terms "connected" and "linked" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection between two components. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.

[0031] Traditional linear voltage regulator circuits require a large number of high-voltage components and may have stability issues. To address these issues, this application provides a high-voltage to low-voltage linear voltage regulator circuit 100 that can achieve high-voltage to low-voltage conversion using fewer high-voltage components.

[0032] The following are definitions of some English terms used in this application:

[0033] VGS: The voltage difference between the gate and the source;

[0034] LDMOS: Laterally diffused metal-oxide semiconductor.

[0035] Example 1

[0036] A schematic diagram of the high-voltage to low-voltage linear voltage regulator circuit 100 provided in Embodiment 1 of this application is shown below. Figure 1 As shown. Reference Figure 1 The linear regulator circuit 100 includes a voltage divider resistor string module 50, an error amplifier module 40, a buffer module 30, a first pre-regulator module 10, and a power transistor M0.

[0037] The power transistor MO is used to output the output voltage VOUT of the linear voltage regulator circuit 100.

[0038] The voltage divider resistor string module 50 is used to divide the output voltage VOUT through a resistor string to obtain the voltage divider VFB.

[0039] Error amplifier module 40 is used to amplify the difference between the voltage divider VFB and the reference voltage VBG to obtain the difference amplified voltage VEA;

[0040] The buffer module 30 includes a third MOSFET M3. The buffer module 30 is used to drive the third MOSFET M3 with the differential amplified voltage VEA to transfer the differential amplified voltage VEA to the gate of the power transistor M0. The buffer module 30 and the power transistor M0 obtain the supply voltage according to the input voltage VIN.

[0041] The first pre-regulator module 10 includes a first bias unit and a second MOSFET M2. The first bias unit is used to generate a first bias voltage. The second MOSFET M2 obtains a first low-voltage power rail VINT5 under the drive of the first bias voltage. The first low-voltage power rail VINT5 is used to power the error amplifier module 40.

[0042] like Figure 1 As shown, the output voltage VOUT is the output voltage of the linear regulator circuit 100. The voltage divider VFB is obtained through the voltage divider resistor series module 50 composed of the first resistor R1 and the second resistor R2. Then, the difference between the voltage divider VFB and the reference voltage VBG is amplified by the error amplifier module 40 to obtain the differential amplified voltage VEA. The differential amplified voltage VEA is transmitted to the gate of the power transistor M0 at the output terminal through the buffer module 30.

[0043] To minimize the number of high-voltage transistors, this circuit includes a simple first pre-regulator module 10, comprising a first bias unit and a second MOSFET M2. The first bias unit includes a first Zener diode D1 and a fifth resistor R5. One end of the fifth resistor R5 is connected to the input voltage VIN, and the other end is connected to the cathode of the first Zener diode D1. The anode of the first Zener diode D1 is connected to ground GND, and the cathode of the first Zener diode D1 is connected to the gate of the second MOSFET M2. The drain of the second MOSFET M2 is connected to the input voltage VIN, and the source of the second MOSFET M2 outputs the first low-voltage power rail VINT5.

[0044] The bias is generated by the first Zener diode D1 and the fifth resistor R5, and then by an N-type LDMOS (such as...). Figure 1 The MOSFET M2 shown generates the first low-voltage power rail VINT5 of internal low voltage 5V to power the error amplifier module 40. Thus, the error amplifier module 40 can be entirely implemented by low-voltage 5V MOSFETs, thereby reducing the number of high-voltage MOSFETs, reducing the power consumption and area of ​​the circuit, and effectively reducing costs.

[0045] The buffer module 30 also includes a first MOSFET M1; the source of the first MOSFET M1 is connected to the input voltage VIN; the gate of the first MOSFET M1 is connected to the gate of the power transistor M0; the gate of the first MOSFET M1 is connected to the input voltage VIN; the gate of the first MOSFET M1 is connected to the drain of the first MOSFET M1; the drain of the first MOSFET M1 is connected to the drain of the third MOSFET M3; the source of the third MOSFET M3 is connected to ground GND; and the gate of the third MOSFET M3 is connected to the differential amplification voltage VEA.

[0046] In some embodiments, in order to achieve the functions of soft start and current limiting, a third resistor R3 is added. That is, the source of the third MOSFET M3 is connected to ground GND through the third resistor R3. The output current of the voltage regulator circuit is limited to K*(VEA-VGS) / R3 by the third resistor R3, where K is the ratio of the size (width-to-length ratio) of the output power transistor M0 and the first MOSFET M1.

[0047] In some embodiments, the gate of the first MOSFET M1 is connected to the input voltage VIN through a fourth resistor R4. The function of the fourth resistor R4 is to ensure that the gate of the output power transistor M0 is pulled up and kept in the off state when the voltage regulator circuit is not started. The entire regulator only requires two high-voltage P-type LDMOS transistors, the output power transistor M0 and the first MOSFET M1, and two high-voltage N-type LDMOS transistors, the second MOSFET M2 and the third MOSFET M3; the rest are low-voltage devices.

[0048] In this embodiment, the buffer module 30 uses a high-voltage MOSFET to generate the required drive voltage for the output power transistor M0, forming a negative feedback control loop to improve the stability and reliability of the linear regulator circuit 100. The capacitor C0 connected across the first resistor R1 in the resistor string is a compensation capacitor, which further ensures the stability of the regulator. An external filter capacitor Cload at the output terminal, typically with a capacitance greater than tens of nF, also contributes to the stability of the regulator circuit.

[0049] Figure 1 The provided voltage regulator circuit uses both N-type and P-type LDMOS. For some process platforms, additional mask layers are required for the P-type LDMOS, which is costly. Therefore, other embodiments make the following improvements based on Embodiment 1.

[0050] Example 2

[0051] The high-voltage to low-voltage linear regulator circuit 100 provided in this embodiment adds a second pre-regulator module 20 to the existing embodiment 1. It does not require a high-voltage P-type LDMOS and only requires three high-voltage N-type LDMOS. It does not require additional mask layers for the P-type LDMOS, thus reducing costs.

[0052] The second pre-regulator module 20 includes a second bias unit and a fourth MOSFET M4;

[0053] The second bias unit is used to generate the second bias voltage VB. The fourth MOSFET M4 obtains the second low-voltage power rail VINT6 under the drive of the second bias voltage VB. The second low-voltage power rail VINT6 is used to power the buffer module 30 and the power transistor M0.

[0054] The power transistor M0 at the output terminal does not need to use a high-voltage P-type LDMOS as in Example 1. In this application, the power transistor M0 can be implemented using only a 5V low-voltage transistor.

[0055] In this embodiment, the output voltage VOUT is divided by the voltage divider resistor string module 50 to obtain the divided voltage VFB. Then, the difference between the divided voltage VFB and the reference voltage VBG is amplified by the error amplifier 40 to the differential amplification voltage VEA, which is then transmitted to the gate VG of the power transistor M0 through the buffer module 30, forming a negative feedback control loop. The first pre-regulator module 10 is biased by the fifth resistor R5 and the first Zener diode D1, and generates an internal first low-voltage power rail VINT5 through the high-voltage N-type LDMOS (second MOS transistor M2) to power the error amplifier module 40. Therefore, the error amplifier module 40 can be implemented entirely with low-voltage transistors.

[0056] In the buffer module 30, the twelfth MOSFET M12 is a high-voltage N-type LDMOS, so the third MOSFET M3 can be implemented with a low-voltage MOSFET. The third resistor R3 can limit the output current of the regulator to K*(VEA-VGS) / R3, where K is the size ratio of the first MOSFET M1 and the power MOSFET M0.

[0057] The fourth resistor R4 is the pull-up resistor for the gate of the power transistor M0, ensuring that the power transistor is in the off state when the regulator is not started.

[0058] C0 is a compensation capacitor, which can ensure the stability of the voltage regulator.

[0059] In this embodiment, a second pre-regulator module 20 is added to generate a second low-voltage power rail VINT6 of 6V to 8V to power the buffer module 30 and the power transistor M0. Therefore, both the power transistor M0 and the PMOS transistor M1 in the buffer module 30 can be implemented using only 5V low-voltage transistors. For example, if VOUT normally outputs a low voltage of 5V, there will be no overvoltage between the ports of the power transistor M0.

[0060] like Figure 2 As shown, the second bias unit includes a sixth resistor R6, a second Zener diode D2, an eighth MOSFET M8, and a ninth MOSFET M9;

[0061] The two ends of the sixth resistor R6 are connected to the input voltage VIN and the cathode of the second Zener diode D2, respectively;

[0062] The anode of the second Zener diode D2 is connected to the drain of the eighth MOSFET M8;

[0063] The source of the eighth MOSFET M8 is connected to the drain of the ninth MOSFET M9, and the gate of the eighth MOSFET M8 is connected to the drain of the eighth MOSFET M9.

[0064] The drain of the ninth MOSFET M9 is connected to the gate of the ninth MOSFET M9, and the source of the ninth MOSFET M9 is connected to ground GND; the cathode of the second Zener diode D2 outputs the second bias voltage VB.

[0065] A bias circuit is formed by low-voltage NMOS transistors (eighth MOS transistor M8 and ninth MOS transistor M9) connected by the sixth resistor R6 and the second Zener diode D2, generating a second bias voltage VB. The second bias voltage VB is connected to the gate of the fourth MOS transistor M4. C2 is the voltage regulator capacitor for the second bias voltage VB.

[0066] In this embodiment, the buffer module 30 further includes a first MOS transistor M1 and a twelfth MOS transistor M12;

[0067] The source of the first MOSFET M1 is connected to the second low-voltage power supply rail VINT6;

[0068] The drain of the first MOSFET M1 is connected to the drain of the twelfth MOSFET M12;

[0069] The drain of the first MOSFET M1 is connected to the gate of the first MOSFET M1;

[0070] The gate of the first MOSFET M1 is connected to the gate of the power transistor M0;

[0071] The gate of the first MOSFET M1 is connected to the second low-voltage power supply rail VINT6.

[0072] The gate of the twelfth MOSFET M12 is connected to the first low-voltage power rail VINT5;

[0073] The source of the twelfth MOSFET M12 is connected to the drain of the third MOSFET M3;

[0074] The source of the third MOSFET M3 is connected to ground (GND).

[0075] The gate of the third MOSFET M3 is connected to the differential amplification voltage VEA.

[0076] To achieve the functions of soft start and current limiting, a third resistor R3 is added. That is, the source of the third MOSFET M3 is connected to ground GND through the third resistor R3. The output current of the voltage regulator circuit is limited to K*(VEA-VGS) / R3 by the third resistor R3, where K is the ratio of the size (width-to-length ratio) of the output power transistor M0 and the first MOSFET M1.

[0077] In some embodiments, the gate of the first MOSFET M1 is connected to the second low-voltage power rail VINT6 via a fourth resistor R4. The function of the fourth resistor R4 is to ensure that the gate of the output power transistor M0 is pulled up and kept in the off state when the voltage regulator circuit is not activated.

[0078] In this embodiment, without the need for a high-voltage P-type LDMOS, only three high-voltage N-type LDMOS transistors (the second MOSFET M2, the twelfth MOSFET M12, and the fourth MOSFET M4) are used to achieve the high-voltage to low-voltage conversion. Furthermore, the twelfth MOSFET M12 only requires an 8V withstand voltage device, which greatly reduces the cost.

[0079] Example 3

[0080] In Embodiment 2, the load current of the second low-voltage power rail VINT6 is mainly the current of the buffer module 30 and the power transistor M0. When the load current of the output voltage VOUT is small, the second low-voltage power rail VINT6 has no path for discharging current. When the input voltage VIN rises rapidly, it is coupled through the parasitic capacitance of the fourth MOSFET M4, which may cause overvoltage risk to the second low-voltage power rail VINT6. Therefore, in this embodiment, if... Figure 3 As shown, a clamping circuit is added to clamp the second low-voltage power rail VINT6 at a preset potential when the second low-voltage power rail VINT6 is higher than the second bias voltage VB.

[0081] like Figure 3 As shown, the clamping circuit consists of the 5V low-voltage transistor, the sixth MOSFET M6, and the seventh MOSFET M7.

[0082] The gate of the sixth MOSFET M6 is connected to the second bias voltage VB, the source of the sixth MOSFET M6 is connected to the source of the fourth MOSFET, the drain of the sixth MOSFET M6 is connected to the source of the seventh MOSFET M7, the gate of the seventh MOSFET M7 is connected to the gate of the eighth MOSFET M8, and the drain of the seventh MOSFET M7 is connected to ground GND.

[0083] When the source low-voltage power rail VINT6 of the sixth MOSFET M6 is higher than its gate second bias voltage VB by a threshold voltage, the sixth MOSFET M6 turns on, forming a discharge current path for the second low-voltage power rail VINT6, clamping the voltage of the second low-voltage power rail VINT6 to VB+VGS. Considering that the second bias voltage VB may reach as high as 9V when the input voltage VIN is high, a seventh MOSFET M7 is connected in series with the drain of the sixth MOSFET M6 to clamp the drain of the sixth MOSFET M6 to 3*VGS, protecting the sixth MOSFET M6 from overvoltage.

[0084] Example 4

[0085] Based on the voltage regulator circuit provided in Embodiment 2 or Embodiment 3, assuming the input voltage VIN ranges from 8V to 55V, and the output voltage VOUT needs to output a low voltage of 5V, when VIN = 8V and the load current of the output voltage VOUT is large (e.g., 50mA), the voltage of the second low-voltage power rail VINT6 may be too low, causing the output voltage VOUT to fail to output 5V. At this time, the voltage across the sixth resistor R6 is small, therefore the bias current of the second Zener diode D2 and the eighth MOSFET M8 and ninth MOSFET M9 is small, resulting in a low second bias voltage VB, a low second low-voltage power rail VINT6, and the power transistor M0 may enter the linear region.

[0086] To address this issue, in this embodiment, as follows: Figure 4 As shown, a low-voltage PMOS transistor, namely the fifth MOS transistor M5, is further added. The source of the fifth MOS transistor M5 is connected to the source of the fourth MOS transistor M4; the drain of the fifth MOS transistor M5 is connected to the gate of the eighth MOS transistor M8; and the gate of the fifth MOS transistor M5 is connected to the gate of the power transistor M0.

[0087] The fifth MOSFET M5 uses the same dimensions as the first MOSFET M1. Therefore, the current of the fifth MOSFET M5 is 1 / K of the load current of the power transistor M0. Injecting the current of the fifth MOSFET M5 into the eighth MOSFET M8 and the ninth MOSFET M9, which are connected to the second Zener diode D2, results in a larger load current for the power transistor M0, a larger current in the fifth MOSFET M5, a higher second bias voltage VB, and a higher second low-voltage power rail VINT6. This alleviates the voltage margin problem of the power transistor M0 and ensures that the regulator can output a low voltage of 5V normally across the entire range.

[0088] Example 5

[0089] The voltage regulator circuits provided in Embodiments 2, 3, and 4 above have solved the problem of the steady-state operating point of the voltage regulator in the absence of a high-voltage P-type LDMOS. However, when the system is powered on, the output voltage VOUT needs to be built up from 0 to the steady-state voltage, while the second low-voltage power rail VINT6 can be built up to 6V~8V quickly. During this process, the power transistor M0 still has the risk of overvoltage.

[0090] Therefore, based on the voltage regulator circuits provided in Embodiments 2, 3, or 4 above, this embodiment adopts a two-stage startup method, adding a power-on reset module 60 and a low-voltage transistor, the tenth MOSFET M10.

[0091] The drain of the tenth MOSFET M10 is connected to the drain of the eighth MOSFET M8, and the source of the tenth MOSFET M10 is connected to ground (GND).

[0092] The power-on reset module 60 includes a Schmitt trigger, a seventh resistor R7, and an eleventh MOSFET M11. The gate of the eleventh MOSFET M11 is connected to the voltage divider tap VDIV of the voltage divider resistor string module 50.

[0093] The source of the eleventh MOSFET M11 is connected to ground (GND).

[0094] The drain of the eleventh MOSFET M11 is pulled up to the first low-voltage power rail VINT5 through the seventh resistor R7. The drain of the eleventh MOSFET M11 is connected to the input of the Schmitt trigger, and the output of the Schmitt trigger is connected to the gate of the tenth MOSFET M10.

[0095] like Figure 5 As shown, when the output voltage VOUT is low, a high-level control signal NOK is generated, controlling the tenth MOSFET M10 to conduct, shorting the anode of the second Zener diode D2 to ground GND, ensuring that the second low-voltage power rail VINT6 is only about 5V at this time, so the power transistor M0 will not be overvoltaged. As the output voltage VOUT gradually rises to about 3V, the high-level control signal NOK goes low, raising the second low-voltage power rail VINT6 to 6V~8V, so there is sufficient voltage margin between the source and drain of the power transistor M0, which can continuously generate current and charge the output voltage VOUT to the steady-state voltage of 5V. During this process, the power transistor M0 will not be overvoltaged. This power-on reset module 60 is powered by the first low-voltage power rail VINT5 and consists of the seventh resistor R7, the eleventh low-voltage MOSFET M11, and a Schmitt trigger I0. The input terminal is connected to the middle voltage divider tap VDIV of the voltage divider resistor string module 50. When the output voltage VOUT is below 3V, the voltage divider tap VDIV is below the threshold voltage of the eleventh MOSFET M11, so the eleventh MOSFET M11 is turned off. The input terminal of the Schmitt trigger I0 is pulled up to the first low-voltage power rail VINT5 by the seventh resistor R7, and NOK is at a high level. When the output voltage VOUT is above 3V, the voltage divider tap VDIV is above the threshold voltage of the eleventh MOSFET M11, so the eleventh MOSFET M11 is turned on, pulling the input terminal of the Schmitt trigger I0 low, and the high-level control signal NOK is at a low level.

[0096] Figure 6 This is a schematic diagram of the waveform of the linear voltage regulator circuit 100 provided in Embodiment 5 of this application after normal power-on. Figure 6 0~t1: Input voltage VIN is powered on, and the internal first low-voltage power rail VINT5 and second low-voltage power rail VINT6 synchronously begin to establish 5V. The regulator starts working, and the output voltage VOUT gradually rises from 0. At this time, the output voltage VOUT is below 3V, and NOK is at a high level.

[0097] t1~t2: The first low-voltage power rail VINT5 and the second low-voltage power rail VINT6 are powered on to 5V, and the high-level control signal NOK is a stable 5V high level.

[0098] t2: The output voltage VOUT rises to 3V, the high-level control signal NOK jumps to low level, and the second low-voltage power rail VINT6 continues to rise to 6V~8V.

[0099] t4: The output voltage VOUT is powered up to 5V, and the voltage regulator is established.

[0100] It is easy to see that the voltage difference between the second low-voltage power rail VINT6 and the output voltage VOUT will not exceed 5V throughout the entire process, so the power transistor M0 will not be over-voltaged.

[0101] Example 6

[0102] This embodiment provides an electronic device 200, such as... Figure 7 As shown, it includes: the linear voltage regulator circuit 100 provided in the above embodiments. The electronic device 200 provided in this application can reduce the number of high-voltage MOSFETs, reduce the power consumption and area of ​​the voltage regulator circuit, and effectively reduce costs.

[0103] It should be understood that the above description is for illustrative purposes and not for limitation. Many embodiments and applications beyond the provided examples will be apparent to those skilled in the art upon reading the above description. Therefore, the scope of this teaching should not be determined by reference to the above description, but rather by reference to the foregoing claims and the full scope of their equivalents. For purposes of completeness, all articles and references, including patent applications and publications, are incorporated herein by reference. The omission of any aspect of the subject matter disclosed herein in the foregoing claims is not intended as a waiver of that subject matter, nor should it be construed as an indication that the applicant has not considered that subject matter as part of the disclosed application subject matter.

Claims

1. A high-voltage to low-voltage linear voltage regulator circuit (100), characterized in that, include: Power transistor M0 is used to output the output voltage VOUT of the linear regulator circuit (100); The voltage divider resistor string module (50) is used to divide the output voltage VOUT through a resistor string to obtain the voltage divider VFB; Error amplifier module (40) is used to amplify the difference between the voltage divider VFB and the reference voltage VBG to obtain the difference amplification voltage VEA; The buffer module (30) includes a third MOS transistor M3. The buffer module (30) is used to drive the third MOS transistor M3 with the differential amplification voltage VEA to amplify the differential amplification voltage VEA. The signal is transmitted to the gate of the power transistor M0; The first pre-regulator module (10) includes a first bias unit and a second MOS transistor M2. The first bias unit is used to generate a first bias voltage. The second MOS transistor M2 obtains a first low-voltage power rail VINT5 under the drive of the first bias voltage. The first low-voltage power rail VINT5 is used to power the error amplifier module (40). The second pre-regulator module (20) includes a second bias unit, a fourth MOSFET M4, and a clamping circuit. The second bias unit is used to generate a second bias voltage VB based on the input voltage VIN. The fourth MOSFET M4 obtains a second low-voltage power rail VINT6 under the drive of the second bias voltage VB. The second low-voltage power rail VINT6 is used to supply power to the buffer module (30) and the power transistor M0. The clamping circuit is used to clamp the second low-voltage power rail VINT6 at a preset potential when the second low-voltage power rail VINT6 is higher than the second bias voltage VB.

2. The high-voltage to low-voltage linear voltage regulator circuit (100) according to claim 1, characterized in that, The first bias unit includes a first Zener diode D1 and a fifth resistor R5; One end of the fifth resistor R5 is connected to the input voltage VIN, and the other end is connected to the cathode of the first Zener diode D1; The anode of the first Zener diode D1 is connected to ground GND, and the cathode of the first Zener diode D1 is connected to the gate of the second MOSFET M2. The drain of the second MOSFET M2 is connected to the input voltage VIN, and the source of the second MOSFET M2 outputs the first low-voltage power rail VINT5.

3. The high-voltage to low-voltage linear voltage regulator circuit (100) according to claim 2, characterized in that, The second bias unit includes a sixth resistor R6, a second Zener diode D2, an eighth MOSFET M8, and a ninth MOSFET M9; One end of the sixth resistor R6 is connected to the input voltage VIN, and the other end is connected to the cathode of the second Zener diode D2; The anode of the second Zener diode D2 is connected to the drain of the eighth MOS transistor M8; The gate of the eighth MOS transistor M8 is connected to the drain of the eighth MOS transistor M8; The source of the eighth MOS transistor M8 is connected to the drain of the ninth MOS transistor M9; The drain of the ninth MOS transistor M9 is connected to the gate of the ninth MOS transistor M9. The source of the ninth MOS transistor M9 is connected to ground GND; The cathode of the second Zener diode D2 outputs the second bias voltage VB.

4. The high-voltage to low-voltage linear voltage regulator circuit (100) according to claim 3, characterized in that, The second pre-regulator module (20) also includes a fifth MOSFET M5; The source of the fifth MOS transistor M5 is connected to the source of the fourth MOS transistor M4; The drain of the fifth MOS transistor M5 is connected to the gate of the eighth MOS transistor M8; The gate of the fifth MOS transistor M5 is connected to the gate of the power transistor M0.

5. The high-voltage to low-voltage linear voltage regulator circuit (100) according to claim 4, characterized in that, The second pre-regulator module (20) also includes a tenth MOSFET M10 and a power-on reset module (60). The drain of the tenth MOS transistor M10 is connected to the drain of the eighth MOS transistor M8, and the source of the tenth MOS transistor M10 is connected to ground (GND). The power-on reset module (60) includes a Schmitt trigger, a seventh resistor R7 and an eleventh MOS transistor M11, the gate of the eleventh MOS transistor M11 being connected to the voltage divider tap VDIV of the voltage divider resistor string module (50). The source of the eleventh MOS transistor M11 is connected to ground GND; The drain of the eleventh MOS transistor M11 is pulled up to the first low-voltage power rail VINT5 through the seventh resistor R7. The drain of the eleventh MOS transistor M11 is connected to the input terminal of the Schmitt trigger, and the output terminal of the Schmitt trigger is connected to the gate of the tenth MOS transistor M10.

6. The high-voltage to low-voltage linear voltage regulator circuit (100) according to claim 2, characterized in that, The buffer module (30) also includes a first MOS transistor M1 and a twelfth MOS transistor M12; The source of the first MOSFET M1 is connected to the second low-voltage power supply rail VINT6; The drain of the first MOS transistor M1 is connected to the drain of the twelfth MOS transistor M12; The drain of the first MOS transistor M1 is connected to the gate of the first MOS transistor M1; The gate of the first MOS transistor M1 is connected to the gate of the power transistor M0; The gate of the first MOSFET M1 is connected to the second low-voltage power supply rail VINT6; The gate of the twelfth MOS transistor M12 is connected to the first low-voltage power rail VINT5. The source of the twelfth MOS transistor M12 is connected to the drain of the third MOS transistor M3; The source of the third MOS transistor M3 is connected to ground (GND). The gate of the third MOS transistor M3 is connected to the differential amplification voltage VEA.

7. The high-voltage to low-voltage linear voltage regulator circuit (100) according to claim 6, characterized in that, The gate of the first MOSFET M1 is connected to the second low-voltage power rail VINT6 via a fourth resistor.

8. An electronic device (200), characterized in that, include: The high-voltage to low-voltage linear voltage regulator circuit (100) as described in any one of claims 1-7.

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