FPGA-based queue message dynamic chain control method

Abstract

The application discloses a kind of queue message dynamic chain control method based on FPGA, specifically includes the following steps: step 1: establishing message frame buffer area, local message head and tail table, local message link list, free pointer pool and state information register;Message frame buffer area is used to store message frame;Local message head and tail table are used to store the head pointer and tail pointer of real-time message ID cache;Local message link list is used to store the pointer between head pointer and tail pointer;Free pointer pool is a FIFO;State information register indicates the state of the message buffer area corresponding to the message ID being accessed by host;Step 2: message cache write management;Step 3: message cache reading management.In the application, software does not need to manage queue message again, greatly reduces the pressure of host software processing, and meets dynamic and real-time.

Description

TECHNICAL FIELD

[0001] The application belongs to the field of computer network, and particularly relates to a queue message dynamic chain control method based on FPGA. BACKGROUND

[0002] In recent years, with the gradual strengthening of the requirements of industrial control and aerospace fields on the efficiency, reliability, stability and safety of data bus, the 1394 bus gradually gets wide application due to the above advantages. The 1394 bus has the characteristics of large bandwidth, low delay, strong anti-interference ability, good transmission stability, support for hot plug, flexible topology structure and support for point-to-point tree connection mode.

[0003] The implementation mode of the 1394 bus generally adopts FPGA as the middleware for data interaction between the host and the PHY. The FPGA realizes sending management in the sending process and realizes receiving management in the receiving process. In general design, double buffers are used in the FPGA for data management. The FPGA actually only plays a role of interface conversion in the system, and the receiving buffer management and the sending buffer management are completed by the host. With the continuous expansion of the message service type, the performance requirement of the host is higher and higher, and if the host is replaced, the cost is also very large. SUMMARY

[0004] The application aims to provide a queue message dynamic chain control method based on FPGA to solve the problems in the prior art, meet the determinacy and real-time requirement of different equipment for processing queue control messages and reduce the pressure of the host for processing queue messages.

[0005] In order to achieve the above task, the application adopts the following technical scheme:

[0006] A queue message dynamic chain control method based on FPGA, specifically comprising the following steps:

[0007] Step 1: establishing a message frame buffer area, a local message head and tail table, a local message link list, an idle pointer pool and a state information register; wherein:

[0008] The message frame buffer area is used for storing message frames;

[0009] The local message head and tail table is used for storing the head pointer and the tail pointer of the real-time message ID cache, representing the positions of the head frame message and the tail frame message corresponding to the message ID in the cache space of the message buffer area;

[0010] The local message link list is used for storing the pointers between the head pointer and the tail pointer, representing the positions of other frame messages of the message ID except the head frame message and the tail frame message in the cache space of the message buffer area;

[0011] Idle pointer pool is a FIFO;

[0012] The state information register indicates the state of the message buffer corresponding to the message ID being accessed by the host, the 0th bit indicates that the space in the message buffer corresponding to the message ID being accessed by the host is empty, the 1st bit indicates that the message buffer corresponding to the message ID being accessed by the host is not empty, the 2nd bit indicates that the message buffer corresponding to the message ID being accessed by the host is full, and the 3rd-31st bits are reserved and filled with 0;

[0013] Step 2: message buffer write management, including the following sub-steps:

[0014] Step 2-1: parse the received data frame to obtain its message ID;

[0015] Step 2-2: read the idle pointer pool FIFO to obtain a block number A; if the idle pointer pool FIFO has been read empty, do not write data, the obtained block number A is invalid, and the received data frame is discarded; otherwise, execute step 2-3;

[0016] Step 2-3: write the received data frame into the empty block number A obtained in step 2-2.

[0017] Step 2-4: read the local message header and tail table according to the message ID of the data frame parsed in step 2-1 to obtain the tail block number B of the message ID; then replace the tail block number B in the local message header and tail table with the block number A, and increase the message count value in the local message header and tail table by 1;

[0018] Step 2-5: fill the content of the next block number corresponding to the base address B of the local message link table with A; at this point, the content of the next block number corresponding to the base address A of the local message link table is filled with A, which represents the tail block number corresponding to the base address A; message buffer write management ends.

[0019] Step 3: message buffer read management, including the following sub-steps:

[0020] Step 3-1: the host issues a message ID to be read;

[0021] Step 3-2: after the FPGA side host access point module receives the message ID read instruction, the FPGA side host access point module reads the local message header and tail table according to the message ID to obtain the message count value C in the local message header and tail table and the head block number D in the local message header and tail table;

[0022] If the message count value C is 0, it means that there is no data frame corresponding to the message ID in the message frame buffer, then fill in the state information register corresponding to the message ID: the 2nd bit is 0, the 1st bit is 0, and the 0th bit is 1;

[0023] If the message count value C is not 0, representing that there is a data frame corresponding to the message ID in the message buffer area, the state information register corresponding to the message ID is filled: the 2nd bit is filled with 01 according to whether the space in the buffer area corresponding to the message ID is full, the 1st bit is 1, and the 0th bit is 0;

[0024] The host access point module reports to the host whether there is state information of the data frame corresponding to the message ID in the message frame buffer area according to the value of the state information register, if the host receives the state information of the data frame, the reading of the data frame of the message ID is stopped; if the host receives the state information of no data frame, step 3-3 is executed;

[0025] Step 3-3: according to the message ID, the local message head and tail table is searched, the head block number D corresponding to the message ID is read, the data frame in the message buffer area corresponding to the head block number D is read, and the host is transmitted through the host access point module;

[0026] Step 3-4: after a frame of data is read, the local message chain table is read using the head block number D as an address to obtain the value E in the next block number corresponding to the head block number D of the message ID;

[0027] Step 3-5: the local message head and tail table is updated. The message count value in the local message head and tail table is updated to C-1, the head block number is updated from D to E, and the head block number D is written into the free pointer pool FIFO, and the message reading buffer management ends.

[0028] Further, the message frame buffer area has 128 buffer spaces, and each buffer space is 2KB in size.

[0029] Further, 1-128 numbers are written in the FIFO during initialization, indicating that the 128 buffer spaces in the message buffer area are empty at the beginning.

[0030] Compared with the prior art, the beneficial effects of the present application are as follows:

[0031] 1. The present application uses FPGA to realize queue message receiving buffer management, FPGA classifies frames of different message IDs, and stores them in a dynamic buffer management unit according to the message ID. Software only needs to configure the message ID to be read to read the message. Software does not need to manage the queue message, greatly reducing the pressure of host software processing, and meeting the dynamic and real-time requirements.

[0032] 2. The present application adopts dynamic chain buffer management, which can maximize the support of the number of messages under limited FPGA resources. If a fixed buffer space is used for each message ID, the FPGA internal buffer resource will not be enough when the number of message IDs increases.

[0033] 3、The dynamic cache management mode adopted by the application uses the storage resource inside the FPGA to store the message, which is enough, and does not need to use the storage outside the chip, thereby reducing the cost. BRIEF DESCRIPTION OF DRAWINGS

[0034] Figure 1 is the overall design block diagram of the method of the application;

[0035] Figure 2 is the format of the local message head and tail table;

[0036] Figure 3 is the format of the local message chain table;

[0037] Figure 4 is the format of the idle pointer pool;

[0038] Figure 5 is the format of the state information definition.

[0039] The application is further explained in the following in combination with the drawings and specific embodiments. DETAILED DESCRIPTION

[0040] Embodiment 1:

[0041] The design block diagram of the embodiment is shown in Figure 1 The FPGA-based queue message dynamic receiving chain control method provided by the embodiment takes the 1394 asynchronous stream packet as an example and specifically includes the following steps:

[0042] Step 1: Establishing a message frame cache area, a local message head and tail table, a local message chain table, an idle pointer pool and a state information register.

[0043] The message frame cache area is used to store message frames. The message frame cache area has 128 cache spaces and can store a maximum of 128 message frames. Each cache space is 2KB in size.

[0044] The local message head and tail table is used to store the head pointer and the tail pointer of the real-time message ID cache, representing the specific positions of the head frame message and the tail frame message corresponding to the message ID in the 128 cache spaces of the message cache area. As shown in Figure 2 . Figure 2 In the table, the initial value of the message count value is 0 and the value range is 1-128.

[0045] The local message chain table is used to store the pointers between the head pointer and the tail pointer, representing the specific positions of the other frame messages of the message ID except the head frame message and the tail frame message in the 128 cache spaces. As shown in Figure 3 .

[0046] Idle pointer pool is a FIFO, when initialized, 1-128 numbers are written in the FIFO, indicating that 128 cache spaces in the message buffer area are empty at the beginning. As shown in Figure 4 .

[0047] Status information register indicates the status of the message buffer area corresponding to the message ID being accessed by the host, the 0th bit indicates that the space in the message buffer area corresponding to the message ID being accessed by the host is empty, the 1st bit indicates that the message buffer area corresponding to the message ID being accessed by the host is not empty, the 2nd bit indicates that the message buffer area corresponding to the message ID being accessed by the host is full, and the 3rd-31st bits are reserved and filled with 0. As shown in Figure 5 .

[0048] Step 2: Message buffer write management.

[0049] Step 2-1: Analyze the received data frame to obtain its message ID.

[0050] Step 2-2: Read the idle pointer pool FIFO to obtain a block number A; if the idle pointer pool FIFO has been read empty, it means that all 128 cache spaces have been full at this time, no longer write data, the obtained block number A is invalid, and the received data frame is discarded; otherwise, execute step 2-3;

[0051] Step 2-3: Write the received data frame into the empty block number A obtained in step 2-2.

[0052] Step 2-4: Read the local message header and tail table according to the message ID of the data frame parsed in step 2-1 to obtain the tail block number B of the message ID; then replace the tail block number B in the local message header and tail table with the block number A, and add 1 to the message count value in the local message header and tail table;

[0053] Step 2-5: Fill the content of the next block number corresponding to the base address B of the local message link table with A; at this time, fill the content of the next block number corresponding to the base address A of the local message link table with A, which represents that the base address A is the tail block number corresponding to the message ID; message buffer write management ends.

[0054] Step 3: Message buffer read management.

[0055] Step 3-1: The host issues a message ID to be read.

[0056] Step 3-2: After the FPGA side host access point module receives the message ID read instruction, the FPGA side host access point module reads the local message header and tail table according to the message ID to obtain the message count value C in the local message header and tail table and the head block number D in the local message header and tail table;

[0057] If the message count value C is 0, representing that there is no data frame corresponding to the message ID in the message frame buffer area, the state information register corresponding to the message ID is filled: the 2nd bit is 0, the 1st bit is 0, and the 0th bit is 1;

[0058] If the message count value C is not 0, representing that there is a data frame corresponding to the message ID in the message buffer area, the state information register corresponding to the message ID is filled: the 2nd bit is filled with 01 according to whether the space in the buffer area corresponding to the message ID is full, the 1st bit is 1, and the 0th bit is 0.

[0059] The host access point module reports to the host the state information of whether there is a data frame corresponding to the message ID in the message frame buffer area according to the value of the state information register. If the host receives the state information of having a data frame, the host stops reading the data frame of the message ID; if the host receives the state information of not having a data frame, step 3-3 is performed.

[0060] Step 3-3: According to the message ID, the local message head and tail table is searched, the head block number D corresponding to the message ID is read, the data in the message buffer area corresponding to the head block number D is read, and the host is transmitted through the host access point module.

[0061] Step 3-4: After a frame of data is read, the local message chain table is read using the head block number D as an address to obtain the value E in the next block number corresponding to the head block number D of the message ID;

[0062] Step 3-5: The local message head and tail table is updated. The message count value in the local message head and tail table is updated to C-1, the head block number is updated from D to E (i.e. the next one becomes the head block number), and the head block number D is written into the free pointer pool FIFO (indicating that the content in the message buffer area corresponding to D is empty). Thus, the message read buffer management is completed.

[0063] In order to verify the feasibility and effectiveness of the application, the application gives the following application examples:

[0064] In the actual application of 1394, the customer requires that the 1394 network card of the applicant supports at least 512 message ID numbers. According to the conventional design method, 2KB of cache is set for each message ID, so 512 message IDs require 1024KB of cache. Such a large cache space must use a FPGA with more resources, which is higher in cost and power consumption. If the cache is placed in software, not only the software development amount is increased, but also the real-time performance of message sending and receiving processing is reduced. Using the method of the application, the cache can be made into 256KB, and dynamic chain control is adopted, which can effectively reduce the FPGA cache requirement, reduce the hardware cost and the power consumption of the network card, reduce the software development workload, and improve the accuracy of message scheduling.

Claims

1. A dynamic chained control method for queued messages based on FPGA, characterized in that, Specifically, the steps include the following: Step 1: Establish a message frame buffer, local message header and tail table, local message linked list, free pointer pool, and status information register; where: The message frame buffer is used to store message frames; The local message header and tail table is used to store the head and tail pointers of the real-time message ID cache, representing the location of the message ID header and tail frame messages corresponding to the message in the cache space of the message cache area; The local message list is used to store the pointer between the head pointer and the tail pointer, which represents the location of the message ID in the cache space of the message buffer, excluding the head frame message and the tail frame message; The free pointer pool consists of one FIFO. The status information register indicates the status of the message buffer corresponding to the message ID that the host is accessing. Bit 0 indicates that the space in the message buffer corresponding to the message ID that the host is accessing is empty, bit 1 indicates that the message buffer corresponding to the message ID that the host is accessing is not empty, bit 2 indicates that the message buffer corresponding to the message ID that the host is accessing is full, and bits 3-31 are reserved and filled with 0. Step 2: Message cache write management, including the following sub-steps: Step 2-1: Parse the received data frame to obtain its message ID; Step 2-2: Read the free pointer pool FIFO and obtain an empty block number A; if the free pointer pool FIFO has been read empty, no more data will be written, the obtained block number A will be invalid, and the received data frame will be discarded; otherwise, proceed to step 2-3. Step 2-3: Write the received data frame into the empty block number A obtained in Step 2-2; Step 2-4: Read the local message header and tail table based on the message ID of the data frame parsed in Step 2-1, and obtain the tail block number B of the message ID; then replace the tail block number B in the local message header and tail table with block number A, and increment the message count value in the local message header and tail table by 1. Steps 2-5: Fill in the content of the next block number corresponding to the base address B of the local message chain with A; at this point, filling in the content of the next block number corresponding to the base address A of the local message chain with A means that the base address A contains the tail block number corresponding to the message ID; message cache write management is complete; Step 3: Message cache read management, including the following sub-steps: Step 3-1: The host sends the message ID that needs to be read; Step 3-2: After receiving the message ID read instruction, the FPGA-side host access point module reads the local message header and footer table according to the message ID, and obtains the message count value C and the header block number D in the local message header and footer table. If the message count value C is 0, it means that there is no data frame corresponding to the message ID in the message frame buffer. Then fill in the status information register corresponding to the message ID: the second position is 0, the first position is 0, and the 0th position is 1. If the message count value C is not 0, it means that there is a data frame corresponding to the message ID in the message buffer. Then fill the status information register corresponding to the message ID: the second bit is filled with 01 according to whether the space in the buffer corresponding to the message ID is full, the first bit is set to 1, and the 0th bit is set to 0. The host access point module reports to the host whether there is a cached data frame corresponding to the message ID in the message frame buffer based on the value of the status information register. If the host receives the status information that there is a data frame, it stops reading the data frame of the message ID; if the host receives the status information that there is no data frame, it executes step 3-3. Step 3-3: Look up the local message header and footer table based on the message ID, read the header block number D corresponding to the message ID, read the data frame in the message buffer corresponding to the header block number D, and transmit it to the host through the host access point module; Steps 3-4: After a frame of data is read, use the header block number D as the address to read the local message list and obtain the value E in the next block number corresponding to the message ID header block number D; Steps 3-5: Update the local message header and tail table. Update the message count value in the local message header and tail table to C-1, update the header block number from D to E, and write the header block number D into the free pointer pool FIFO. The message read cache management ends here.

2. The FPGA-based dynamic chained control method for queued messages as described in claim 1, characterized in that, The message frame buffer has 128 buffer spaces, each with a size of 2KB.

3. The FPGA-based dynamic chained control method for queued messages as described in claim 2, characterized in that, During initialization, numbers 1-128 are written into the FIFO to indicate that the 128 buffer spaces in the message buffer area are empty at the beginning.

Images