Redundant pixel circuit, display panel and manufacturing and driving method thereof, and display device

Abstract

The application discloses a kind of for compensating display circuit redundancy pixel circuit, display panel and its manufacturing method and driving method, and display device, the redundancy pixel circuit of the embodiment of the application includes: including first transistor, second transistor and first capacitor redundancy pixel circuit, and the first electrode of first transistor is electrically connected to first node, second electrode is electrically connected to reset signal end, control electrode is electrically connected to redundancy reset control end, the first electrode of second transistor is electrically connected to data signal end, second electrode is electrically connected to first node, control electrode is electrically connected to redundancy row scanning end, the first end of first capacitor is electrically connected to first power signal end, second end is electrically connected to first node, and it is arranged between first power signal end and reset signal end of display circuit, to generate parasitic compensation using redundancy pixel circuit in the driving current of display circuit, can improve display unevenness, improve display effect, with wide application prospect.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of display, in particular to a redundant pixel circuit for compensating display circuit, a display panel and a manufacturing method and a driving method thereof, and a display device. BACKGROUND

[0002] In a display product, a display panel includes a plurality of light emitting units, each of which is driven to emit light by a pixel driving unit, and each pixel driving unit corresponding to a row of light emitting units generates a driving current under the control of a row scanning signal output by a gate driver on array (GOA).

[0003] With the development of display technology, in order to improve the switching transistor hysteresis and fixed gaze point rendering (FFR) of the display product, the GOA is usually controlled to scan the corresponding row of pixel driving units with multiple scanning signals, that is, in each row scanning process, the row scanning end of the corresponding row of pixel driving units continuously receives a row scanning signal with multiple effective levels, which in turn causes the light emitting units in each row to be parasitically disturbed multiple times. The driving current of each row of light emitting units is the result of multiple parasitic effects. This will cause the parasitic disturbance of the last few rows of pixel units to be inconsistent with that of other rows, resulting in inconsistent display brightness and visual virtual edge quality problems. SUMMARY

[0004] To solve at least one of the above problems, the first aspect of the present application provides a redundant pixel circuit for compensating a display circuit,

[0005] The display circuit includes a plurality of pixel circuits, each of which includes a light emitting unit and a pixel driving unit for driving the light emitting unit to emit light, and the pixel driving unit includes a driving control module and a reset module, wherein the driving control module generates a driving current based on signals input from a data signal end, a row scanning end, a light emitting control end and a first power signal end, and drives the light emitting unit to emit light, and the reset module resets the pixel driving unit based on signals input from a reset control end and a reset signal end,

[0006] The redundant pixel circuit includes a first transistor, a second transistor and a first capacitor, wherein

[0007] The first electrode of the first transistor is electrically connected to a first node, the second electrode is electrically connected to a reset signal end, and the control electrode is electrically connected to a redundant reset control end,

[0008] The first electrode of the second transistor is electrically connected to a data signal end, the second electrode is electrically connected to the first node, and the control electrode is electrically connected to a redundant row scanning end,

[0009] The first end of the first capacitor is electrically connected to a first power signal end, and the second end is electrically connected to the first node.

[0010] The second aspect of the present application provides a display panel, comprising: a display circuit and at least one redundant pixel circuit as described above, wherein

[0011] The display circuit comprises: a plurality of pixel circuits, each pixel circuit comprising a light emitting unit and a pixel driving unit driving the light emitting unit to emit light, the pixel driving unit comprising a driving control module and a reset module, wherein the driving control module generates a driving current based on signals input from a data signal terminal, a row scan terminal and a first power signal terminal, and drives the light emitting unit to emit light, and the reset module resets the pixel driving unit based on signals input from a reset control terminal and a reset signal terminal.

[0012] In some optional embodiments, the display panel comprises an array of light emitting units, wherein

[0013] The at least one redundant pixel circuit is M, and the row scan terminal of the pixel circuit is driven by N low-level signals, wherein

[0014] M = A x B, A = 2N-2, A represents the number of rows of the redundant pixel circuit, B represents the number of columns of the redundant pixel circuit, which is equal to the number of columns of the light emitting units, A, B, M and N are positive integers, and N is greater than 1.

[0015] In some optional embodiments, the display panel comprises a driving circuit layer and a light emitting unit layer arranged in sequence on a substrate, the driving circuit layer comprises a gate layer and a metal wiring layer arranged on the gate layer, and the first capacitor comprises a first plate and a second plate, wherein

[0016] The gate of the first transistor, the gate of the second transistor, and the first plate are arranged in the gate layer, the second plate is arranged in the metal wiring layer, and

[0017] One of the first plate and the second plate leads out a first end of the first capacitor, and the other leads out a second end of the first capacitor.

[0018] In some optional embodiments, the driving control module comprises: an input submodule, a driving submodule, a first light emitting control submodule, and a second light emitting control submodule, wherein

[0019] The input submodule comprises a first terminal, a second terminal and a control terminal, wherein the control terminal of the input submodule is electrically connected to the row scan terminal, the first terminal of the input submodule is electrically connected to the data signal terminal, and the second terminal of the input submodule is electrically connected to the second node, and is configured to write the signal input from the data signal terminal to the second node in response to the row scan signal input from the row scan terminal;

[0020] The driving submodule includes a first end, a second end, a third end and a fourth end, wherein the first end of the driving submodule is electrically connected to the first power signal end, the second end of the driving submodule is electrically connected to the second node, the third end of the driving submodule is electrically connected to the third node, and the fourth end of the driving submodule is electrically connected to the fourth node, and the driving submodule is configured to turn on the second node and the fourth node according to the voltage of the third node to form a driving current.

[0021] The first light-emitting control submodule includes a first end, a second end and a control end, wherein the first end of the first light-emitting control submodule is electrically connected to the first power signal end, the second end of the first light-emitting control submodule is electrically connected to the second node, and the control end of the first light-emitting control submodule is electrically connected to the light-emitting control end, and the first light-emitting control submodule is configured to turn on the first end and the second end of the first light-emitting control submodule in response to a signal input to the light-emitting control end to input the first power signal.

[0022] The second light-emitting control submodule includes a first end, a second end and a control end, wherein the first end of the second light-emitting control submodule is electrically connected to the fourth node, the second end of the second light-emitting control submodule is electrically connected to the second power signal end, and the control end of the second light-emitting control submodule is electrically connected to the light-emitting control end, and the second light-emitting control submodule is configured to turn on the first end and the second end of the second light-emitting control submodule in response to a signal input to the light-emitting control end to transmit the driving current to the light-emitting unit.

[0023] In some optional embodiments, the driving submodule includes a third transistor, a fourth transistor and a second capacitor, the first electrode of the third transistor is electrically connected to the second node, the second electrode is electrically connected to the fourth node, and the control electrode is electrically connected to the third node, the first electrode of the fourth transistor is electrically connected to the fourth node, the second electrode is electrically connected to the third node, and the control electrode is electrically connected to the row scan end, and the first end of the second capacitor is electrically connected to the first power signal end, and the second end is electrically connected to the third node.

[0024] In some optional embodiments, the capacitance value of the first capacitor is equal to the capacitance value of the second capacitor.

[0025] In some optional embodiments, the reset module includes a fifth transistor, the fifth transistor includes a first electrode, a second electrode and a control electrode, the first electrode is electrically connected to the third node, the second electrode is electrically connected to the reset signal end, and the control electrode is electrically connected to the reset control end, and the fifth transistor is configured to reset the voltage of the third node by using a signal input to the reset signal end in response to a signal input to the reset control end.

[0026] The third aspect of the present application provides a display device including the display panel described above.

[0027] The fourth aspect of the present application provides a driving method for the display panel described above, the display panel comprising M1 rows of pixel circuits and A rows of redundant pixel circuits, the sum of M1 and A being equal to the number of output ends of the gate driving circuit, the gate driving circuit being configured to provide signals to the row scanning end and the redundant row scanning end, M1 and A being positive integers, M1 being greater than 1,

[0028] In driving the m1th row of pixel circuits and the ath row of redundant pixel circuits, wherein m1=M1-A+a, a=1, 2, …, A, the driving method comprises:

[0029] a reset stage: the redundant pixel circuit resets the voltage of the first node by using the signal of the reset signal end in response to the signal inputted by the reset control end;

[0030] a charging and compensation stage:

[0031] the driving control module charges the second capacitor according to the signals inputted by the row scanning end and the data signal end, and the redundant pixel circuit charges the first capacitor according to the signals inputted by the redundant row scanning end and the data signal end to compensate the pixel circuit;

[0032] a light emitting control stage: the driving control module generates a driving current according to the signals inputted by the data signal end, the row scanning end, the light emitting control end and the first power signal end, and drives the light emitting unit to emit light.

[0033] The fifth aspect of the present application provides a manufacturing method of the display panel described above, comprising:

[0034] providing a substrate,

[0035] forming a driving circuit layer and a light emitting unit layer on the substrate in sequence, the driving circuit layer comprising a gate layer and a metal wiring layer arranged on the gate layer, and the first capacitor comprising a first plate and a second plate, wherein

[0036] the gate of the first transistor, the gate of the second transistor and the first plate are arranged in the gate layer, and the second plate is arranged in the metal wiring layer, and

[0037] one of the first plate and the second plate leads out the first end of the first capacitor, and the other leads out the second end of the first capacitor.

[0038] The beneficial effects of the present application are as follows:

[0039] The present application aims at the existing problems, and formulates a redundant pixel circuit for compensating a display circuit, a display panel and a manufacturing method and a driving method thereof, and a display device. The redundant pixel circuit including a first transistor, a second transistor and a first capacitor is provided between a first power signal end and a reset signal end of the display circuit, the first electrode of the first transistor is electrically connected to a first node, the second electrode is electrically connected to the reset signal end, and the control electrode is electrically connected to a redundant reset control end, the first electrode of the second transistor is electrically connected to a data signal end, the second electrode is electrically connected to the first node, and the control electrode is electrically connected to a redundant row scanning end, the first end of the first capacitor is electrically connected to the first power signal end, and the second end is electrically connected to the first node. Thus, the driving current in the display circuit is parasitically compensated by the redundant pixel circuit, the display unevenness is improved, the display effect is improved, and the application prospect is wide. BRIEF DESCRIPTION OF DRAWINGS

[0040] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the embodiment description will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without any creative effort.

[0041] Figure 1 A circuit schematic diagram of a conventional pixel circuit is shown;

[0042] Figure 2 A schematic row scanning signal timing diagram of multi-scanning signal driving of a conventional pixel circuit is shown;

[0043] Figure 3 A virtual edge display phenomenon generated in a driving display process in the related art is shown;

[0044] Figure 4 A pixel circuit block diagram according to an embodiment of the present application and a redundant pixel circuit for compensating the pixel circuit are shown;

[0045] Figure 5 A circuit schematic diagram of a pixel circuit and its redundant pixel circuit according to an embodiment of the present application is shown;

[0046] Figure 6 A key port timing diagram of a redundant pixel circuit according to an embodiment of the present application is shown;

[0047] Figure 7 A schematic timing diagram of a GOA output end connected with a row scanning end and a redundant row scanning end in a display panel according to an embodiment of the present application is shown;

[0048] Figure 8 A partial cross-sectional view of a redundant pixel circuit according to an embodiment of the present application is shown; and

[0049] Figures 9 to 15 A method flow chart for manufacturing the display panel of the present application is shown. DETAILED DESCRIPTION

[0050] In order to more clearly illustrate the present application, the present application will be further described below with reference to the preferred embodiments and accompanying drawings. Like reference numerals in the drawings denote like elements throughout. It should be understood by those skilled in the art that the specific description given below is merely illustrative and non-limiting and should not be construed as limiting the scope of the present application.

[0051] It should be noted that unless otherwise defined, technical terms or scientific terms used in the present disclosure should be understood as having the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terms "first", "second" and similar terms used in the present disclosure do not denote any order, quantity or importance, but are only used to distinguish different components. Similarly, the terms "one", "a" or "the" and similar terms do not denote a quantity restriction, but mean that there is at least one. The terms "include" or "contain" and similar terms mean that the elements or objects before the terms encompass the elements or objects listed after the terms and their equivalents, and do not exclude other elements or objects. The terms "connected" or "connected" and similar terms are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect.

[0052] In addition, in the present application, the term "disposed in the same layer" means that two layers, components, members, elements or parts can be formed by the same preparation process (such as a patterning process, etc.), and the two layers, components, members, elements or parts are generally formed of the same material. For example, two or more functional layers disposed in the same layer means that these functional layers disposed in the same layer can be formed using the same material layer and the same preparation process, so that the preparation process of the display substrate can be simplified.

[0053] Before the embodiments of the present application are described, the problems existing in the conventional display panel in the related art will be further described in combination with the pixel circuit structure features and the multi-scan driving principle.

[0054] As shown in FIG. 1, the display panel 100 includes a plurality of pixel units 110, a plurality of scan lines 120, a plurality of data lines 130, a plurality of scan driving lines 140, and a plurality of data driving lines 150. Figure 1As shown in FIG. 1, a basic structure schematic diagram of a pixel circuit in a related art display panel is shown. In the figure, transistor M1 is a reset transistor, transistor M2 is a data input transistor, transistor M3 is a drive transistor, transistor M4 is a compensation transistor, transistors M5 and M6 are light emitting control transistors, and transistor M7 is a reset transistor. The control electrode of transistor M2 and transistor M3 is electrically connected to a row scan end to access a row scan signal, the control electrode of transistor M1 is electrically connected to a reset control end to access a reset control signal, and the signal end label represents Figure 1 The light emitting unit D of the nth row and its pixel driving unit are shown.

[0055] The inventors have found that when a plurality of scan signals are used to scan the corresponding row pixel driving unit, the lower plate charging potential of the capacitor Cst connected to the control electrode of the drive transistor M3 in the last few rows of pixel circuits is inconsistent.

[0056] With reference to the drawings Figure 2 As shown in FIG. 3, a wearable display product with a resolution of 384x384 resolution and Mux 1:2 is taken as an example. Currently, a 3GSTV is commonly used to output three low level signals from the output end Gout of the GOA to the row scan end in a frame of picture display, for example, Gout(379), Gout(380), Gout(381), Gout(382), Gout(383), and Gout(384). Figure 2 As shown in FIG. 4, the output timing of the output ends Gout(379), Gout(380), Gout(381), Gout(382), Gout(383), and Gout(384) of the last 6 rows of GOA is shown. It can be understood that these signals correspond to the row scan end of the last 6 rows of pixel circuits. In each row scan process, due to the continuous access of three low level row scan signals, there is a moment when the adjacent row pixel circuits are simultaneously active.

[0057] For example Figure 2As shown, in the third low-level pulse period of the 379th row pixel circuit, the row scanning signal terminals of the 379th, 381st and 383rd rows are connected to low-level signals at the same time, in the third low-level pulse period of the 380th row pixel circuit, the row scanning signal terminals of the 380th, 382nd and 384th rows are connected to low-level signals at the same time, at this time, the potentials of the N3 nodes of the 379th row pixel circuit and the 380th row pixel circuit are: V(379)=V(380)=Cdata×Q / (3Cst+Cdata), wherein Cdata represents the capacitance value of the parasitic capacitance introduced by the data signal line, Cst represents the capacitance value of the capacitor Cst, and Q represents the amount of charge stored in the Cst capacitor during display of a picture; in the third low-level pulse period of the 381st row pixel circuit, the row scanning signal terminals of the 381st and 383rd rows are connected to low-level signals at the same time, in the third low-level pulse period of the 382nd row pixel circuit, the row scanning signal terminals of the 382nd and 384th rows are connected to low-level signals at the same time, at this time, the potentials of the N3 nodes of the 381st row pixel circuit and the 382nd row pixel circuit are: V(381)=V(382)=Cdata×Q / (2Cst+Cdata), wherein Cdata, Cst and Q represent the same meaning as above; however, in the third low-level pulse period of the 383rd row pixel circuit, only the row scanning signal terminal of the 383rd row is connected to a low-level signal, in the third low-level pulse period of the 384th row pixel circuit, only the row scanning signal terminal of the 384th row is connected to a low-level signal, at this time, the potentials of the N3 nodes of the 383rd row pixel circuit and the 384th row pixel circuit are: V(383)=V(384)=Cdata×Q / (Cst+Cdata), wherein Cdata, Cst and Q represent the same meaning as above. It can be seen that the potentials of the N3 nodes of the last four row pixel circuits are different from the potentials of the N3 nodes of the previous row pixel circuits, which leads to different display brightness, and finally the visual quality problem of the virtual edge appears, as shown in Figure 3 As shown, in the third low-level pulse period of the 379th row pixel circuit, the row scanning signal terminals of the 379th, 381st and 383rd rows are connected to low-level signals at the same time, in the third low-level pulse period of the 380th row pixel circuit, the row scanning signal terminals of the 380th, 382nd and 384th rows are connected to low-level signals at the same time, at this time, the potentials of the N3 nodes of the 379th row pixel circuit and the 380th row pixel circuit are: V(379)=V(380)=Cdata×Q / (3Cst+Cdata), wherein Cdata represents the capacitance value of the parasitic capacitance introduced by the data signal line, Cst represents the capacitance value of the capacitor Cst, and Q represents the amount of charge stored in the Cst capacitor during display of a picture; in the third low-level pulse period of the 381st row pixel circuit, the row scanning signal terminals of the 381st and 383rd rows are connected to low-level signals at the same time, in the third low-level pulse period of the 382nd row pixel circuit, the row scanning signal terminals of the 382nd and 384th rows are connected to low-level signals at the same time, at this time, the potentials of the N3 nodes of the 381st row pixel circuit and the 382nd row pixel circuit are: V(381)=V(382)=Cdata×Q / (2Cst+Cdata), wherein Cdata, Cst and Q represent the same meaning as above; however, in the third low-level pulse period of the 383rd row pixel circuit, only the row scanning signal terminal of the 383rd row is connected to a low-level signal, in the third low-level pulse period of the 384th row pixel circuit, only the row scanning signal terminal of the 384th row is connected to a low-level signal, at this time, the potentials of the N3 nodes of the 383rd row pixel circuit and the 384th row pixel circuit are: V(383)=V(384)=Cdata×Q / (Cst+Cdata), wherein Cdata, Cst and Q represent the same meaning as above. It can be seen that the potentials of the N3 nodes of the last four row pixel circuits are different from the potentials of the N3 nodes of the previous row pixel circuits, which leads to different display brightness, and finally the visual quality problem of the virtual edge appears, as shown in

[0058] To solve at least one of the above problems, an embodiment of the present application provides a redundant pixel circuit for compensating a display circuit,

[0059] The display circuit comprises a plurality of pixel circuits, each pixel circuit comprising a light emitting unit and a pixel driving unit for driving the light emitting unit to emit light, the pixel driving unit comprising a driving control module and a reset module, wherein the driving control module generates a driving current based on signals input from a data signal terminal, a row scanning terminal, a light emitting control terminal and a first power signal terminal, and drives the light emitting unit to emit light, and the reset module resets the pixel driving unit based on signals input from a reset control terminal and a reset signal terminal,

[0060] The redundant pixel circuit comprises a first transistor, a second transistor and a first capacitor, wherein,

[0061] The first electrode of the first transistor is electrically connected to a first node, the second electrode is electrically connected to a reset signal terminal, and the control electrode is electrically connected to a redundant reset control terminal,

[0062] The first electrode of the second transistor is electrically connected to a data signal terminal, the second electrode is electrically connected to the first node, and the control electrode is electrically connected to a redundant row scanning terminal,

[0063] The first end of the first capacitor is electrically connected to a first power signal terminal, and the second end is electrically connected to the first node.

[0064] In the embodiment, by providing the redundant pixel circuit comprising the first transistor, the second transistor and the first capacitor between the first power signal terminal and the reset signal terminal of the display circuit, and electrically connecting the first electrode of the first transistor to the first node, the second electrode to the reset signal terminal, and the control electrode to the redundant reset control terminal, electrically connecting the first electrode of the second transistor to the data signal terminal, the second electrode to the first node, and the control electrode to the redundant row scanning terminal, and electrically connecting the first end of the first capacitor to the first power signal terminal and the second end to the first node, parasitic compensation of the driving current in the display circuit is generated by the redundant pixel circuit, display unevenness is improved, display effect is improved, and the application prospect is wide.

[0065] In order to describe the structure and functional advantages of the redundant pixel circuit in the embodiments of the present application in detail, specific examples are described in detail below.

[0066] In a specific example, continuing to refer to Figure 4 and Figure 5 In order to facilitate understanding of the function of the redundant pixel circuit, the application scenario of the circuit is shown in the figure. The display circuit 20 receiving compensation is shown.

[0067] As Figure 4As shown, the display circuit 20 includes a plurality of pixel circuits 20-1, 20-2, …, and 20-n, each of which includes a light emitting unit 220 and a pixel driving unit 210 for driving the light emitting unit 220 to emit light. The light emitting unit 220 can be an organic light emitting diode, a quantum dot light emitting diode (QLED) or a micro light emitting diode (Micro LED), etc. The pixel driving unit 210 includes a driving control module and a reset module. The driving control module generates a driving current based on signals input from a data signal terminal Vdata, a row scanning terminal Gate, a light emitting control terminal Em, and a first power signal terminal VDD, and drives the light emitting unit 220 to emit light. Although not specifically shown, the reset module resets the pixel driving unit based on signals input from a reset control terminal and a reset signal terminal.

[0068] It should be noted that, for ease of description, the display circuit 20 shown in the figure includes n rows of 1 column display units and their pixel driving units, and n is a positive integer greater than 2. However, the display circuit in the present application is not limited thereto, and in actual applications, the display circuit usually includes arrayed display units, i.e., multiple rows and multiple columns of display units. In this case, the display circuit also includes pixel driving units corresponding to the display units one by one, i.e., the pixel driving units are also multiple rows and multiple columns. In addition, when it is not necessary to distinguish the specific circuit order, the light emitting units are collectively referred to as light emitting units 220, the pixel driving units are collectively referred to as pixel driving units 210, the row scanning terminals are collectively referred to as row scanning terminals Gate, and the light emitting control terminals are collectively referred to as light emitting control terminals Em.

[0069] In particular, as shown in Figure 4 The redundant pixel circuit 10 of the embodiment of the present application includes a first transistor T1, a second transistor T2, and a first capacitor Cst1. The first electrode of the first transistor T1 is electrically connected to a first node N1, the second electrode is electrically connected to a reset signal terminal Reset(n+1), and the control electrode is electrically connected to a redundant reset control terminal Vinit. The first electrode of the second transistor T2 is electrically connected to a data signal terminal Vdata, the second electrode is electrically connected to the first node N1, and the control electrode is electrically connected to a redundant row scanning terminal Gate(n+1). The first end of the first capacitor Cst1 is electrically connected to a first power signal terminal VDD, and the second end is electrically connected to the first node N1.

[0070] In Figure 4In the example, the redundant pixel circuit 10 is equivalent to being added below the n rows of pixel circuits as a row of redundant compensation circuits, and the control electrode of the first transistor T1 is electrically connected to a reset signal terminal Reset(n+1), and the control electrode of the second transistor T2 is electrically connected to a redundant row scanning terminal Gate(n+1), a row of scanning signals is added as the control signal of the second transistor T2 in addition to the n rows of scanning signals, and the data signal written by the data signal terminal Vdata is received and the first node N1 is charged in response to the control signal, and parasitic compensation is generated by the storage function of the first capacitor Cst1. The control electrode of the first transistor T1 receives the n+1 row reset signal, and resets the first node N1 in response to the reset signal received by the reset signal terminal Vinit.

[0071] Through the above arrangement, the redundant pixel circuit of the embodiment of the application provides the first transistor T1, the second transistor T2, and the first capacitor Cst1, and uses the redundant row scanning terminal to input the data signal as a parasitic branch through the storage effect of the first capacitor Cst1, to increase the brightness of the display units of the third last row and the last row in the display circuit, and to improve the virtual edge problem.

[0072] In order to further compensate the display circuit by the redundant pixel circuit, the specific circuit structure and timing shown in Figures 5 to 7 will be described in detail below.

[0073] This example still takes a wearable display product with a resolution of 384x384 resolution and Mux 1:2 as an example for description, and the row scanning terminal of the pixel circuit in the display panel is driven by 3 low-level signals to generate a driving current, that is, a row scanning signal is output by a 3GSTV control GOA circuit. In addition, in order to simplify, Figure 5 In the example, only one pixel circuit in the n-th row of pixel circuits and the redundant pixel circuit for compensating the pixel circuit are shown, where n=384.

[0074] In this example, the display panel includes a display circuit 20, and the display circuit 20 includes a plurality of pixel circuits. The number of pixel circuits is equal to the number of light emitting units D, specifically 384x384. Each pixel circuit includes a light emitting unit 220 and a pixel driving unit 210 for driving the light emitting unit 220 to emit light. The pixel driving unit 220 includes a driving control module and a reset module.

[0075] Referring specifically to Figure 5 , the driving control module includes an input submodule, a driving submodule, a first light emitting control submodule, and a second light emitting control submodule.

[0076] The input submodule includes a first end, a second end and a control end. The control end of the input submodule is electrically connected to the row scanning end Gate(n), the first end is electrically connected to the data signal end Vdata, and the second end of the input submodule is electrically connected to the second node N2, configured to write the signal accessed by the data signal end Vdata into the second node N2 in response to the row scanning signal accessed by the row scanning end Gate(n). The input submodule specifically includes a sixth transistor T6, the first electrode of the sixth transistor T6 is electrically connected to the data signal end Vdata, the second electrode is electrically connected to the second node N2, and the control electrode is electrically connected to the row scanning end Gate(n).

[0077] The driving submodule includes a first end, a second end, a third end and a fourth end. The first end of the driving submodule is electrically connected to the first power signal end VDD, the second end is electrically connected to the second node N2, the third end is electrically connected to the third node N3, and the fourth end is electrically connected to the fourth node N4, configured to turn on the second node N2 and the fourth node N4 according to the voltage of the third node N3 to form a driving current.

[0078] Specifically, the driving submodule includes a third transistor T3, a fourth transistor T4 and a second capacitor Cst2. The first electrode of the third transistor T3 is electrically connected to the second node N2, the second electrode is electrically connected to the fourth node N4, and the control electrode is electrically connected to the third node N3. The first electrode of the fourth transistor T4 is electrically connected to the fourth node N4, the second electrode is electrically connected to the third node N3, and the control electrode is electrically connected to the row scanning end Gate(n). The first end of the second capacitor Cst2 is electrically connected to the first power signal end VDD, and the second end is electrically connected to the third node N3. The fourth transistor T4 serves as a compensation transistor of the driving submodule, and turns on in response to the row scanning signal accessed by the row scanning end Gate(n) to set the control electrode of the third transistor T3 to Vdata+Vth, wherein Vdata represents the digital signal accessed by the data input end Vdata, and Vth represents the threshold voltage of the transistor. The second capacitor Cst2 is used to hold the potential of the third node N3.

[0079] The first light emitting control submodule includes a first end, a second end and a control end, wherein the first end of the first light emitting control submodule is electrically connected to the first power signal end VDD, the second end is electrically connected to the second node N2, and the control end is electrically connected to the light emitting control end Em(n), configured to turn on the first end and the second end of the first light emitting control submodule in response to the signal accessed by the light emitting control end Em(n) to access the first power signal VDD. The first light emitting control submodule specifically includes a seventh transistor T7, the first electrode of the seventh transistor T7 is electrically connected to the first power signal end VDD, the second electrode is electrically connected to the second node N2, and the control electrode is electrically connected to the light emitting control end Em(n).

[0080] The second light-emitting control submodule includes a first terminal, a second terminal, and a control terminal. The first terminal of the second light-emitting control submodule is electrically connected to the fourth node N4, the second terminal is electrically connected to the second power signal terminal VSS, and the control terminal is electrically connected to the light-emitting control terminal EM(n). It is configured to conduct the first and second terminals of the second light-emitting control submodule in response to a signal input to the light-emitting control terminal Em(n) to transmit driving current to the light-emitting unit 200-n. The first light-emitting control submodule specifically includes an eighth transistor T8, whose first electrode is electrically connected to the fourth node N4, its second electrode is electrically connected to the second power signal terminal VSS, and its control electrode is electrically connected to the light-emitting control terminal Em(n).

[0081] The reset module includes a first terminal, a second terminal, and a control terminal. The first terminal is electrically connected to the third node N3, the second terminal is electrically connected to the reset signal terminal Vinit, and the control terminal is electrically connected to the reset control terminal Reset(n). It is configured to reset the third node N3 using the potential of the reset signal terminal Vinit in response to the reset control signal connected to the reset control terminal Reset(n), that is, to reset the pixel driving unit. Specifically, the reset module includes a fifth transistor T5, whose first electrode is electrically connected to the third node N3, its second electrode is electrically connected to the reset signal terminal Vinit, and its control electrode is electrically connected to the reset control terminal Reset(n).

[0082] In addition, refer to Figure 5 As shown, the pixel driving unit may further include an auxiliary reset module, which includes a first terminal, a second terminal, and a control terminal. The first terminal is electrically connected to the fifth node N5, the second terminal is electrically connected to the reset signal terminal Vinit, and the control terminal is electrically connected to the auxiliary reset control terminal Reset(n-1). It is configured to reset the fifth node N5 using the potential of the reset signal terminal Vinit in response to a reset control signal connected to the auxiliary reset control terminal Reset(n-1), that is, to reset the light-emitting unit 220-n. Specifically, the auxiliary reset module includes a ninth transistor T9, whose first electrode is electrically connected to the fifth node N5, its second electrode is electrically connected to the auxiliary reset signal terminal Vinit, and its control electrode is electrically connected to the auxiliary reset control terminal Reset(n-1).

[0083] Specifically, the display panel includes multiple redundant pixel circuits 10. The redundant pixel circuits 10 include the first transistor T1, the second transistor T2, and the first capacitor Cst1 described above, and utilize the parasitic effects they provide to compensate for the pixel circuits in the display circuitry.

[0084] Preferably, when the row scanning terminal in the display panel generates a driving current from three low-level signals, the display panel includes four rows of redundant pixel circuits, which can completely eliminate the virtual edge problem caused by this driving method.

[0085] Specific combinationFigure 6 and Figure 7 as shown in FIG. 10, Figure 6 FIG. 10 shows a timing diagram of the reset signal and the row scanning signal received by the reset control terminal Reset(n+1) and the redundant row scanning terminal (n+1) of the redundant pixel circuit 10, Figure 7 FIG. 10 shows a timing diagram of the row scanning signal received by the row scanning terminal of the 379th to 384th pixel circuits and the redundant row scanning signal of the redundant row scanning terminal of the 1st to 4th redundant pixel circuits, and the influence between the signals. In the figure, in order to distinguish the signals accessed by the row scanning terminal and the redundant row scanning terminal, the GOA output terminals connected with the row scanning terminal and the redundant row scanning terminal are marked.

[0086] For the pixel circuit generating the driving current for the 3 low level signals, the 1st redundant pixel circuit compensates for the period when the third low level signal is received by the row scanning terminal of the 381st pixel circuit, that is, referring to Figure 7 as shown, the period when the third low level signal is received by the row scanning terminal of the 381st pixel circuit is called the charging and compensating stage. When driving the 381st pixel circuit and the 1st redundant pixel circuit, the driving method of the display panel comprises: a reset stage, a charging and compensating stage, and an emission control stage.

[0087] In the reset stage, at t1, the reset control terminal of the 1st redundant pixel circuit receives a low level signal, the first transistor T1 is turned on, and the voltage of the first node N1 is reset by the potential of the reset signal terminal Vinit.

[0088] In the charging and compensating stage, at t2, the driving control module of the 381st pixel circuit charges the second capacitor Cst2 according to the signals accessed by the row scanning terminal and the data signal terminal of the row of pixel circuits, and the 1st redundant pixel circuit 10 charges the first capacitor Cst1 according to the signals accessed by the redundant row scanning terminal and the data signal terminal Vdata. Based on the charging of the first capacitor Cst1 of the redundant pixel circuit, it is equivalent to adding a non-emitting circuit branch to compensate the second node N2 of the 381st pixel circuit.

[0089] That is, referring to Figure 7As shown, the first low voltage period of Dummy (1) coincides with the third low voltage period of Gout (381), and the 1st row redundant pixel circuit has the same effect on the 381st row pixel circuit as the 384th row pixel circuit has on the 380th row pixel circuit in the first low voltage period of Gout (384). Preferably, when the capacitance value of the first capacitor Cst1 is equal to the capacitance value of the second capacitor Cst2, the effect of the 1st row redundant pixel circuit on the 381st row pixel circuit in this period is exactly the same as the effect of the 384th row pixel circuit on the 380th row pixel circuit in the first low voltage period of Gout (384), and the potential of the second node N2 is V(381) = V(379) = V(380) = Cdata x Q / (3Cst + Cdata), wherein Cst represents the capacitance value of the second capacitor Cst2, Cdata represents the capacitance value of the parasitic capacitance introduced by the data signal line, and Q represents the amount of charge stored in the Cst capacitor when displaying a picture.

[0090] In the light-emitting control stage: those skilled in the art can understand that the driving control module generates a driving current according to the signals input from the data signal end, the row scanning end, the light-emitting control end and the first power signal end, and drives the light-emitting unit to emit light. Based on the compensation effect of the 1st row redundant pixel circuit on the 381st row pixel circuit, the brightness of the display unit in the 381st row pixel circuit is the same as that of the display unit in the first 380 rows of pixel circuits in the display panel.

[0091] It should be noted that the above description refers to Figure 7As shown, the 2nd row of redundant pixel circuits forms parasitic compensation for the third low voltage period output by the GOA output terminal Gout(382) for the 382nd row of pixel circuits, and when the capacitance value of the first capacitor Cst1 in the 2nd row of redundant pixel circuits is equal to the capacitance value of the second capacitor Cst2 in the 382nd row of pixel circuits, the potential of the second node N2 is V(382) = V(379) = V(380) = Cdata x Q / (3Cst+Cdata); the 3rd row of redundant pixel circuits forms parasitic compensation for the third low voltage period output by the GOA output terminal Gout(383) for the 383rd row of pixel circuits, and when the capacitance value of the first capacitor Cst1 in the 3rd row of redundant pixel circuits is equal to the capacitance value of the second capacitor Cst2 in the 383rd row of pixel circuits, the potential of the second node N2 is V(383) = V(379) = V(380) = Cdata x Q / (3Cst+Cdata); the 4th row of redundant pixel circuits forms parasitic compensation for the third low voltage period output by the GOA output terminal Gout(383) for the 384th row of pixel circuits, and when the capacitance value of the first capacitor Cst1 in the 4th row of redundant pixel circuits is equal to the capacitance value of the second capacitor Cst2 in the 384th row of pixel circuits, the potential of the second node N2 is V(384) = V(379) = V(380) = Cdata x Q / (3Cst+Cdata). Thus, the 4th row of redundant pixel circuits can completely eliminate the false edge display problem caused by driving a plurality of low voltage level horizontal scanning signals. The meanings of Cdata, Q, and Cst are consistent with the description above, and will not be described again here.

[0092] According to an embodiment of the present application, when the display panel includes M1 rows of pixel circuits, if the row scanning end of the pixel circuits is driven by N low voltage signals to generate a driving current, when the capacitance value of the first capacitor Cst1 in the redundant pixel circuit is equal to the capacitance value of the second capacitor Cst2 in the pixel circuit, A rows of redundant pixel circuits can be provided, A = 2N-2, A, M1, and N are positive integers, and N is greater than 1. In addition, because each pixel circuit includes a display unit, when the display unit is in multiple rows and multiple columns, the redundant pixel circuit is also in multiple rows and multiple columns, i.e., when the number of columns of the light emitting unit is B, the redundant pixel circuit is also B columns, and the number of redundant pixel circuits M = A x B, where B is a positive integer.

[0093] According to an embodiment of the present application, the redundant pixel circuit can be provided in the same layer as the metal layer of the transistor or the capacitor in the pixel circuit of the existing display panel.

[0094] Specifically, referring to Figure 8 As shown, a partial cross-sectional view of the redundant pixel circuit is shown in the figure.

[0095] According to embodiments of the present application, the display panel can include a substrate 100, a driving circuit layer 200 formed on the substrate, and a light emitting unit layer. An isolation column (PS) layer 400 can also be included on the light emitting unit layer, and of course, an encapsulation layer (not shown) can also be included on the isolation column layer 400.

[0096] Each transistor in the pixel circuits 20-1, 20-2, …, 20-n can be a thin film transistor, and each transistor is disposed in the driving circuit layer 200. The first transistor T1 and the second transistor T2 in the redundant pixel circuit 10 are also disposed in the driving circuit layer 200, as shown in FIG. 2A, which shows the layer structure of the first transistor T1, and the structure of the second transistor T2 is the same. Figure 8

[0097] Specifically, the driving circuit layer 200 includes a gate layer, for example, a Gate1 layer, in which the gate of at least part of the transistors in the pixel circuit is disposed, for example, if the display panel is an LPTS (Low Temperature Poly-silicon) display panel, the gate of all the transistors in the pixel circuit is disposed in the gate layer, and if the display panel is an LPTO (Low Temperature Polycrystalline Oxide) display panel, the gate of part of the transistors in the pixel circuit is disposed in the gate layer. In order to simplify the process flow, the gate of the first transistor T1 and the gate of the second transistor T2 in the redundant pixel circuit 10 are also disposed in the gate layer.

[0098] In addition to the gate layer, the driving circuit layer 200 also includes a metal wiring layer, for example, a Gate2 layer, or other circuit layer, one of the two substrates in the first capacitor Cst1 in the redundant pixel circuit 10 can be disposed in the metal wiring layer, and the other substrate can be disposed in the gate layer.

[0099] That is, the gate of the first transistor T1, the gate of the second transistor T2, and one of the first plate and the second plate of the first capacitor Cst1 in the redundant pixel circuit 10 can be disposed in the same layer as the gate of at least part of the transistors in the pixel circuit, and the other plate of the first capacitor Cst1 can be disposed in the same layer as the metal wiring layer, and through the above arrangement, the redundant pixel circuit does not additionally increase the process flow, and the manufacturing process is simplified.

[0100] Specifically, referring to Figure 8 ​As shown, the first transistor T1 of the redundant pixel circuit 10 includes, in sequence, an active layer 201, a first gate insulating layer (GI1) 202, a gate 203-1, a second gate insulating layer (GI2) 204, a dielectric insulating layer 206, and a source and drain 207-1, which are arranged on the substrate 100. The second gate insulating layer 204 substantially serves as an insulating layer between the first and second plates of the first capacitor Cst1.

[0101] In this example, the first capacitor Cst1 includes a first plate 203-2 and a second plate 205, the first plate 203-2 being connected to a first node (not shown) through a data line 207-2 arranged in the same layer as the source and drain 207-1. Of course, in actual implementation, the second plate 205 can also be connected to the first node through a data line, that is, the present application does not limit which of the two plates is connected to the first end and the second end of the capacitor.

[0102] In addition, the light-emitting unit layer can include an anode, a pixel definition layer, a light-emitting layer, and a cathode, Figure 8 Only the pixel definition layer 301 is shown here and will not be described again.

[0103] It should be further noted that the present application does not intend to limit the specific area of the redundant pixel circuit region in the display panel, and the display panel includes a display area and a non-display area. The redundant pixel circuit can be arranged in the display area or the non-display area, and the position is determined according to the layout of the specific display product.

[0104] Based on the same inventive concept, the embodiments of the present application also provide the display panel described above, which includes a display circuit and at least one redundant pixel circuit described above.

[0105] It should be noted that the specific structure of the display panel has been described in detail above when describing the structure and function of the redundant pixel circuit, and will not be described again here.

[0106] By providing the redundant pixel circuit including the first transistor, the second transistor, and the first capacitor between the first power signal end and the reset signal end of the display circuit, and electrically connecting the first plate of the first transistor to the first node, the second plate to the reset signal end, and the control plate to the redundant reset control end, electrically connecting the first plate of the second transistor to the data signal end, the second plate to the first node, and the control plate to the redundant row scanning end, and electrically connecting the first end of the first capacitor to the first power signal end and the second end to the first node, the parasitic compensation of the driving current in the display circuit is generated by using the redundant pixel circuit, the display unevenness is improved, the display effect is improved, and the application prospect is wide.

[0107] Based on the same inventive concept, the embodiments of the present application also provide a driving method of the display panel described in the above embodiments, the display panel comprising M1 rows of pixel circuits and A rows of redundant pixel circuits, the sum of M1 and A being equal to the number of output ends of a gate driving circuit, the gate driving circuit being configured to provide signals to the row scanning end and the redundant row scanning end, M1 and A being positive integers, M1 being greater than 1,

[0108] In driving the m1th row of pixel circuits and the ath row of redundant pixel circuits, wherein m1=M1-A+a, a=1, 2, …, A, the driving method comprises:

[0109] a reset stage: the redundant pixel circuit resets the voltage of the first node by using the signal of the reset signal end in response to the signal inputted into the reset control end;

[0110] a charging and compensation stage:

[0111] the driving control module charges the second capacitor of the module according to the signals inputted into the row scanning end and the data signal end, and the redundant pixel circuit charges the first capacitor according to the signals inputted into the redundant row scanning end and the data signal end to compensate the pixel circuit;

[0112] a light emitting control stage: the driving control module generates a driving current and drives the light emitting unit to emit light according to the signals inputted into the data signal end, the row scanning end, the light emitting control end and the first power signal end.

[0113] The above driving method and process have been described in detail when describing the function of the specific redundant circuit in the display panel, and will not be described here again.

[0114] By the driving method, the redundant pixel circuit is used to generate parasitic compensation for the driving current in the display circuit, which can improve the display unevenness, improve the display effect, and has a broad application prospect.

[0115] Based on the same inventive concept, the embodiments of the present application also provide a manufacturing method of the display panel described above, comprising:

[0116] providing a substrate,

[0117] sequentially driving a driving circuit layer and a light emitting unit layer on the substrate, the driving circuit layer comprising a gate layer and a metal wiring layer arranged on the gate layer, and the first capacitor comprising a first plate and a second plate, wherein

[0118] the gate of the first transistor, the gate of the second transistor and the first plate are arranged in the gate layer, and the second plate is arranged in the metal wiring layer, and

[0119] One of the first and second plates leads to the first terminal of the first capacitor, and the other leads to the second terminal of the first capacitor.

[0120] As an example, refer to the following Figures 9 to 15 The process flow illustrates the manufacturing method, showing only the first transistor T1 and the first capacitor Cst1.

[0121] In step S1, refer to Figure 9 As shown, a polysilicon layer is deposited on the provided substrate to form an active layer 201. The deposition method can be plasma chemical vapor deposition, and the deposition thickness can be, for example, 50 nm.

[0122] In step S2, refer to Figure 10 As shown, a first gate insulating layer 202 is deposited on the active layer 201. The deposition method can also be plasma-enhanced chemical vapor deposition, and the material can be silicon oxide, with a deposition thickness of, for example, 120 nm. Alternatively, the first gate insulating layer 202 can be made of other inorganic insulating materials such as silicon nitride or silicon oxynitride, and the first gate insulating layer 202 can be a single layer or multiple layers.

[0123] In step S3, refer to Figure 11 As shown, a first substrate 203-2, on which the gate 203-1 and the first capacitor Cst1 are formed in a single patterning process on the first gate insulating layer 202. Specifically, a 250nm thick molybdenum (Mo) layer can be formed by magnetron sputtering, followed by patterning of the first substrate 203-2 containing the gate 203-1 and the first capacitor Cst1. The materials of the gate 203-1 and the first capacitor Cst1 can also be a multilayer metal structure, and the film layer combination can be selected from one of molybdenum / aluminum / molybdenum (Mo / AL / Mo), molybdenum / copper (Mo / Cu), molybdenum-niobium alloy / copper (MoNb / Cu), molybdenum-niobium alloy / copper / molybdenum-titanium alloy (MoNb / Cu / MoTi), or a stack thereof.

[0124] In step S4, refer to Figure 12 As shown, a second gate insulating layer 204 is deposited on the first substrate 203-2 of the gate 203-1 and the first capacitor Cst1, and a second substrate 205 of the first capacitor Cst1 is formed on the second gate insulating layer 204 to form the first capacitor Cst1. The material of the second gate insulating layer 204 can also be an inorganic insulating material such as silicon oxide, silicon nitride, or silicon oxynitride, and the second gate insulating layer 204 can be a single layer or multiple layers.

[0125] In step S5, refer to Figure 13As shown, a dielectric insulation layer 206 is deposited on the second substrate 205, and via etching is performed to form a via to the active layer in the region where the first transistor T1 is to be formed and a via to the first substrate 203-2 in the region of the first capacitor Cst1.

[0126] In step S6, with reference to Figure 14 As shown, the source and drain 207-1 and the data line 207-2 are formed on the dielectric insulation layer 206. Specifically, a metal layer can be deposited by magnetron sputtering, which can be a multi-layer metal structure, and the film layer combination can be selected from one of Mo / AL / Mo, Mo / Cu, MoNb / Cu, MoNb / Cu / MoTi, etc. or a stack thereof. By one-time patterning etching, the source and drain 207-1 and the data line 207-2 are formed, and at the same time, the first transistor T1 and the metal interconnection to the first capacitor Cst1 are formed.

[0127] In step S7, with reference to Figure 15 As shown, a planarization layer 208 is formed, and then the light emitting unit layer and the isolation column (PS) 400 are formed by coating, exposure, development, curing, etc., and the light emitting unit layer includes the pixel defining layer 301.

[0128] It should be understood by those skilled in the art that in the above setting process, the first transistor T1 and the first capacitor Cst1 use the film layer where the transistor in the pixel circuit and the second capacitor Cst1 are located, the flow is simplified, easy to implement, and has a broad application prospect.

[0129] Based on the same inventive concept, the embodiments of the present application also provide a display device, which includes the display panel described above.

[0130] In the present embodiment, the display device can be a wearable device, a mobile phone, a tablet computer, a television, a display, a notebook computer, a vehicle-mounted display, a digital photo frame, or a navigator, etc. any product or component with display function. By using the display device with the above display panel, the virtual edge problem can be avoided in the display process, the display uniformity is improved, and has a broad application prospect.

[0131] The present application is directed to the current existing problems, and formulates a kind of redundant pixel circuit for compensating display circuit, display panel and its manufacturing method and driving method, and display device, by providing redundant pixel circuit including first transistor, second transistor and first capacitor between the first power signal end and reset signal end of display circuit, and the first electrode of first transistor is electrically connected to the first node, the second electrode is electrically connected to reset signal end, the control electrode is electrically connected to redundant reset control end, the first electrode of second transistor is electrically connected to data signal end, the second electrode is electrically connected to the first node, the control electrode is electrically connected to redundant row scanning end, the first end of first capacitor is electrically connected to the first power signal end, and the second end is electrically connected to the first node, so as to utilize redundant pixel circuit to generate parasitic compensation to driving current in display circuit, can improve display unevenness, improve display effect, and have wide application prospect.

[0132] Obviously, the above embodiments of the present application are only examples for clearly illustrating the present application, and are not the limitation to the embodiments of the present application. For ordinary skilled in the art, on the basis of the above description, other different forms of changes or variations can be made, and here it is impossible to enumerate all the embodiments, and any changes or variations derived from the technical solution of the present application still fall within the protection scope of the present application.

Claims

1. A circuit for compensating redundant pixels in a display circuit, characterized in that, The display circuit includes multiple pixel circuits. Each pixel circuit includes a light-emitting unit and a pixel driving unit for driving the light-emitting unit to emit light. The pixel driving unit includes a driving control module and a reset module. The driving control module generates a driving current based on signals input from a data signal terminal, a line scan terminal, a light-emitting control terminal, and a first power signal terminal, and drives the light-emitting unit to emit light. The reset module resets the pixel driving unit based on signals input from a reset control terminal and a reset signal terminal. The redundant pixel circuit includes: a first transistor, a second transistor, and a first capacitor, wherein, The first electrode of the first transistor is electrically connected to the first node, the second electrode is electrically connected to the reset signal terminal, and the control electrode is electrically connected to the redundant reset control terminal. The first electrode of the second transistor is electrically connected to the data signal terminal, the second electrode is electrically connected to the first node, and the control electrode is electrically connected to the redundant row scan terminal. The first terminal of the first capacitor is electrically connected to the first power signal terminal, and the second terminal is electrically connected to the first node.

2. A display panel, characterized in that, include: The display circuit and at least one redundant pixel circuit according to claim 1, wherein... The display circuit includes: multiple pixel circuits, each pixel circuit including a light-emitting unit and a pixel driving unit for driving the light-emitting unit to emit light, the pixel driving unit including a driving control module and a reset module, wherein the driving control module generates a driving current based on signals connected to a data signal terminal, a line scanning terminal and a first power signal terminal and drives the light-emitting unit to emit light, and the reset module resets the pixel driving unit based on signals connected to a reset control terminal and a reset signal terminal.

3. The display panel according to claim 2, characterized in that, Including the light-emitting units arranged in an array, wherein The at least one is M, and the row scanning terminal of the pixel circuit generates the driving current from N low-level signals, wherein... M=A B, A=2N-2, where A represents the number of rows of the redundant pixel circuit, B represents the number of columns of the redundant pixel circuit, and the number is equal to the number of columns of the light-emitting unit. A, B, M and N are positive integers, and N is greater than 1.

4. The display panel according to claim 2, characterized in that, The pixel circuit includes a driving circuit layer and a light-emitting unit layer sequentially stacked on a substrate. The driving circuit layer includes a gate layer and a metal wiring layer disposed on the gate layer. At least some of the transistors in the pixel circuit have their gates disposed in the gate layer. The first capacitor includes a first electrode and a second electrode. The gate of the first transistor, the gate of the second transistor, and the first electrode plate are disposed in the gate layer, and the second electrode plate is disposed in the metal wiring layer. One of the first plate and the second plate leads out to the first terminal of the first capacitor, and the other leads out to the second terminal of the first capacitor.

5. The display panel according to claim 2, characterized in that, The drive control module includes: an input submodule, a drive submodule, a first light-emitting control submodule, and a second light-emitting control submodule, wherein... The input submodule includes a first terminal, a second terminal, and a control terminal, wherein the control terminal of the input submodule is electrically connected to the row scanning terminal, the first terminal of the input submodule is electrically connected to the data signal terminal, and the second terminal of the input submodule is electrically connected to a second node and is configured to write the signal received by the data signal terminal into the second node in response to the row scanning signal received by the row scanning terminal. The driving submodule includes a first terminal, a second terminal, a third terminal, and a fourth terminal, wherein the first terminal of the driving submodule is electrically connected to the first power signal terminal, the second terminal of the driving submodule is electrically connected to the second node, the third terminal of the driving submodule is electrically connected to the third node, and the fourth terminal of the driving submodule is electrically connected to the fourth node, and is configured to conduct the second node and the fourth node according to the voltage of the third node to form the driving current; The first light-emitting control submodule includes a first end, a second end, and a control end, wherein the first end of the first light-emitting control submodule is electrically connected to the first power signal end, the second end of the first light-emitting control submodule is electrically connected to the second node, and the control end of the first light-emitting control submodule is electrically connected to the light-emitting control end, and is configured to conduct the first end and the second end of the first light-emitting control submodule to access the first power signal in response to a signal accessed by the light-emitting control end. The second light-emitting control submodule includes a first terminal, a second terminal, and a control terminal. The first terminal of the second light-emitting control submodule is electrically connected to the fourth node, the second terminal of the second light-emitting control submodule is electrically connected to the second power signal terminal, and the control terminal of the second light-emitting control submodule is electrically connected to the light-emitting control terminal. It is configured to conduct the first and second terminals of the second light-emitting control submodule in response to a signal received by the light-emitting control terminal to transmit the driving current to the light-emitting unit.

6. The display panel according to claim 5, characterized in that, in, The driving submodule includes a third transistor, a fourth transistor, and a second capacitor. The first terminal of the third transistor is electrically connected to the second node, the second terminal is electrically connected to the fourth node, and the control terminal is electrically connected to the third node. The first terminal of the fourth transistor is electrically connected to the fourth node, the second terminal is electrically connected to the third node, and the control terminal is electrically connected to the row scan terminal. The first terminal of the second capacitor is electrically connected to the first power signal terminal, and the second terminal is electrically connected to the third node.

7. The display panel according to claim 6, characterized in that, The capacitance value of the first capacitor is equal to the capacitance value of the second capacitor.

8. The display panel according to claim 5, characterized in that, The reset module includes a fifth transistor, which has a first electrode, a second electrode, and a control electrode. The first electrode is electrically connected to the third node, the second electrode is electrically connected to the reset signal terminal, and the control electrode is electrically connected to the reset control terminal. It is configured to reset the voltage of the third node in response to a signal input to the reset control terminal using the signal input to the reset signal terminal.

9. A display device, characterized in that, Includes the display panel as described in any one of claims 2-8.

10. A driving method for a display panel according to any one of claims 2-8, characterized in that, The display panel includes M1 row pixel circuits and A row redundant pixel circuits. The sum of M1 and A is equal to the number of output terminals of the gate driving circuit. The gate driving circuit is used to provide signals to the row scanning terminals and the redundant row scanning terminals. M1 and A are positive integers, with M1 greater than 1. When driving the m1-th row pixel circuit and the a-th row redundant pixel circuit, where m1 = M1 - A + a, a = 1, 2, ..., A, the driving method includes: Reset phase: The redundant pixel circuit responds to the signal input to the reset control terminal by using the signal from the reset signal terminal to reset the voltage of the first node; Charging and compensation phase: The drive control module charges the second capacitor of the module according to the signals received by the row scanning terminal and the data signal terminal, and the redundant pixel circuit charges the first capacitor according to the signals received by the redundant row scanning terminal and the data signal terminal to compensate the pixel circuit. Light emission control stage: The drive control module generates a drive current based on the signals connected to the data signal terminal, the row scanning terminal, the light emission control terminal and the first power signal terminal, and drives the light emission unit to emit light.

11. A method for manufacturing a display panel as described in any one of claims 2-8, characterized in that, include: Provide substrate, A driving circuit layer and a light-emitting unit layer are sequentially formed on the substrate. The driving circuit layer includes a gate layer and a metal wiring layer disposed on the gate layer. The first capacitor includes a first electrode and a second electrode. The gate of the first transistor, the gate of the second transistor, and the first electrode plate are disposed in the gate layer, and the second electrode plate is disposed in the metal wiring layer. One of the first electrode plate and the second electrode plate is connected to the first terminal of the first capacitor, and the other is connected to the second terminal of the first capacitor.

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