Read / write conversion circuit and memory

Abstract

The present disclosure provides a read-write conversion circuit and a memory. The read-write conversion circuit is connected with a global signal line and a local signal line and a complementary local signal line, and is used for transmitting a signal on the local signal line to the global signal line when a read control signal is received, and transmitting a signal on the global signal line to the local signal line when a write control signal is received. The read-write conversion circuit comprises a precharge module connected with a preset voltage source, the local signal line and the complementary local signal line. The preset voltage source is used for providing a first voltage during a read-write gap and providing a second voltage during an idle period. The precharge module is used for transmitting the first voltage to the local signal line and the complementary local signal line during the read-write gap, and transmitting the second voltage to the local signal line and the complementary local signal line during the idle period. The second voltage is less than the first voltage. The present disclosure can reduce the area occupied by the read-write conversion circuit.

Description

Technical Field

[0001] This disclosure relates to the field of integrated circuit technology, and more specifically, to a read / write conversion circuit and a memory using the read / write conversion circuit. Background Technology

[0002] The Local Sensing Amplifier (LSA) is an auxiliary circuit used to realize data exchange between global signal lines and local signal lines in the memory and between the Sense Amplifier (SA) / memory array.

[0003] Figure 1 This is a schematic diagram of a read / write conversion circuit in existing technology. For example... Figure 1 As shown, the read / write conversion circuit (hereinafter referred to as the LSA circuit) can be divided into two parts, LSA_1 and LSA_2. One part (LSA_1) is distributed in the middle of the SA array (LSA_1×4), and the other part (LSA_2) is distributed in the SWC (Sub Wordline Control) area (LSA_2×8). LSA_1 is used to perform data exchange tasks, and LSA_2 is used to set the local signal line Ldata and the complementary local signal line Ldata# connected to LSA_1 to different state voltages under different operating states. Therefore, the LSA_2 part includes two voltage transmission circuits controlled by two control signals (corresponding to different operating states).

[0004] In memory chips, LSA circuits require a significant layout area. For example, in LPDDR5, one section (memory unit) requires eight LSA circuits (each including LSA_1 + LSA_2). With increasingly smaller process dimensions, how to place these devices while ensuring sufficient component size to meet design performance requirements remains a major challenge.

[0005] It should be noted that the information disclosed in the background section above is only used to enhance the understanding of the background of this disclosure, and therefore may include information that does not constitute prior art known to those skilled in the art. Summary of the Invention

[0006] The purpose of this disclosure is to provide a read / write conversion circuit and a memory using the read / write conversion circuit, so as to overcome, at least to some extent, the problem that the LSA circuit occupies a large layout area due to the limitations and defects of related technologies.

[0007] According to a first aspect of this disclosure, a read / write conversion circuit is provided. This circuit is connected to a global signal line and to a sensitive amplifier array via local signal lines and complementary local signal lines. It is used to transmit signals on the local signal lines to the global signal line when a read control signal is received, and to transmit signals on the global signal line to the local signal line when a write control signal is received. The circuit includes a pre-charge module connected to a preset voltage source, the local signal lines, and the complementary local signal lines. The preset voltage source provides a first voltage during a read / write interval and a second voltage during an idle period. The pre-charge module transmits the first voltage to the local signal lines and the complementary local signal lines during the read / write interval and transmits the second voltage to the local signal lines and the complementary local signal lines during the idle period, wherein the second voltage is less than the first voltage.

[0008] In an exemplary embodiment of this disclosure, the pre-charge module includes: a first transistor, with a first terminal connected to the preset voltage source, a second terminal connected to the local signal line, and a control terminal connected to the pre-charge signal line; a second transistor, with a first terminal connected to the preset voltage source, a second terminal connected to the complementary local signal line, and a control terminal connected to the pre-charge signal line; and a third transistor, with a first terminal connected to the local signal line, a second terminal connected to the complementary local signal line, and a control terminal connected to the pre-charge signal line.

[0009] In one exemplary embodiment of this disclosure, the first transistor, the second transistor, and the third transistor are all N-type transistors.

[0010] In an exemplary embodiment of this disclosure, a complementary global signal line, a read control signal line, and a write control signal line are also connected. The read control signal line is used to transmit a read control signal, and the write control signal line is used to transmit a write control signal. The read-write conversion circuit further includes: a first read-write control module connected to the local signal line, the complementary local signal line, the global signal line, the read control signal line, and the write control signal line, configured to transmit the signal on the global signal line to the local signal line when the write control signal is enabled, and to output a second signal to the global signal line when the read control signal is enabled and the complementary local signal line transmits a first signal, the second signal being inverse of the first signal; and a second read-write control module connected to the local signal line, the complementary local signal line, the complementary global signal line, the read control signal line, and the write control signal line, configured to transmit the signal on the complementary global signal line to the complementary local signal line when the write control signal is enabled, and to output a second signal to the complementary global signal line when the read control signal is enabled and the local signal line transmits the first signal.

[0011] In an exemplary embodiment of this disclosure, the first read / write control module includes: a fourth transistor, with a first terminal connected to the local signal line, a second terminal connected to the global signal line, and a control terminal connected to the write control signal line; a fifth transistor, with a first terminal connected to the global signal line and a control terminal connected to the complementary local signal line; a sixth transistor, with a first terminal connected to the second terminal of the fifth transistor, the second terminal being used to receive the second signal, and a control terminal connected to the read control signal line; the second read / write control module includes: a seventh transistor, with a first terminal connected to the complementary local signal line, a second terminal connected to the complementary global signal line, and a control terminal connected to the write control signal line; an eighth transistor, with a first terminal connected to the complementary global signal line and a control terminal connected to the local signal line; and a ninth transistor, with a first terminal connected to the second terminal of the eighth transistor, the second terminal being used to receive the second signal, and a control terminal connected to the read control signal line.

[0012] In an exemplary embodiment of this disclosure, the read / write conversion circuit further includes: a second signal control module, with a first end connected to the first read / write control module and the second read / write control module, and a second end used to receive the second signal, controlled by a preset enable signal, and used to transmit the second signal to the first read / write control module and the second read / write control module when the preset enable signal is in an enabled state.

[0013] In an exemplary embodiment of this disclosure, the second signal control module includes: a tenth transistor, a first terminal connected to the first read / write control module and the second read / write control module, a second terminal for receiving the second signal, and a control terminal for receiving the preset enable signal.

[0014] In one exemplary embodiment of this disclosure, the second signal is at a low level and the first signal is at a high level.

[0015] In an exemplary embodiment of this disclosure, a read control signal line and a write control signal line are also connected. The read control signal line is used to transmit a read control signal, and the write control signal line is used to transmit a write control signal. The read-write conversion circuit further includes: a read control module connected to the global signal line, the complementary local signal line, and the read control signal line, used to output a second signal to the global signal line when the complementary local signal line transmits a first signal and the read control signal is enabled; a first write control module connected to the global signal line, the local signal line, and the write control signal line, used to transmit the signal on the global signal line to the local signal line when the write control signal is enabled; and a second write control module connected to the global signal line, the complementary local signal line, and the write control signal line, used to output a second signal to the complementary local signal line when the write control signal is enabled and the global signal line transmits the first signal.

[0016] In an exemplary embodiment of this disclosure, the read-write conversion circuit further includes: a read-write auxiliary module connected to the first write control module, the local signal line, and the complementary local signal line, configured to output a first signal to the complementary local signal line when the write control signal is enabled and the global signal line is a second signal; the read-write auxiliary module is further configured to amplify the signals transmitted by the local signal line and the complementary local signal line when the read control signal is enabled.

[0017] In an exemplary embodiment of this disclosure, the read / write assist module includes: a second signal assist module, which receives the second signal and is controlled by a preset enable signal, for transmitting the second signal to the complementary local signal line when the preset enable signal is enabled and the voltage transmitted by the local signal line is greater than the voltage transmitted by the complementary local signal line; and for transmitting the second signal to the local signal line when the preset enable signal is enabled and the voltage transmitted by the local signal line is less than the voltage transmitted by the complementary local signal line.

[0018] In an exemplary embodiment of this disclosure, the read / write assist module is further connected to the preset voltage source, which is used to provide a first voltage when the read control signal is enabled. The read / write assist module is also used to output the first signal to the local signal line when the voltage transmitted on the local signal line is greater than the voltage transmitted on the complementary local signal line, and to output the first signal to the complementary local signal line when the voltage transmitted on the local signal line is less than the voltage transmitted on the complementary local signal line. The first signal is equal to the first voltage.

[0019] In an exemplary embodiment of this disclosure, the read control module includes a fourth transistor, a first terminal of which is connected to the local signal line, a second terminal of which is connected to the global signal line, and a control terminal of which is connected to the write control signal line; the first write control module includes: a fifth transistor, a first terminal of which is connected to the global signal line, and a control terminal of which is connected to the complementary local signal line; a sixth transistor, a first terminal of which is connected to the second terminal of the fifth transistor, the second terminal of which is used to receive the second signal, and a control terminal of which is connected to the read control signal line; the second write control module includes: an eleventh transistor, a first terminal of which is connected to the complementary local signal line, and a control terminal of which is connected to the global signal line; and a twelfth transistor, a first terminal of which is connected to the second terminal of the eleventh transistor, the second terminal of which is used to receive the second signal, and a control terminal of which is connected to the write control signal line.

[0020] In an exemplary embodiment of this disclosure, the read / write auxiliary module includes: a thirteenth transistor, with a first terminal connected to the preset voltage source, a second terminal connected to the complementary local signal line, and a control terminal connected to the local signal line; a fourteenth transistor, with a first terminal connected to the preset voltage source, a second terminal connected to the local signal line, and a control terminal connected to the complementary local signal line; a fifteenth transistor, with a first terminal connected to the local signal line, a second terminal for receiving a second signal, and a control terminal connected to the complementary local signal line; and a sixteenth transistor, with a first terminal connected to the complementary local signal line, a second terminal for receiving a second signal, and a control terminal connected to the local signal line.

[0021] In an exemplary embodiment of this disclosure, the second signal auxiliary module includes: a seventeenth transistor, a first terminal connected to the second terminal of the fifteenth transistor and the second terminal of the sixteenth transistor, the second terminal being used to receive a second signal, and a control terminal being used to receive a preset enable signal, and to output the second signal to the fifteenth transistor and the sixteenth transistor when the preset enable signal is in an enabled state.

[0022] In one exemplary embodiment of this disclosure, the preset voltage source is simultaneously connected to multiple read / write conversion circuits.

[0023] In an exemplary embodiment of this disclosure, the preset voltage source is disposed in the line decoding and control circuit. The preset voltage source includes: a first switching element, with a first terminal connected to the first voltage, a second terminal connected to the output terminal of the preset voltage source, and a control terminal connected to the first voltage output control signal; a second switching element, with a first terminal connected to the second voltage, a second terminal connected to the output terminal of the preset voltage source, and a control terminal connected to the second voltage output control signal; and a voltage switching unit connected to the first switching element and the second switching element, used to output the first voltage output control signal during the read / write interval and to output the second voltage output control signal during the idle period.

[0024] In one exemplary embodiment of this disclosure, the pre-charge module is disposed in a sensitive amplifier array.

[0025] According to a second aspect of this disclosure, a memory is provided, comprising: a plurality of memory arrays, wherein a sensitive amplifier array is disposed between each two adjacent memory arrays, and each sensitive amplifier array is connected to the two adjacent memory arrays; a read / write conversion circuit as described in any of the preceding claims, connected to a global signal line and connected to the sensitive amplifier arrays through a local signal line and a complementary local signal line; and a row decoding and control circuit, provided with a preset voltage source, the preset voltage source being used to output a first voltage and a second voltage to the read / write conversion circuit.

[0026] This embodiment of the disclosure modifies the circuit structure of the read / write conversion circuit, sets up a read / write conversion circuit connected to different power supply voltages, and adjusts the timing to make the read / write conversion circuit connect to different power supply voltages and achieve different functions in different working stages. This can integrate the two parts of the read / write conversion circuit (LSA) into one, reducing the layout area of ​​the read / write conversion circuit.

[0027] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Attached Figure Description

[0028] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure. It is obvious that the drawings described below are merely some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.

[0029] Figure 1 This is a schematic diagram of a read / write conversion circuit in the prior art.

[0030] Figure 2 This is a schematic diagram of the read / write conversion circuit in an exemplary embodiment of this disclosure.

[0031] Figure 3 This is a circuit diagram of a pre-charging module in one embodiment of this disclosure.

[0032] Figure 4 This is a schematic diagram of a preset voltage source in one embodiment of this disclosure.

[0033] Figure 5 This is a schematic diagram of a read / write conversion circuit in one embodiment of this disclosure.

[0034] Figure 6A and Figure 6B They are Figure 5Two circuit embodiments of the read / write conversion circuit are shown.

[0035] Figure 7 This is a schematic diagram of a read / write conversion circuit in another embodiment of this disclosure.

[0036] Figure 8 yes Figure 7 The diagram shows a circuit embodiment of the read / write conversion circuit.

[0037] Figure 9 yes Figure 7 A schematic diagram of one embodiment of the read / write conversion circuit shown.

[0038] Figure 10 yes Figure 9 The diagram shows a schematic of a read / write conversion circuit.

[0039] Figure 11 yes Figure 9 A schematic diagram of one embodiment of the read / write conversion circuit shown.

[0040] Figure 12 This is a schematic diagram of a memory provided in an exemplary embodiment of this disclosure. Detailed Implementation

[0041] Example embodiments will now be described more fully with reference to the accompanying drawings. However, example embodiments can be implemented in many forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided to make this disclosure more comprehensive and complete, and to fully convey the concept of the example embodiments to those skilled in the art. The described features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. In the following description, numerous specific details are provided to give a full understanding of embodiments of this disclosure. However, those skilled in the art will recognize that the technical solutions of this disclosure can be practiced with one or more of the specific details omitted, or other methods, components, apparatus, steps, etc., can be employed. In other instances, well-known technical solutions are not shown or described in detail to avoid obscuring various aspects of this disclosure.

[0042] Furthermore, the accompanying drawings are merely illustrative of this disclosure, and the same reference numerals in the drawings denote the same or similar parts, thus repeated descriptions of them will be omitted. Some of the schematic diagrams shown in the drawings are functional entities and do not necessarily correspond to physically or logically independent entities. These functional entities may be implemented in software, in one or more hardware modules or integrated circuits, or in different network and / or processor devices and / or microcontroller devices.

[0043] The exemplary embodiments of this disclosure will now be described in detail with reference to the accompanying drawings.

[0044] Figure 2 This is a schematic diagram of the read / write conversion circuit in an exemplary embodiment of this disclosure.

[0045] refer to Figure 2 The read / write conversion circuit 200 is connected to the global signal line Gdata and to the sensitive amplifier array SA via the local signal line Ldata and the complementary local signal line Ldata#. It is used to transmit the signal on the local signal line Ldata to the global signal line Gdata when a read control signal Rd is received, and to transmit the signal on the global signal line Gdata to the local signal line Ldata when a write control signal Wr is received. It may include:

[0046] The pre-charge module 1 is connected to a preset voltage source 2, a local signal line Ldata, and a complementary local signal line Ldata#. The preset voltage source 1 is used to provide a first voltage Vcc during the read / write interval and a second voltage VEQ during the idle period. During the read / write interval, the first voltage Vcc is transmitted to the local signal line Ldata and the complementary local signal line Ldata#, and during the idle period, the second voltage VEQ is transmitted to the local signal line Ldata and the complementary local signal line Ldata#. The second voltage VEQ is less than the first voltage Vcc.

[0047] In this embodiment of the disclosure, the pre-charge module 1 is disposed in the sensitive amplifier array SA.

[0048] Compared to existing technologies that divide the read / write conversion circuit into two parts, the present invention uses a pre-charge module 1 capable of providing two voltages to transmit different voltages to the local signal line Ldata and the complementary local signal line Ldata# under different operating states, which can reduce the number of components and the layout area of ​​the read / write conversion circuit.

[0049] The embodiments of this disclosure will now be described in detail.

[0050] Figure 3 This is a circuit diagram of a pre-charging module in one embodiment of this disclosure.

[0051] refer to Figure 3 In one embodiment, the pre-charging module 1 includes:

[0052] The first transistor M1 has its first terminal connected to the preset voltage source 2, its second terminal connected to the local signal line Ldata, and its control terminal connected to the pre-charge signal line Eq.

[0053] The second transistor M2 has its first terminal connected to a preset voltage source 2, its second terminal connected to a complementary local signal line Ldata#, and its control terminal connected to a pre-charge signal line Eq.

[0054] The third transistor M3 has its first terminal connected to the local signal line Ldata, its second terminal connected to the complementary local signal line Ldata#, and its control terminal connected to the precharge signal line Eq.

[0055] The precharge signal line Eq is used to transmit the precharge signal, which controls the voltage settings of the local signal line Ldata and the complementary local signal line Ldata# under different operating states. When the precharge signal is high, the first transistor M1, the second transistor M2, and the third transistor M3 can all be N-type transistors to respond to the precharge signal and set the local signal line Ldata and the complementary local signal line Ldata# to be equal, and both equal to the first voltage Vcc or the second voltage VEQ.

[0056] In other embodiments, the pre-charging module 1 may also be implemented by other components, and this disclosure does not impose any special restrictions on it.

[0057] Figure 4 This is a schematic diagram of a preset voltage source in one embodiment of this disclosure.

[0058] refer to Figure 4 In this embodiment of the disclosure, a preset voltage source 2 is disposed in the line decoding and control circuit (X Decoder, XDEC), and the preset voltage source 2 includes:

[0059] The first switching element K1 has a first terminal connected to a first voltage, a second terminal connected to the output terminal of a preset voltage source 2, and a control terminal connected to the first voltage output control signal.

[0060] The second switching element K2 has a first terminal connected to the second voltage, a second terminal connected to the output terminal of the preset voltage source 2, and a control terminal connected to the second voltage output control signal EN1.

[0061] The voltage switching unit 21 is connected to the first switching element K1 and the second switching element K2, and is used to output the first voltage output control signal EN1 during the read / write interval and the second voltage output control signal EN2 during the idle period.

[0062] The voltage output from the output terminal of the preset voltage source 2 can be labeled as the mode voltage VLSAloc. As can be seen from the above embodiment, the mode voltage VLSAloc is equal to the first voltage Vcc during the read / write interval and equal to the second voltage VEQ during the idle period.

[0063] The voltage switching unit 21 can be a controller in XDEC. Depending on the type of the first voltage output control signal EN1 and the second voltage output control signal EN2 output by the voltage switching unit 21, the first switching element K1 and the second switching element K2 can be implemented using transistors or other components. Figure 4In the illustrated embodiment, both the first switching element K1 and the second switching element K2 are N-type transistors. In other embodiments, the first switching element K1 and the second switching element K2 may be other elements.

[0064] In this embodiment of the disclosure, the preset voltage source 2 is connected to multiple read / write conversion circuits simultaneously, that is, to multiple pre-charge modules 1 simultaneously.

[0065] By using a preset voltage source 2 set in the XDEC to provide a first voltage Vcc and a second voltage VEQ at different working periods, the two functions of the read / write conversion circuit can be realized by a single precharge module 1. Each read / write conversion module can be configured with only one precharge module 1, and the read / write conversion module can be set only in the SA array. There is no need to set another part of the read / write conversion module in the SWC circuit (in the prior art, this part is usually two sets of voltage transmission circuits controlled by control signals corresponding to the two working states). There is no need to consider the setting and area of ​​two voltage transmission circuits during layout, which can greatly save the number of components and layout area of ​​the read / write conversion circuit.

[0066] Figure 5 This is a schematic diagram of a read / write conversion circuit in one embodiment of this disclosure.

[0067] refer to Figure 5 In one embodiment, the read / write conversion circuit 500, based on the read / write conversion circuit 200, is further connected to a complementary global signal line Gdata#, a read control signal line, and a write control signal line. The read control signal line is used to transmit the read control signal Rd, and the write control signal line is used to transmit the write control signal Wr. The read / write conversion circuit 500 also includes:

[0068] The first read / write control module 51 is connected to the local signal line Ldata, the complementary local signal line Ldata#, the global signal line Gdata, the read control signal line Rd, and the write control signal line Wr. It is used to transmit the signal on the global signal line Gdata to the local signal line Ldata when the write control signal is enabled, and to output a second signal S2 to the global signal line Gdata when the read control signal is enabled and the complementary local signal line Ldata# transmits the first signal S1. The second signal S2 is out of phase with the first signal S1.

[0069] The second read / write control module 52 is connected to the local signal line Ldata, the complementary local signal line Ldata#, the complementary global signal line Gdata#, the read control signal line Rd, and the write control signal line Wr. It is used to transmit the signal on the complementary global signal line Gdata# to the complementary local signal line Ldata# when the write control signal is enabled, and to output the second signal S2 to the complementary global signal line Gdata# when the read control signal is enabled and the local signal line Ldata transmits the first signal S1.

[0070] Figure 6A and Figure 6B They are Figure 5 Two circuit embodiments of the read / write conversion circuit are shown.

[0071] refer to Figure 6A In one embodiment, the first read / write control module 51 may include:

[0072] The fourth transistor M4 has its first terminal connected to the local signal line Ldata, its second terminal connected to the global signal line Gdata, and its control terminal connected to the write control signal line Wr.

[0073] The fifth transistor M5 has its first terminal connected to the global signal line Gdata, and its control terminal connected to the complementary local signal line Ldata#.

[0074] The sixth transistor M6 has its first terminal connected to the second terminal of the fifth transistor M5. The second terminal is used to receive the second signal S2, and the control terminal is connected to the read control signal line Rd.

[0075] The second read / write control module 52 may include:

[0076] The seventh transistor M7 has its first terminal connected to the complementary local signal line Ldata#, its second terminal connected to the complementary global signal line Gdata#, and its control terminal connected to the write control signal line Wr.

[0077] The eighth transistor M8 has its first terminal connected to the complementary global signal line Gdata#, and its control terminal connected to the local signal line Ldata.

[0078] The ninth transistor M9 has its first terminal connected to the second terminal of the eighth transistor M8. The second terminal is used to receive the second signal S2, and the control terminal is connected to the read control signal line Rd.

[0079] Figure 6A The working principle of the embodiment shown is as follows:

[0080] During the read / write interval, the pre-charge phase begins. The pre-charge signal is enabled, and the first transistor M1 and the second transistor M2 are turned on. The signals on the local signal line Ldata and the complementary local signal line Ldata# are equal, both equal to the first voltage Vcc, resulting in a logic level of 1. Next, the pre-charge signal enters an inactive state, ending the pre-charge phase.

[0081] When the read control signal is enabled, the write control signal is disabled, and the sixth transistor M6 and the ninth transistor M9 are turned on. At this time, the gate of the fifth transistor M5 is controlled by the complementary local signal line Ldata#, and the gate of the eighth transistor M8 is controlled by the local signal line Ldata.

[0082] When the local signal line Ldata is set to the first signal (logic level 1) by the sensitive amplifier and the complementary local signal line Ldata# is set to the second signal (logic level 0) by the sensitive amplifier, the fifth transistor M5 is off, the eighth transistor M8 is on, and the complementary global signal line Gdata# is grounded through the on-state eighth transistor M8 and the ninth transistor M9, exhibiting a logic level of 0. The state of the complementary global signal line Gdata# is the same as the state of the complementary local signal line Ldata#.

[0083] When the local signal line Ldata is set to the second signal (logic level 0) by the sensitive amplifier, and the complementary local signal line Ldata# is set to the first signal (logic level 1) by the sensitive amplifier, the fifth transistor M5 is turned on, the eighth transistor M8 is turned off, and the global signal line Gdata is grounded through the turned-on fifth transistor M5 and the sixth transistor M6, exhibiting a logic level of 0. The state of the global signal line Gdata is the same as the state of the local signal line Ldata.

[0084] Therefore, the data transmitted by the sensitive amplifier to the local signal line Ldata and the complementary local signal line Ldata# is transmitted to the global signal line Gdata and the complementary global signal line Gdata# respectively through the read-write conversion circuit.

[0085] When the write control signal is enabled, the read control signal is disabled. At this time, the fourth transistor M4 and the seventh transistor M7 are turned on. The state of the global signal line Gdata is the same as the state of the local signal line Ldata, and the state of the complementary global signal line Gdata# is the same as the state of the complementary local signal line Ldata#. Data on the global signal line Gdata and the complementary global signal line Gdata# is transmitted to the local signal line Ldata and the complementary local signal line Ldata# respectively through the read-write conversion circuit, and then transmitted to the sensitive amplifier through the local signal line Ldata and the complementary local signal line Ldata#.

[0086] During idle periods (e.g., when the read / write process ends), after the pre-charge phase ends, the third transistor M3 is turned off, and the voltages of the local signal line Ldata and the complementary local signal line Ldata# are equal, both equal to the second voltage VEQ which is lower than the first voltage Vcc. At this time, both the read control signal and the write control signal are in an inactive state, and neither the first read / write control module 51 nor the second read / write control module 52 works. The circuit operates at a low power consumption.

[0087] refer to Figure 6B In one embodiment, the read / write switching circuit may further include:

[0088] The second signal control module 61 has its first end connected to the first read / write control module 51 and the second read / write control module 52, and its second end used to receive the second signal S2. It is controlled by a preset enable signal En and is used to transmit the second signal S2 to the first read / write control module 51 and the second read / write control module 52 when the preset enable signal En is enabled.

[0089] exist Figure 6B In the illustrated embodiment, the second signal control module 61 may include:

[0090] The tenth transistor M10 has its first terminal connected to the first read / write control module 51 and the second read / write control module 52, its second terminal used to receive the second signal S2, and its control terminal used to receive the preset enable signal En. In the embodiment shown in Figure 6, the second signal S2 is equal to a 0 potential, i.e., logic level 0, and the first signal S2 is equal to a logic level 1.

[0091] exist Figure 6A and Figure 6B In the embodiment shown, the fourth transistor M4, the fifth transistor M5, the sixth transistor M6, the seventh transistor M7, the eighth transistor M8, the ninth transistor M9, and the tenth transistor M10 are all N-type transistors, the second signal S2 is logic level 0, and the first signal S1 is logic level 1.

[0092] Figure 6A and Figure 6B The circuit shown is merely an example; in other embodiments, it can be implemented using other logic circuits. Figure 6A and Figure 6B The function of the circuit shown can be achieved through other means. Figure 6A and Figure 6B When the circuit shown functions, the first signal S1 and the second signal S2 can also have other relationships, and this disclosure does not impose any special restrictions on this.

[0093] Figure 7 This is a schematic diagram of a read / write conversion circuit in another embodiment of this disclosure.

[0094] refer to Figure 7In one embodiment, the read / write conversion circuit 700, based on the read / write conversion circuit 200, is further connected to a read control signal line Rd and a write control signal line Wr. The read control signal line Rd is used to transmit read control signals, and the write control signal line Wr is used to transmit write control signals. The read / write conversion circuit also includes:

[0095] The read control module 71 is connected to the global signal line Gdata, the complementary local signal line Ldata#, and the read control signal line Rd. It is used to output the second signal S2 to the global signal line Gdata when the first signal S1 is transmitted on the complementary local signal line Ldata# and the read control signal is enabled.

[0096] The first write control module 72 is connected to the global signal line Gdata, the local signal line Ldata and the write control signal line Wr. It is used to transmit the signal on the global signal line Gdata to the local signal line Ldata when the write control signal is enabled.

[0097] The second write control module 73 is connected to the global signal line Gdata, the complementary local signal line Ldata#, and the write control signal line Wr. When the write control signal is enabled and the global signal line Gdata transmits the first signal S1, it outputs the second signal S2 to the complementary local signal line Ldata#.

[0098] Figure 8 yes Figure 7 The diagram shows a circuit embodiment of the read / write conversion circuit.

[0099] refer to Figure 8 In one embodiment, the read control module 71 includes a fourth transistor M4, the first terminal of which is connected to the local signal line Ldata, the second terminal of which is connected to the global signal line Gdata, and the control terminal of which is connected to the write control signal line Wr.

[0100] The first write control module 72 includes:

[0101] The fifth transistor M5 has its first terminal connected to the global signal line and its control terminal connected to the complementary local signal line.

[0102] The sixth transistor M6 has its first terminal connected to the second terminal of the fifth transistor M5. The second terminal is used to receive the second signal S2, and the control terminal is connected to the read control signal line Rd.

[0103] The second write control module 73 includes:

[0104] The eleventh transistor M11 has its first terminal connected to the complementary local signal line and its control terminal connected to the global signal line.

[0105] The twelfth transistor M12 has its first terminal connected to the second terminal of the eleventh transistor M11. The second terminal is used to receive the second signal S2, and the control terminal is connected to the write control signal line Wr.

[0106] exist Figure 8 In the embodiment shown, the fourth transistor M4, the fifth transistor M5, the sixth transistor M6, the eleventh transistor M11, and the twelfth transistor M12 are all N-type transistors, the first signal S1 is logic level 1, and the second signal S2 is logic level 0.

[0107] Figure 8 The working process of the illustrated embodiment is as follows:

[0108] During the read / write interval, the pre-charge phase begins. The pre-charge signal is enabled, and the first transistor M1 and the second transistor M2 are turned on. The signals on the local signal line Ldata and the complementary local signal line Ldata# are equal, both equal to the first voltage Vcc, resulting in a logic level of 1. Next, the pre-charge signal enters an inactive state, ending the pre-charge phase.

[0109] When the read control signal is enabled, the write control signal is disabled, and the sixth transistor M6 is turned on. At this time, the gate of the fifth transistor M5 is controlled by the complementary local signal line Ldata#. The global signal line Gdata is first pre-charged to the first voltage Vcc, which is represented by logic level 1. When the complementary local signal line Ldata# is set to the second signal (logic level 0) by the sensitive amplifier, the fifth transistor M5 is turned off, and the global signal line Gdata remains at the first voltage Vcc, which is represented by logic level 1.

[0110] When the complementary local signal line Ldata# is set to the first signal (logic level 1) by the sensitive amplifier, it means that the local signal line Ldata is set to the second signal (logic level 0) by the sensitive amplifier. The fifth transistor M5 is turned on, and the global signal line Gdata is grounded through the turned-on fifth transistor M5 and sixth transistor M6, which is reflected as a logic level of 0. The state of the global signal line Gdata is the same as the state of the local signal line Ldata.

[0111] When the write control signal is enabled, the read control signal is disabled. At this time, the fourth transistor M4 is turned on, and the state of the global signal line Gdata is the same as the state of the local signal line Ldata. That is, the data on the global signal line Gdata is transmitted to the local signal line Ldata, and then transmitted to the sensitive amplifier through the local signal line Ldata.

[0112] At this point, if the global signal line Gdata transmits logic level 1, the eleventh transistor M11 is turned on, and the complementary local signal line Ldata# is grounded through the turned-on eleventh transistor M11 and twelfth transistor M12, exhibiting logic level 0, which is the opposite of the state of the local signal line Ldata. If the global signal line Gdata transmits logic level 0, the eleventh transistor M11 is turned off, and the complementary local signal line Ldata# remains at logic level 1 at the end of the pre-charge state, which is the opposite of the state of the local signal line Ldata. Thus, the signal from the global signal line Gdata is transmitted to the sensitive amplifier through the local signal lines Ldata and Ldata#, which are in opposite states.

[0113] During the idle period, after the pre-charging phase ends, the third transistor M3 is turned off, and the voltages of the local signal line Ldata and the complementary local signal line Ldata# are equal, both equal to the second voltage VEQ which is lower than the first voltage Vcc. At this time, the read control signal and the write control signal are both in a disabled state, and the read control module 71, the first write control module 72, and the second write control module 73 are all not working, and the circuit operates at a low power consumption.

[0114] Figure 9 yes Figure 7 A schematic diagram of one embodiment of the read / write conversion circuit shown.

[0115] refer to Figure 9 In one embodiment, the read / write conversion circuit 900, based on the read / write conversion circuit 700, further includes:

[0116] The read / write auxiliary module 91 is connected to the first write control module 72, the local signal line Ldata, and the complementary local signal line Ldata#. When the write control signal is enabled and the global signal line Gdata is the second signal S2, it outputs the first signal S1 to the complementary local signal line Ldata#.

[0117] The read / write auxiliary module 91 is also used to amplify the signals transmitted by the local signal line Ldata and the complementary local signal line Ldata# when the read control signal Rd is enabled.

[0118] In one embodiment, the read / write auxiliary module 91 is also connected to a preset voltage source 2. The preset voltage source 2 is used to provide a first voltage Vcc when the read control signal is enabled. The read / write auxiliary module 91 is also used to output a first signal S1 to the local signal line Ldata when the voltage transmitted by the local signal line Ldata is greater than the voltage transmitted by the complementary local signal line Ldata#, and to output a first signal S1 to the complementary local signal line Ldata# when the voltage transmitted by the local signal line Ldata is less than the voltage transmitted by the complementary local signal line Ldata#. The first signal S1 is equal to the first voltage Vcc.

[0119] Figure 10 yes Figure 9 The diagram shows a schematic of a read / write conversion circuit.

[0120] refer to Figure 10 In one embodiment, the read / write assistance module 91 may include:

[0121] The thirteenth transistor M13 has its first terminal connected to the preset voltage source 2 (mode voltage VLSAloc), its second terminal connected to the complementary local signal line Ldata#, and its control terminal connected to the local signal line Ldata.

[0122] The fourteenth transistor M14 has its first terminal connected to the preset voltage source 2 (mode voltage VLSAloc), its second terminal connected to the local signal line Ldata, and its control terminal connected to the complementary local signal line Ldata#.

[0123] The fifteenth transistor M15 has its first terminal connected to the local signal line Ldata, its second terminal used to receive the second signal S2, and its control terminal connected to the complementary local signal line Ldata#.

[0124] The sixteenth transistor M16 has its first terminal connected to the complementary local signal line Ldata#, its second terminal used to receive the second signal S2, and its control terminal connected to the local signal line Ldata.

[0125] exist Figure 10 In the illustrated embodiment, the thirteenth transistor M13 and the fourteenth transistor M14 are both P-type transistors, and the fifteenth transistor M15 and the sixteenth transistor M16 are both N-type transistors. The first signal S1 is logic level 1, and the second signal S2 is logic level 0.

[0126] Figure 10 The operation of the read / write assistance module 91 in the illustrated embodiment is as follows:

[0127] Regardless of whether it's during read / write intervals or idle periods, after the pre-charge phase ends, the third transistor M3 turns off. If the voltage of the local signal line Ldata is higher than the voltage of the complementary local signal line Ldata#, the fourteenth transistor M14 and the sixteenth transistor M16 turn on first, causing the thirteenth transistor M13 and the fifteenth transistor M15 to turn off. The voltage on the local signal line Ldata connected to the second terminal of the fourteenth transistor M14 is equal to the mode voltage VLSAloc, and the voltage on the complementary local signal line Ldata# connected to the first terminal of the sixteenth transistor M16 is equal to the second signal S2, i.e., logic level 0. Conversely, if the voltage of the local signal line Ldata is lower than the voltage of the complementary local signal line Ldata#, the thirteenth transistor M13 and the fifteenth transistor M15 turn on first, causing the fourteenth transistor M14 and the sixteenth transistor M16 to turn off. The voltage on the local signal line Ldata connected to the first terminal of the fifteenth transistor M15 is equal to the second signal S2, i.e., logic level 0, and the voltage on the complementary local signal line Ldata# connected to the second terminal of the thirteenth transistor M13 is equal to the mode voltage VLSAloc.

[0128] Therefore, as long as there is a voltage difference between the local signal line Ldata and the complementary local signal line Ldata#, the read / write auxiliary module 91 can amplify this voltage difference into the mode voltage VLSAloc. The mode voltage VLSAloc varies depending on the operating stage, which will not be elaborated here.

[0129] Figure 11 yes Figure 9 A schematic diagram of one embodiment of the read / write conversion circuit shown.

[0130] refer to Figure 11 In one embodiment, the read / write switching circuit further includes:

[0131] The second signal auxiliary module 111 receives the second signal S2 and is controlled by a preset enable signal En. When the preset enable signal En is enabled and the voltage transmitted by the local signal line Ldata is greater than the voltage transmitted by the complementary local signal line Ldata#, the second signal S2 is transmitted to the complementary local signal line Ldata#. When the preset enable signal En is enabled and the voltage transmitted by the local signal line Ldata is less than the voltage transmitted by the complementary local signal line Ldata#, the second signal S2 is transmitted to the local signal line Ldata#.

[0132] exist Figure 11 In the illustrated embodiment, when the second signal assistance module 111 is connected to the read / write assistance module 91, the second signal assistance module 111 may include:

[0133] The seventeenth transistor M17 has its first terminal connected to the second terminal of the fifteenth transistor M15 and the second terminal of the sixteenth transistor M16. The second terminal is used to receive the second signal S2, and the control terminal is used to receive the preset enable signal En. When the preset enable signal En is enabled, the control terminal outputs the second signal S2 to the fifteenth transistor M15 and the sixteenth transistor M16.

[0134] exist Figure 11 In the circuit shown, the fifteenth transistor M15 and the sixteenth transistor M16 are both N-type transistors, the fifth transistor M5 and the eleventh transistor M11 are both N-type transistors, the first signal S1 is logic level 1, and the second signal S2 is logic level 0.

[0135] Figure 12 This is a schematic diagram of a memory provided in an exemplary embodiment of this disclosure.

[0136] refer to Figure 12 The memory 1200 may include:

[0137] Multiple memory arrays 121 are provided, and a sensitive amplifier array 122 is provided between each two adjacent memory arrays. Each sensitive amplifier array 122 is connected to two adjacent memory arrays 121.

[0138] like Figures 2 to 11 The read / write conversion circuit 123 of the illustrated embodiment is connected to the global signal line Gdata, and is connected to the sensitive amplifier array 122 through the local signal line Ldata and the complementary local signal line Ldata#; the row decoding and control circuit XDEC is provided with a preset voltage source 124, which is used to output a first voltage Vcc and a second voltage VEQ to the read / write conversion circuit 123.

[0139] exist Figure 12 In the embodiment shown, the read / write conversion circuit 123 can be disposed in the sensitive amplifier array 122 and connected to the sensitive amplifier array 122.

[0140] The read / write conversion circuit and the memory using the read / write conversion circuit provided in this embodiment of the present disclosure, by setting a preset voltage source that provides two voltages in two operating states and connecting a pre-charge module of multiple read / write conversion circuits, allows the read / write conversion circuit to set the local signal line / complementary local signal line to the first voltage and the second voltage in two operating states with only one pre-charge module. This reduces the number of components in the read / write conversion circuit, reduces the circuit complexity, and allows the read / write conversion circuit to be set only in the sensitive amplifier array, reducing the number of components and the component layout area of ​​the entire storage circuit, and reducing the size of the memory.

[0141] It should be noted that although several modules or units for the device used to perform actions have been mentioned in the detailed description above, this division is not mandatory. In fact, according to embodiments of this disclosure, the features and functions of two or more modules or units described above can be embodied in one module or unit. Conversely, the features and functions of one module or unit described above can be further divided and embodied by multiple modules or units.

[0142] Other embodiments of this disclosure will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of this disclosure that follow the general principles of this disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and concept of this disclosure are indicated by the claims.

Claims

1. A read / write conversion circuit, connected to a global signal line and connected to a sensitive amplifier array via local signal lines and complementary local signal lines, for transmitting signals on the local signal lines to the global signal line when a read control signal is received, and transmitting signals on the global signal line to the local signal line when a write control signal is received, characterized in that... The read / write conversion circuit includes: A pre-charge module is connected to a preset voltage source, the local signal line, and a complementary local signal line. The preset voltage source provides a first voltage during read / write intervals and a second voltage during idle periods. The pre-charge module transmits the first voltage to the local signal line and the complementary local signal line during read / write intervals and transmits the second voltage to the local signal line and the complementary local signal line during idle periods. Wherein, the second voltage is less than the first voltage; The read / write conversion circuit is also connected to a complementary global signal line, a read control signal line, and a write control signal line. The read control signal line is used to transmit read control signals, and the write control signal line is used to transmit write control signals. The read / write conversion circuit further includes: The first read / write control module is connected to the local signal line, the complementary local signal line, the global signal line, the read control signal line, and the write control signal line. It is used to transmit the signal on the global signal line to the local signal line when the write control signal is enabled, and to output a second signal to the global signal line when the read control signal is enabled and the complementary local signal line transmits a first signal. The second signal is inversely related to the first signal. The second read / write control module is connected to the local signal line, the complementary local signal line, the complementary global signal line, the read control signal line, and the write control signal line. It is used to transmit the signal on the complementary global signal line to the complementary local signal line when the write control signal is enabled, and to output a second signal to the complementary global signal line when the read control signal is enabled and the local signal line transmits the first signal.

2. The read / write conversion circuit as described in claim 1, characterized in that, The pre-charging module includes: The first transistor has a first terminal connected to the preset voltage source, a second terminal connected to the local signal line, and a control terminal connected to the pre-charge signal line. The second transistor has a first terminal connected to the preset voltage source, a second terminal connected to the complementary local signal line, and a control terminal connected to the pre-charge signal line. The third transistor has a first terminal connected to the local signal line, a second terminal connected to the complementary local signal line, and a control terminal connected to the pre-charge signal line.

3. The read / write conversion circuit as described in claim 2, characterized in that, The first transistor, the second transistor, and the third transistor are all N-type transistors.

4. The read / write conversion circuit as described in claim 1, characterized in that, The first read / write control module includes: The fourth transistor has its first terminal connected to the local signal line, its second terminal connected to the global signal line, and its control terminal connected to the write control signal line. The fifth transistor has its first terminal connected to the global signal line and its control terminal connected to the complementary local signal line. The sixth transistor has its first terminal connected to the second terminal of the fifth transistor, the second terminal being used to receive the second signal, and its control terminal connected to the read control signal line; The second read / write control module includes: The seventh transistor has its first terminal connected to the complementary local signal line, its second terminal connected to the complementary global signal line, and its control terminal connected to the write control signal line. The eighth transistor has its first terminal connected to the complementary global signal line and its control terminal connected to the local signal line. The ninth transistor has its first terminal connected to the second terminal of the eighth transistor, the second terminal being used to receive the second signal, and its control terminal connected to the read control signal line.

5. The read / write conversion circuit as described in claim 1, characterized in that, Also includes: The second signal control module has a first end connected to the first read / write control module and the second read / write control module, and a second end used to receive the second signal. It is controlled by a preset enable signal and is used to transmit the second signal to the first read / write control module and the second read / write control module when the preset enable signal is enabled.

6. The read / write conversion circuit as described in claim 5, characterized in that, The second signal control module includes: The tenth transistor has a first terminal connected to the first read / write control module and the second read / write control module, a second terminal for receiving the second signal, and a control terminal for receiving the preset enable signal.

7. The read / write conversion circuit as described in any one of claims 1 to 6, characterized in that, The second signal is at a low level, and the first signal is at a high level.

8. The read / write conversion circuit as described in claim 1, characterized in that, The preset voltage source is connected to multiple read / write conversion circuits simultaneously.

9. The read / write conversion circuit as described in claim 1, characterized in that, The preset voltage source is located in the line decoding and control circuit, and the preset voltage source includes: A first switching element has a first terminal connected to the first voltage, a second terminal connected to the output terminal of the preset voltage source, and a control terminal connected to the first voltage output control signal. The second switching element has a first terminal connected to the second voltage, a second terminal connected to the output terminal of the preset voltage source, and a control terminal connected to the second voltage output control signal. A voltage switching unit, connected to the first switching element and the second switching element, is used to output the first voltage output control signal during the read / write interval and to output the second voltage output control signal during the idle period.

10. The read / write conversion circuit as described in claim 1, characterized in that, The pre-charge module is located in the sensitive amplifier array.

11. A memory, characterized in that, include: Multiple memory arrays, with a sensitive amplifier array disposed between each two adjacent memory arrays, and each sensitive amplifier array connected to the two adjacent memory arrays; The read / write conversion circuit as described in any one of claims 1 to 10 is connected to the global signal line and connected to the sensitive amplifier array through local signal lines and complementary local signal lines; The line decoding and control circuit is equipped with a preset voltage source, which is used to output a first voltage and a second voltage to the read-write conversion circuit.

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