Semiconductor device, method of manufacturing the same, and method of measuring the same
By employing a stepped alignment mark structure in semiconductor devices, the problem of accurate alignment of alignment marks in lithography processes is solved, thereby improving the structural integrity and operational performance of the devices.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- FUJIAN JINHUA INTEGRATED CIRCUIT CO LTD
- Filing Date
- 2023-05-18
- Publication Date
- 2026-05-22
Smart Images
Figure CN116705766B_ABST
Abstract
Description
Technical Field
[0001] The present invention generally relates to a semiconductor device, a method for manufacturing the same, and a method for measuring the same, and more specifically, to a semiconductor device having alignment marks, a method for manufacturing the same, and a method for measuring the same. Background Technology
[0002] Photolithography is a crucial step in semiconductor device manufacturing. It involves transferring a design pattern from a photoresist layer to the photoresist layer using exposure and development. The photoresist layer is then used as an etching mask to etch the underlying material layer, transferring the design pattern further down into the material layer to create the circuit structure. Semiconductor manufacturing processes involve repeatedly performing deposition, photolithography, and etching processes to build the integrated circuit structure of semiconductor devices layer by layer. However, as circuit patterns become increasingly detailed and precise, the alignment specifications between upper and lower circuit layers become increasingly stringent. Even slight alignment misalignment can lead to defects such as abnormal contacts, short circuits, or open circuits in the integrated circuit structure. Therefore, the manufacturing processes and designs related to alignment marks require further improvement to effectively enhance the performance and reliability of semiconductor devices. Summary of the Invention
[0003] The purpose of this invention is to provide a semiconductor device and a method for fabricating the same, which ensures that interconnect structures formed in other regions are located in the intended positions by forming alignment marks with a stepped structure. Accordingly, the semiconductor device of this invention has advantages such as structural integrity and optimized operational performance.
[0004] The purpose of this invention is to provide a measurement method for semiconductor devices, which verifies the position of alignment marks on the substrate by detecting alignment marks with a stepped structure, so as to ensure that interconnect structures formed in other regions can be formed in the expected positions.
[0005] To achieve the above objectives, the present invention provides a semiconductor device including a substrate, a first dielectric layer, a plurality of first alignment marks, a second dielectric layer, and a plurality of second alignment marks. The first dielectric layer is disposed on the substrate. The first alignment marks are disposed within the first dielectric layer, each first alignment mark having at least one first sidewall in the horizontal direction. The second dielectric layer is disposed on the first dielectric layer. The second alignment marks are disposed within the second dielectric layer, spaced apart from each other, each second alignment mark having a stepped structure and having a plurality of second sidewalls in the horizontal direction, wherein the plurality of second sidewalls of each second alignment mark are disposed between two adjacent first sidewalls.
[0006] Optionally, the bottom surface of each of the second alignment marks may only physically contact a single material.
[0007] Optionally, at least one of the second alignment marks is disposed between two adjacent first alignment marks and in physical contact with the top surface of the first dielectric layer.
[0008] Optionally, at least one of the second alignment marks is arranged alternately with each of the first alignment marks and does not overlap with each of the first alignment marks in the vertical direction.
[0009] Optionally, at least one of the second alignment marks overlaps with one of the first alignment marks in the vertical direction and physically contacts the top surface of the first alignment mark.
[0010] Optionally, at least one of the second alignment marks includes a plurality of stepped structures connected to each other.
[0011] Optionally, at least one of the second alignment marks overlaps with one of the first alignment marks in the vertical direction and physically contacts the top surface of the first alignment mark.
[0012] Optionally, a plurality of first alignment marks are disposed between two adjacent second alignment marks, and the top surfaces of the plurality of first alignment marks are made of the same material.
[0013] To achieve the above objectives, the present invention provides a method for fabricating a semiconductor device, comprising the following steps: A substrate is provided, and a first dielectric layer is formed on the substrate. A plurality of first alignment marks are formed within the first dielectric layer, wherein each first alignment mark has at least one first sidewall in a horizontal direction. A plurality of second alignment marks are formed on the first dielectric layer, the plurality of second alignment marks being formed on the first alignment marks in a spaced-apart manner, each second alignment mark having a stepped structure and having a plurality of second sidewalls in a horizontal direction, wherein the plurality of second sidewalls of each second alignment mark are disposed between two adjacent first sidewalls.
[0014] Optionally, forming the second alignment mark further includes: forming a metal layer on the first dielectric layer; forming a mask layer on the metal layer to expose a portion of the top surface of the metal layer; performing a first etching process on the metal layer through the mask layer to partially remove the metal layer; and performing a trimming-etching process on the metal layer after the first etching process to form the stepped structure of the second alignment mark.
[0015] Optionally, the trimming-etching process further includes: step (a), trimming the mask layer to expose another portion of the top surface of the metal layer; step (b), performing a second etching process through the mask layer after step (a) to form a step on the metal layer; and repeating steps (a) and (b) to form a plurality of the steps of the second alignment mark.
[0016] Optionally, the width of the steps decreases progressively from bottom to top in the horizontal direction, and each step has a different height.
[0017] Optionally, at least one of the second alignment marks is disposed between two adjacent first alignment marks.
[0018] Optionally, at least one of the second alignment marks overlaps with one of the first alignment marks in the vertical direction.
[0019] To achieve the above objectives, the present invention provides a method for measuring semiconductor devices, comprising the following steps: A semiconductor structure is provided, the semiconductor structure including a substrate, a plurality of first alignment marks disposed on the substrate, and a plurality of stepped structures disposed on the first alignment marks. The semiconductor structure is then measured using a testing machine to obtain the positions of the first alignment marks and the stepped structures on the substrate.
[0020] Optionally, the semiconductor structure further includes: a first semiconductor structure, the first semiconductor structure including: a first substrate; a plurality of first alignment marks disposed on the first substrate; and a plurality of first stepped structures disposed on the first alignment marks on the first substrate, each of the first stepped structures being disposed between two first alignment marks on the first substrate; and a second semiconductor structure, the second semiconductor structure including: a second substrate; a plurality of first alignment marks disposed on the second substrate; and a plurality of second stepped structures disposed on the first alignment marks on the second substrate, at least a portion of the second stepped structures overlapping one of the first alignment marks on the second substrate in the vertical direction.
[0021] Optionally, it further includes: generating different first signals and second signals respectively by detecting the material difference between the first alignment mark, the first stepped structure and the first substrate on the first substrate using the detection equipment; and generating a third signal by detecting the material difference between the first alignment mark, the second stepped structure and the second substrate on the second substrate using the detection equipment.
[0022] Optionally, each of the first alignment marks has at least one first sidewall in the horizontal direction; each of the stepped structures has a plurality of second sidewalls in the horizontal direction, and the plurality of second sidewalls of each stepped structure are disposed between two adjacent first sidewalls.
[0023] Optionally, it also includes: combining the first signal, the second signal, and the third signal to obtain a filtered signal.
[0024] Optionally, it also includes: defining the position of the first alignment mark on the first substrate using the filter signal. Attached Figure Description
[0025] Figure 1 A cross-sectional schematic diagram of a semiconductor device according to a first embodiment of the present invention is shown.
[0026] Figures 2 to 4 A schematic diagram illustrating a method for fabricating a semiconductor device according to a first embodiment of the present invention is shown, wherein...
[0027] Figure 2 This is a schematic cross-sectional view of a semiconductor device after the metal layer has been formed.
[0028] Figure 3 This is a cross-sectional view of a semiconductor device after an etching process; and
[0029] Figure 4 This is a schematic cross-sectional view of a semiconductor device after a trimming-etching process.
[0030] Figure 5 A cross-sectional schematic diagram of a semiconductor device according to a second embodiment of the present invention is shown.
[0031] Figure 6 A cross-sectional schematic diagram of a semiconductor device according to a third embodiment of the present invention is shown.
[0032] Figure 7 A cross-sectional schematic diagram of a semiconductor device according to a fourth embodiment of the present invention is shown.
[0033] Figure 8 and Figure 9 A cross-sectional schematic diagram of a semiconductor device according to a fifth embodiment of the present invention is shown, wherein...
[0034] Figure 8 This is a cross-sectional schematic diagram of the semiconductor device in the fifth embodiment of the present invention; and
[0035] Figure 9 This is a cross-sectional schematic diagram of another semiconductor device in the fifth embodiment of the present invention.
[0036] Figure 10A cross-sectional schematic diagram of a semiconductor device according to the sixth embodiment of the present invention is shown.
[0037] Figures 11 to 12 A schematic diagram illustrating a measurement method for a semiconductor device according to a preferred embodiment of the present invention is shown, wherein...
[0038] Figure 11 A schematic diagram illustrating the steps of a measurement method for semiconductor devices; and
[0039] Figure 12 This is a schematic diagram of the testing steps for a semiconductor device.
[0040] The reference numerals in the attached figures are explained as follows:
[0041] 10, 20, 30, 40, 50, 50a, 60 semiconductor devices
[0042] 70 Semiconductor Structure
[0043] 72 First Semiconductor Structure
[0044] 74 Second Semiconductor Structure
[0045] 100 substrate
[0046] 102 Dielectric Layer
[0047] 104 Dielectric Layer
[0048] 106 Etching Stop Layer
[0049] 108 First dielectric layer
[0050] 108a Top surface
[0051] 110 First alignment mark
[0052] 110a Top surface
[0053] 114 Second Dielectric Layer
[0054] 116 Second Alignment Mark
[0055] Steps 116a, 116b, and 116c
[0056] 118 Metal Layer
[0057] 118a Top surface
[0058] 118b Low-lying top surface
[0059] Mask layers 120 and 122
[0060] 124 steps
[0061] Second alignment marks 126, 136, 146, 146a, 146b
[0062] Second alignment marks 156, 158, 166, 166a, 166b
[0063] 176 First step structure
[0064] 178 Second step structure
[0065] A1 First Signal
[0066] A2 Second Signal
[0067] A3 Third Signal
[0068] E1 First Etching Process
[0069] E2 Trimming-Etching Process
[0070] H1, H2, H3 height
[0071] Steps S1 and S2
[0072] Widths of W1, W2, and W3 Detailed Implementation
[0073] To enable those skilled in the art to further understand this invention, several preferred embodiments are listed below, along with accompanying drawings, to explain in detail the technical solutions and desired effects of this invention. Those skilled in the art can, without departing from the spirit of this invention, substitute, recombine, or mix features from the following embodiments to complete other embodiments.
[0074] Figure 1A cross-sectional schematic diagram of a semiconductor device 10 according to a first embodiment of the present invention is shown. The semiconductor device 10 includes a substrate 100, such as a silicon substrate, a silicon-containing substrate, an epitaxial silicon substrate, a silicon-on-insulator substrate, or a substrate made of other suitable materials, but not limited thereto. A dielectric layer 102, a dielectric layer 104, an etch stop layer 106, and a first dielectric layer 108 are sequentially disposed on the substrate 100. It should be noted that a plurality of first alignment marks 110 are disposed on the substrate 100, spaced apart from each other within the first dielectric layer 108, the etch stop layer 106, and a portion of the dielectric layer 104, such that the top surface 110a of the first alignment mark 110 is coplanar (108a / 110a) with the top surface 108a of the first dielectric layer 108. Furthermore, a second dielectric layer 114 and a plurality of second alignment marks 116 are also disposed on the substrate 100. The second dielectric layer 114 is disposed on the first dielectric layer 108, and the second alignment marks 116 are disposed within the second dielectric layer 114, spaced apart from each other. The second alignment marks 116 are located on the coplanar plane 108a / 110a of the first alignment marks 110 and the first dielectric layer 108, and each has a stepped structure. In this embodiment, the second alignment marks 116 physically contact the top surface 108a of the first dielectric layer 108, and do not overlap with the plurality of lower first alignment marks 110, such as... Figure 1 As shown. That is, a plurality of first alignment marks 110 are disposed between two adjacent second alignment marks 116 such that their top surfaces 110a only contact the second dielectric layer 114.
[0075] Dielectric layer 102, dielectric layer 104, etch stop layer 106, first dielectric layer 108, and second dielectric layer 114 each comprise a dielectric material, such as silicon oxide (SiO2), silicon nitride (SiN), silicon oxynitride (SiON), or silicon carbonitride (SiCN). First alignment mark 110 and second alignment mark 116 comprise, for example, tungsten (W), copper (Cu), aluminum (Al), titanium (Ti), tantalum (Ta), or other suitable low-resistivity metal materials, but are not limited thereto. In this embodiment, dielectric layer 102 and etch stop layer 106 preferably comprise the same material, such as silicon nitride, while dielectric layer 104, first dielectric layer 108, and second dielectric layer 114 preferably comprise the same material, such as silicon oxide, different from dielectric layer 102 and etch stop layer 106, but are not limited thereto.
[0076] In detail, the stepped structure of the second alignment mark 116 includes multiple steps 116a, 116b, and 116c. The specific number of steps 116a, 116b, and 116c can be adjusted according to the actual device requirements, and is not limited to... Figure 1 The examples shown are for illustrative purposes only. In one embodiment, the widths W1, W2, and W3 of each step 116a, 116b, and 116c arranged sequentially from bottom to top decrease successively in the horizontal direction (i.e., the direction parallel to the top surface of the substrate 100), and / or the heights H1, H2, and H3 of each step 116a, 116b, and 116c in the vertical direction (i.e., the direction perpendicular to the top surface of the substrate 100) may be the same for each other or different for each other, but are not limited thereto.
[0077] In this configuration, the first alignment mark 110 and the second alignment mark 116 are positioned non-overlappingly in the semiconductor device 10 of this embodiment, and thus do not interfere with each other. The first alignment mark 110 serves as a zero-layer mark or outer mark of the semiconductor device 10, used to align with other alignment marks (not shown) to be formed in subsequent fabrication processes. The second alignment mark 116 serves as an inner mark of the semiconductor device 10, used to ensure that the subsequently formed interconnect structures are formed in the expected positions. Therefore, the semiconductor device 10 of this embodiment obtains interconnect structures (not shown) with relatively accurate relative positions, thereby optimizing the operational performance of the semiconductor device 10.
[0078] To enable those skilled in the art to easily understand the semiconductor device 10 of the present invention, the manufacturing method of the semiconductor device 10 of the present invention will be further described below.
[0079] Please see Figures 2 to 4 The diagram shown illustrates a method for fabricating a semiconductor device 10 according to a first embodiment of the present invention. Firstly, as... Figure 2As shown, a substrate 100 is provided, on which a dielectric layer 102, a dielectric layer 104, an etch stop layer 106, and a first dielectric layer 108 are sequentially formed. Next, an etching process is performed through a mask layer (not shown) to form a plurality of vias (not shown) in the first dielectric layer 108, wherein each via sequentially penetrates the first dielectric layer 108 and the etch stop layer 106, partially exposing the dielectric layer 104. Then, the mask layer is completely removed, and the vias are filled with a metallic material, such as tungsten, copper, aluminum, titanium, tantalum, or other suitable low-resistivity metallic materials, to form a first alignment mark 110. In one embodiment, the fabrication of the first alignment mark 110 may be integrated into the fabrication process of interconnect structures in other regions, for example, into the fabrication process of interconnect structures also formed within the dielectric layers 102, 104, etch stop layer 106, and the first dielectric layer 108, but is not limited thereto. Then, a metal layer 118 is formed on the first alignment mark 110 and the first dielectric layer 108, integrally covering the substrate 100. The metal layer 118 may include, for example, tungsten, copper, aluminum, titanium, tantalum or other suitable low-resistivity metal materials, but is not limited thereto.
[0080] Please see Figure 3 As shown, a mask layer 120 is formed on the substrate 100, partially covering the metal layer 118 to expose a portion of the top surface 118a of the metal layer 118. A first etching process E1 (e.g., dry etching and / or wet etching) is performed using the mask layer 120 as an etching shield, partially removing the exposed metal layer 118 to obtain a recessed top surface 118b. The recessed top surface 118b is lower than the top surface 118a of the metal layer 118 in the vertical direction. In one embodiment, the first etching process E1 preferably includes an isotropic etching process, but is not limited thereto.
[0081] Please see Figure 4 As shown, a trim-etching process E2 is performed on the metal layer 118. Specifically, the trim-etching process E2 includes step (a), trimming... Figure 3 The mask layer 120 shown forms a mask layer 122 with a reduced overall size (including length, width, and / or height), while exposing the top surface 118a and the recessed top surface 118b of another portion of the metal layer 118. In step (b), a second etching process (e.g., dry etching and / or wet etching) is performed using the mask layer 122 as an etching shield, continuing to remove the exposed metal layer 118 downwards to form a step 124 on the metal layer 118. By repeating steps (a) and (b) in this operation, a step 124 can be formed as shown. Figure 1The second alignment mark 116 shown has multiple steps 116a, 116b, 116c. In one embodiment, the second etching process preferably includes anisotropic etching, but is not limited thereto.
[0082] Subsequently, after forming the stepped structure of the second alignment mark 116, a second dielectric layer 114 is formed to cover the stepped structure and planarize it. Thus, the semiconductor device 10 of this embodiment is completed. Those skilled in the art will readily understand that by adjusting the etching conditions of the aforementioned first etching process E1 and / or trimming-etching process E2, such as etching time and etching selection, the steps of the stepped structure can have various differences to meet the actual device requirements. For example, in one embodiment, by adjusting the etching time of the trimming-etching process E2 in each cycle, the heights H1, H2, and H3 of steps 116a, 116b, and 116c in the vertical direction can all be different. In another embodiment, before the first etching process E1, at least one etching process is performed on the area where the stepped structure is to be set, forming a step height difference in at least a portion of the area, so that the steps on both sides of the stepped structure are of unequal height (not shown), but this is not a limitation.
[0083] Those skilled in the art will readily understand that, while meeting actual product requirements, the semiconductor device and its fabrication method of this invention may have other forms or be achieved by other means, and are not limited to the foregoing. Further embodiments or variations of the semiconductor device of this invention will be described below. For the sake of simplicity, the following description focuses on the differences between the embodiments, without repeating the similarities. Furthermore, identical components in the embodiments of this invention are designated with the same reference numerals to facilitate comparison between embodiments.
[0084] Please see Figure 5 The illustration shows a cross-sectional view of the semiconductor device 20 in the second embodiment of the present invention. The semiconductor device 20 of this embodiment has a substantially the same structure as the semiconductor device 10 of the first embodiment described above, and the similarities will not be repeated here. The difference between the semiconductor device 20 of this embodiment and the semiconductor device 10 of the first embodiment is that a plurality of second alignment marks 126 and a plurality of first alignment marks 110 are arranged alternately in the horizontal direction.
[0085] In detail, in this embodiment, the second alignment mark 126 also physically contacts the top surface 108a of the first dielectric layer 108, and does not overlap the lower first alignment mark 110. Furthermore, the second alignment mark 126 and the first alignment mark 110 are arranged repeatedly within the second dielectric layer 114 in a manner where one second alignment mark 126 is adjacent to one first alignment mark 110, such that each first alignment mark 110 is positioned between any two adjacent second alignment marks 126, as shown below. Figure 5 As shown.
[0086] In this configuration, the first alignment mark 110 has a plurality of first sidewalls 1101 in the horizontal direction. The stepped structure of each second alignment mark has a plurality of second sidewalls 1161 in the horizontal direction, and the plurality of second sidewalls 1161 are disposed in the horizontal direction between two adjacent first sidewalls 1101 among the plurality of first sidewalls 1101.
[0087] In this embodiment, the first alignment mark 110 and the second alignment mark 126 do not interfere with each other, serving as a zero-layer mark / external mark and an internal mark, respectively, to ensure that the subsequently formed interconnect structure is formed in the expected position. Therefore, the semiconductor device 20 in this embodiment also obtains an interconnect structure with precise relative positioning, thereby optimizing the operational performance of the semiconductor device 20.
[0088] Please see Figure 6 The illustration shows a cross-sectional view of the semiconductor device 30 in the third embodiment of the present invention. The semiconductor device 30 of this embodiment has a substantially the same structure as the semiconductor device 10 of the first embodiment described above, and the similarities will not be repeated here. The difference between the semiconductor device 30 of this embodiment and the semiconductor device 10 of the first embodiment is that each of the second alignment marks 136 overlaps with each of the first alignment marks 110 in the vertical direction and physically contacts the top surface 110a of each of the first alignment marks 110 without contacting the top surface 108a of the first dielectric layer 108.
[0089] In detail, each of the second alignment marks 136 and each of the first alignment marks 110 are overlapped in the vertical direction by aligning their centerlines with each other, such that each of the upper second alignment marks 136 only contacts the top surface 110a of the first alignment mark 110, while each of the lower first alignment marks 110 contacts both the second alignment mark 136 and the second dielectric layer 114. That is, the surface area of each first alignment mark 110 in the horizontal direction is larger than the bottom area of the second alignment mark 126 directly above it, such as... Figure 6 As shown.
[0090] In this configuration, since the top surfaces of each of the first alignment marks 110 at their opposite ends are not covered by the second alignment marks 136, the first alignment marks 110 and the second alignment marks 136 in this embodiment will not interfere with each other, serving as the zero-layer mark / outer mark and the inner mark respectively, ensuring that the subsequently formed interconnect structure is formed in the expected position. Therefore, the semiconductor device 30 in this embodiment can also be configured with a precisely positioned interconnect structure, thereby optimizing the operational performance of the semiconductor device 30.
[0091] In this configuration, the first alignment mark 110 has a plurality of first sidewalls 1101 in the horizontal direction. The stepped structure of each second alignment mark has a plurality of second sidewalls 1161 in the horizontal direction, and the plurality of second sidewalls 1161 are also disposed in the horizontal direction between two adjacent first sidewalls of the plurality of first sidewalls 1101.
[0092] Please see Figure 7 The illustration shows a cross-sectional view of the semiconductor device 40 in the fourth embodiment of the present invention. The semiconductor device 40 of this embodiment has a substantially the same structure as the semiconductor device 10 of the first embodiment described above, and the similarities will not be repeated. The difference between the semiconductor device 40 of this embodiment and the semiconductor device 10 of the first embodiment is that, among the plurality of second alignment marks 146 in this embodiment, at least one second alignment mark 146a overlaps with one of the first alignment marks 110 in the vertical direction, and at least another second alignment mark 146b does not overlap with any of the first alignment marks 110 in the vertical direction.
[0093] In detail, each second alignment mark 146a is directly located on each first alignment mark 110 and only contacts the top surface 110a of the first alignment mark 110, and exposes the top surface 110a of the first alignment mark 110 located at the two opposite ends below it; each second alignment mark 146b is arranged alternately with each first alignment mark 110 in the horizontal direction, and is located between two adjacent first alignment marks 110, and physically contacts the top surface 108a of the first dielectric layer 108.
[0094] Under this configuration, the first alignment mark 110 and the second alignment mark 146 in this embodiment will not interfere with each other, serving as a zero-layer mark or external mark, and an internal mark, respectively, to ensure that the subsequently formed interconnect structure is formed in the expected position. Thus, the semiconductor device 40 in this embodiment can also be configured with a precisely positioned interconnect structure, thereby optimizing the operational performance of the semiconductor device 40.
[0095] Please see Figure 8 and Figure 9The illustration shows a cross-sectional view of semiconductor devices 50 and 50a in the fifth embodiment of the present invention. Semiconductor devices 50 and 50a in this embodiment have substantially the same structure as semiconductor device 10 in the first embodiment described above; the similarities will not be repeated here. The difference between semiconductor devices 50 and 50a in this embodiment and semiconductor device 10 in the first embodiment is that the plurality of second alignment marks 156 or the plurality of second alignment marks 158 do not overlap the first alignment mark 110 in the vertical direction, and are disposed between adjacent first alignment marks 110 in the horizontal direction.
[0096] In detail, the second alignment marks 156 and 158 are located on the first dielectric layer 108 and only physically contact its top surface 108a. The plurality of second alignment marks 156 located between two adjacent first alignment marks 110 are, for example, separated from each other, such that a portion of the top surface 108a of the first dielectric layer 108 is exposed between two adjacent second alignment marks 156, as shown below. Figure 8 As shown. On the other hand, the plurality of second alignment marks 158 located between two adjacent first alignment marks 110 are, for example, connected to each other, or can also be regarded as a single second alignment mark 158 that simultaneously includes multiple stepped structures, such as Figure 9 As shown.
[0097] Under this configuration, the first alignment mark 110 and the second alignment marks 156 / 158 in this embodiment will not interfere with each other, serving as the zero-layer mark / external mark and internal mark respectively, ensuring that the subsequently formed interconnect structure is formed in the expected position. Therefore, the semiconductor device 50 / 50a in this embodiment can also be configured with a precisely positioned interconnect structure, thereby optimizing the operational performance of the semiconductor device 50 / 50a.
[0098] Please see Figure 10 The illustration shows a cross-sectional view of the semiconductor device 60 in the sixth embodiment of the present invention. The semiconductor device 60 of this embodiment has a substantially the same structure as the semiconductor device 10 of the first embodiment described above, and the similarities will not be repeated here. The difference between the semiconductor device 60 of this embodiment and the semiconductor device 10 of the first embodiment is that, among the plurality of second alignment marks 166 in this embodiment, at least one second alignment mark 166a overlaps with one of the first alignment marks 110 in the vertical direction, while at least another second alignment mark 166b does not overlap with any of the first alignment marks 110 in the vertical direction.
[0099] Specifically, one or more second alignment marks 166a are located on the same first alignment mark 110 and only contact the top surface 110a of the first alignment mark 110, and at least expose the top surfaces 110a of the first alignment mark 110 located at its two opposite ends. Furthermore, one or more second alignment marks 166b are located between two adjacent first alignment marks 110 and physically contact the top surface 108a of the first dielectric layer 108.
[0100] Under this configuration, the first alignment mark 110 and the second alignment mark 166 in this embodiment will not interfere with each other, serving as a zero-layer mark / outer mark and an internal mark respectively, ensuring that the subsequently formed interconnect structure is formed in the expected position. Therefore, the semiconductor device 60 in this embodiment can also be configured with a precisely positioned interconnect structure, thereby optimizing the operational performance of the semiconductor device 60.
[0101] Overall, the semiconductor device of the present invention includes a plurality of first alignment marks disposed below, and a plurality of second alignment marks having a stepped structure. The first alignment marks and the second alignment marks are respectively disposed within a first dielectric layer and a second dielectric layer stacked sequentially. In the present invention, the bottom surface of the second alignment mark physically contacts the coplanarity of the first alignment mark and the first dielectric layer, such that each second alignment mark physically contacts only a single material, such as the metal material of the first alignment mark or the dielectric material of the first dielectric layer. Thus, the first alignment marks and the second alignment marks do not interfere with each other, ensuring that the interconnect structure within the semiconductor device is positioned as intended.
[0102] Furthermore, the semiconductor device of the present invention can also be applied to semiconductor inspection, whereby the material differences of components within the semiconductor device are detected using an inspection machine (not shown) to determine the position of alignment marks within the semiconductor device. Please refer to [link to relevant documentation]. Figure 11 and Figure 12 As shown, Figures 11 to 12 A schematic diagram illustrating a measurement method for semiconductor devices in a preferred embodiment of the present invention is shown.
[0103] In this embodiment, the measurement method for semiconductor devices includes, but is not limited to, the following steps. First, as... Figure 11 and Figure 12 As shown, a semiconductor structure 70 is provided (step S1). The semiconductor structure 70 further includes a first semiconductor structure 72 and a second semiconductor structure 74, but is not limited thereto. Both the first semiconductor structure 72 and the second semiconductor structure 74 include a substrate 100, a plurality of first alignment marks 110, and a plurality of stepped structures 176, 178. The first semiconductor structure 72 includes, for example, the structure shown in the aforementioned second embodiment (e.g., Figure 5As shown), its details include a substrate 100, a plurality of first alignment marks 110 disposed on the substrate 100, and a plurality of first stepped structures 176 disposed above the first alignment marks 110. The plurality of first stepped structures 176 do not overlap the lower first alignment marks 110, and are respectively disposed between two adjacent first alignment marks 110. The second semiconductor structure 74 includes, for example, the structure shown in the aforementioned third embodiment (e.g. Figure 6 As shown, its details include a substrate 100, a plurality of first alignment marks 110 disposed on the substrate 100, and a plurality of second stepped structures 178 disposed above the first alignment marks 110. The plurality of second stepped structures 178 overlap each of the first alignment marks 110 in the vertical direction and physically contact the top surface 110a of each of the first alignment marks 110.
[0104] Then, the semiconductor structure 70 is inspected (step S2). This is done by measuring the locations within the semiconductor structure 70 with material differences using a testing machine (not shown) and generating corresponding signals. Examples include the location where the first alignment mark 110 (including a metal material) is adjacent to the substrate 100 (including a semiconductor or dielectric material), and / or the location where the first stepped structure 176 / second stepped structure 178 (including a metal material) is adjacent to the substrate 100 (including a semiconductor or dielectric material). Figure 12 As shown, step S2 includes detecting the first semiconductor structure 72 and the second semiconductor structure 74 using the detection equipment. Specifically, for the first semiconductor structure 72, the detection equipment generates a peak value corresponding to each of the two opposite sides of the first alignment marks 110 on the substrate 100, and obtains a first signal A1 from these two peak values. It also generates another peak value corresponding to each of the first stepped structures 176, obtaining a second signal A2. Furthermore, for the second semiconductor structure 74, the detection equipment generates consecutive peak values corresponding to each of the second stepped structures 178 on the substrate 100, obtaining a third signal A3. Therefore, by measuring the first signal A1, the second signal A2, and the third signal A3, the positions of the first alignment mark 110 and / or the first step structure 176 on the substrate 100 in the first semiconductor structure 72 relative to the substrate 100, and the positions of the first alignment mark 110 and / or the second step structure 178 on the substrate 100 in the second semiconductor structure 74 relative to the substrate 100, can be defined. This allows the measurement method of this embodiment to accurately obtain the positions of the first alignment mark 110, the first step structure 176, and the second step structure 178 within the semiconductor structure 70.
[0105] It should be noted that, because in the second semiconductor structure 74, each of the second step structures 178 overlaps with each of the first alignment marks 110 on the substrate 100, the peak intensity of the third signal A3 is significantly different from the peak intensity of the second signal A2, such as... Figure 12 As shown. Therefore, in one embodiment, the aforementioned semiconductor device measurement method may further include a filtering step (not shown), which combines the first signal A1, the second signal A2 and the third signal A3 to obtain a filtered signal (not shown), and uses the filtered signal to exclude the first alignment mark 110 or the second stepped structure 178 with overlapping structures, thereby more precisely defining the position of the first alignment mark 110 with non-overlapping structures on the substrate 100, so as to improve the accuracy of the measurement method.
[0106] The above description is merely a preferred embodiment of the present invention and is not intended to limit the invention. Various modifications and variations can be made to the present invention by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.
Claims
1. A semiconductor device, characterized in that, include: Substrate; A first dielectric layer is disposed on the substrate; Multiple first alignment marks are disposed within the first dielectric layer, wherein each first alignment mark is a metal material layer; wherein each first alignment mark has at least one first sidewall in the horizontal direction. A second dielectric layer is disposed on the first dielectric layer; and Multiple second alignment marks are disposed separately within the second dielectric layer. Each second alignment mark is a metal material layer. Each second alignment mark has a stepped structure and multiple second sidewalls in the horizontal direction. The stepped structure is a convex metal stepped structure. The step width of the convex metal stepped structure decreases from bottom to top, and each convex metal stepped structure includes at least three steps. The multiple second sidewalls of each second alignment mark are disposed between two adjacent first sidewalls.
2. The semiconductor device according to claim 1, characterized in that, The bottom surface of each of the second alignment marks is in physical contact with a single material.
3. The semiconductor device according to claim 2, characterized in that, At least one of the second alignment marks is disposed between two adjacent first alignment marks and in physical contact with the top surface of the first dielectric layer.
4. The semiconductor device according to claim 2, characterized in that, At least one of the second alignment marks is arranged alternately with each of the first alignment marks and does not overlap with each of the first alignment marks in the vertical direction.
5. The semiconductor device according to claim 3, characterized in that, At least one of the second alignment marks overlaps with one of the first alignment marks in the vertical direction and physically contacts the top surface of the first alignment mark.
6. The semiconductor device according to claim 3, characterized in that, The at least one of the second alignment marks includes a plurality of stepped structures connected to each other.
7. The semiconductor device according to claim 2, characterized in that, At least one of the second alignment marks overlaps with one of the first alignment marks in the vertical direction and physically contacts the top surface of the first alignment mark.
8. The semiconductor device according to claim 2, characterized in that, A plurality of first alignment marks are disposed between two adjacent second alignment marks, and the top surfaces of the plurality of first alignment marks are made of the same material.
9. A method for fabricating a semiconductor device, characterized in that, include: Provide substrate; A first dielectric layer is formed on the substrate; A plurality of first alignment marks are formed within the first dielectric layer, wherein each first alignment mark is a metal material layer; wherein each first alignment mark has at least one first sidewall in the horizontal direction. A plurality of second alignment marks are formed on the first dielectric layer, the plurality of second alignment marks being formed on the first alignment marks in a spaced manner. Each second alignment mark is a metal material layer, and each second alignment mark has a stepped structure and a plurality of second sidewalls in the horizontal direction. The stepped structure is a convex metal stepped structure, the step width of which decreases progressively from bottom to top, and each convex metal stepped structure includes at least three steps. The plurality of second sidewalls of each second alignment mark are disposed between two adjacent first sidewalls. A second dielectric layer is formed to cover the second alignment mark.
10. The method for fabricating a semiconductor device according to claim 9, characterized in that, Forming the second alignment mark further includes: A metal layer is formed on the first dielectric layer; A mask layer is formed on the metal layer to expose a portion of the top surface of the metal layer; and A first etching process is performed on the metal layer through the mask layer to partially remove the metal layer; and After the first etching process, the metal layer is trimmed and etched to form the stepped structure of the second alignment mark.
11. The method for fabricating a semiconductor device according to claim 10, characterized in that, The trimming-etching process also includes: Step (a): Trim the mask layer to expose another portion of the top surface of the metal layer; Step (b) involves performing a second etching process through the mask layer after step (a) to form a step on the metal layer; and Steps (a) and (b) are repeated cyclically to form a plurality of steps of the second alignment mark.
12. The method for fabricating a semiconductor device according to claim 11, characterized in that, The width of each step decreases from bottom to top in the horizontal direction, and each step has a different height.
13. The method for fabricating a semiconductor device according to claim 9, characterized in that, At least one of the second alignment marks is positioned between two adjacent first alignment marks.
14. The method for fabricating a semiconductor device according to claim 9, characterized in that, At least one of the second alignment marks overlaps with one of the first alignment marks in the vertical direction.
15. A method for measuring a semiconductor device, characterized in that, include: A semiconductor structure is provided, the semiconductor structure comprising: Substrate; A plurality of first alignment marks are disposed on the substrate, the first alignment marks being a layer of metallic material; wherein each of the first alignment marks has at least one first sidewall in the horizontal direction; and Multiple stepped structures are disposed on the first alignment mark. The stepped structures are convex metal stepped structures, and the step width of the convex metal stepped structures decreases from bottom to top. Each convex metal stepped structure includes at least three steps. The multiple second sidewalls of each of the multiple stepped structures are disposed between two adjacent first sidewalls. The semiconductor structure is inspected using a testing machine to obtain the positions of the first alignment mark and the stepped structure on the substrate.
16. The method for measuring semiconductor devices according to claim 15, characterized in that, The semiconductor structure also includes: A first semiconductor structure, the first semiconductor structure comprising: First substrate; A plurality of first alignment marks disposed on the first substrate; and Multiple first stepped structures are disposed on the first alignment marks on the first substrate, and each first stepped structure is respectively disposed between two first alignment marks on the first substrate; and A second semiconductor structure, the second semiconductor structure comprising: Second substrate; A plurality of first alignment marks disposed on the second substrate; and A plurality of second step structures are disposed on the first alignment mark on the second substrate, and at least a portion of the second step structures overlap one of the first alignment marks on the second substrate in the vertical direction.
17. The method for measuring semiconductor devices according to claim 16, characterized in that, Also includes: The detection equipment detects the material differences between the first alignment mark, the first stepped structure and the first substrate on the first substrate, and generates different first and second signals respectively. as well as The third signal is generated by detecting the material differences between the first alignment mark, the second stepped structure and the second substrate on the second substrate using the detection machine.
18. The method for measuring semiconductor devices according to claim 15, characterized in that, Each of the first alignment marks has at least one first sidewall in the horizontal direction; Each of the stepped structures has a plurality of second sidewalls in the horizontal direction, and the plurality of second sidewalls of each stepped structure are disposed between two adjacent first sidewalls.
19. The method for measuring semiconductor devices according to claim 17, characterized in that, Also includes: The first signal, the second signal, and the third signal are combined to obtain the filtered signal.
20. The method for measuring semiconductor devices according to claim 19, characterized in that, Also includes: The position of the first alignment mark on the first substrate is defined by the filtered signal.