Methods for fabricating memory elements

Abstract

This application provides a method for fabricating a memory element. The method includes the steps of: providing a semiconductor substrate, including an active region disposed on or therein; forming an oxide film on the semiconductor substrate; forming a nitride film on the oxide film; forming a trench extending through the oxide film and the nitride film; forming a first hollow spacer on the nitride film; forming a second hollow spacer around the first hollow spacer; forming a third hollow spacer surrounded by the first hollow spacer; and removing portions of the oxide film and the nitride film exposed through the second hollow spacer and the third hollow spacer.

Description

Technical Field

[0001] This application claims priority to U.S. Patent Applications Nos. 17 / 685,520 and 17 / 686,106 (i.e., priority date “March 3, 2022”), the contents of which are incorporated herein by reference in their entirety.

[0002] This disclosure relates to a memory element and a method for fabricating the same. In particular, it relates to a memory element having strip-shaped active regions (AA) and a method for fabricating the memory element. Background Technology

[0003] Non-volatile memory elements retain data even when power is cut off. One type of non-volatile memory element is an one-time programmable design (OTP) memory element. With an OTP memory element, the user can only program the OTP memory element once, and the data stored in the OTP memory element cannot be modified. Signals are transmitted to metal interconnects disposed on a semi-conductive substrate.

[0004] However, this type of metal interconnect wiring poses an obstacle to increasing the wiring density of memory elements. Such wiring can result in a narrower process window and may lead to misalignment or leakage between memory cells within the memory element, thus limiting the reduction of the minimum feature size. Therefore, improvements are desired to address these manufacturing challenges.

[0005] The above description of "prior art" is merely to provide background information and does not acknowledge that the above description of "prior art" discloses the subject matter of this disclosure. It does not constitute prior art to this disclosure, and no description of the above "prior art" should be considered part of this case. Summary of the Invention

[0006] One aspect of this disclosure provides a method for fabricating a memory element. The method includes the steps of: providing a semiconductor substrate, including an active region disposed on or therein, a first dielectric layer on the semiconductor substrate, a second dielectric layer on the first dielectric layer, and a patterned photoresist layer on the second dielectric layer; removing a first portion of the semiconductor substrate, the first dielectric layer, and the second dielectric layer exposed through the patterned photoresist layer to form a trench; removing the patterned photoresist layer; disposing an isolation member within the trench; disposing a sacrificial pillar on the second dielectric layer; disposing a first spacer around the sacrificial pillar; removing the sacrificial pillar; disposing a second spacer around the first spacer; and removing a second portion of the first dielectric layer and the second dielectric layer exposed through the second spacer.

[0007] In some embodiments, the preparation method further includes removing the first spacer and the second spacer after removing the second portion of the first dielectric layer and the second dielectric layer exposed through the second spacer.

[0008] In some embodiments, the sacrificial post is removed after the first spacer is set and before the second spacer is set.

[0009] In some embodiments, the fabrication method further includes removing a third portion of the semiconductor substrate exposed through the second spacer, the first dielectric layer, and the second dielectric layer.

[0010] In some embodiments, the sacrificial column comprises a nitride.

[0011] In some embodiments, one cross-section of the sacrificial column is circular.

[0012] In some embodiments, the first spacer and the second spacer comprise the same dielectric material.

[0013] In some embodiments, removing the second portion of the first dielectric layer and the second dielectric layer exposed through the second spacer includes removing a fourth portion of the first dielectric layer and the second dielectric layer appearing within the second spacer from a top view, and removing a fifth portion of the first dielectric layer and the second dielectric layer appearing outside the second spacer from the top view.

[0014] In some embodiments, the removal of the first dielectric layer and the fourth portion of the second dielectric layer appearing within the second spacer from the top view is performed before or after the removal of the fifth portion of the first dielectric layer and the second dielectric layer appearing outside the second spacer from the top view.

[0015] In some embodiments, the removal of the fourth portion of the first dielectric layer and the second dielectric layer appearing within the second spacer from the top view is performed simultaneously with the removal of the fifth portion of the first dielectric layer and the second dielectric layer outside the second spacer from the top view.

[0016] In some embodiments, the arrangement of the second spacer includes forming an opening surrounded by the first spacer and the second spacer.

[0017] In some embodiments, the first dielectric layer and the second portion of the second dielectric layer exposed through the second gap are at least partially disposed within the opening from the top view.

[0018] In some embodiments, the second spacer includes a first annular component that contacts an outer surface of the first spacer, and a second annular component that contacts an inner surface of the first spacer.

[0019] In some embodiments, the first dielectric layer comprises an oxide.

[0020] In some embodiments, the second dielectric layer comprises a nitride.

[0021] In some embodiments, the insulating component comprises an oxide.

[0022] Another aspect of this disclosure provides a method for fabricating a memory element. The method includes the steps of: providing a semiconductor substrate, including an active region disposed on or therein; forming an oxide film on the semiconductor substrate; forming a nitride film on the oxide film; forming a trench extending through the oxide film and the nitride film; forming a first hollow spacer on the nitride film; forming a second hollow spacer around the first hollow spacer; forming a third hollow spacer surrounded by the first hollow spacer; and removing portions of the oxide film and the nitride film exposed through the second and third hollow spacers.

[0023] In some embodiments, the second hollow spacer surrounds the first hollow spacer and the third hollow spacer.

[0024] In some embodiments, the technique for fabricating the oxide film includes oxidizing the semiconductor substrate.

[0025] In some embodiments, the fabrication technique for the nitride film includes chemical vapor deposition (CVD).

[0026] In some embodiments, the ditch is filled with an insulating material.

[0027] In some embodiments, the preparation method further includes depositing a photoresist material on the nitride film and patterning the photoresist material to form a patterned photoresist layer.

[0028] In some embodiments, forming the trench includes removing the oxide film and the nitride film exposed through the patterned photoresist layer.

[0029] In some embodiments, the preparation method further includes forming a sacrificial column on the nitride film before forming the first hollow spacer.

[0030] In some embodiments, the first hollow spacer surrounds the sacrificial column.

[0031] In some embodiments, the preparation method further includes removing the sacrificial column after forming the first hollow spacer.

[0032] In some embodiments, the formation of the second hollow space element and the formation of the third hollow space element are performed separately or simultaneously.

[0033] In some embodiments, the second hollow space element and the third hollow space element comprise the same dielectric material.

[0034] In some embodiments, the preparation method further includes removing a portion of the semiconductor substrate exposed through the nitride film to form a hole, and filling the hole with an isolation member.

[0035] Another aspect of this disclosure provides a memory element. The memory element includes a semiconductor substrate having an active region defined on or therein, and including a recess surrounding the active region; a first dielectric layer disposed on the active region of the semiconductor substrate; a second dielectric layer disposed on the first dielectric layer; and an isolation member disposed within the recess and completely surrounding the active region.

[0036] In some embodiments, a top surface of the second dielectric layer is substantially coplanar with a top surface of the isolation member.

[0037] In some embodiments, a top surface of the first dielectric layer is substantially lower than a top surface of the isolation member.

[0038] In some embodiments, the first dielectric layer and the insulating component comprise the same material.

[0039] In some embodiments, the semiconductor substrate includes silicon.

[0040] In some embodiments, the first dielectric layer and the isolation component are integral.

[0041] In summary, since the active region of the semiconductor substrate is defined by setting a plurality of annular spacers on the semiconductor substrate and removing a predetermined portion of the semiconductor substrate exposed through the annular spacers, the size of the active region can be kept to a minimum or not reduced during the removal process. Therefore, the subsequent process window on the active region will not be further reduced. Consequently, misalignment or leakage between memory cells in the memory element can be prevented or minimized, and the overall performance of the memory element can be improved.

[0042] The foregoing has provided a fairly broad overview of the technical features and advantages of this disclosure, enabling a better understanding of the detailed description that follows. Other technical features and advantages constituting the subject matter of the claims will be described below. Those skilled in the art to which this disclosure pertains will understand that the concepts and specific embodiments disclosed below can be readily utilized to achieve the same purpose as this disclosure by modifying or designing other structures or processes. Those skilled in the art will also understand that such equivalent constructions cannot depart from the spirit and scope of this disclosure as defined by the appended claims. Attached Figure Description

[0043] When referring to the drawings in conjunction with the embodiments and claims, a more comprehensive understanding of the disclosure of this application can be obtained. The same element symbols in the drawings refer to the same elements.

[0044] Figure 1 This is a cross-sectional side view illustrating memory elements of some embodiments of this disclosure.

[0045] Figure 2 This is a top view of the cross-section, for example. Figure 1 The memory element in.

[0046] Figure 3 This is a flowchart illustrating methods for fabricating memory elements according to some embodiments of this disclosure.

[0047] Figures 4 to 27 This is a cross-sectional view illustrating an intermediate stage in the fabrication of a memory element according to some embodiments of this disclosure.

[0048] The reference numerals in the attached figures are explained as follows:

[0049] 100: Memory element

[0050] 101: Semiconductor substrate

[0051] 101a: Array region

[0052] 101b: Active Zone

[0053] 101c: Groove

[0054] 102: First dielectric layer

[0055] 102a: Top surface

[0056] 103: Second dielectric layer

[0057] 103a: Top surface

[0058] 104: Isolation Components

[0059] 104a: Top surface

[0060] 105: Patterned photoresist layer

[0061] 105a: Photoresist material

[0062] 106: Ditch

[0063] 107: Insulation materials

[0064] 108: Sacrifice Pillar

[0065] 109: First Gap

[0066] 109a: Outer surface

[0067] 109b: Inner surface

[0068] 110: Second gap

[0069] 110a: First annular component

[0070] 110b: Second annular component

[0071] 111: Opening

[0072] 112: Kong

[0073] AA: Line

[0074] BB: Line

[0075] CC: Line

[0076] DD: Line

[0077] EE: Line

[0078] FF: Line

[0079] GG: Line

[0080] HH: Line

[0081] S200: Preparation Method

[0082] S201: Steps

[0083] S202: Steps

[0084] S203: Steps

[0085] S204: Steps

[0086] S205: Steps

[0087] S206: Steps

[0088] S207: Steps

[0089] S208: Steps

[0090] S209: Steps Detailed Implementation

[0091] The following disclosure provides numerous different embodiments, or examples, for implementing different features of the provided subject matter. To simplify this disclosure, specific examples of elements and arrangements are described below. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, the formation of a first feature on a second feature may include embodiments where the first and second features are in direct contact, or embodiments where an additional feature is formed between the first and second features, so that the first and second features may not be in direct contact.

[0092] Furthermore, reference numerals and / or letters may be repeated in various embodiments of this disclosure. Such repetition is for simplicity and clarity and does not in itself determine the relationship between the various embodiments and / or settings discussed.

[0093] Furthermore, spatial relative terms, such as "below," "below," "under," "above," and "above," are used here for ease of description to describe the relationship between one element or feature and another element(s) shown in the figure. Spatially relative terms are intended to include different orientations of the element in use or operation, as well as the orientations described in the figure. The element may have other orientations (rotated 90 degrees or other orientations), and the spatial relative descriptors used here can be interpreted accordingly.

[0094] Figure 1 This is a cross-sectional side view illustrating a memory element 100 according to some embodiments of the present disclosure. Figure 2 This is an example Figure 1 A top cross-sectional view of the memory element 100. Figure 1 It is along Figure 2 A side view of the cross-section of line AA in the diagram. In some embodiments, such as... Figure 1 The memory element 100 shown may be part of an element. In some embodiments, the memory element 100 includes a plurality of unit cells arranged along columns and rows.

[0095] In some embodiments, the memory element 100 includes a semiconductor substrate 101. In some embodiments, the semiconductor substrate 101 is inherently semiconducting. In some embodiments, the semiconductor substrate 101 is a semiconductor wafer (e.g., a silicon wafer) or a semiconductor on insulator (SOI) wafer (e.g., a silicon wafer on insulator). In some embodiments, the semiconductor substrate 101 is a silicon substrate.

[0096] In some embodiments, a semiconductor substrate 101 is defined to have a peripheral region (not shown) and an array region 101a. In some embodiments, the array region 101a is at least partially surrounded by the peripheral region. In some embodiments, the peripheral region is adjacent to the periphery of the semiconductor substrate 101, while the array region 101a is adjacent to the central region of the semiconductor substrate 101. In some embodiments, the array region 101a can be used to fabricate electronic components, such as capacitors, transistors, or similar components. In some embodiments, a boundary is disposed between the peripheral region and the array region 101a.

[0097] In some embodiments, the semiconductor substrate 101 includes a recess 101c extending into the semiconductor substrate and surrounding the active region 101b. In some embodiments, the semiconductor substrate 101 includes an active region 101b disposed on or within the semiconductor substrate 101. In some embodiments, the active region 101b is a doped region in the semiconductor substrate 101. In some embodiments, the active region 101b extends horizontally on or below the top surface of the semiconductor substrate 101. In some embodiments, the dimensions of the top cross-section of each active region 101b may be the same or different from each other.

[0098] In some embodiments, each active region 101b includes the same type of dopant. In some embodiments, each active region 101b includes a dopant type different from that included in the other active regions 101b. In some embodiments, each active region 101b has the same conductivity type. In some embodiments, the active region 101b includes N-type dopant.

[0099] In some embodiments, a first dielectric layer 102 is disposed on a semiconductor substrate 101. In some embodiments, the first dielectric layer 102 is disposed on an active region 101b of the semiconductor substrate 101. In some embodiments, the first dielectric layer 102 comprises a dielectric material, such as an oxide, silicon dioxide (SiO2), or a similar material. In some embodiments, the first dielectric layer 102 is an oxide film. In some embodiments, the first dielectric layer 102 may be part of a gate dielectric or a gate dielectric subsequently formed on the active region 101b of the semiconductor substrate 101.

[0100] In some embodiments, a second dielectric layer 103 is disposed on the first dielectric layer 102 and the semiconductor substrate 101. In some embodiments, the second dielectric layer 103 is disposed on the active region 101b of the semiconductor substrate 101. In some embodiments, the second dielectric layer 103 comprises a nitride, silicon nitride, or a similar material. In some embodiments, the second dielectric layer 103 is a nitride film. In some embodiments, the second dielectric layer 103 can serve as a masking layer to protect the semiconductor substrate 101. In some embodiments, such as Figure 2As shown, the active region 101b covered by the first dielectric layer 102 and the second dielectric layer 103 is strip-shaped, elongated, rectangular or polygonal.

[0101] In some embodiments, the memory element 100 includes an isolation member 104 surrounding an active region 101b of a semiconductor substrate 101. In some embodiments, the active regions 101b are surrounded by the isolation member 104, thus separating and electrically isolating the active regions 101b from each other by means of the isolation member 104. In some embodiments, the active regions 101b are arranged in a row or column direction. In some embodiments, the active regions 101b are completely surrounded by the isolation member 104.

[0102] In some embodiments, the isolation member 104 surrounds the first dielectric layer 102 and the second dielectric layer 103 disposed on the active region 101b of the semiconductor substrate 101. In some embodiments, the isolation member 104 is at least partially disposed within a recess 101c of the semiconductor substrate 101. In some embodiments, the isolation member 104 completely surrounds the active region 101b of the semiconductor substrate 101.

[0103] In some embodiments, the top surface 103a of the second dielectric layer 103 is substantially coplanar with the top surface 104a of the isolation member 104. In some embodiments, the top surface 102a of the first dielectric layer 102 is substantially lower than the top surface 104a of the isolation member 104. In some embodiments, the depth of the isolation member 104 is substantially greater than or equal to the depth of the active region 101b. In some embodiments, the isolation member 104 is a shallow trench isolation (STI) or a part of an STI. In some embodiments, the isolation member 104 defines the boundary of the active region 101b.

[0104] In some embodiments, the fabrication technique of the isolation component 104 includes insulating materials such as silicon oxide, silicon nitride, silicon oxynitride, or combinations thereof. In some embodiments, the first dielectric layer 102 and the isolation component 104 comprise the same material. In some embodiments, the first dielectric layer 102 and the isolation component 104 are integral.

[0105] Figure 3 This is a flowchart illustrating a method S200 for fabricating a memory element 100 according to some embodiments of this disclosure. Figures 4 to 27 This is a cross-sectional view illustrating an intermediate stage in the fabrication of a memory element 100 according to some embodiments of this disclosure.

[0106] Figures 4 to 27 The stages shown are in Figure 3 The flowchart also illustrates this. In the following discussion, Figures 4 to 27 The preparation stages shown are based on Figure 3The process steps shown will be discussed. Preparation method S200 includes several operations, and the description and explanation should not be regarded as a limitation on the order of operations. Method S200 includes several steps (S201, S202, S203, S204, S205, S206, S207, S208 and S209).

[0107] Reference Figures 4 to 8 ,according to Figure 3 In step S201, a semiconductor substrate 101 is provided, a first dielectric layer 102 on the semiconductor substrate, a second dielectric layer 103 on the first dielectric layer, and a patterned photoresist layer 105 on the second dielectric layer.

[0108] In such Figure 4 In some of the embodiments shown, a semiconductor substrate 101 is provided, including an active region 101b disposed thereon or therein. In some embodiments, the semiconductor substrate 101 includes a semiconducting material. In some embodiments, the semiconductor substrate 101 is a silicon substrate. In some embodiments, the semiconductor substrate 101 is defined to have a peripheral region (not shown) and an array region 101a at least partially surrounded by the peripheral region. In some embodiments, the array region 101a is adjacent to a central region of the semiconductor substrate 101.

[0109] In some embodiments, the active region 101b is a doped region in the semiconductor substrate 101. In some embodiments, the active region 101b extends horizontally on or below the top surface of the semiconductor substrate 101. In some embodiments, each active region 101b includes the same type of dopant. In some embodiments, each active region 101b includes a dopant type different from that included in the other active regions 101b. In some embodiments, each active region 101b has the same conductivity type. In some embodiments, the fabrication technique of the active region 101b includes an ion implantation process or an ion doping process.

[0110] In such Figure 5 In some embodiments shown, a first dielectric layer 102 is formed on a semiconductor substrate 101. In some embodiments, the first dielectric layer 102 is formed on an active region 101b of the semiconductor substrate 101. In some embodiments, the fabrication technique of the first dielectric layer 102 includes oxidizing the semiconductor substrate 101 or a portion of the semiconductor substrate 101, deposition, or any other suitable process. In some embodiments, the first dielectric layer 102 comprises a dielectric material, such as an oxide, silicon dioxide (SiO2), or a similar material. In some embodiments, the first dielectric layer 102 is an oxide film.

[0111] In some embodiments, such as Figure 6As shown, a second dielectric layer 103 is formed on the first dielectric layer 102. In some embodiments, the second dielectric layer 103 is disposed on the active region 101b of the semiconductor substrate 101. In some embodiments, the second dielectric layer 103 comprises a nitride, silicon nitride, or the like. In some embodiments, the second dielectric layer 103 is a nitride film. In some embodiments, the fabrication techniques for the second dielectric layer 103 include chemical vapor deposition (CVD), spin coating, or any other suitable process.

[0112] In such Figure 7 and Figure 8 In some embodiments shown, a patterned photoresist layer 105 is formed on a second dielectric layer 103. In some embodiments, the fabrication technique of the patterned photoresist layer 105 includes depositing a photoresist material 105a on the second dielectric layer 103, such as... Figure 7 As shown, and as Figure 8 The patterning of photoresist material 105a is shown. The patterning technique for photoresist material 105a includes etching or any other suitable process to remove portions of the photoresist material 105a. For example... Figure 8 As shown, the second dielectric layer 103 is exposed at least partially through the patterned photoresist layer 105.

[0113] Reference Figure 9 and Figure 10 ,according to Figure 3 In step S202, the semiconductor substrate 101, the first dielectric layer 102, and the first portion of the second dielectric layer 103 exposed by the patterned photoresist layer 105 are removed to form a trench 106. Figure 10 yes Figure 9 Top view. Figure 9 It is along Figure 10 A cross-sectional side view of line BB in the diagram. Trench 106 extends through the first dielectric layer 102 and the second dielectric layer 103. In some embodiments, the removal technique for the first portion of the semiconductor substrate 101, the first dielectric layer 102, and the second dielectric layer 103 exposed by the patterned photoresist layer 105 includes etching or any other suitable process. In some embodiments, in such... Figure 9 After the ditch 106 shown is formed, it forms as follows: Figure 10 The striped pattern shown in the top view.

[0114] Reference Figure 11 and Figure 12 ,according to Figure 3 In step S203, the patterned photoresist layer 105 is removed. Figure 12 yes Figure 11 Top view. Figure 11 It is along Figure 12A cross-sectional side view of line CC in the diagram. In some embodiments, the removal technique for the patterned photoresist layer 105 includes etching, stripping, or any other suitable process. Figure 12 As shown, after removing the patterned photoresist layer 105, the second dielectric layer 103 is exposed.

[0115] Reference Figures 13 to 15 ,according to Figure 3 In step S204, the isolation component 104 is installed in the ditch 106. Figure 15 yes Figure 14 Top view. Figure 14 It is along Figure 15 A cross-sectional side view of line DD in the diagram. In some embodiments, the fabrication technique of the isolation member 104 includes disposing an isolation material 107 on the semiconductor substrate 101 and the second dielectric layer 103, such as... Figure 13 As shown, then a portion of the insulating material 107 is removed to form the insulating component 104, as... Figure 14 As shown. In some embodiments, trench 106 is filled with insulating material 107. In some embodiments, the technique for removing a portion of the insulating material 107 includes planarization, etching, or any other suitable process. In some embodiments, insulating member 104 surrounds a first dielectric layer 102 and a second dielectric layer 103 disposed on an active region 101b of a semiconductor substrate 101. In some embodiments, insulating member 104 comprises oxide.

[0116] Reference Figure 16 and Figure 17 ,according to Figure 3 In step S205, a sacrificial pillar 108 is provided on the second dielectric layer 103. Figure 17 yes Figure 16 Top view. Figure 16 It is along Figure 17 The image shows a cross-sectional side view of line EE. The sacrificial pillar 108 is fabricated using deposition or any other suitable process. In some embodiments, the sacrificial pillar 108 is in contact with the insulating member 104 and the second dielectric layer 103. In some embodiments, the sacrificial pillar 108 comprises a nitride. In some embodiments, the sacrificial pillar 108 has a circular cross-section.

[0117] Reference Figure 18 and Figure 19 ,according to Figure 3 In step S206, a first gap 109 is set around the sacrificial column 108. Figure 19 yes Figure 18 Top view. Figure 18 It is along Figure 19A cross-sectional side view of line FF in the diagram. A first spacer 109 is formed on the isolation member 104 and the second dielectric layer 103. In some embodiments, the sacrificial pillar 108 is surrounded by the first spacer 109. In some embodiments, the first spacer 109 contacts the entire outer surface of the sacrificial pillar 108. In some embodiments, the first spacer 109 is hollow. In some embodiments, the sacrificial pillar 108 is formed on the second dielectric layer 103 before the first spacer 109 is formed. In some embodiments, the first spacer 109 comprises a dielectric material, such as an oxide, nitride, oxynitride, or similar material.

[0118] Reference Figure 20 and Figure 21 ,according to Figure 3 In step S207, remove the sacrificial column 108. Figure 21 yes Figure 20 Top view. Figure 20 It is along Figure 21 A cross-sectional side view of line GG in the diagram. In some embodiments, the removal technique for the sacrificial post 108 includes etching or any other suitable process. In some embodiments, the sacrificial post 108 is removed after the first spacer 109 is formed.

[0119] Reference Figure 22 and Figure 23 ,according to Figure 3 In step S208, a second spacer 110 is set around the first spacer 109. Figure 23 yes Figure 22 Top view. Figure 22 It is along Figure 23 A cross-sectional side view of line HH in the diagram. In some embodiments, the fabrication technique of the second spacer 110 includes deposition or any other suitable process. In some embodiments, the sacrificial pillar 108 is removed before the second spacer 110 is installed. In some embodiments, the first spacer 109 and the second spacer 110 comprise the same dielectric material. In some embodiments, the first spacer 109 and the second spacer 110 comprise a dielectric material such as an oxide, nitride, oxynitride, or similar material.

[0120] In some embodiments, the second spacer 110 is configured by forming a first annular member 110a that contacts the outer surface 109a of the first spacer 109 and a second annular member 110b that contacts the inner surface 109b of the first spacer 109. In some embodiments, the first annular member 110a is a second hollow spacer, and the second annular member 110b is a third hollow spacer. In some embodiments, the first annular member 110a surrounds the first spacer 109, and the second annular member 110b is surrounded by the first spacer 109. The first annular member 110a surrounds the first spacer 109 and the second annular member 110b. In some embodiments, the formation of the first annular member 110a and the formation of the second annular member 110b are performed separately or simultaneously.

[0121] In some embodiments, the provisioning of the second spacer 110 includes forming an opening 111 surrounded by the first spacer 109 and the second spacer 110. After the second spacer 110 is provided, at least a portion of the second dielectric layer 103 is exposed through the second spacer 110, and as... Figure 23 As shown in the top view, it is set within opening 111.

[0122] Reference Figure 24 and Figure 25 ,according to Figure 3 In step S209, the second portion of the first dielectric layer 102 and the second dielectric layer 103 exposed through the second spacer 110 is removed. Figure 24 This is a top view, illustrating the removal of portions of the first dielectric layer 102 and the second dielectric layer 103 exposed through the second spacer 110 and surrounded by the second annular member 110b from the top view. Figure 25 This is a top view, illustrating the removal of portions of the first dielectric layer 102 and the second dielectric layer 103 exposed through the second spacer 110 and outside the first annular member 110a from the top view.

[0123] In some embodiments, removing the second portion of the first dielectric layer 102 and the second dielectric layer 103 exposed through the second spacer 110 includes, as follows: Figure 24 The portion of the first dielectric layer 102 and the second dielectric layer 103 removed from the second spacer 110 as shown in the top view, and as... Figure 25 The portion of the first dielectric layer 102 and the second dielectric layer 103 outside the second spacer 110 is shown removed from the top view.

[0124] In some embodiments, such as Figure 24 The portion shown in the top view where the first dielectric layer 102 and the second dielectric layer 103 are removed from the second spacer 110 is as follows: Figure 25This is performed before or after removing portions of the first dielectric layer 102 and the second dielectric layer 103 outside the second spacer, as shown in the top view. In some embodiments, such as Figure 24 The portion of the first dielectric layer 102 and the second dielectric layer 103 removed from the second spacer 110 as shown in the top view is as follows: Figure 25 The removal of portions of the first dielectric layer 102 and the second dielectric layer 103 outside the second spacer, as shown in the top view, is performed simultaneously.

[0125] In some embodiments, such as Figure 25 Before or after removing portions of the first dielectric layer 102 and the second dielectric layer 103 outside the second spacer in the top view shown, the following procedure is performed: Figure 24 After removing portions of the first dielectric layer 102 and the second dielectric layer 103 within the second spacer 110 as shown in the top view, at least a portion of the semiconductor substrate 101 appears as... Figure 25 The image shows exposure through the second dielectric layer 103.

[0126] In some embodiments, after removing the second portion of the first dielectric layer 102 and the second dielectric layer 103 exposed through the second spacer 110, as Figure 26 and Figure 27 As shown, the first spacer 109 and the second spacer 110 are removed. Figure 27 yes Figure 26 A top view. In some embodiments, the removal techniques for the first spacer 109 and the second spacer 110 include etching, stripping, or any other suitable process. In some embodiments, the removal of the first spacer 109 and the removal of the second spacer 110 are performed separately or simultaneously. In some embodiments, the removal of the first spacer 109 is performed before or after the removal of the second spacer 110.

[0127] In some embodiments, such as Figure 25 As shown, the portion of the semiconductor substrate 101 exposed through the second dielectric layer 103 is removed, and then the isolation member 104 is also disposed in the hole 112, as... Figure 27 As shown. In some embodiments, the isolation member 104 fills the hole 112. In some embodiments, the removal of a portion of the semiconductor substrate 101 exposed through the second dielectric layer 103 is performed before or after the removal of the first spacer 109 and the removal of the second spacer 110. In some embodiments, as Figure 1 and Figure 2 The memory element 100 shown is formed in Figure 26 and Figure 27 middle.

[0128] In some embodiments, the second dielectric layer 103 is removed after the via 112 is filled by the isolation member 104. In some embodiments, after the removal of the second dielectric layer 103, the isolation member 104 and the first dielectric layer 102 are planarized. In some embodiments, after planarization, dopant implantation is performed on the active region 101b.

[0129] One aspect of this disclosure provides a method for fabricating a memory element. The method includes the steps of: providing a semiconductor substrate, including an active region disposed on or therein, a first dielectric layer on the semiconductor substrate, a second dielectric layer on the first dielectric layer, and a patterned photoresist layer on the second dielectric layer; removing a first portion of the semiconductor substrate, the first dielectric layer, and the second dielectric layer exposed through the patterned photoresist layer to form a trench; removing the patterned photoresist layer; disposing an isolation member within the trench; disposing a sacrificial pillar on the second dielectric layer; disposing a first spacer around the sacrificial pillar; removing the sacrificial pillar; disposing a second spacer around the first spacer; and removing a second portion of the first dielectric layer and the second dielectric layer exposed through the second spacer.

[0130] Another aspect of this disclosure provides a method for fabricating a memory element. The method includes the steps of: providing a semiconductor substrate, including an active region disposed on or therein; forming an oxide film on the semiconductor substrate; forming a nitride film on the oxide film; forming a trench extending through the oxide film and the nitride film; forming a first hollow spacer on the nitride film; forming a second hollow spacer around the first hollow spacer; forming a third hollow spacer surrounded by the first hollow spacer; and removing portions of the oxide film and the nitride film exposed through the second and third hollow spacers.

[0131] Another aspect of this disclosure provides a memory element. The memory element includes a semiconductor substrate having an active region defined on or therein, and including a recess surrounding the active region; a first dielectric layer disposed on the active region of the semiconductor substrate; a second dielectric layer disposed on the first dielectric layer; and an isolation member disposed within the recess and completely surrounding the active region.

[0132] In summary, since the active region of the semiconductor substrate is defined by setting a plurality of annular spacers on the semiconductor substrate and removing a predetermined portion of the semiconductor substrate exposed through the annular spacers, the size of the active region can be kept to a minimum or not reduced during the removal process. Therefore, the subsequent process window on the active region will not be further reduced. Consequently, misalignment or leakage between memory cells in the memory element can be prevented or minimized, and the overall performance of the memory element can be improved.

[0133] While this disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions, and alternatives may be made without departing from the spirit and scope of this disclosure as defined in the claims. For example, many of the processes described above may be implemented using different methods, and other processes or combinations thereof may be substituted for many of the processes described above.

[0134] Furthermore, the scope of this application is not limited to the specific embodiments of the processes, machinery, manufacturing, material composition, means, methods, and steps described in the specification. Those skilled in the art will understand from the disclosure of this publication that existing or future processes, machinery, manufacturing, material composition, means, methods, or steps that have the same function or achieve substantially the same results as the corresponding embodiments described herein can be used based on this disclosure. Therefore, such processes, machinery, manufacturing, material composition, means, methods, or steps are included within the scope of the claims of this application.

Claims

1. A method for fabricating a memory element, comprising: A semiconductor substrate is provided, including an active region disposed on or therein, a first dielectric layer on the semiconductor substrate, a second dielectric layer on the first dielectric layer, and a patterned photoresist layer on the second dielectric layer. A first portion of the semiconductor substrate, the first dielectric layer, and the second dielectric layer exposed through the patterned photoresist layer is removed to form a trench. Remove the patterned photoresist layer; An isolation component is installed inside the ditch; A sacrificial pillar is placed on the second dielectric layer; A first gap is set around the sacrificial pillar; Remove the sacrificial column; A second spacer is provided around the first spacer; as well as Remove the first dielectric layer and a second portion of the second dielectric layer that are exposed through the second gap.

2. The preparation method according to claim 1, further comprising: After removing the first dielectric layer and the second portion of the second dielectric layer exposed through the second spacer, the first spacer and the second spacer are removed.

3. The preparation method of claim 1, wherein the sacrificial column is removed after the first spacer is set and before the second spacer is set.

4. The preparation method according to claim 1, further comprising: Remove a third portion of the semiconductor substrate exposed through the second spacer, the first dielectric layer, and the second dielectric layer.

5. The preparation method according to claim 1, wherein the sacrificial column comprises a nitride.

6. The preparation method according to claim 1, wherein one cross-section of the sacrificial column is circular.

7. The preparation method according to claim 1, wherein the first spacer and the second spacer comprise the same dielectric material.

8. The preparation method of claim 1, wherein removing the second portion of the first dielectric layer and the second dielectric layer exposed through the second spacer comprises: Remove a fourth portion of the first dielectric layer and the second dielectric layer within the second spacer from a top view, and remove a fifth portion of the first dielectric layer and the second dielectric layer outside the second spacer from the top view.

9. The preparation method of claim 8, wherein the removal of the first dielectric layer and the fourth portion of the second dielectric layer within the second spacer from the top view is performed before or after the removal of the fifth portion of the first dielectric layer and the second dielectric layer outside the second spacer from the top view.

10. The preparation method of claim 8, wherein removing the fourth portion of the first dielectric layer and the second dielectric layer within the second spacer from the top view and removing the fifth portion of the first dielectric layer and the second dielectric layer outside the second spacer from the top view are performed simultaneously.

11. The preparation method according to claim 1, wherein the provision of the second spacer includes: An opening is formed by the first spacer and the second spacer.

12. The preparation method of claim 11, wherein the first dielectric layer and the second portion of the second dielectric layer exposed through the second spacer are at least partially disposed within the opening in the top view.

13. The preparation method of claim 1, wherein the second spacer includes a first annular component in contact with an outer surface of the first spacer, and includes a second annular component in contact with an inner surface of the first spacer.

14. The preparation method according to claim 1, wherein the first dielectric layer comprises an oxide.

15. The preparation method according to claim 1, wherein the second dielectric layer comprises a nitride.

16. The preparation method according to claim 1, wherein the insulating component comprises an oxide.

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