Pixel array driving method, apparatus and display panel

Abstract

A driving method, apparatus, and display panel for a pixel array. The pixel array includes multiple rows and columns of sub-pixels (101), multiple gate lines (102) and multiple data lines (103) intersecting to define the multiple rows and columns of sub-pixels (101). The data lines electrically connected to the sub-pixels (101) are electrically connected to a data signal terminal through a switching module. The switching module receives a selection control signal to switch the connection state of the data lines and the data signal terminal. The multiple rows of sub-pixels include adjacent first row sub-pixels and second row sub-pixels. The driving method includes: applying gate signals to the gate lines corresponding to the first row sub-pixels and the second row sub-pixels respectively (S10); during the period when the gate signals applied to the second row sub-pixels are used to control the second row sub-pixels, after a first time length after the gate signals applied to the first row sub-pixels switch from an on state to an off state, the selection control signal corresponding to the second row sub-pixels controls the switching module to switch the connection state (S20).

Description

TECHNICAL FIELD

[0001] Embodiments of the present disclosure relate to a pixel array driving method, device and display panel. BACKGROUND

[0002] In the field of display technology, a pixel array of a display panel such as a liquid crystal display panel usually includes multiple rows of gate lines and multiple columns of data lines staggered with the rows of gate lines. The driving of the gate lines can be achieved by an integrated driving circuit. In recent years, with the continuous improvement of the preparation process of amorphous silicon thin film transistors or oxide thin film transistors, the gate line driving circuit can also be directly integrated on a thin film transistor array substrate to prepare a GOA (Gate driver On Array) as a gate driving circuit to drive the gate lines. The GOA technology helps to realize the narrow frame design of the display panel and can reduce the production cost of the display panel. SUMMARY

[0003] At least one embodiment of the present disclosure provides a pixel array driving method. The pixel array includes multiple rows and multiple columns of sub-pixels, multiple rows of gate lines and multiple columns of data lines intersecting to define the multiple rows and multiple columns of sub-pixels, and a data line to which a sub-pixel is electrically connected is electrically connected to a data signal terminal through a switch module. The switch module receives a selection control signal to switch the connection state of the data line and the data signal terminal. The multiple rows of sub-pixels include adjacent first and second rows of sub-pixels. The method includes: applying a gate signal to the gate lines corresponding to the first and second rows of sub-pixels, the gate signal including an on state and an off state; and after a first time length during which the gate signal applied to the first row of sub-pixels is switched from the on state to the off state, the selection control signal corresponding to the second row of sub-pixels controls the switch module to switch the connection state, the first time length being greater than 0.

[0004] For example, in the driving method provided by an embodiment of the present disclosure, each row of sub-pixels is divided into multiple sub-pixel groups, multiple data lines electrically connected to multiple sub-pixels in each sub-pixel group are respectively electrically connected to one data signal terminal through a switch module, each sub-pixel corresponding switch module includes multiple switch elements, the selection control signal includes multiple selection control signals, and the multiple switch elements respectively receive the multiple selection control signals to switch the connection state of the multiple data lines corresponding to the multiple switch elements and the data signal terminal.

[0005] For example, in the driving method provided by an embodiment of the present disclosure, each sub-pixel group includes a first sub-pixel and a second sub-pixel, a data line connected to the first sub-pixel is connected to a data signal end through a first switch element, a data line connected to the second sub-pixel is connected to the data signal end through a second switch element, and the plurality of selection control signals include a first selection control signal and a second selection control signal; during application of a gate signal to the second row of sub-pixels to control the second row of sub-pixels, the first selection control signal and the second selection control signal are respectively applied to the first switch element and the second switch element corresponding to each sub-pixel group in the second row of sub-pixels, so that the first switch element and the second switch element are sequentially turned on.

[0006] For example, in the driving method provided by an embodiment of the present disclosure, the first selection control signal controls the first switch element to switch from being turned on to being turned off, and the second selection control signal controls the second switch element to be turned on, and the second time length between the two has a second time length, and the second time length is greater than 0.

[0007] For example, in the driving method provided by an embodiment of the present disclosure, two sub-pixels in each row of sub-pixels that are separated by one column are respectively taken as a first sub-pixel and a second sub-pixel to form a sub-pixel group.

[0008] For example, in the driving method provided by an embodiment of the present disclosure, the ratio of the first time length to the second time length is in the range of [0.8, 3.0].

[0009] For example, in the driving method provided by an embodiment of the present disclosure, the second time length is determined according to the time length required for the data signal end to switch from the first data signal to the second data signal, the time length required for the first switch element to switch from being turned on to being turned off, and the time length required for the second switch element to switch from being turned off to being turned on.

[0010] For example, in the driving method provided by an embodiment of the present disclosure, each sub-pixel group includes N sub-pixels, N is an integer greater than or equal to 2, the gate signal is a periodic signal, and during a third time length in which the gate signal is in an on state in each period, the selection control signal corresponding to the second row of sub-pixels controls the switch module to switch the connection state, and the calculation formula of the pulse width of the selection control signal is: W=(T3-T1-(N-1)×T2) / N, where W represents the pulse width, T3 represents the third time length, T1 represents the first time length, and T2 represents the second time length.

[0011] For example, in the driving method provided by an embodiment of the present disclosure, the ratio of the third time length T3 to the first time length T1 is in the range of [1.0, 5.0].

[0012] For example, in the driving method provided by an embodiment of the present disclosure, the ratio of the second time length T2 to the pulse width is in the range of [0.3, 2].

[0013] For example, in the driving method provided by an embodiment of the present disclosure, the ratio of the first time length T1 to the pulse width is in the range of [0.7, 3.0].

[0014] For example, in the driving method provided by an embodiment of the present disclosure, the first time length is positively correlated with the length of the connection line of the first row of sub-pixels, and the connection line is used to connect a signal source of the gate signal and a receiving end of the gate line corresponding to each row of sub-pixels.

[0015] For example, in the driving method provided by an embodiment of the present disclosure, the method further includes determining the first time length corresponding to the longest connection line among the multiple connection lines of the multiple first rows of sub-pixels; and determining the first time length corresponding to the other connection lines except the longest connection line among the multiple connection lines according to the first time length corresponding to the longest connection line.

[0016] For example, in the driving method provided by an embodiment of the present disclosure, the method further includes dividing the pixel array into multiple regions, each region including multiple consecutive rows of sub-pixels; determining the first time length corresponding to the longest connection line among the multiple connection lines of the multiple first rows of sub-pixels includes: determining a far-end region farthest from the signal source of the gate signal from the multiple regions; determining the first time length corresponding to the longest connection line based on the connection lines corresponding to the multiple first rows of sub-pixels in the far-end region; and determining the first time length corresponding to the other connection lines except the longest connection line among the multiple connection lines according to the first time length corresponding to the longest connection line includes: determining one first time length for the multiple rows of sub-pixels in each region according to the first time length corresponding to the longest connection line.

[0017] An embodiment of the present disclosure provides a display panel, which includes a pixel array formed by multiple rows and multiple columns of sub-pixels, multiple gate lines and multiple data lines intersecting to define the multiple rows and multiple columns of sub-pixels, a data line electrically connected to a sub-pixel and electrically connected to a data signal end through a switching module, the switching module receiving a selection control signal to switch the connection state of the data line and the data signal end, and the multiple rows of sub-pixels including adjacent first and second rows of sub-pixels, the first and second rows of sub-pixels respectively receiving a gate signal of a corresponding gate line, the gate signal including an open state and a closed state; during the application of the gate signal to the second row of sub-pixels to control the second row of sub-pixels, and after a first time length during which the gate signal received by the first row of sub-pixels is switched from the open state to the closed state, the switching module of the second row of sub-pixels receives the selection control signal to control the switching module of the second row of sub-pixels to switch the connection state.

[0018] For example, in the display panel provided by an embodiment of the present disclosure, each row of sub-pixels is divided into a plurality of sub-pixel groups, a plurality of data lines electrically connected to the plurality of sub-pixels in each sub-pixel group are electrically connected to a data signal terminal through a switch module, each switch module corresponding to each sub-pixel includes a plurality of switch elements, the selection control signal includes a plurality of selection control signals, and the plurality of switch elements receive the plurality of selection control signals to switch the connection state between the plurality of data lines connected to the plurality of switch elements and the data signal terminal.

[0019] For example, in the display panel provided by an embodiment of the present disclosure, each sub-pixel group includes a first sub-pixel and a second sub-pixel, the data line connected to the first sub-pixel is connected to the data signal terminal through a first switch element, the data line connected to the second sub-pixel is connected to the data signal terminal through a second switch element, and the plurality of selection control signals includes a first selection control signal and a second selection control signal; during the second row of sub-pixels receiving the gate signal, the first switch element and the second switch element corresponding to each sub-pixel group in the second row of sub-pixels are turned on in turn in response to the first selection control signal and the second selection control signal, respectively.

[0020] For example, in the display panel provided by an embodiment of the present disclosure, the first switch element is switched from the on state to the off state, and the second switch element is switched from the on state to the off state, and the second time length is greater than 0.

[0021] For example, in the display panel provided by an embodiment of the present disclosure, the display panel includes a non-display area and a display area, the pixel array is located in the display area, and the non-display area includes a signal source of the gate signal.

[0022] An embodiment of the present disclosure provides a driving device of a pixel array, the pixel array including a plurality of rows and a plurality of columns of sub-pixels, a plurality of gate lines and a plurality of data lines intersecting to define the plurality of rows and the plurality of columns of sub-pixels, a data line electrically connected to a sub-pixel being electrically connected to a data signal terminal through a switch module, the switch module receiving a selection control signal to switch a connection state between the data line and the data signal terminal, the plurality of rows of sub-pixels including adjacent first and second rows of sub-pixels, the driving device including: a gate driving circuit configured to apply a gate signal to the gate line corresponding to the first and second rows of sub-pixels, the gate signal including an on state and an off state; a control circuit configured to apply the selection control signal to the second row of sub-pixels, wherein, during the application of the gate signal to the second row of sub-pixels to control the second row of sub-pixels, the selection control signal corresponding to the second row of sub-pixels controls the switch module to switch the connection state after a first time length in which the gate signal applied to the first row of sub-pixels is switched from the on state to the off state, and a data driving circuit including the data signal terminal and configured to provide a data signal to the data line connected to the data signal terminal, the first time length being greater than 0. BRIEF DESCRIPTION OF DRAWINGS

[0023] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly introduced as follows. Obviously, the drawings in the following description are only some embodiments of the present disclosure and not limit the present disclosure.

[0024] Figure 1A A schematic diagram of a display panel is shown;

[0025] Figure 1B A timing relationship schematic diagram of a cycle group is shown;

[0026] Figure 1C And Figure 1D A schematic diagram of pixel mischarging in a display screen is shown according to at least one embodiment of the present disclosure;

[0027] Figure 2A A flowchart of a driving method of a pixel array is shown according to at least one embodiment of the present disclosure;

[0028] Figure 2B A timing diagram of the driving method of the pixel array is shown according to at least one embodiment of the present disclosure;

[0029] Figure 2C A connection schematic diagram of a sub-pixel and a data signal terminal is shown according to at least one embodiment of the present disclosure;

[0030] Figure 2D A timing diagram of a sub-pixel group including three sub-pixels is shown according to at least one embodiment of the present disclosure;

[0031] Figure 3 A display panel is shown according to at least one embodiment of the present disclosure;

[0032] Figure 4 A display panel is shown according to at least one embodiment of the present disclosure; Figure 3 A timing diagram of the gate signals received by each row of sub-pixels in the display panel is shown;

[0033] Figure 5 A flowchart of another driving method is shown according to at least one embodiment of the present disclosure; and

[0034] Figure 6 A block diagram of a driving device is shown according to at least one embodiment of the present disclosure. DETAILED DESCRIPTION

[0035] In order to make the objects, technical solutions and advantages of the embodiments of the present disclosure clearer, the following will be combined with the accompanying drawings for the embodiments of the present disclosure to make a clear and complete description of the technical solutions of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, rather than all the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by a person of ordinary skill in the art without any inventive effort fall within the protection scope of the present disclosure.

[0036] Unless otherwise defined, technical terms or scientific terms used in the present disclosure shall have the ordinary meaning understood by a person of ordinary skill in the art to which the present disclosure pertains. The terms "first", "second" and similar terms used in the present disclosure do not denote any order, quantity or importance, but are used to distinguish different components. Similarly, the terms "one", "a" or "the" and similar terms do not denote quantity limitation, but mean that there is at least one. The terms "include" or "contain" and similar terms mean that the components or objects before the terms encompass the components or objects listed after the terms and their equivalents, without excluding other components or objects. The terms "connect" or "connected" and similar terms are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. The terms "upper", "lower", "left", "right" and the like only represent relative positional relationships, which can change when the absolute positions of the described objects change.

[0037] For example, the GOA can be used to provide gate signals (scanning signals) for multiple rows of gate lines of a pixel array, so as to control multiple rows of sub-pixels to be sequentially turned on, and at the same time, data signals are provided to the sub-pixels of the corresponding rows in the pixel array from the data lines, so as to form the gray voltage required by each sub-pixel to display an image, and then display a frame of image. At present, the display panel more and more uses the GOA technology to prepare the gate driving circuit, so as to drive the gate lines.

[0038] Figure 1A A schematic diagram of a display panel 100 is shown.

[0039] As Figure 1AAs shown, the display panel 100 includes multiple rows and columns of sub-pixels 101 arranged in an array. For example, each row of sub-pixels is connected to the same gate line 102 to receive a gate signal, and each column of sub-pixels is connected to the same data line 103. Thus, multiple gate lines and multiple data lines intersect to define multiple rows and columns of sub-pixels. In this disclosure, sub-pixels connected to the same gate line are considered to be in the same row of sub-pixels. Sub-pixels in the same row may or may not be arranged in the same row. Similarly, sub-pixels connected to the same data line are considered to be in the same column. Sub-pixels in the same column may or may not be arranged in the same column. This invention also applies to dual-gate structures, i.e., two gate lines are included between two adjacent rows of sub-pixels, and a row of sub-pixels is controlled by two gate lines. This is not limited here.

[0040] The display panel 100 may be, for example, a liquid crystal display panel or an OLED display panel. For instance, if the display panel is a liquid crystal display panel, it includes an array substrate and a counter substrate, with a liquid crystal layer sandwiched between them. Gate lines, data lines, sub-pixels, etc., are formed on the array substrate. Sub-pixels include pixel electrodes, switching elements, etc., and the switching elements of a pixel unit are coupled to corresponding gate lines and data lines to receive gate signals and data signals provided by the gate lines and data lines.

[0041] like Figure 1A As shown, the data lines for the sub-pixels are electrically connected to multiple data signal terminals (S1, ..., Sn) via multiple switch modules. These switch modules can be in a one-to-one correspondence with each data signal terminal, or k (an integer greater than 0) switch modules can correspond to a single data signal terminal. Each switch module receives a selection control signal to switch the connection state between the data line and the data signal terminal. For example, if each column of sub-pixels is connected to the same switch module, the connection state between that column of sub-pixels and the data signal terminal is controlled by the same switch module.

[0042] For example, when the selection control signal is high, the switch module control data line is connected to the data signal terminal; when the selection control signal is low, the switch module control data line is disconnected from the data signal terminal.

[0043] The gate signal includes an on state and an off state. When the gate signal of a row of sub-pixels is in the on state and the switching module of that row of sub-pixels controls the data lines and data signal terminals connected to the multiple sub-pixels to be turned on, the data signal terminal charges the multiple sub-pixels to write the data signal of the data signal terminal to the multiple sub-pixels.

[0044] For example, such as Figure 1A As shown, the pixel array consists of N rows, where N is an integer greater than 1, and PI <1> The sub-pixel of the row receives gate signals CK1 and PI. <2> The sub-pixels of the row receive gate signals CK2, ..., PI <n>The sub-pixels in the row receive a gate signal CKN. It should be noted that the number of rows of sub-pixels included in the display panel can be set as required.

[0045] In some embodiments of the present disclosure, for example, 8 gate signals form a cycle group, and the gate signals are applied to each row of sub-pixels in the pixel array. It should be understood that although the embodiments of the present disclosure are described with 8 gate signals as a cycle group, the present disclosure does not limit the number of gate signals in a cycle group, for example, 6 or 12 gate signals can also form a cycle group.

[0046] Figure 1B A timing relationship diagram of a cycle group is shown.

[0047] As shown in Figure 1B , the 8 gate signals are CK1, CK2, CK3, CK4, CK5, CLK6, CK7 and CK8 respectively, which correspond to different clock signals applied to the gate drive circuit.

[0048] For example, the duty cycle (i.e. the ratio of the time of high level to the period) of the gate signals CK1 to CK8 is 25% and the periods are equal. For example, the high level time of each of CK1 to CK8 is 2H, and the low level time is 6H. H is the length of time required to charge a row of sub-pixels.

[0049] As shown in Figure 1B , for example, for a time period, the high level time of the gate signal is 2H, and in the first 1H period, the sub-pixels in the row corresponding to the gate signal are pre-charged. In the second 1H period, that is, in the adjacent two rows of sub-pixels, the part of the time between the opening time of the gate signal of the first row of sub-pixels and the opening time of the gate signal of the second row of sub-pixels is the pre-charging process of the second row of sub-pixels, and the part of the time between the opening time of the gate signal of the first row of sub-pixels and the opening time of the gate signal of the second row of sub-pixels is the actual charging time of the second row of sub-pixels, at this time the data signal end charges the sub-pixels in the row corresponding to the gate signal to write the data signal to the corresponding row of sub-pixels. In the first 1 / 2H period of the second 1H period, the selection control signal MUX1 controls the data line and the data signal end of the first part of the sub-pixels in the row to be conductive, so that the data signal end charges the first part of the sub-pixels. In the second 1 / 2H period of the second 1H period, MUX2 controls the data line and the data signal end of the second part of the sub-pixels in the row to be conductive, so that the data signal end charges the second part of the sub-pixels. In this way, at least two parts of a row of pixels are charged, and for large-size products, the pixel charging rate can be ensured.

[0050] As shown in Figure 1B As shown, for example, when the gate signal CK1 transitions from high to low, the selection control signal MUX1 corresponding to the next row of gate signals CK2 also immediately switches to high to charge the first portion of sub-pixels in the second row of sub-pixels, with a holding time of H / 2. When the selection control signal MUX1 switches to low, the selection control signal MUX2 also synchronously switches to high, with a holding time of H / 2, to charge the second portion of sub-pixels in the second row of sub-pixels, and then switches to low.

[0051] However, due to the GOA characteristics and wiring limitations of large-size display panels, the delay of the resistor-capacitor is large. For the first row of sub-pixels and the second row of sub-pixels being charged in sequence, when the gate of the first row of sub-pixels is opened and the gate signal of the first row of sub-pixels switches from high to low, for example, due to the influence of the resistor-capacitor impedance, the gate signal is delayed in closing, and cannot be switched immediately. When the second row of sub-pixels is charged, the data signal of the second row of sub-pixels charges the first row of sub-pixels, resulting in pixel mischarging and other problems, such as causing black and white grid images, and other image display abnormalities similar to jaggedness.

[0052] Figure 1C And Figure 1D A schematic diagram showing pixel mischarging in a display image is shown.

[0053] Figure 1C A later frame of display image (i.e., a second frame of display image) in two adjacent frames of display image sequentially displayed by the pixel array is shown. Figure 1D A schematic diagram showing pixel mischarging in a display image is shown. Figure 1C An eyepiece actual image of the second frame of display image is shown.

[0054] As Figure 1C As shown, in the second frame of display image, pixel 1 is black, pixel 2 is white, pixel 3 is white, and pixel 4 is black. In the previous frame of display image (i.e., a first frame of display image) of the second frame of display image, pixel 1 is white, pixel 2 is black, pixel 3 is black, and pixel 4 is white.

[0055] When the display image displayed by the pixel array is switched from the first frame of display image to the second frame of display image, as Figure 1D As shown, pixel mischarging occurs in the mth row of sub-pixels 110 of the second frame of display image, and appears jagged. Figure 1C And Figure 1D The area enclosed by the dotted middle-ellipse line is the area where the mth row of sub-pixels 110 is located. The pixel mischarging of the second frame display picture is because when at least part of the sub-pixels in the mth row are not turned off, the data signal end has already written data to the m+1th row, and thus the data signal of the m+1th row is also written to the mth row. Since part of the sub-pixels in the mth row have been turned off, and the other part of the sub-pixels have not been turned off, the pixels in the mth row are displayed as jagged in the second frame display picture.

[0056] To this end, at least one embodiment of the present disclosure provides a driving method of a pixel array, which comprises: applying a gate signal to a gate line corresponding to a first row of sub-pixels and a second row of sub-pixels, the gate signal comprising an on state and an off state, the first row of sub-pixels and the second row of sub-pixels being adjacent two rows of sub-pixels; during application of the gate signal to the second row of sub-pixels to control the second row of sub-pixels, applying a selection control signal corresponding to the second row of sub-pixels after a first time length in which the gate signal applied to the first row of sub-pixels switches from the on state to the off state, the first time length being greater than 0. This method can alleviate problems such as pixel mischarging and abnormal picture display caused by the first row of sub-pixels not being completely turned off.

[0057] Figure 2A A flowchart of a driving method of a pixel array provided by at least one embodiment of the present disclosure is shown.

[0058] As shown in Figure 2A , the method can comprise steps S10-S20.

[0059] Step S10: applying a gate signal to a gate line corresponding to a first row of sub-pixels and a second row of sub-pixels, the gate signal comprising an on state and an off state.

[0060] Step S20: during application of the gate signal to the second row of sub-pixels to control the second row of sub-pixels, applying a selection control signal corresponding to the second row of sub-pixels to control the switching connection state of the switching module after a first time length in which the gate signal applied to the first row of sub-pixels switches from the on state to the off state, the first time length being greater than 0.

[0061] The driving method provided by at least one embodiment of the present disclosure can be applied to a pixel array as shown in Figure 1A . The pixel array comprises a plurality of rows and columns of sub-pixels, a plurality of gate lines and a plurality of data lines intersecting to define the plurality of rows and columns of sub-pixels, a data line to which a sub-pixel is electrically connected being electrically connected to a data signal end through a switching module, the switching module receiving a selection control signal to switch the connection state of the data line and the data signal end. Embodiments of the pixel array are described above. Figure 1A

[0062] ​Here, multiple rows of sub-pixels include adjacent first and second rows of sub-pixels; that is, the first and second rows of sub-pixels can be any two adjacent rows of sub-pixels. It should be understood that, in at least one embodiment of this disclosure, two adjacent rows of sub-pixels do not refer to two rows of sub-pixels that are adjacent in the pixel array arrangement, but rather to two rows of sub-pixels whose gate signals are sequentially adjacent. For example, two rows of sub-pixels that are sequentially adjacent refer to two rows of sub-pixels whose gate signals differ by one time unit; one time unit can be the charging time of one row of sub-pixels. For example, in... Figure 1A and Figure 1B In the scenario shown, PI <1> With PI <2> If the gate signals differ by 1H, then PI <1> For the first row of sub-pixels, PI <2> To cooperate with PI <1> The adjacent second row of sub-pixels. Similarly, PI <3> For the first row of sub-pixels, PI <4> To cooperate with PI <3> The adjacent second row of sub-pixels. Similarly, if in a scenario, PI <11> The gate signal ratio of PI <8> If the gate signal is delayed by 1H, then PI <8> and PI <11> It can be two adjacent rows of sub-pixels, with the first row of sub-pixels being PI. <11> The second row of sub-pixels is PI. <8> .

[0063] It should be noted that, in this disclosure, except for the last row of sub-pixels in the pixel array, all other rows of sub-pixels can be the first row of sub-pixels, and except for the first row of sub-pixels in the pixel array, all other rows of sub-pixels can be the second row of sub-pixels.

[0064] For step S10, for example, gate signals are sequentially applied to the gate lines corresponding to the first row of sub-pixels and the second row of sub-pixels, respectively, and the gate signal of the second row of sub-pixels is delayed by 1H compared with the gate signal of the first row of sub-pixels.

[0065] For example, for Figure 1A The pixel array shown applies multiple gate signals sequentially to multiple gate lines corresponding to multiple rows of sub-pixels in the pixel array.

[0066] Figure 2B A timing diagram of a pixel array driving method provided in at least one embodiment of the present disclosure is shown.

[0067] like Figure 2B As shown, the first row of sub-pixels and the second row of sub-pixels are two adjacent rows of sub-pixels. The gate signal of the second row of sub-pixels is time-adjacent to the gate signal of the first row of sub-pixels, and the gate signal of the second row of sub-pixels is delayed by 1H compared to the gate signal of the first row of sub-pixels.

[0068] For step S20, during the period when a gate signal is applied to each row of sub-pixels in the multi-row sub-pixels to control each row of sub-pixels, a selection control signal corresponding to each row of sub-pixels is applied.

[0069] For example, after a first time length in which the gate signal applied to the first row of sub-pixels is switched from the on state to the off state, the selection control signal corresponding to the second row of sub-pixels controls the switch module to switch the connection state. For example, the selection control signal of the second row of sub-pixels controls the switch module to turn on the data line corresponding to the first part of the sub-pixels in the second row of sub-pixels and the data signal line.

[0070] For example, the on state of the gate signal is high, the off state of the gate signal is low, and when the selection control signal is high, the switch module turns on the data line and the data signal end. As shown in Figure 2B During the period in which the gate signal of the second sub-pixel is high, the gate signal applied to the first row of sub-pixels is switched from high to low at time t1, and at time t2, the selection control signal MUX1 is switched from low to high to control the switch module to turn on the data line corresponding to the first part of the sub-pixels in the second row of sub-pixels and the data signal end. Time t2 is later than time t1 by a time length T1, and T1 is greater than 0.

[0071] In at least one embodiment of the present disclosure, a level reaching 90% of the highest level is considered to reach a high level, and a level reaching 10% of the lowest level is considered to reach a low level.

[0072] In at least one embodiment of the present disclosure, the first time length T1 is such that when the selection control signal is applied to the second row of sub-pixels, the gate signal applied to the first row of sub-pixels is in the off state.

[0073] In at least one embodiment of the present disclosure, after a first time length in which the gate signal applied to the first row of sub-pixels is switched from the on state to the off state, the selection control signal of the second row of sub-pixels controls the switch module corresponding to the second row of sub-pixels to switch from off to on, so that the first row of sub-pixels is charged to the second row of sub-pixels to write the data signal after being sufficiently turned off, thereby alleviating the problem of pixel mischarging due to the first row of sub-pixels not being completely turned off, display abnormality, and the like.

[0074] Figure 2C A connection diagram of a sub-pixel and a data signal end provided by at least one embodiment of the present disclosure is shown.

[0075] In some embodiments of the present disclosure, each row of sub-pixels is divided into a plurality of sub-pixel groups, and a plurality of data lines electrically connected to a plurality of sub-pixels in each sub-pixel group are electrically connected to a data signal end through a switch module.

[0076] For example, each sub-pixel group includes a first sub-pixel and a second sub-pixel, the data line connected to the first sub-pixel is connected to the data signal end through a first switch element, and the data line connected to the second sub-pixel is connected to the data signal end through a second switch element.

[0077] For example, as shown in FIG. 2, the same row of sub-pixels includes sub-pixel 201 to sub-pixel 208, and so on, wherein sub-pixel 201 and sub-pixel 203 form a sub-pixel group, sub-pixel 202 and sub-pixel 204 form a sub-pixel group, sub-pixel 205 and sub-pixel 207 form a sub-pixel group, and sub-pixel 206 and sub-pixel 208 form a sub-pixel group. This embodiment is not limited to the specific positions of the row of sub-pixels. Figure 2C

[0078] In the example shown in FIG. 2, two sub-pixels in each row of sub-pixels that are separated by one column serve as a first sub-pixel and a second sub-pixel to form a sub-pixel group. For example, sub-pixel 201 and sub-pixel 203 form a sub-pixel group, sub-pixel 202 and sub-pixel 204 form a sub-pixel group, sub-pixel 205 and sub-pixel 207 form a sub-pixel group, and sub-pixel 206 and sub-pixel 208 form a sub-pixel group. Figure 2C

[0079] As shown in FIG. 2, the switch module corresponding to the sub-pixel group formed by sub-pixel 201 and sub-pixel 203 includes switch element 211 and switch element 213, and the data lines electrically connected to sub-pixel 201 and sub-pixel 203 are electrically connected to data signal terminal S1 through switch element 211 and switch element 213, respectively. The switch module corresponding to the sub-pixel group formed by sub-pixel 202 and sub-pixel 204 includes switch element 212 and switch element 214, and the data lines electrically connected to sub-pixel 202 and sub-pixel 204 are electrically connected to data signal terminal S2 through switch element 212 and switch element 214, respectively. The switch module corresponding to the sub-pixel group formed by sub-pixel 205 and sub-pixel 207 includes switch element 215 and switch element 217, and the data lines electrically connected to sub-pixel 205 and sub-pixel 207 are electrically connected to data signal terminal S3 through switch element 215 and switch element 217, respectively. The switch module corresponding to the sub-pixel group formed by sub-pixel 206 and sub-pixel 208 includes switch element 216 and switch element 218, and the data lines electrically connected to sub-pixel 206 and sub-pixel 208 are electrically connected to data signal terminal S4 through switch element 216 and switch element 218, respectively. The switch elements may, for example, be thin film transistors. Figure 2C In this embodiment, the selection control signal includes a plurality of selection control signals. The plurality of selection control signals are respectively applied to different sub-pixels in a sub-pixel group. For example, the plurality of selection control signals include a first selection control signal and a second selection control signal; during application of the gate signal to the second row of sub-pixels to control the second row of sub-pixels, the first selection control signal and the second selection control signal are respectively applied to the first switch element and the second switch element corresponding to each sub-pixel group in the second row of sub-pixels, so that the first switch element and the second switch element are sequentially turned on.

[0080] In this embodiment, the selection control signal includes a plurality of selection control signals. The plurality of selection control signals are respectively applied to different sub-pixels in a sub-pixel group. For example, the plurality of selection control signals include a first selection control signal and a second selection control signal; during application of the gate signal to the second row of sub-pixels to control the second row of sub-pixels, the first selection control signal and the second selection control signal are respectively applied to the first switch element and the second switch element corresponding to each sub-pixel group in the second row of sub-pixels, so that the first switch element and the second switch element are sequentially turned on.​​

[0081] For example, such as Figure 2C As shown, the selection control signal for each row of sub-pixels includes selection control signal MUX1 and selection control signal MUX2. In some embodiments of this disclosure, selection control signals can be applied to multiple sub-pixels through multiple signal lines respectively. For example, selection control signal MUX1 includes MUX1_1, MUX1_2, MUX1_3, and MUX1_4, and selection control signal MUX2 includes MUX2_1, MUX2_2, MUX2_3, and MUX2_4. MUX1_1, MUX1_2, MUX1_3, and MUX1_4 are signals with the same timing sequence, and MUX2_1, MUX2_2, MUX2_3, and MUX2_4 are signals with the same timing sequence. MUX1_1, MUX1_2, MUX1_3, and MUX1_4 are each from four signal lines, and MUX2_1, MUX2_2, MUX2_3, and MUX2_4 are each from four signal lines, which improves the driving capability of the selection control signals.

[0082] In other embodiments of this disclosure, a selection control signal is applied to multiple sub-pixels via a single signal line. For example, MUX1 is provided via a single signal line to sub-pixels 201, 202, 205, and 206. Similarly, MUX2 is provided via another signal line to sub-pixels 203, 204, 207, and 208. This embodiment saves layout space on the display panel and simplifies the circuitry.

[0083] like Figure 2C As shown, switch element 211 and switch element 213 respectively receive selection control signal MUX1 and selection control signal MUX2 to switch the connection state of multiple data lines connected to switch element 211 and switch element 213 respectively with data signal terminal S1.

[0084] For example, for the row containing sub-pixels 201 to 208, while the gate signal corresponding to the sub-pixel in that row is in the on state, selection control signals MUX1 and MUX2 are applied to the first and second switching elements respectively. These signals sequentially turn on the first and second switching elements. For instance, if selection control signal MUX1 is high and selection control signal MUX2 is low, switching element 211 connects the data line and data signal terminal S1 corresponding to sub-pixel 201 to charge sub-pixel 201, and switching element 213 disconnects sub-pixel 203 from data signal terminal S1. If selection control signal MUX1 is low and selection control signal MUX2 is high, switching element 213 connects the data line and data signal terminal S1 corresponding to sub-pixel 203 to charge sub-pixel 203, and switching element 211 disconnects sub-pixel 201 from data signal terminal S1. Other sub-pixel groups and sub-pixel groups composed of sub-pixels 201 and 203 are not described further here.

[0085] like Figure 2C As shown, when the selection control signal MUX1 is high, the data lines corresponding to sub-pixels 201, 202, 205, and 206 are connected to data signal terminals S1, S2, S3, and S4, respectively, to charge sub-pixels 201, 202, 205, and 206 through these terminals. Similarly, when the selection control signal MUX2 is high, the data lines corresponding to sub-pixels 203, 204, 207, and 208 are connected to data signal terminals S1, S2, S3, and S4, respectively, to charge sub-pixels 203, 204, 207, and 208 through these terminals.

[0086] For example, sub-pixels 201, 202, and 203 are red, green, and blue light sub-pixels, respectively, and sub-pixels 204, 205, and 206 are red, green, and blue light sub-pixels, respectively.

[0087] Understandably, although Figure 2C In the example, two subpixels form a subpixel group, but this disclosure is not limited to two subpixels forming a subpixel group. For example, it could also be three subpixels forming a subpixel group, four subpixels forming a subpixel group, and so on. That is, each subpixel group includes at least two subpixels.

[0088] In some embodiments of the present disclosure, the first selection control signal controls the first switch element to switch from being turned on to being turned off, and the second selection control signal controls the second switch element to be turned on, and the second time length is greater than 0.

[0089] As shown in FIG. 3, during the period when the gate signal of the second row of sub-pixels is at a high level, the selection control signal MUX1 is switched from a high level to a low level at time t3 to make the first part of sub-pixels switch from being turned on to being turned off, and after a second time length T2 at time t3, the selection control signal MUX2 is switched from a low level to a high level to control the switch module to turn on the data line and the data signal end corresponding to the second part of sub-pixels in the second row of sub-pixels, and the second time length T2 is greater than 0. Figure 2B

[0090] The driving method can make the switch element corresponding to the first part of sub-pixels in the second row of sub-pixels be fully turned off, and then turn on the data line and the data signal end corresponding to the second part of sub-pixels in the second row of sub-pixels, thereby further improving the display quality and being more in line with the characteristics of the display panel.

[0091] In some embodiments of the present disclosure, the second time length is determined according to the time length required for the data signal end to switch from the first data to the second data, the time length required for the first switch element to switch from being turned on to being turned off, and the time length required for the second switch to switch from being turned off to being turned on.

[0092] For example, the second time length T2 is the sum of the time length required for the data signal end to switch from the first data to the second data, the time length required for the first switch element to switch from being turned on to being turned off, and the time length required for the second switch to switch from being turned off to being turned on. For example, the time length required for the first switch element to switch from being turned on to being turned off is the time length T22 required for the selection control signal MUX1 corresponding to the first switch element to switch from a high level to a low level. The time length required for the second switch to switch from being turned off to being turned on is the time length T23 required for the selection control signal MUX2 corresponding to the second switch element to switch from a low level to a high level.

[0093] As shown in FIG. 3, the second time length T2 is the sum of the time length T21 required for the data signal end to switch from the first data to the second data, the time length T22 required for the selection control signal MUX1 to switch from a high level to a low level, and the time length T23 required for the selection control signal MUX2 to switch from a low level to a high level. That is, T2 = T21 + T22 + T23. Figure 2B

[0094] ​​In some embodiments of the present disclosure, each sub-pixel group includes N sub-pixels, N is an integer greater than or equal to 2, the gate signal is a periodic signal, and in each period, the selection control signal corresponding to the second row of sub-pixels controls the switch module to switch the connection state in the third time length during which the gate signal is in the open state. The calculation formula of the pulse width of the selection control signal is:

[0095] W = (T3-T1-(N-1) x T2) / N.

[0096] W represents the pulse width, T3 represents the third time length, T1 represents the first time length, and T2 represents the second time length.

[0097] The third time length T3 is the time period during which the gate signal of the second row of sub-pixels is in the open state and the gate signal of the first row of sub-pixels is in the closed state in the adjacent two rows of sub-pixels, that is, the time period corresponding to the position where the opening time of the adjacent two rows of gate lines does not overlap. As shown in Figure 2B In one period of the gate signal, the time period during which the gate signal of the second row of sub-pixels is in the open state and the gate signal of the first row of sub-pixels is in the closed state is 1H, so in this example, the third time length T3 is 1H.

[0098] For example, in the example of Figure 2B N = 2, W = (1H-T1-T2) / 2. For example, T1 = 1300ns, T2 = 750ns, and 1H = 3700ns, then W = 825ns.

[0099] In some other embodiments of the present disclosure, the calculation formula of the pulse width of the selection control signal is:

[0100] W = (T3-T1-(N-1) x T2-T4) / N.

[0101] T4 is the time length between the time when the gate signal of the second row of sub-pixels switches from the open state to the closed state and the time when the last selection control signal in one sub-pixel group switches from high level to low level. As shown in Figure 2B T4 is the time length between the time t4 when the gate signal of the second row of sub-pixels switches from the open state to the closed state and the time t5 when MUX2 switches from high level to low level. In this way, it can be ensured that the gate signal is always in the open state during the charging of the second row of sub-pixels, thereby ensuring sufficient charging of the second row of sub-pixels.

[0102] For example, in the example of Figure 2B N = 2, W = (1H-T1-T2-T4) / 2. For example, T1 = 1300ns, T2 = 750ns, 1H = 3700ns, and T4 = 150ns, then W = 750ns.

[0103] The duration of T4 can be set by those skilled in the art based on experience or actual needs; for example, T4 can be 50ns, 100ns, etc.

[0104] Figure 2D A timing diagram illustrating a subpixel group comprising three subpixels, provided in at least one embodiment of the present disclosure, is shown.

[0105] like Figure 2D As shown, when N=3, selection control signals MUX1, MUX2, and MUX3 are applied to the three sub-pixels in the same sub-pixel group, respectively. The pulse widths of selection control signals MUX1, MUX2, and MUX3 are all W', where W' = (1H - T1 - 2 × T2) / 3.

[0106] In some embodiments of this disclosure, the ratio of the first time length T1 to the second time length T2 can range from [0.8, 3.0]. For example, the ratio of the first time length T1 to the second time length T2 can be a value between 1.5 and 2.0. For example, T1 = 1300 ns, T2 = 750 ns.

[0107] In some embodiments of this disclosure, the ratio between the third time length T3 and the first time length T1 can range from [1.0, 5.0]. For example, the ratio between the third time length T3 and the first time length T1 is a value between 2.0 and 3.5. For example, the third time length T3 is 1H, where 1H = 3700ns.

[0108] In some embodiments of this disclosure, the ratio between the second time length T2 and the pulse width can range from [0.3, 2.0]. For example, the ratio between the second time length T2 and the pulse width is a value between 0.8 and 1.2. For example, the second time length T2 and the pulse width are equal.

[0109] In some embodiments of this disclosure, the ratio between the first time length T1 and the pulse width can range from [0.7, 3.0]. For example, the ratio between the first time length T1 and the pulse width is a value between 1.5 and 2.0.

[0110] In embodiments of this disclosure, the first time length T1 needs to be a suitable value to ensure that the gate signal applied to the first row of sub-pixels is in the off state when the selection control signal is applied to the second row of sub-pixels.

[0111] For example, multiple different values ​​can be assigned to the first time length T1, and then a display test can be performed for each value to determine the appropriate T1 value from the multiple different T1 values ​​to alleviate pixel misfilling.

[0112] In some embodiments of the present disclosure, for example, the picture used for display test can be a black-and-white checkerboard, when performing the display test, the gate signal and the selection control signal are applied to the pixel array according to the timing of the gate signal and the selection control signal of the adjacent two rows of sub-pixels as described above, and the pixel array displays two different black-and-white checkerboard pictures in turn. The black pixels in the first frame of the black-and-white checkerboard picture become white pixels in the second frame of the black-and-white checkerboard picture, and the white pixels in the first frame of the black-and-white checkerboard picture become black pixels in the second frame of the black-and-white checkerboard picture. Whether there is pixel mischarging at the black-and-white boundary in the second frame of the picture is detected. If there is no mischarging in the black-and-white grid picture displayed by the display panel when the first time length is a first value, the first value meets the display requirement, and the first value can be used as the first time length.

[0113] In some embodiments of the present disclosure, for example, a plurality of values of the first time length T1 can be set from small to large in turn, and then the display test is performed for each value to determine the minimum value meeting the display requirement from the plurality of values, and the minimum value is used as the first time length T1.

[0114] For example, the first time length T1 is set to 800ns, 900ns, 1000ns, 1100ns, 1200ns, 1300ns, 1400ns, and 1500ns, respectively, and the display test is performed in turn according to the time length from small to large. If the display picture has pixel mischarging when the first time length T1 is 800ns, 900ns, 1000ns, 1100ns, and 1200ns, respectively, and the display picture has no pixel mischarging when the first time length T1 is 1300ns, the minimum value of the first time length T1 is 1300ns.

[0115] In some embodiments of the present disclosure, for example, the bisection method can be used to determine the optimal first time length T1 from 1200ns and 1300ns.

[0116] In some embodiments of the present disclosure, the first time length is positively correlated with the length of the connection line of the first row of sub-pixels, and the connection line is used to connect the signal source of the gate signal and the receiving end of the gate line corresponding to each row of sub-pixels. The following embodiment is described in combination with Figure 3 .

[0117] Figure 3 A display panel 200 provided by at least one embodiment of the present disclosure is shown.

[0118] As shown in Figure 3 , the display panel 200 includes a display region DR and a non-display region PR other than the display region DR, for example, the non-display region PR surrounds the display region DR.

[0119] It needs to be understood that, Figure 3 For the purpose of easy illustration, the display region DR is reduced and the non-display region PR is enlarged in the diagram, thus Figure 3 The area size relationship between the display region DR and the non-display region PR shown in the diagram is not the real size relationship. For example, the area of the display region is usually larger than the area of the non-display region.

[0120] The display region DR includes a pixel array, which includes a plurality of rows and a plurality of columns of sub-pixels. The pixel array may, for example, be similar to Figure 1A The pixel array in the display panel 100 shown, Figure 3 1, 2, 3, 4, 5, 6, 7, 8 in the above respectively represent the gate lines connected with each row of sub-pixels (for example Figure 1A The PI<1> row of sub-pixels, …, the PI<8> row of sub-pixels of the pixel array in the above). The non-display region PR includes a gate drive circuit 10 and a gate drive circuit 30. The gate drive circuit 10 and the gate drive circuit 30 each include a plurality of cascaded shift register units. For example, the plurality of cascaded shift register units are, for example, a first-stage shift register unit GOA1, a second-stage shift register unit GOA2, …, an eighth-stage shift register unit GOA8, etc. It needs to be understood that although 8 shift register units are shown in the diagram, the number of shift register units is not limited in the present disclosure, and the number of shift register units can be determined according to actual needs.

[0121] For example, the gate lines of the plurality of sub-pixels in the same row are connected with one shift register unit in the gate drive circuit 10 and the gate drive circuit 30 to receive the gate signal output by the shift register unit. For example, the plurality of sub-pixels close to the gate drive circuit 10 in a row of sub-pixels are provided with the gate signal by the gate drive circuit 10, and the plurality of sub-pixels close to the gate drive circuit 30 are provided with the gate signal by the gate drive circuit 30. In some other embodiments of the present disclosure, the display panel can also include only one gate drive circuit, and the gate lines of the sub-pixels in the same row are connected with one shift register unit of the gate drive circuit, and the shift register unit provides the gate signal to the sub-pixels in the row.

[0122] As shown in Figure 3 For example, the gate drive circuit includes CLK1-CLK8, and the 8 clock signals are taken as an example. It can also be 6CLK or 12CLK, etc., which is not limited herein. Each shift register unit has a first voltage terminal VDD1, a second voltage terminal VDD2, a clock signal terminal CLKi (i is 1, 2, …, N (N is an integer greater than 1)), a third voltage terminal LVGL, a fourth voltage terminal VGL, a reset signal terminal Total reset, an input terminal IN, a first output terminal GOUT, and a second output terminal GOUT_C. As shown in Figure 3 As shown, the input IN of the shift register unit of the k+4th stage is connected with the first output GOUT_C of the shift register unit of the kth stage, k is an integer greater than or equal to 1. The input IN of each of the first to fourth shift register units is connected with the signal line STV1, the signal line STV2, the signal line STV3 and the signal line STV4 respectively to receive a frame start signal from the signal line STV1, the signal line STV2, the signal line STV3 and the signal line STV4, and optionally, STV1-STV4 are the same frame start signal. The first output GOUT is configured to output a gate signal to a gate line. Each shift register unit receives a voltage signal from the signal line VDD1, the signal line VDD2, the signal line LVGL and the signal line VGL. For example, the voltage signal VDD1 on the signal line VDD1 and the voltage signal VDD2 on the signal line VDD2 are high and low respectively, which can be used in a noise reduction circuit in the shift register unit. The voltage signal VGL on the signal line VGL is used to pull down the level of the display area, and the voltage signal LVGL on the signal line LVGL is used to pull down the level of the noise reduction circuit.

[0123] As shown in Figure 3 The gate drive circuit 10 and the gate drive circuit 30 each further include a sub-clock signal line CLK1 transmitting a first sub-clock signal, a sub-clock signal line CLK2 transmitting a second sub-clock signal, a sub-clock signal line CLK3 transmitting a third sub-clock signal, a sub-clock signal line CLK4 transmitting a fourth sub-clock signal, a sub-clock signal line CLK5 transmitting a fifth sub-clock signal, a sub-clock signal line CLK6 transmitting a sixth sub-clock signal, a sub-clock signal line CLK7 transmitting a seventh sub-clock signal, and a sub-clock signal line CLK8 transmitting an eighth sub-clock signal.

[0124] For example, the number N of the shift register units included in the gate drive circuit 10 and the gate drive circuit 30 is an integer multiple of 8, and each 8 shift register units are a cyclic group, respectively receive clock signals of the sub-clock signal lines CLK1-CLK8, and output gate signals to a plurality of rows of sub-pixels from a plurality of first outputs GOUT in response to the clock signals. For example, as shown in Figure 3 As shown, the clock signal end CLK1 of the first stage shift register unit and the sub clock signal line CLK1 are connected; the clock signal end CLK2 of the second stage shift register unit and the sub clock signal line CLK2 are connected; the clock signal end CLK3 of the third stage shift register unit and the sub clock signal line CLK3 are connected; the clock signal end CLK4 of the fourth stage shift register unit and the sub clock signal line CLK4 are connected; the clock signal end CLK5 of the fifth stage shift register unit and the sub clock signal line CLK5 are connected; the clock signal end CLK6 of the sixth stage shift register unit and the sub clock signal line CLK6 are connected; the clock signal end CLK7 of the seventh stage shift register unit and the sub clock signal line CLK2 are connected; the clock signal end CLK8 of the eighth stage shift register unit and the sub clock signal line CLK2 are connected; and the clock signal end CLK9 of the ninth stage shift register unit and the sub clock signal line CLK1 are connected. Embodiments of the present disclosure do not limit the specific structure of the shift register unit, Figure 3 The schematic diagram illustrates double-side driving, that is, the same row of pixels is driven by the gate driving circuit at the left and right ends. Of course, it can also be single-side driving, for example, only the gate driving circuit at one side of the non-display area is reserved. It can also be double-side odd-even driving, for example, the gate driving circuit at one side drives odd-numbered rows of pixels, and the gate driving circuit at the other side drives even-numbered rows of pixels. Here, no limitation is made.

[0125] As Figure 3 shown, the gate driving circuit 10 and the gate driving circuit 30 can further respectively include a signal source 11 and a signal source 31. The signal source 11 is configured to provide the above-mentioned various signals to the shift register units of the gate driving circuit 10, for example. The signal source 31 is configured to provide the above-mentioned various signals to the shift register units of the gate driving circuit 30, for example. It should be noted that the phase relationship between the multiple clock signals provided by the signal source 11 and the signal source 31 can be determined according to actual needs. In different examples, more clock signals can also be provided according to different configurations. Since the gate driving circuit 10 and the gate driving circuit 30 are similar, the embodiments of the present disclosure will be described below by taking the gate driving circuit 10 and the signal source 11 as an example.

[0126] For example, the signal source 11 provides clock signals to each shift register unit through the sub clock signal lines CLK1 to CLK8, so that each shift register unit outputs a gate signal. For example, each shift register unit outputs the gate signal CK1~CK8 of the example in the middle. Figure 1A In fact, the clock signals provided by the sub clock signal lines CLK1 to CLK8 are the same signals as the gate signals CK1~CK8.

[0127] When the clock signal end CLKi of the kth stage shift register unit receives the sub-clock signal (one of CLK1-CLK8) as high level, the gate signal output by the first output end GOUT of the kth stage shift register unit is in the open state.

[0128] Since the above-mentioned sub-clock signals CLK1-CLK8 are adjacent in time sequence, Figure 3 The time sequence of the gate signals output by the eight shift register units shown in FIG. 8 is as follows: the gate signal output by the first output end GOUT of the first stage shift register unit—> the gate signal output by the first output end GOUT of the second stage shift register unit—> the gate signal output by the first output end GOUT of the third stage shift register unit—> the gate signal output by the first output end GOUT of the fourth stage shift register unit—> the gate signal output by the first output end GOUT of the fifth stage shift register unit—> the gate signal output by the first output end GOUT of the sixth stage shift register unit—> the gate signal output by the first output end GOUT of the seventh stage shift register unit—> the gate signal output by the first output end GOUT of the eighth stage shift register unit, Figure 3 As shown in FIG. 9, the gate driving circuit includes two output ends, the GOUT output end is used to output the gate driving signal to the corresponding row of pixels, and the GOUT_C is used to transmit the cascade signal. For example, the GOUT_C of the first stage shift register unit provides an input signal for the fifth stage shift register unit. The gate driving circuit can also be provided with only the GOUT output end, that is, the GOUT is used as the output signal of the current row and also as the input signal of the cascade of other rows, which is not limited here.

[0129] Since the plurality of sub-pixels are arranged into multiple rows from far to near, the distance from the receiving end of the gate signal of each row of sub-pixels to the signal source 11 is different, and thus the length of the connection line required by each row of sub-pixels is different. Here, the different lengths of the connection lines refer to different circuit transmission paths for transmitting the CLK signal for displaying each row of pixels from the signal source end. The connection line is used to connect the signal source of the gate signal and the receiving end of the corresponding gate line of each row of sub-pixels. For example, Figure 3 As shown, the connection line refers to the wire between the signal source 11 and the receiving end of the gate line corresponding to each row of sub-pixels. The signal source can refer to a timing controller IC. For example, the timing controller IC is connected to the CLK line of the display panel through the level-shifter and the flexible circuit board, for example, the display panel is bound by the COF (chip on film) method, that is, the source IC is bound to the FPC flexible circuit board, one end of the flexible circuit board is bound to the non-display area of the display panel, the other end of the flexible circuit board is bound to the PCB circuit board, and the timing controller IC (TCON-IC) is arranged on the PCB circuit board. The clock signal output by the timing controller IC passes through the level-shifter and the signal line on the flexible circuit board and is transmitted to the CLK signal line of the display panel. Optionally, the connection between the signal line of the flexible circuit board and the CLK signal line of the display panel can be realized by electrical connection through respective binding terminals, that is, the pad of the display panel and the gold finger of the flexible circuit board. Of course, the present application also includes the COG (chip on glass) method, that is, the source IC is directly bound to the non-display area of the display panel, which is not limited herein. The wire includes the sub-clock signal line between the signal source 11 and each level of the shift register unit and the wire between each level of the shift register unit and the receiving end of the corresponding connected gate line. Since the lengths of the multiple wires between each level of the shift register unit and the receiving end of the corresponding connected gate line are not much different, the difference in the distance from the receiving end of the gate signal of each row of sub-pixels to the signal source 11 mainly reflects the different lengths of the multiple sub-clock signal lines (that is, the sub-clock signal line CLK1 to the sub-clock signal line CLK8). It should be noted that the different lengths herein refer to the different distances of the transmitted signals in electricity, Figure 3 The physical lengths of CLK1-CLK8 clock signal lines are shown to be different. Of course, the physical lengths of CLK1-CLK8 clock signal lines can also be the same in design. However, the electrical transmission path of the CLK1 signal corresponding to the first row of pixels from the signal source is to the position of the black node in the drawing, and the electrical transmission path of the CLK8 signal corresponding to the eighth row of pixels is to the position of the black node in the drawing. It can be seen that the electrical transmission path of the CLK signal of the first row of pixels is longer than that of the CLK signal of the eighth row of pixels.

[0130] For example, the signal source 11 is located at the lower left corner of the display panel 200, and the sub-clock signal lines CLK1 to CLK8 corresponding to the PI<1> row of sub-pixels to the PI<8> row of sub-pixels are getting shorter and shorter, that is, the connection lines between the PI<1> row of sub-pixels to the PI<8> row of sub-pixels and the signal source 11 are getting shorter and shorter. For example, the sub-clock signal line CLK7 required by the seventh row of sub-pixels is longer than the sub-clock signal line CLK8 required by the eighth row of sub-pixels.

[0131] Because the length of the sub-clock signal line required for each row of sub-pixels is different, the gate signal received by each row of sub-pixels has a different delay on the sub-clock signal line.

[0132] Figure 4 At least one embodiment of the present disclosure is shown. Figure 3 The timing diagram shown is of the gate signals received by each row of sub-pixels in the display panel.

[0133] like Figure 4 As shown, since the sub-clock signal line CLK1 corresponding to the first row of sub-pixels becomes shorter and shorter to the sub-clock signal line CLK8 corresponding to the eighth row of sub-pixels, the delay between the gate signal CK1 received by the first row of sub-pixels and the gate signal CK8 received by the eighth row of sub-pixels becomes smaller and smaller. Therefore, the duration of the rising edge of CK1 to CK8 becomes shorter and shorter, that is, the duration of the rising edge of the gate signal received by the first row of sub-pixels to the eighth row of sub-pixels becomes shorter and shorter.

[0134] In some embodiments of this disclosure, for example, due to PI <1> row sub-pixel to PI <n>The connecting lines of the row of sub-pixels are getting shorter, and thus, the PI<1> row of sub-pixels to the PI<1+1> row of sub-pixels are connected by a connecting line of a length of 1 pixel. <n>the delay of the gate signal of the PI<1>th row sub-pixel is shorter than that of the PI<1>th row sub-pixel (i.e., the time length required for the rising edge and the falling edge is shorter), so the PI<1>th row sub-pixel to the PI <n>The time required for switching the gate signal of each row of sub-pixels from the on state to the off state is shorter and shorter, so the first time length for switching of each row of sub-pixels is also shorter and shorter.

[0135] For example, the connection line corresponding to the PI<1> row of sub-pixels is longer than the connection line corresponding to the PI<2> row of sub-pixels, so the first time length for switching of the PI<1> row of sub-pixels is longer than the first time length for switching of the PI<2> row of sub-pixels.

[0136] In this way, the appropriate first time length can be set for each row of sub-pixels, which not only alleviates the pixel charging error, but also improves the display efficiency.

[0137] Figure 5 A flowchart of another driving method provided by at least one embodiment of the present disclosure is shown.

[0138] As shown in Figure 5 In addition to steps S10 and S20, the driving method can also include steps S30 and S40. Steps S30 and S40 can be performed before steps S10 and S20, for example.

[0139] Step S30: Determine the first time length corresponding to the longest connection line in the plurality of connection lines of the plurality of first row of sub-pixels.

[0140] Step S40: According to the first time length corresponding to the longest connection line, determine the first time length corresponding to the other connection lines in the plurality of connection lines except the longest connection line.

[0141] This method can reduce the time for determining the first time length corresponding to each row of sub-pixels, and improve the efficiency of determining the first time length.

[0142] For step S30, the first time length corresponding to the longest connection line can be the first time length corresponding to the row of sub-pixels farthest from the signal source. For example, in Figure 1A the example shown, the PI<1> row of sub-pixels is the row of sub-pixels farthest from the signal source, so in step S30, the first time length corresponding to the PI<1> row of sub-pixels can be determined.

[0143] For example, the first time length corresponding to the longest connection line is determined according to the method of displaying the black and white checkerboard pattern described above.

[0144] For step S40, for example, according to the first time length corresponding to the PI<1> row of sub-pixels, the first time length corresponding to the PI<2> row of sub-pixels, …, the first time length corresponding to the PI <n>The first time length of each row of sub-pixels.

[0145] In some embodiments of the present disclosure, for example, a person skilled in the art can determine the difference value of the first time length between two adjacent rows according to experience, and then the first time length corresponding to each row of sub-pixels is sequentially reduced by the difference value.

[0146] In some other embodiments of the present disclosure, the first time length corresponding to the shortest connection line can also be determined, and the difference value of the first time length between two adjacent rows is determined according to the first time length corresponding to the shortest connection line and the first time length corresponding to the longest connection line.

[0147] As shown in FIG. 5, in addition to steps S10-S40, the driving method can also include step S50. Step S50 can be performed before step S3, for example. Figure 5

[0148] Step S50: dividing the pixel array into a plurality of regions, each region including a plurality of continuous rows of sub-pixels.

[0149] In this embodiment, step S30 includes determining a far-end region farthest from the signal source of the gate signal from the plurality of regions, and determining the first time length corresponding to the longest connection line based on the connection lines corresponding to the plurality of first rows of sub-pixels in the far-end region.

[0150] In this embodiment, step S40 includes determining one first time length for the plurality of rows of sub-pixels in each region according to the first time length corresponding to the longest connection line.

[0151] In this embodiment, the first time length corresponding to the plurality of rows of sub-pixels in each region can be the same.

[0152] This embodiment divides the pixel array into a plurality of regions, and determines the first time length for each region respectively, thereby improving the calculation efficiency.

[0153] In some embodiments of the present disclosure, the number of rows of sub-pixels in each region can or can not be the same.

[0154] The plurality of regions of the pixel array can be divided by a person skilled in the art according to the circuit traces in the display panel. For example, a plurality of rows of sub-pixels with little difference in delay of the gate signal are divided into one region.

[0155] For example, the pixel array includes PI<1> rows of sub-pixels, PI<2> rows of sub-pixels, …, PI <n>There are N (N > 50) rows of row sub-pixels, and PI<1> row sub-pixels, PI<2> row sub-pixels, …, PI <n>The receiving end of the gate line of the row of sub-pixels is closer and closer to the signal source. Every 50 rows of sub-pixels are taken as a region, and the far end region farthest from the signal source of the gate signal is the region where PI<1>, PI<2>, …, PI<50> are located.

[0156] In some embodiments of the present disclosure, the step S30 described above of determining the first time length corresponding to the longest connection line based on the connection lines corresponding to the plurality of first rows of sub-pixels in the far end region comprises: taking the first time length corresponding to the first row of sub-pixels farthest from the signal source in the far end region as the first time length corresponding to the longest connection line.

[0157] For example, the PI<1> row of sub-pixels is farthest from the signal source, and the first time length corresponding to the PI<1> row of sub-pixels is taken as the first time length corresponding to the longest connection line.

[0158] In some embodiments of the present disclosure, the step S30 described above of determining the first time length corresponding to the longest connection line based on the connection lines corresponding to the plurality of first rows of sub-pixels in the far end region comprises: taking the first time length corresponding to the first row of sub-pixels farthest from the signal source in the far end region as the first time length corresponding to the longest connection line. PI<1> PI<2> PI<50> PI<1> PI<2> PI<50> respectively represent the first time lengths corresponding to PI<1>, PI<2>, …, PI<50> respectively.

[0159] In some embodiments of the present disclosure, the step S40 described above of determining a first time length for a plurality of rows of sub-pixels in each region according to the first time length corresponding to the longest connection line comprises: determining the difference between the first time lengths in adjacent regions, and determining a first time length for a plurality of rows of sub-pixels in each region according to the difference.

[0160] For example, the difference between the first time lengths of the adjacent two regions can be determined by the person skilled in the art according to experience, and the first time length corresponding to each region is determined according to the difference and the first time length corresponding to the longest connection line. The first time lengths corresponding to the plurality of rows of sub-pixels in each region are the same.

[0161] In some other embodiments of the present disclosure, the first time length corresponding to the region closest to the signal source can also be determined, and the difference between the first time lengths of the adjacent two regions is determined according to the first time length corresponding to the region closest to the signal source and the first time length corresponding to the longest connection line. ​​​​​

[0162] Another aspect of the present disclosure provides a display panel, the display panel comprising a pixel array formed by a plurality of rows and a plurality of columns of sub-pixels, a plurality of gate lines and a plurality of data lines intersecting to define the plurality of rows and the plurality of columns of sub-pixels, a data line to which a sub-pixel is electrically connected being electrically connected to a data signal terminal through a switch module, the switch module receiving a selection control signal to switch a connection state of the data line and the data signal terminal. The plurality of rows of sub-pixels comprises a first row of sub-pixels and a second row of sub-pixels adjacent to the first row of sub-pixels, the first row of sub-pixels and the second row of sub-pixels respectively receiving a gate signal of a corresponding gate line, the gate signal comprising an on state and an off state. During application of the gate signal to the second row of sub-pixels to control the second row of sub-pixels, and after a first time length during which the gate signal received by the first row of sub-pixels switches from the on state to the off state, the switch module of the second row of sub-pixels receives the selection control signal to control the switch module of the second row of sub-pixels to switch the connection state.

[0163] The display panel may, for example, be Figure 1A Alternatively Figure 3 The examples shown are described in relation to the above description of Figure 1A Alternatively Figure 3 .

[0164] In some embodiments of the present disclosure, each row of sub-pixels is divided into a plurality of sub-pixel groups, a plurality of data lines electrically connected to a plurality of sub-pixels in each sub-pixel group are respectively electrically connected to one data signal terminal through a switch module, each switch module corresponding to a sub-pixel comprises a plurality of switch elements, the selection control signal comprises a plurality of selection control signals, and the plurality of switch elements respectively receive the plurality of selection control signals to switch the connection state of the plurality of data lines electrically connected to the plurality of switch elements and the data signal terminal.

[0165] In some embodiments of the present disclosure, each sub-pixel group comprises a first sub-pixel and a second sub-pixel, a data line connected to the first sub-pixel is connected to the data signal terminal through a first switch element, a data line connected to the second sub-pixel is connected to the data signal terminal through a second switch element, the plurality of selection control signals comprises a first selection control signal and a second selection control signal, and during reception of the gate signal by the second row of sub-pixels, the first switch element and the second switch element corresponding to each sub-pixel group in the second row of sub-pixels are sequentially turned on in response to the first selection control signal and the second selection control signal, respectively.

[0166] In some embodiments of the present disclosure, the first switch element switches from being turned on to being turned off, and the second switch element is turned on, with a second time length, the second time length being greater than 0.

[0167] In some embodiments of the present disclosure, the display panel comprises a non-display area and a display area, the pixel array is located in the display area, and the non-display area comprises a signal source of the gate signal.

[0168] As Figure 3 shown, the display panel 200 includes a non-display area PR and a display area DR. The pixel array is located in the display area DR, and the non-display area PR includes the signal source 11 and the signal source 31 of the gate signal.

[0169] Another aspect of the present disclosure provides a driving device of a pixel array, the pixel array including a plurality of rows and columns of sub-pixels, a plurality of gate lines and a plurality of data lines intersecting to define the plurality of rows and columns of sub-pixels. The data line to which the sub-pixel is electrically connected is electrically connected to a data signal terminal through a switch module, the switch module receiving a selection control signal to switch the connection state of the data line and the data signal terminal, and the plurality of rows of sub-pixels include adjacent first and second rows of sub-pixels. The pixel array can refer to Figure 1A the pixel array in the display panel 100 shown.

[0170] Figure 6 A block diagram of the driving device 600 according to at least one embodiment of the present disclosure is shown.

[0171] As Figure 6 shown, the driving device 600 can include a gate drive circuit 601, a control circuit 602, and a data drive circuit 603.

[0172] As Figure 6 shown, the driving device 600 can be connected to a pixel array 610, which can be, for example, the pixel array shown in Figure 1A .

[0173] The gate drive circuit 601 is configured to apply a gate signal to the gate line corresponding to the first and second rows of sub-pixels, respectively, the gate signal including an on state and an off state. For example, the gate drive circuit can be the gate drive circuit 10 and the gate drive circuit 30 in Figure 3 , and the description of the gate drive circuit can refer to the related description of the gate drive circuit 10 and the gate drive circuit 30.

[0174] The control circuit 602 is configured to apply a selection control signal to the second row of sub-pixels, and the selection control signal corresponding to the second row of sub-pixels controls the switch module to switch the connection state after a first time length during which the gate signal applied to the first row of sub-pixels switches from the on state to the off state. The first time length is greater than 0.

[0175] The data drive circuit 603 includes a data signal terminal configured to provide a data signal to the data line connected to the data signal terminal. It should be understood that Figure 6 the number of connection lines in Figure 6 The connection relationship between the driving device 600 and the pixel array 610 is only schematically represented, and does not limit the present disclosure.

[0176] The following points need to be explained:

[0177] (1) The drawings of the embodiments of the present disclosure only relate to the structures involved in the embodiments of the present disclosure, and other structures can be referred to the general design.

[0178] (2) In the case of no conflict, the embodiments of the present disclosure and the features in the embodiments can be combined with each other to obtain new embodiments.

[0179] The above is only a specific implementation of the present disclosure, but the protection scope of the present disclosure is not limited thereto, and the protection scope of the present disclosure should be subject to the protection scope of the claims.< / n> < / n> ​< / n> < / n> < / n> < / n> < / n>

Claims

1. A method of driving a pixel array, wherein, The pixel array includes a plurality of rows and columns of sub-pixels, a plurality of gate lines and a plurality of data lines intersecting to define the plurality of rows and columns of the sub-pixels, The data line to which the sub-pixel is electrically connected is electrically connected to a data signal terminal through a switch module, and the switch module receives a selection control signal to switch the connection state of the data line and the data signal terminal, The plurality of rows of sub-pixels includes adjacent first and second rows of sub-pixels, The method includes: Applying a gate signal to the gate line corresponding to the first and second rows of sub-pixels, the gate signal including an on state and an off state; During the application of the gate signal to the second row of sub-pixels to control the second row of sub-pixels, the selection control signal corresponding to the second row of sub-pixels controls the switch module to switch the connection state after a first time length in which the gate signal applied to the first row of sub-pixels switches from the on state to the off state, wherein the first time length is greater than 0, wherein each row of sub-pixels is divided into a plurality of sub-pixel groups, and a plurality of data lines electrically connected to a plurality of sub-pixels in each sub-pixel group are respectively electrically connected to a data signal terminal through a switch module, and each sub-pixel corresponds to a switch module including a plurality of switch elements, The selection control signal includes a plurality of selection control signals, The plurality of switch elements respectively receive the plurality of selection control signals to switch the connection state of the plurality of data lines connected to the plurality of switch elements and the data signal terminal, Each sub-pixel group includes a first sub-pixel and a second sub-pixel, and the data line connected to the first sub-pixel is connected to the data signal terminal through a first switch element, and the data line connected to the second sub-pixel is connected to the data signal terminal through a second switch element, The plurality of selection control signals includes a first selection control signal and a second selection control signal; During the application of the gate signal to the second row of sub-pixels to control the second row of sub-pixels, the first and second switch elements corresponding to each sub-pixel group in the second row of sub-pixels are respectively applied with the first and second selection control signals to make the first and second switch elements conductive, The first selection control signal controls the first switch element to switch from conduction to disconnection, and the second selection control signal controls the second switch element to be conductive, and the second time length between the two is greater than 0.

2. The method of claim 1, wherein, Two sub-pixels in each row of sub-pixels separated by one column serve as the first and second sub-pixels to form a sub-pixel group.

3. The method of claim 1, wherein, The ratio of the first time length to the second time length is in the range [0.8, 3.0].

4. The method of claim 1, wherein, The second time length is determined according to the time length required for the data signal terminal to switch from a first data signal to a second data signal, the time length required for the first switch element to switch from conduction to disconnection, and the time length required for the second switch element to switch from disconnection to conduction.

5. The method of claim 1, wherein, Each sub-pixel group includes N sub-pixels, and N is an integer greater than or equal to 2, The gate signal is a periodic signal, and in a third time length during which the gate signal is in the on state in each period, a selection control signal corresponding to the second row of sub-pixels controls the switch module to switch the connection state, The calculation formula of the pulse width of the selection control signal is: W=(T3-T1-(N-1)×T2) / N Wherein, W represents the pulse width, T3 represents the third time length, T1 represents the first time length, and T2 represents the second time length.

6. The method of claim 5, wherein, The ratio between the third time length T3 and the first time length T1 is in the range of [1.0, 5.0].

7. The method of claim 5, wherein, The ratio between the second time length T2 and the pulse width is in the range of [0.3, 2.0].

8. The method of claim 5, wherein, The ratio between the first time length T1 and the pulse width is in the range of [0.7, 3.0].

9. The method of claim 1, wherein, The first time length is positively correlated with the length of the connection line of the first row of sub-pixels, and the connection line is used to connect the signal source of the gate signal and the receiving end of the gate line corresponding to each row of sub-pixels.

10. The method of claim 9, further comprising: determining the first time length corresponding to the longest connection line among multiple connection lines of multiple first rows of sub-pixels; determining the first time length corresponding to other connection lines except the longest connection line among the multiple connection lines according to the first time length corresponding to the longest connection line.

11. The method of claim 10, further comprising: dividing the pixel array into multiple regions, each region including multiple consecutive rows of sub-pixels; determining the first time length corresponding to the longest connection line among multiple connection lines of multiple first rows of sub-pixels, comprising: determining a far-end region farthest from the signal source of the gate signal from the multiple regions; determining the first time length corresponding to the longest connection line based on the connection lines corresponding to multiple first rows of sub-pixels in the far-end region; determining the first time length corresponding to other connection lines except the longest connection line among the multiple connection lines according to the first time length corresponding to the longest connection line, comprising: determining one first time length for multiple rows of sub-pixels in each region according to the first time length corresponding to the longest connection line.

12. A display panel, wherein, The display panel includes a pixel array formed by multiple rows and multiple columns of sub-pixels, multiple gate lines and multiple data lines intersecting to define multiple rows and multiple columns of the sub-pixels, a data line to which the sub-pixel is electrically connected is electrically connected to a data signal end through a switch module, and the switch module receives a selection control signal to switch the connection state of the data line and the data signal end, The multiple rows of sub-pixels include adjacent first and second rows of sub-pixels, The first and second rows of sub-pixels respectively receive a gate signal of a corresponding gate line, and the gate signal includes an on state and an off state; The switch module of the second row of sub-pixels receives a selection control signal to control the switch module of the second row of sub-pixels to switch the connection state after a first time length from when the gate signal is received by the first row of sub-pixels to when the gate signal switches from the open state to the closed state, wherein each row of sub-pixels is divided into a plurality of sub-pixel groups, and a plurality of data lines electrically connected to the plurality of sub-pixels in each sub-pixel group are electrically connected to a data signal terminal through a switch module, and each sub-pixel corresponds to a switch module including a plurality of switch elements, the selection control signal includes a plurality of selection control signals, the plurality of switch elements respectively receive the plurality of selection control signals to switch the connection state between the plurality of data lines connected to the plurality of switch elements and the data signal terminal, each sub-pixel group includes a first sub-pixel and a second sub-pixel, the data line connected to the first sub-pixel is connected to the data signal terminal through a first switch element, and the data line connected to the second sub-pixel is connected to the data signal terminal through a second switch element, the plurality of selection control signals include a first selection control signal and a second selection control signal; during the period when the second row of sub-pixels receives the gate signal, the first switch element and the second switch element corresponding to each sub-pixel group in the second row of sub-pixels are turned on in response to the first selection control signal and the second selection control signal, respectively, the first switch element switches from being turned on to being turned off with a second time length between the first switch element being turned on and the second switch element being turned on, and the second time length is greater than 0.

13. The display panel of claim 12, wherein, The display panel includes a non-display area and a display area, the pixel array is located in the display area, and the non-display area includes a signal source of the gate signal.

14. An apparatus for driving a pixel array, wherein, The pixel array includes a plurality of rows and a plurality of columns of sub-pixels, a plurality of gate lines and a plurality of data lines intersecting to define a plurality of rows and a plurality of columns of the sub-pixels, the data line electrically connected to the sub-pixel is electrically connected to a data signal terminal through a switch module, and the switch module receives a selection control signal to switch the connection state between the data line and the data signal terminal, the plurality of rows of sub-pixels include adjacent first and second rows of sub-pixels, the driving device includes: a gate driving circuit configured to apply a gate signal to the gate lines corresponding to the first and second rows of sub-pixels, respectively, the gate signal including an open state and a closed state; a control circuit configured to apply a selection control signal to the second row of sub-pixels, wherein during the period when the gate signal is applied to the second row of sub-pixels to control the second row of sub-pixels, the selection control signal corresponding to the second row of sub-pixels controls the switch module to switch the connection state after a first time length from when the gate signal applied to the first row of sub-pixels switches from the open state to the closed state, a data driving circuit including the data signal terminal and configured to provide a data signal to the data line connected to the data signal terminal; wherein the first time length is greater than 0, Each row of sub-pixels is divided into a plurality of sub-pixel groups, a plurality of data lines electrically connected with a plurality of sub-pixels in each sub-pixel group are electrically connected with a data signal terminal through a switch module respectively, each switch module corresponding to a sub-pixel includes a plurality of switch elements, The selection control signals include a plurality of selection control signals, The plurality of switch elements respectively receive the plurality of selection control signals to switch the connection state between the plurality of data lines and the data signal terminal corresponding to the plurality of switch elements, Each sub-pixel group includes a first sub-pixel and a second sub-pixel, the data line connected with the first sub-pixel is connected with the data signal terminal through a first switch element, and the data line connected with the second sub-pixel is connected with the data signal terminal through a second switch element, The plurality of selection control signals include a first selection control signal and a second selection control signal; During the period when the second row of sub-pixels receives the gate signal, the first switch element and the second switch element corresponding to each sub-pixel group in the second row of sub-pixels are turned on in response to the first selection control signal and the second selection control signal respectively, The first switch element is switched from being turned on to being turned off with a second time length between the turning on and the turning off of the second switch element, and the second time length is greater than 0.

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