Semiconductor device scm sample preparation method
By removing the metal layer and setting conductive pads, the problems of weak signal and blurred boundaries in SCM sample preparation were solved, enabling clear junction morphology analysis and supporting failure analysis of semiconductor devices.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- CSMC TECH FAB2 CO LTD
- Filing Date
- 2022-03-03
- Publication Date
- 2026-05-15
AI Technical Summary
In existing technologies, the weak signal and blurred boundaries caused by SCM sample preparation methods affect the failure analysis results of semiconductor devices.
By removing the metal layer from the surface of the device sample and placing a non-metallic conductive pad on the front side, followed by side polishing to the region of interest, stable electrical connections are ensured and metal contamination is avoided.
It improves the capacitance signal strength during SCM testing, provides clearer junction morphology and contour boundaries, facilitates failure analysis, and optimizes manufacturing processes.
Smart Images
Figure CN116735296B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of semiconductor manufacturing, and in particular to a method for preparing SCM samples for semiconductor devices. Background Technology
[0002] The statements herein are provided only as background information in connection with this application and do not necessarily constitute prior art.
[0003] Scanning capacitance microscopy (SCM) is an atomic force microscopy (AFM) imaging technique for characterizing the nano-electrical properties of materials. It can be used to measure the type and level of micro-doping in semiconductor materials.
[0004] For semiconductor device failure analysis, which involves observing the micro-junction morphology, SCM is a very useful tool. However, sample preparation is one of the challenges in SCM analysis. Samples prepared using exemplary SCM sample preparation methods often exhibit weak signals and blurred boundaries during SCM testing, resulting in poor performance. Summary of the Invention
[0005] Therefore, it is necessary to provide a method for preparing SCM samples of semiconductor devices with strong SCM signals and clear junction morphology boundaries during SCM testing.
[0006] A method for preparing a semiconductor CM sample includes: removing a metal layer from the surface of a device sample; after the metal layer is removed, placing a pad that is fixedly connected to the device sample on the front side; the pad is made of a non-metallic material and includes a conductive material; and polishing the device sample with the pad attached from the side to the region of interest to obtain the SCM sample.
[0007] The above-mentioned method for preparing SCM samples of semiconductor devices removes the metal layer on the surface of the device sample before polishing, which can avoid the contamination of the metal layer by metal impurities during the polishing process and improve the capacitance signal strength. Therefore, the obtained SCM sample has a strong SCM signal and clear junction morphology contour boundary during SCM testing.
[0008] In one embodiment, the step of providing a gasket fixedly connected to the front side of the device sample includes bonding the gasket to the front side of the device sample with an adhesive, the adhesive including epoxy resin.
[0009] In one embodiment, the step of removing the metal layer from the surface of the device sample includes removing the metal layers from the front and back sides of the device sample.
[0010] In one embodiment, the step of removing the metal layer from the surface of the device sample includes removing the metal layer by means of an acid solution.
[0011] In one embodiment, the acid solution is aqua regia.
[0012] In one embodiment, the step of performing SCM testing on the SCM sample is also included.
[0013] In one embodiment, before the step of performing SCM testing on the SCM sample and after the step of polishing the device sample with the gasket attached from the side to the region of interest, the method further includes a step of wrapping the device sample and the gasket with conductive tape.
[0014] In one embodiment, the step of wrapping the device sample and the pad with conductive tape refers to wrapping the device sample with a back surface area less than or equal to a first threshold with conductive tape, while the device sample with a back surface area greater than the first threshold is not wrapped with conductive tape.
[0015] In one embodiment, the conductive tape includes a copper tape.
[0016] In one embodiment, a second device sample is used instead of the gasket, i.e., the step of removing the metal layer on the surface of the device sample includes removing the metal layer on the surfaces of the first device sample and the second device sample; the first device sample and the second device sample are samples of the same device; the step of setting a gasket fixedly connected to the device sample on the front side of the device sample includes connecting the front side of the first device sample and the front side of the second device sample face to face.
[0017] In one embodiment, the step of connecting the front side of the first device sample to the front side of the second device sample face to face involves curing the front side of the first device sample to the front side of the second device sample face to face using an adhesive; the adhesive includes epoxy resin.
[0018] In one embodiment, the device sample is a SiC substrate device sample. Attached Figure Description
[0019] To more clearly illustrate the technical solutions in the embodiments of this application or the conventional technology, the drawings used in the description of the embodiments or the conventional technology will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0020] Figure 1 This is a flowchart of a method for preparing a semiconductor device using a microprocessor (SCM).
[0021] Figure 2aThis is a schematic cross-sectional view of a SiC substrate device sample in one embodiment. Figure 2b yes Figure 2a The diagram shown is a cross-sectional view of the device sample after the front and back metals have been removed. Figure 2c yes Figure 2b The diagram shows a cross-sectional view of the device sample after the gasket has been cured on the front side.
[0022] Figure 3 It is a test image obtained by performing SCM testing on a pair of proportional SCM samples;
[0023] Figure 4 This is a test image obtained by performing SCM testing on an SCM sample prepared in one embodiment;
[0024] Figure 5 This is a flowchart of a semiconductor device SCM sample preparation method in another embodiment;
[0025] Figure 6a This is a schematic diagram of a large core sample being cured on a gasket in one embodiment. Figure 6b This is a schematic diagram of a small core sample solidified on a gasket in one embodiment. Figure 6c This is a schematic diagram of one embodiment where a small core sample and a gasket are wrapped with conductive tape;
[0026] Figure 7 This is a flowchart of a method for preparing SCM samples of a semiconductor device in yet another embodiment;
[0027] Figure 8 This is a schematic diagram of a sample structure formed by curing the front sides of the first device sample face to face in one embodiment. Detailed Implementation
[0028] To facilitate understanding of the present invention, a more complete description will be given below with reference to the accompanying drawings. Preferred embodiments of the invention are shown in the drawings. However, the invention can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.
[0029] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. The terminology used herein in the description of the invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.
[0030] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this invention, the first element, component, area, layer, or portion discussed below may be referred to as the second element, component, area, layer, or portion.
[0031] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below” or “under” the other element or feature will be oriented “above” the other element or feature. Therefore, the exemplary terms “below” and “under” can include both upper and lower orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.
[0032] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the invention. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising” and / or “including,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.
[0033] Embodiments of the invention are described herein with reference to cross-sectional views that serve as schematic diagrams of ideal embodiments (and intermediate structures). Thus, variations in the shape shown can be anticipated due to, for example, manufacturing techniques and / or tolerances. Therefore, embodiments of the invention should not be limited to the specific shapes of the regions shown herein, but include shape deviations due to, for example, manufacturing processes. For example, implantation regions shown as rectangular typically have rounded or curved features at their edges and / or implantation concentration gradients, rather than a binary change from implantation regions to non-implantation regions. Similarly, the buried regions formed by implantation can result in some implantation in the region between the buried region and the surface traversed during implantation. Therefore, the regions shown in the figures are substantially schematic, and their shapes are not intended to show the actual shapes of the regions of the device and are not intended to limit the scope of the invention.
[0034] The semiconductor terminology used in this article is the technical terminology commonly used by those skilled in the art. For example, for P-type and N-type impurities, in order to distinguish the doping concentration, P+ type represents heavily doped P-type, P type represents moderately doped P-type, P- type represents lightly doped P-type, N+ type represents heavily doped N-type, N type represents moderately doped N-type, and N- type represents lightly doped N-type.
[0035] Compared to conventional Si substrates, SiC substrates exhibit unique material property changes. Among the most significant are SiC's high hardness and high thermal conductivity. This makes semiconductor device failure analysis, including the observation of micro-junction morphology, primarily reliant on surface-mount microstructure (SCM) analysis. The effectiveness of SCM analysis of the cross-sectional junction morphology of SiC devices is highly dependent on the sample preparation level. An exemplary SCM sample preparation method for SiC devices or Si devices is as follows:
[0036] 1. For samples with a large area, directly cleave them and grind and polish the cross-sections to the region of interest.
[0037] 2. For small die (DIE) samples, epoxy resin and gaskets are used to cover and protect them, forming a sandwich-like structure (both the front and back of the device are covered and protected by gaskets, and epoxy resin is used as an adhesive). Then, the die is split and the cross-section is ground and polished to the region of interest.
[0038] However, the SCM samples prepared by the above methods have weak signals and blurred boundaries during SCM testing, resulting in poor performance. This application proposes a method for preparing SCM samples for semiconductor devices, which can significantly improve the analysis effect of SCM cross-sectional junction morphology, making it easier for semiconductor device manufacturing plants to find the cause of failure and optimize the manufacturing process.
[0039] Figure 1 This is a flowchart of a method for preparing a semiconductor device SCM sample in one embodiment, including the following steps:
[0040] S110, removes the metal layer from the surface of the device sample.
[0041] In one embodiment of this application, the metal layer on the surface of the device sample is removed by acid solution. Figure 2a This is an example of a SiC substrate device sample, in which the front side of the device sample (i.e., Figure 2a The top side and the back side (i.e., the middle side) Figure 2a The device sample includes a metal layer on the front side (facing down), a dielectric layer 220, a substrate 230, and a back side metal layer 240. Figure 2a The structure of the device is partially omitted and will not be described here. The structure of the device sample after removing the front metal layer 210 and the back metal layer 240 is as follows: Figure 2b As shown. For a device sample with a metal layer on only one side (e.g., the front side of the device), the metal layer on only one side is removed in step S110.
[0042] Furthermore, the acid used to remove the metal layer should be an acid with a high etching selectivity—that is, a high etching selectivity for both the metal layer and the film layer in direct contact with the metal layer (e.g., dielectric layer, substrate, etc.). In one embodiment of this application, the acid used to remove the metal layer is aqua regia.
[0043] S120, a gasket is provided on the front of the device sample to be fixedly connected to the device sample.
[0044] The gasket should be made of non-metallic material to avoid contamination from metal debris during subsequent polishing. Furthermore, the gasket should be conductive, allowing for electrical connection between the device sample and the SCM testing equipment base. Additionally, the side of the gasket facing away from the device sample should have a flat surface. This ensures stable micro-contact between the AFM microprobe and the gasket during SCM testing, and the gasket also prevents large edge drops in the sample, resulting in a good SCM signal. In one embodiment of this application, the gasket 260 is cured onto the front side of the device sample using adhesive 250. See [link to relevant documentation]. Figure 2c In one embodiment of this application, the adhesive 250 is made of epoxy resin.
[0045] S130, polish the device sample from the side to the region of interest.
[0046] Polishing refers to a processing method that uses mechanical, chemical, or electrochemical actions to reduce the surface roughness of a workpiece, thereby obtaining a bright and smooth surface. In one embodiment of this application, polishing cloths known in the art are used for polishing. Polishing can achieve an ideal smooth and clean surface state, and is less susceptible to interference from foreign impurities compared to dicing or ion milling. In one embodiment of this application, the region of interest includes the PN junction structure of the device. In other embodiments, the region of interest may also be other structures in the semiconductor device that a tester wants to test.
[0047] After step S130 is completed, the obtained SCM sample can be subjected to SCM testing.
[0048] The aforementioned method for preparing SCM samples of semiconductor devices removes the metal layer from the sample surface before polishing. This avoids metal impurities from the metal layer during polishing, improving the capacitance signal strength. Consequently, the resulting SCM sample exhibits a stronger SCM signal and clearer junction morphology boundaries during SCM testing, facilitating clear and concise analytical results. This makes it easier for semiconductor device manufacturers to identify failure causes and optimize processes. Furthermore, compared to a sandwich structure with spacers on both the front and back of the sample, the SCM sample offers better conductivity with the SCM testing equipment base, further enhancing the capacitance signal strength. Figure 4 This is a test image obtained by performing SCM testing on an SCM sample prepared according to an embodiment of this application. Figure 3 It is a test image obtained by performing SCM testing on a pair of proportional SCM samples.
[0049] In one embodiment of this application, after step S130 and before the SCM test, a step of wrapping the device sample and the gasket with conductive tape is also included.
[0050] The above-described SCM sample preparation method for semiconductor devices is applicable not only to devices on SiC substrates but also to devices on silicon or other material substrates. However, devices on silicon substrates are typically analyzed for semiconductor device failure using other methods.
[0051] Figure 5 This is a flowchart of a semiconductor device SCM sample preparation method according to another embodiment, including the following steps:
[0052] S510 removes the metal layer from the surface of the device sample.
[0053] In one embodiment of this application, the metal layer on the surface of the device sample is removed by acid. For device samples with metal layers on both the front and back sides, step S510 removes the metal layers on the front and back sides of the first and second device samples; for device samples with a metal layer on only one side (e.g., the front side of the device), step S510 removes the metal layer on only one side. The processing of the device sample involved in step S510 can also be referred to the same method. Figure 2a and Figure 2b .
[0054] Furthermore, the acid used to remove the metal layer should be an acid with a high etching selectivity. In one embodiment of this application, the acid used to remove the metal layer is aqua regia.
[0055] S520, a gasket is provided on the front of the device sample to be fixedly connected to the device sample.
[0056] Figure 6a This is a schematic diagram of a large core sample being cured on a gasket in one embodiment. Figure 6b This is a schematic diagram of a small die sample cured on a gasket in one embodiment. The gasket should be made of a non-metallic material to avoid contamination from metal debris during subsequent polishing. The gasket is also made of a conductive material, allowing for electrical connection between the device sample and the base of the SCM testing equipment. Furthermore, the side of the gasket facing away from the device sample should have a flat surface, ensuring stable micro-contact between the AFM microprobe and the gasket during SCM testing, thereby obtaining a good SCM signal. In one embodiment of this application, the gasket is cured on the front side of the device sample using an adhesive. In another embodiment of this application, the adhesive is made of epoxy resin.
[0057] S530 polishes the device sample from the side to the region of interest.
[0058] Polishing refers to a processing method that uses mechanical, chemical, or electrochemical actions to reduce the surface roughness of a workpiece, thereby obtaining a bright and smooth surface. In one embodiment of this application, polishing cloths known in the art are used for polishing. Polishing can achieve an ideal smooth and clean surface state, and is less susceptible to interference from foreign impurities compared to dicing or ion milling. In one embodiment of this application, the region of interest includes the PN junction structure of the device. In other embodiments, the region of interest may also be other structures in the semiconductor device that a tester wants to test.
[0059] S540, For small die samples, proceed to step S550; otherwise, proceed to step S560.
[0060] In one embodiment of this application, the size of the back surface area of the device sample can be used as the criterion for determining whether it is a small die or a large die. For example, a device sample with a back surface area greater than a first threshold is considered a large die. The first threshold can be set empirically.
[0061] S550, the device sample and gasket are wrapped with conductive tape.
[0062] See Figure 6c Conductive tape can be wrapped around the surface of the device sample and the pad with half a turn, one turn, or multiple turns. Wrapping conductive tape around the surface of small die samples helps to achieve good electrical contact between the small die sample and the base of the SCM testing equipment during SCM testing. Large die samples can achieve good electrical contact with the base of the SCM testing equipment without conductive tape. Placing the step of wrapping with conductive tape after polishing can prevent the adhesive components of the tape from contaminating the sample surface during polishing. In one embodiment of this application, the conductive tape is copper tape.
[0063] S560, perform SCM testing.
[0064] Figure 7 This is a flowchart of a method for preparing an SCM sample of a semiconductor device in another embodiment, including the following steps:
[0065] S710, remove the metal layer from the surface of the first device sample and the second device sample.
[0066] The first device sample and the second device sample are samples of the same device, such as two different dies on the same wafer, and the two dies have the same device.
[0067] In one embodiment of this application, the metal layer on the surface of the first device sample and the second device sample is removed by acid solution. For device samples with metal layers on both the front and back sides, step S710 removes the metal layers on the front and back sides of the first and second device samples; for device samples with metal layers on only one side (e.g., the front side of the device), step S710 removes the metal layer on only one side.
[0068] Furthermore, the acid used to remove the metal layer should be an acid with a high etching selectivity. In one embodiment of this application, the acid used to remove the metal layer is aqua regia.
[0069] S720 connects the front side of the first device sample to the front side of the second device sample face to face.
[0070] In one embodiment of this application, the front surfaces of the first device sample and the second device sample are cured face-to-face using an adhesive, which can replace the function of a gasket. See also Figure 8Substrate 231 and dielectric layer 221 constitute the structure of the first device sample, and substrate 232 and dielectric layer 222 constitute the structure of the second device sample. In one embodiment of this application, the adhesive 250 is made of epoxy resin.
[0071] S730 polishes the sample from the side to the region of interest.
[0072] After face-to-face curing, the sample is polished from the side to the region of interest. In one embodiment of this application, a polishing cloth known in the art is used for polishing. In one embodiment of this application, the first device sample is the sample to be tested, and the second device sample acts as a substitute for a spacer; therefore, the region of interest includes the PN junction structure in the first device sample. In other embodiments, the region of interest may also be other structures in the first device sample that the tester wants to test.
[0073] After step S730 is completed, the obtained SCM sample can be subjected to SCM testing.
[0074] Figure 7 In the illustrated embodiment, a second device sample is used to replace the spacer. Similarly, the metal layer on the surface of the device sample is removed before polishing, avoiding metal impurities from the polishing process and improving the capacitance signal strength. Therefore, the resulting SCM sample exhibits a strong SCM signal and clear junction morphology boundaries during SCM testing, facilitating clear and concise analytical results. This makes it easier for semiconductor device manufacturing plants to identify failure causes and optimize processes. Since the first and second device samples are two dies with the same device on the same wafer, both can be used as sampling targets during testing, increasing the sampling area and simplifying operation. However, this method of preparing SCM samples requires twice the number of dies and is suitable for environments with a sufficient number of samples.
[0075] It should be understood that although the steps in the flowchart of this application are shown sequentially as indicated by the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, at least some steps in the flowchart of this application may include multiple steps or multiple stages, which are not necessarily completed at the same time, but may be executed at different times, and the execution order of these steps or stages is not necessarily sequential, but may be performed alternately or in turn with other steps or at least some of the steps or stages of other steps.
[0076] In the description of this specification, references to terms such as "some embodiments," "other embodiments," and "ideal embodiments" indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the invention. In this specification, the illustrative descriptions of the above terms do not necessarily refer to the same embodiments or examples.
[0077] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features of the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.
[0078] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.
Claims
1. A method for preparing a semiconductor device SCM sample, comprising: Remove the metal layer from the surface of the device sample; After the metal layer is removed, a gasket is provided on the front side of the device sample and fixedly connected to the device sample. The gasket is made of non-metallic material and includes conductive material; The device sample with the gasket attached is polished from the side to the region of interest to obtain an SCM sample; The step of removing the metal layer on the surface of the device sample includes removing the metal layer by means of an acid solution.
2. The method for preparing SCM samples of a semiconductor device according to claim 1, characterized in that, The step of setting a gasket fixedly connected to the front of the device sample includes bonding the gasket to the front of the device sample with an adhesive, wherein the adhesive includes epoxy resin.
3. The method for preparing SCM samples of a semiconductor device according to claim 1, characterized in that, The step of removing the metal layer from the surface of the device sample includes removing the metal layers from the front and back sides of the device sample.
4. The method for preparing SCM samples of a semiconductor device according to claim 1, characterized in that, It also includes the step of performing SCM testing on the SCM sample.
5. The method for preparing SCM samples of a semiconductor device according to claim 4, characterized in that, Before the step of performing SCM testing on the SCM sample and after the step of polishing the device sample with the gasket attached from the side to the region of interest, the method further includes a step of wrapping the device sample and the gasket with conductive tape.
6. The method for preparing SCM samples of a semiconductor device according to claim 5, characterized in that, The step of wrapping the device sample and the gasket with conductive tape refers to wrapping the device sample with a back surface area less than or equal to a first threshold, while not wrapping the device sample with a back surface area greater than the first threshold.
7. The method for preparing SCM samples of a semiconductor device according to claim 5, characterized in that, The conductive tape includes copper tape.
8. The method for preparing SCM samples of a semiconductor device according to claim 1, characterized in that, The step of removing the metal layer on the surface of the device sample includes removing the metal layer on the surface of the first device sample and the second device sample; the first device sample and the second device sample are samples of the same device; The step of setting a gasket fixedly connected to the front of the device sample includes connecting the front of the first device sample and the front of the second device sample face to face.
9. The method for preparing SCM samples of a semiconductor device according to any one of claims 1-8, characterized in that, The device sample is a SiC substrate device sample.