A lidar detection chip for perceptual data compression

Abstract

The application relates to a laser radar detection chip for perception data compression, which comprises a detection pixel array, column processing circuit and peripheral processing circuit, each pixel comprises a detection front-end circuit, correlation detection circuit, TDC control circuit and handshake interface, each pixel in the array can detect the target in the field of view in the depth direction, and after correlation detection and delay triggering, sparse data without resolution loss is obtained; each column processing circuit comprises an asynchronous arbitration circuit, histogram circuit and buffer circuit; the peripheral processing circuit comprises a synchronous arbitration circuit, micro control unit, row selection / column selection control circuit and clock generation circuit. Compared with the prior art, the application utilizes the spatial correlation of laser pulses on adjacent pixels and the correlation of modulated emission signals in time, greatly compresses the perception data amount of the laser radar detection chip, reduces the data rate, and solves the data transmission bottleneck problem of the bus.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of laser radar detection, and in particular to a laser radar detection chip for sensing data compression. BACKGROUND

[0002] A laser radar detection system can sense the three-dimensional spatial information of a target and has wide applications in the fields of spatial detection and intelligent driving. A new type of laser radar uses a Geiger-mode avalanche photodetector as a photoelectric detector. Due to its extremely high gain, it can realize the detection of single photons, record the time of flight of the photons, and convert the time of flight into distance information of the target. A sensing array composed of single-photon Geiger-mode avalanche photodetectors detects a target, and finally a three-dimensional image of the target can be obtained.

[0003] Compared with traditional CMOS image sensor imaging, an important problem of laser radar is that, in addition to receiving signal photons, a single-photon detector is also very sensitive to a large amount of background light and can be triggered to dark count by noise in the device at any time. In a detection frame period, in addition to collecting signal photons at a specific time, a large number of noise photons are received at other times, and therefore a large amount of random noise is contained in the sensed distance data. Although the total number of noise is much larger than the number of signal photons, if a large number of frames are collected and the statistical distribution of avalanche events of the single-photon detector is performed on a time scale, the number of signal photons in a subdivided time period is still greater than the number of background noise photons in the time period, and therefore the time position of the signal can still be determined from a histogram statistical graph of multiple frames. In outdoor long-distance detection, the total background noise is much larger than the number of signal photons, and therefore a large number of frames need to be counted. The number of counted frames usually needs to reach 10 3 -10 4 orders of magnitude to statistically determine the position of the signal. Therefore, compared with a CMOS image sensor, the data volume of laser radar imaging is 3-4 orders of magnitude higher to achieve the same detection frame rate, which brings huge transmission pressure and on-chip storage pressure to the bus.

[0004] The prior art directly performs preliminary processing on the original signal in the pixel, such as correlation detection, clock gating, histogram statistics, and the like, which can improve the signal-to-noise ratio of detection and in turn reduce the overall data volume. However, these technologies need to sacrifice the resolution of the original data or need to occupy a large amount of storage resources for statistics. SUMMARY

[0005] The purpose of the present application is to provide a laser radar detection chip for sensing data compression, which fully utilizes the sparsity of signal in time and the correlation characteristics in space to greatly improve the detection frame rate while maintaining the detection resolution and accuracy.

[0006] The object of the application can be achieved by the following technical solutions:

[0007] A laser radar detection chip for sensing data compression, comprising:

[0008] A detection pixel array, a column processing circuit and a peripheral processing circuit, wherein the detection pixel array and the column processing circuit interact through a column data bus, the peripheral processing circuit controls the detection pixel array through a control bus and controls the interaction between the column processing circuit through a global data bus;

[0009] The detection pixel array comprises M rows x N columns of pixels, each pixel comprising a detection front-end circuit for receiving a signal to generate a pulse, a correlation detection circuit for correlation detection of the pulse, a TDC control circuit for time-to-digital conversion of the pulse signal, and a handshake interface for interaction with the column processing circuit;

[0010] The chip comprises N column processing circuits, each column processing circuit interacting with all pixels in a single column, and the N column processing circuits sharing a set of global data buses; the column processing circuit comprises an asynchronous arbitration circuit for priority arbitration of transmission event requests in a single column of pixels, a histogram circuit for interval verification of output data of the TDC control circuit (153), and a buffer circuit for buffering transmission event data;

[0011] The peripheral processing circuit is responsible for global control of the chip and global data interaction, comprising a clock generation circuit for generating a clock signal, a row / column selection control circuit for signal gating in synchronous mode, a synchronous arbitration circuit for synchronous reading of data in the buffer circuit according to the priority arbitration result of the asynchronous arbitration circuit in asynchronous mode, and a micro control unit for generating all global static control signals.

[0012] The detection front-end circuit comprises a plurality of single photon detectors and quenching circuits and a clock gate switch, the single photon detector generates avalanche breakdown after detecting a photon, the pulse signal enters the quenching circuit to form a pulse; in one detection, a plurality of single photon detectors and quenching circuits generate corresponding pulses at different times; the clock gate switch is used to control the generation of pulses of the detection front-end only at a specific time.

[0013] The correlation detection circuit detects the multiple pulse signals output by the front-end detection circuit twice. If the number of pulses detected in the front-end detection circuit exceeds a preset threshold in a time window with a width of the pulse signal width after detecting the pulse signal, it is considered that the first correlation detection is successful, the first correlation signal is set high, and the clock gate switch of the front-end detection circuit is immediately closed to stop the generation of the front-end detection pulse. According to the time correlation of the pulse emission, the clock gate switch is opened again after a time interval equal to the interval between the two pulses emitted by the emission end to allow the front-end detection circuit to perform the second detection and the second correlation detection. If the second correlation detection is successful, the second correlation signal is set high.

[0014] The TDC control circuit includes two parts of a coarse TDC and a fine TDC. When the first correlation signal of the correlation detection circuit is set high, the coarse TDC is triggered to sample the low-bit TDC code value and transmit it to the column processing circuit for histogram statistics. The column processing circuit returns an interval judgment signal according to the low-bit TDC code value.

[0015] If the interval judgment signal and the second correlation signal of the correlation detection circuit are both high, the multiple pulses detected in the second correlation detection time window are subjected to different delays, respectively, and the fine TDC is triggered based on the multiple sparse signals after the delay to record all the TDC code values of each signal.

[0016] The handshake interface processes the bus request of the transmission event and receives the interval judgment signal fed back by the column processing circuit.

[0017] The asynchronous arbitration circuit arbitrates the priority of the transmission event request in a single column of pixels to ensure that only one pixel occupies the column data bus at any time, and the remaining pixels wait in turn and are queued for transmission according to the priority.

[0018] Each column processing circuit includes M histogram circuits corresponding to M pixels in the column. Each histogram circuit counts the low-bit TDC code value sampled in the first correlation detection of the pixel, checks whether the transmission event is in the coarse interval of the signal, and feeds back a pixel interval judgment signal according to the result to determine whether the current pixel continues to process and transmit the data of the second detection.

[0019] The buffer circuit buffers all the transmission event data of the corresponding column in the current frame detection pixel array, including the pixel address, the TDC code value, and the pixel front-end address. The write port uses asynchronous event-triggered writing, and the read port uses external synchronous clock reading. In the asynchronous mode, the read port of the buffer circuit is connected to the global data bus of the chip. In the synchronous mode, the pixel data is selected using the signal generated by the row selection / column selection control circuit in the peripheral processing circuit, and the buffer circuit is enabled to be closed.

[0020] The clock generation circuit is used for generating the clock required by the coarse TDC count in the TDC control circuit and the frequency division control clock for controlling the fine TDC switch, and the fine TDC is closed after two rising edges of the frequency division control clock.

[0021] The global static control signal generated by the micro control unit includes a synchronous / asynchronous mode selection signal, a histogram threshold selection signal and a probe front end enable signal.

[0022] Compared with the prior art, the present application has the following beneficial effects:

[0023] (1) The present application adopts a twice correlation detection mode, fully utilizes the time correlation of the signal and the spatial correlation between the probe front ends, filters out most of the random environmental noise, and improves the signal-to-noise ratio of the probe end.

[0024] (2) The present application greatly compresses the number of signals generated by the design of twice correlation detection and histogram interval judgment in the column circuit, and effectively reduces the bandwidth demand of the bus.

[0025] (3) The asynchronous arbitration circuit of the present application is suitable for asynchronous transmission of the greatly compressed signals described in (2), and in the sparse signal scenario, compared with the synchronous transmission mode, the asynchronous transmission mode has lower power consumption and faster transmission speed.

[0026] (4) In the TDC control circuit, the present application performs unequal delay on different front end pulses, solves the problem that multiple pulses cannot access the TDC simultaneously in a very short window, and ensures that all trigger events are sampled and transmitted, which can detect more fine scene information compared with the traditional correlation detection method. BRIEF DESCRIPTION OF DRAWINGS

[0027] Figure 1 is a structural schematic diagram of the present application;

[0028] Figure 2 is a structural schematic diagram of the circuit included in a single pixel;

[0029] Figure 3 is a structural schematic diagram of the column processing circuit;

[0030] Figure 4 is a structural schematic diagram of the peripheral processing circuit. DETAILED DESCRIPTION

[0031] The present application will be described in detail below in combination with the drawings and specific embodiments. The present embodiment is implemented on the basis of the technical scheme of the present application, and gives a detailed implementation mode and specific operation process, but the protection scope of the present application is not limited to the following embodiments.

[0032] As Figure 1 shown, the embodiment provides a laser radar detection chip 10 for sensing data compression, including a detection pixel array 100, a column processing circuit 200 and a peripheral processing circuit 300. Wherein the detection pixel array 100 and the column processing circuit 200 interact through the column data bus, the peripheral processing circuit 300 controls the detection pixel array 100 through the control bus, and controls the interaction between the column processing circuit 200 through the global data bus.

[0033] (1) Detection pixel array 100

[0034] The detection pixel array 100 includes M rows × N columns of pixels, each pixel 150 including a detection front-end circuit 151, a correlation detection circuit 152, a TDC control circuit 153 and a handshake interface 154, as shown in Figure 2 .

[0035] (11) Detection front-end circuit 151

[0036] As shown in 151 in Figure 2 , each detection front-end circuit 151 includes 4 single-photon detectors and quenching circuits. After the Geiger avalanche single-photon detector detects a photon, an avalanche breakdown occurs, and the pulse signal enters the quenching circuit to form a pulse with a width of T signal . In one detection, the 4 single-photon detectors and quenching circuits can respectively generate pulses with a width of T signal at t1, t2, t3, t4.

[0037] The detection front-end circuit also includes a clock gate switch that can only turn on the pulse generation of the detection front-end at a specific time.

[0038] (12) Correlation detection circuit 152

[0039] Each detection period, the transmitting end emits two pulses with a distance of T DTG , and the correlation detection circuit 152 performs two correlation detections on the 4 pulse signals P0, P1, P2, P3 output by the detection front-end circuit 151. Within the T signal wide time window after detecting the pulse signal at a certain time, K pulses are detected in the detection front-end circuit 151, K ≤ 4. If K exceeds the preset threshold K th , it is considered that the first correlation detection is successful, the CD1_OK signal is set high, and the clock gate switch of the detection front-end circuit is immediately closed to stop the generation of the detection front-end pulse. According to the time correlation of pulse emission, after T DTG , the clock gate switch is opened again to allow the detection front-end circuit to generate a pulse at T CD2A second probe is performed within a specified time frame, along with a second correlation check. If the second correlation check is successful, the CD2_OK signal is set high.

[0040] (13) TDC control circuit 153

[0041] The TDC control circuit 153 includes two parts: coarse TDC and fine TDC. The coarse TDC enables full-window detection. After the CD1_OK signal of the correlation detection circuit 152 is set high, the coarse TDC is triggered, and the sampled low-order TDC code value is transmitted to the column processing circuit 200 for histogram statistics. The sampled TDC code value reflects the time length from when the laser pulse is emitted to when CD1_OK is set high; that is, the farther the target is, the larger the sampled TDC code value.

[0042] The column processing circuit 200 determines whether the signal is in the coarse interval based on the TDC code value. If the determination is successful, the returned MASKOK signal is set high.

[0043] If both the MASKOK signal and the CD2_OK signal of the correlation detection circuit 152 are high, then the K' pulses detected within the second correlation detection time window are processed by T... D1 T D2 …T DK’ The K' sparse signals after the delay are used to trigger the fine TDC respectively, and all TDC code values ​​of each signal are recorded. In this embodiment, there is only one fine TDC, which cannot respond to multiple trigger signals at the same time. Therefore, the K' pulses are delayed so that only one signal triggers the fine TDC at a time.

[0044] After two rising edges of the frequency division control clock, the fine TDC is turned off, and the TDC sampling of this frame is completed.

[0045] (14) Handshake Interface 154

[0046] The handshake interface 154 processes bus requests for transmission events and receives the MASKOK signal from the column processing circuit 200. In asynchronous mode, the bus interacts with the column processing circuit 200 using the TDC_REQ and TDC_ACK handshake signals. When a pixel is selected according to the sorting result of the asynchronous arbitration circuit, the TDC code value, pixel row address encoding value, and probe front-end address encoding value obtained by the TDC control circuit 153 of that pixel are sent to the column data bus.

[0047] In one embodiment, such as Figure 2 As shown, the laser emits two beams with a distance of T. DTGThe target reflected pulse, after being reflected by the target, has a certain probability of causing avalanche breakdown on the 4 detection front-end circuits 151 in the pixel 150, and after passing through the quenching circuit, 4 spread pulses P0, P1, P2, P3 are generated, and two correlation triggers are detected in turn using the correlation detection circuit 152, and two signals CD1_OK and CD2_OK can be generated. After CD1_OK is set high, the Coarse CLK in the TDC control circuit 153 controls the coarse TDC to generate the TDC code value <3:0> and send it to the column processing circuit 200 for processing. After CD2_OK and MASKOK are both set high, the fine TDC in the TDC control circuit 153 is turned on, and the DT0, DT1, DT2 and DT3 delays of the second detection front-end pulse P0-P3 pulse are used as the trigger fine TDC pulse DP0, DP1, DP2 and DP3, and up to 4 event data are obtained in turn, including the TDC code value TDC<12:0>, the front-end address code value and the pixel address code value ADDR<7:0>. Among them, TDC<12:0> totals 13 bits, including the code value <3:0> generated by the coarse TDC and the code value <12:4> generated by the fine TDC, and one event data corresponds to one TDC<12:0>. When splicing the code values sampled by the coarse TDC and the fine TDC, no matter how many pulses are detected in the first time, the low TDC code value is finally generated by CD1_OK trigger, so the coarse TDC code value <3:0> only includes one set of data, that is, it is not triggered by the pulse generated by the detection front-end circuit. The fine TDC code value can obtain up to 4 sets of code values <12:4> according to the pulse DP0, DP1, DP2 and DP3 triggering the fine TDC, and the multiple TDC<12:0> obtained by splicing the code value generated by the coarse CLK controlling the coarse TDC at the time of the DP0, DP1, DP2 and DP3 pulse trigger time. At this time, the coarse TDC code values of multiple events may be different, and the coarse TDC code values generated in the first correlation detection may also be different. When the second rising edge of the frequency division control clock MCC CLK is waited, the fine TDC is turned off to reduce power consumption. Through the handshake interface 154, TDC_REQ and TDC_ACK are used to interact with the column data bus, and the TDC code value and address data are sent to the column data bus, and the feedback control signal MASKOK is obtained from the column data bus and sent back to the TDC control logic.

[0048] (2) Column processing circuit 200

[0049] The detection pixel array 100 includes M rows × N columns of pixels, so it includes N column processing circuits 200 in total, and each column processing circuit 200 interacts with all pixels 150 in a single column. The N column processing circuits 200 share a set of global data buses.

[0050] The column processing circuit 200 includes an asynchronous arbitration circuit 201, a histogram circuit 202, and a buffer circuit 203.

[0051] (21) Asynchronous arbitration circuit 201

[0052] The asynchronous arbitration circuit 201 arbitrates the priority of the transmission event request in a single column of pixels. M rows of pixels in a single column share a set of data bus and address bus, and M sets of independent TDC_ACK and TDC_REQ handshake signals. The asynchronous arbitration circuit arbitrates the priority of the M sets of handshake signals to ensure that only one pixel occupies the column data bus at any time, and the remaining pixels wait in turn and are queued for transmission according to priority.

[0053] As shown in FIG. 2, in an embodiment, the asynchronous arbitration circuit 201 arbitrates the M sets of TDC ACK and TDC REQ handshake signals corresponding to the M pixels of the handshake interface 154, processes asynchronous transmission events, and sequentially transmits data on the column data bus. Figure 3 (22) Histogram circuit 202

[0054] The column processing circuit 200 includes M histogram circuits 202 corresponding to the M pixels of the column. Each histogram circuit 202 counts the coarse TDC code value (i.e., the low-bit TDC code value corresponding to the CD1_OK event) TDC<3:0> of the first correlation detection in the pixel, checks whether the transmission event is in the coarse interval of the signal, and feeds back the pixel MASKOK signal according to the result to determine whether the current pixel continues to process and transmit the data of the second detection, further reducing redundant data. When the transmission event is in the coarse interval of the signal, the MASKOK signal is high; otherwise, the MASKOK signal is low. The high and low of the MASKOK signal can feed back whether the fine TDC in the TDC control circuit 153 of the pixel continues to be turned on.

[0055] In an embodiment, the implementation of the histogram circuit refers to the patent application with the application number 202310497860X and the patent name “Peak fast search circuit for laser radar statistical distribution histogram”. The peak fast search circuit for laser radar statistical distribution histogram can quickly search for the peak value of the histogram and the corresponding coarse TDC code value, thereby judging whether the peak value is in the coarse interval of the signal.

[0056] (23) Buffer circuit 203

[0057]

[0058] ​The buffer circuit 203 buffers all the transmission event data of the current frame of the column, including pixel address, TDC code value, and pixel front address. The write port uses asynchronous event trigger to write, and the read port uses external synchronous clock to read out, so as to synchronize the data. In the asynchronous mode, the read port of the buffer circuit 203 is connected to the global data bus of the chip; in the synchronous mode, the pixel data is selected directly using the row selection and column selection signals generated by the peripheral processing circuit 300, and the buffer circuit 203 is enabled to be closed.

[0059] The data on the column data bus is written asynchronously, but the data needs to be read at the same time, so the asynchronous data on the column data bus is written into the buffer circuit, and the buffered data is read out synchronously to the global data bus using a global read clock at the read port. One column data is read at each rising edge of the global read clock.

[0060] (3) Peripheral processing circuit 300

[0061] The peripheral processing circuit 300 is responsible for the global control of the chip and the global data interaction, including a clock generation circuit 301, a row / column selection control circuit 302, a synchronization arbitration circuit 303, and a micro control unit 304, as shown in Figure 4 .

[0062] (31) Clock generation circuit 301

[0063] The clock generation circuit 301 is used to generate the clock Coarse CLK required for coarse TDC counting in the TDC control circuit 153 and the frequency division control clock MCC CLK for fine TDC switch control.

[0064] (32) Row / column selection control circuit 302

[0065] The row / column selection control circuit 302 is used to generate the synchronization mode row-by-row and column-by-column selection signal. In another embodiment, if the asynchronous mode is selected, the row / column selection control circuit 302 can not be included.

[0066] In an embodiment, the row / column selection control circuit can be implemented using a shift register, and each bit output of the shift register is connected to the enable end of each row / column. The input end of the shift register is controlled by the input and clock signal, and according to the output state of each bit of the shift register, the selection of any row and column can be realized.

[0067] (33) Synchronization arbitration circuit 303

[0068] The synchronous arbitration circuit 303 is used to determine whether there is remaining data in the buffer circuit 203 in each column processing circuit 200 in the asynchronous mode. If there is remaining data, the arbitration result of the asynchronous arbitration circuit 201 and the state of the buffer circuit 203 are used to send the data in the buffer circuit into the global data bus one by one, and all the data is read column by column to realize the synchronous column data reading.

[0069] (34) Micro control unit 304

[0070] The micro control unit 304 is used to generate all the global static control signals required by the chip, including but not limited to the synchronous / asynchronous mode selection signal, the histogram threshold selection signal, and the detection front end enable signal.

[0071] In an embodiment, the micro control unit can generate different global control signals by using the configuration register. The state of the configuration register in the micro control unit can be modified by controlling the write enable signal and the written value at the write end of the micro control unit, and then different global control signals are generated by the state machine.

[0072] The preferred embodiments of the present application are described in detail above. It should be understood that those skilled in the art can make many modifications and variations without departing from the concept of the present application. Therefore, any technical solution obtained by logical analysis, reasoning, or limited experiments based on the prior art according to the concept of the present application should be within the protection scope defined by the claims.

Claims

1. A lidar detection chip for sensing data compression, characterized in that, include: The system includes a detection pixel array (100), a column processing circuit (200), and a peripheral processing circuit (300). The detection pixel array (100) and the column processing circuit (200) interact with each other via a column data bus. The peripheral processing circuit (300) controls the detection pixel array (100) via a control bus and controls the interaction with the column processing circuit (200) via a global data bus. The detector pixel array (100) includes M rows × N columns of pixels. Each pixel (150) includes a detector front-end circuit (151) for receiving signals to generate pulses, a correlation detection circuit (152) for detecting the correlation of pulses, a TDC control circuit (153) for converting pulse signals from time to digital code value, and a handshake interface (154) for interacting with the column processing circuit. The chip includes N column processing circuits (200), each column processing circuit (200) interacts with all pixels (150) in a single column, and the N column processing circuits (200) share a set of global data buses; The column processing circuit (200) includes an asynchronous arbitration circuit (201) for priority arbitration of transmission event requests in a single column of pixels, a histogram circuit (202) for interval verification of the output data of the TDC control circuit (153), and a buffer circuit (203) for buffering transmission event data. The peripheral processing circuit (300) is responsible for the global control of the chip and global data interaction, including a clock generation circuit (301) for generating clock signals, a row / column selection control circuit (302) for signal gating in synchronous mode, a synchronous arbitration circuit (303) for synchronously reading data in the buffer circuit (203) according to the priority arbitration result of the asynchronous arbitration circuit (201) in asynchronous mode, and a microcontroller unit (304) for generating all global static control signals.

2. The lidar detection chip for sensing data compression according to claim 1, characterized in that, The detection front-end circuit (151) includes multiple single-photon detectors and quenching circuits and a clock gate switch. After a single-photon detector detects a photon, it undergoes avalanche breakdown, and the pulse signal enters the quenching circuit to form a pulse. In one detection, multiple single-photon detectors and quenching circuits generate corresponding pulses at different times. The clock gate switch is used to control the pulse generation of the detection front-end to be activated only at specific times.

3. The lidar detection chip for sensing data compression according to claim 2, characterized in that, The correlation detection circuit (152) performs two correlation detections on the multiple pulse signals output by the detection front-end circuit (151). If the number of pulse triggers detected in the detection front-end circuit (151) exceeds a preset threshold within a time window with a width equal to the width of the pulse signal after the pulse signal is detected, the first correlation detection is considered successful, the first correlation signal is set high, and the clock gate switch of the detection front-end circuit (151) is immediately turned off to stop the generation of the detection front-end pulse. According to the time correlation of the pulse transmission, after a time interval equal to the distance between the two pulses transmitted by the transmitting end, the clock gate switch is turned on again to allow the detection front-end circuit to perform a second detection and a second correlation detection. If the second correlation detection is successful, the second correlation signal is set high.

4. A lidar detection chip for sensing data compression according to claim 3, characterized in that, The TDC control circuit (153) includes two parts: coarse TDC and fine TDC. When the first correlation signal of the correlation detection circuit (152) is set high, the coarse TDC is triggered, the low-order TDC code value is sampled and transmitted to the column processing circuit (200) for histogram statistics. The column processing circuit (200) returns the interval judgment signal based on the low-order TDC code value. If the interval judgment signal and the second correlation signal of the correlation detection circuit (152) are both high, then the multiple pulses detected within the second correlation detection time window are delayed unequally, and the multiple sparse signals after the delay are triggered to trigger fine TDC, and all TDC code values ​​of each signal are recorded.

5. A lidar detection chip for sensing data compression according to claim 1, characterized in that, The handshake interface (154) processes bus requests for transmission events and receives interval judgment signals fed back by the column processing circuit (200).

6. A lidar detection chip for sensing data compression according to claim 1, characterized in that, The asynchronous arbitration circuit (201) performs priority arbitration on the transmission event requests in a single column of pixels, ensuring that only one pixel occupies the column data bus at any given time, while the remaining pixels wait in sequence and are transmitted in order of priority.

7. A lidar detection chip for sensing data compression according to claim 4, characterized in that, Each column processing circuit (200) includes M histogram circuits (202) corresponding to the M pixels of the column. Each histogram circuit (202) performs statistics on the low-order TDC code value of the first correlation detection sample in the pixel, verifies whether the transmission event is in the coarse interval where the signal is located, and judges the signal based on the result feedback of the pixel interval to determine whether the current pixel should continue to process and transmit the data of the second detection.

8. A lidar detection chip for sensing data compression according to claim 1, characterized in that, The buffer circuit (203) buffers all transmission event data of the corresponding column in the current frame detection pixel array (100), including pixel address, TDC code value, and pixel front-end address. The write port uses asynchronous event triggering for writing, and the read port uses an external synchronous clock for reading. In asynchronous mode, the read port of the buffer circuit (203) is connected to the global data bus of the chip. In synchronous mode, the pixel data is selected directly using the signal generated by the row selection / column selection control circuit (302) in the peripheral processing circuit (300), and the buffer circuit (203) is enabled or disabled.

9. A lidar detection chip for sensing data compression according to claim 1, characterized in that, The clock generation circuit (301) is used to generate the clock required for coarse TDC counting in the TDC control circuit (153) and the frequency division control clock for controlling the fine TDC switch. After the rising edge of the frequency division control clock twice, the fine TDC is turned off.

10. A lidar detection chip for sensing data compression according to claim 1, characterized in that, The global static control signals generated by the microcontroller unit (304) include a synchronous / asynchronous mode selection signal, a histogram threshold selection signal, and a probe front-end enable signal.

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