Time-to-digital converter, time-to-digital conversion method, apparatus, and electronic device

Abstract

The time-to-digital converter, the time-to-digital conversion method, the device and the electronic equipment provided by the embodiment of the application are applied to the circuit field, correct the circuit, and are used for receiving a clock signal and a reverse clock signal; the clock signal and the reverse clock signal are input into a frequency reduction module for frequency reduction to obtain a frequency-reduced clock signal and a frequency-reduced reverse clock signal; a delay correction signal is generated according to the frequency-reduced clock signal and the frequency-reduced reverse clock signal; a time measurement circuit is used for receiving a START signal and a STOP signal; the START signal is input into a delay chain for multiple times of delay; the delay chain includes multiple delay units, the delay time length of the delay chain is corrected through the delay correction signal; the signal after each time of delay is sampled through the STOP signal to obtain multiple delay signals; and the time measurement is performed according to the multiple delay signals through an encoding circuit. Through the time-to-digital converter of the embodiment of the application, the PVT stability of the measurement precision of the time measurement circuit can be improved.

Description

Technical Field

[0001] This application relates to the field of circuit technology, and in particular to a time-to-digital converter, a time-to-digital conversion method, an apparatus, and an electronic device. Background Technology

[0002] Time-to-digital converters (TD-SCDMAs), which can identify the time of an event and convert it into a digital signal, have been widely used in fields such as statistical laser backpulse distribution, particle collision time, quantum optics, quantum key distribution, optical detection, and lidar ranging.

[0003] However, the measurement accuracy of time-to-digital converters (TD-to-time converters) can deviate due to variations in manufacturing processes, voltage, temperature, and other factors. Therefore, to improve the stability of the measurement accuracy of TD-to-time converters, a correction circuit is needed to rectify the measurement accuracy. The applicant's research has found that current TD-to-time converter delay correction often relies on high-frequency clock signals, which not only consumes significant power but also tends to have poor correction performance. Summary of the Invention

[0004] The purpose of this application is to provide a time-to-digital converter, a time-to-digital conversion method, an apparatus, and an electronic device to improve the accuracy of time measurement. The specific technical solution is as follows:

[0005] In a first aspect of the embodiments of this application, a time-to-digital converter is provided, including a time measurement circuit and a correction circuit;

[0006] The correction circuit is used to receive a clock signal and an inverted clock signal; input the clock signal and the inverted clock signal into a down-frequency module for down-frequency reduction to obtain a down-frequency clock signal and a down-frequency inverted clock signal; and generate a delay correction signal based on the down-frequency clock signal and the down-frequency inverted clock signal.

[0007] The time measurement circuit is used to receive START and STOP signals; input the START signal into a delay chain and perform multiple delays according to the delay correction signal, wherein the delay chain includes multiple delay units; sample the signal after each delay using the STOP signal to obtain multiple delay signals; and measure the time based on the multiple delay signals using an encoding circuit.

[0008] Optionally, the correction circuit is specifically used to input the down-frequency clock signal into a multi-stage delay unit to obtain a delayed clock signal; input the delayed clock signal and the down-frequency inverse clock signal into a delay comparison circuit for delay comparison, and calculate the delay correction signal based on the delay comparison result, wherein the delay correction signal is used to feed back to the multi-stage delay unit so that the delay duration of the multi-stage delay unit is half a cycle.

[0009] Optionally, the correction circuit is specifically used to input the delayed clock signal and the down-frequency inverted clock signal into a delay comparison circuit for delay comparison. When the delay duration of the delayed clock signal and the down-frequency inverted clock signal is greater than half a cycle, the voltage of the delay correction signal is decreased; when the delay duration of the delayed clock signal and the down-frequency inverted clock signal is less than half a cycle, the voltage of the delay correction signal is increased to obtain a corrected delay correction signal. The corrected delay correction signal is fed back to the multi-stage delay unit, and the down-frequency clock signal is corrected by the multi-stage delay unit so that the delay duration of the delayed clock signal and the down-frequency inverted clock signal is half a cycle.

[0010] Optionally, the number of delay units in the delay chain is twice the number of delay units in the multi-level delay unit.

[0011] Optionally, the time measurement circuit includes a sampling circuit and an encoding circuit;

[0012] The sampling circuit is used to input the STOP signal into the sampling circuit; the sampling circuit samples the signal after each delay according to the STOP signal to obtain multiple delayed signals; and the multiple delayed signals are stored in multiple registers.

[0013] The encoding circuit is used to read the delay signals in the plurality of registers and to measure the time based on the plurality of delay signals;

[0014] The sampling circuit is specifically used to be driven by the rising edge of the STOP signal to record the propagation state of the signal after each delay, thereby obtaining multiple delayed signals.

[0015] The encoding circuit is specifically used to read the delay signals in the plurality of registers, and calculate the time difference between the STOP signal and the signal after each delay based on the plurality of delay signals; and to measure the time based on the time difference.

[0016] A second aspect of this application provides a time-to-digital conversion method, including:

[0017] Receives clock signal and reverse clock signal;

[0018] The clock signal and the reverse clock signal are down-frequency to obtain a down-frequency clock signal and a down-frequency reverse clock signal.

[0019] A delay correction signal is generated based on the down-frequency clock signal and the down-frequency inverse clock signal;

[0020] Receive START and STOP signals;

[0021] The START signal is delayed multiple times according to the delay correction signal, and the signal after each delay is sampled by the STOP signal to obtain multiple delayed signals;

[0022] Time is measured based on the multiple delay signals.

[0023] Optionally, generating a delay correction signal based on the down-clocked clock signal and the down-clocked inverse clock signal includes:

[0024] The down-frequency clock signal is delayed in multiple stages to obtain a delayed clock signal;

[0025] The delayed clock signal and the down-frequency reverse clock signal are compared for delay, and the delay correction signal is calculated based on the delay comparison result. The delay correction signal is used to make the delay duration of the multi-level delay unit half a cycle.

[0026] Optionally, the step of performing a delay comparison between the delayed clock signal and the down-frequency inverted clock signal, and calculating the delay correction signal based on the delay comparison result, includes:

[0027] The delayed clock signal and the down-frequency inverted clock signal are input into a delay comparison circuit for delay comparison. When the delay duration of the delayed clock signal and the down-frequency inverted clock signal is greater than half a cycle, the voltage of the delay correction signal is decreased. When the delay duration of the delayed clock signal and the down-frequency inverted clock signal is less than half a cycle, the voltage of the delay correction signal is increased to obtain the corrected delay correction signal.

[0028] The corrected delay correction signal is fed back to the multi-level delay unit, and the down-frequency clock signal is corrected by the multi-level delay unit so that the delay duration of the delayed clock signal and the down-frequency reverse clock signal is half a cycle.

[0029] Optionally, the number of times the START signal is delayed is twice the number of times the down-frequency clock signal is delayed.

[0030] Optionally, the step of delaying the START signal multiple times based on the delay correction signal, and sampling the signal after each delay using the STOP signal to obtain multiple delayed signals, including:

[0031] The START signal is delayed multiple times according to the delay correction signal;

[0032] The signal after each delay of the START signal is sampled using the STOP signal to obtain multiple delayed signals, which are then buffered.

[0033] The measurement of time based on the plurality of delay signals includes:

[0034] Read multiple cached delay signals and measure their time.

[0035] Optionally, the step of sampling the signal after each delay of the START signal using the STOP signal to obtain multiple delayed signals and buffering them includes:

[0036] The rising edge of the STOP signal is used as the sampling start signal, and the propagation state of the signal after each delay of the START signal is recorded to obtain multiple delayed signals.

[0037] The process of reading multiple delayed signals from the buffer and measuring their time includes:

[0038] Read the plurality of delayed signals and calculate the time difference between the STOP signal and the START signal based on the plurality of delayed signals;

[0039] Time is measured based on the time difference.

[0040] A third aspect of this application provides a time-to-digital conversion apparatus, comprising:

[0041] A clock signal receiving module is used to receive clock signals and reverse clock signals;

[0042] The signal down-frequency module is used to down-frequency the clock signal and the reverse clock signal to obtain a down-frequency clock signal and a down-frequency reverse clock signal.

[0043] The signal correction module is used to generate a delay correction signal based on the down-frequency clock signal and the down-frequency reverse clock signal;

[0044] Start / stop signal receiving module, used to receive START and STOP signals;

[0045] The signal delay module is used to delay the START signal multiple times according to the delay correction signal, and to sample the signal after each delay through the STOP signal to obtain multiple delayed signals;

[0046] The time measurement module is used to measure time based on the multiple delay signals.

[0047] Optionally, the signal correction module includes:

[0048] A multi-level delay submodule is used to perform multi-level delay on the down-frequency clock signal to obtain a delayed clock signal;

[0049] The delay comparison submodule is used to compare the delay clock signal and the down-frequency reverse clock signal, and calculate the delay correction signal based on the delay comparison result. The delay correction signal is used to make the delay duration of the multi-level delay unit half a cycle.

[0050] Optionally, the delay comparison submodule includes:

[0051] The correction signal generation submodule is used to input the delayed clock signal and the down-frequency inverted clock signal into the delay comparison circuit for delay comparison. When the delay duration of the delayed clock signal and the down-frequency inverted clock signal is greater than half a cycle, the voltage of the delay correction signal is reduced. When the delay duration of the delayed clock signal and the down-frequency inverted clock signal is less than half a cycle, the voltage of the delay correction signal is increased to obtain the corrected delay correction signal.

[0052] The correction signal correction submodule is used to feed back the corrected delay correction signal to the multi-level delay unit, and to correct the down-frequency clock signal through the multi-level delay unit so that the delay duration of the delayed clock signal and the down-frequency inverse clock signal is half a cycle.

[0053] Optionally, the number of times the START signal is delayed is twice the number of times the down-frequency clock signal is delayed.

[0054] Optionally, the signal delay module includes:

[0055] The delay correction submodule is used to delay the START signal multiple times according to the delay correction signal;

[0056] The signal sampling submodule is used to sample the signal after each delay of the START signal using the STOP signal, obtain multiple delayed signals, and buffer them.

[0057] The time measurement module is specifically used to read multiple cached delay signals and measure their time.

[0058] Optionally, the signal sampling submodule includes:

[0059] The state recording unit is used to take the rising edge of the STOP signal as the sampling start signal, record the propagation state of the signal after each delay of the START signal, and obtain multiple delayed signals.

[0060] The time measurement module includes:

[0061] The time difference calculation submodule is used to read the plurality of delayed signals and calculate the time difference between the STOP signal and the START signal based on the plurality of delayed signals;

[0062] The time measurement submodule is used to measure time based on the time difference.

[0063] A third aspect of this application provides an electronic device, including:

[0064] Any of the time-to-digital converters described above.

[0065] Beneficial effects of the embodiments in this application:

[0066] The time-to-digital converter, time-to-digital conversion method, apparatus, and electronic device provided in this application include a correction circuit for receiving a clock signal and an inverted clock signal; inputting the clock signal and the inverted clock signal into a down-frequency module for down-frequency reduction to obtain a down-frequency clock signal and a down-frequency inverted clock signal; and generating a delay correction signal based on the down-frequency clock signal and the down-frequency inverted clock signal. A time measurement circuit is used to receive a START signal and a STOP signal; inputting the START signal into a delay chain for multiple delays to obtain a delay signal for each delay; the delay chain includes multiple delay units, and the delay duration of the delay chain is controlled by the delay correction signal; the signal after each delay is sampled using the STOP signal to obtain multiple delay signals; and an encoding circuit measures the time based on the multiple delay signals. The time-to-digital converter provided in this application embodiment can generate a delay correction signal by down-frequency reduction of the clock signal through a correction circuit. Then, the delay duration in the delay chain is corrected by the generated delay correction signal, and then the time is measured. Compared with direct correction through a high-frequency clock signal, the time-to-digital converter in this application embodiment can not only significantly reduce the power consumption of the correction circuit, but also improve the PVT stability of the measurement accuracy of the time measurement circuit.

[0067] Of course, implementing any product or method of this application does not necessarily require achieving all of the advantages described above at the same time. Attached Figure Description

[0068] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other embodiments can be obtained based on these drawings.

[0069] Figure 1 This is a schematic diagram of a time-to-digital converter provided in an embodiment of this application;

[0070] Figure 2 Another schematic diagram of the time-to-digital converter provided in the embodiments of this application;

[0071] Figure 3 A schematic diagram of a clock signal and its inverted signal provided in an embodiment of this application;

[0072] Figure 4 A schematic diagram of yet another structure of the time-to-digital converter provided in this application embodiment;

[0073] Figure 5a A schematic diagram of a simulation result of a time-to-digital converter provided in an embodiment of this application;

[0074] Figure 5b A schematic diagram illustrating another simulation result of the time-to-digital converter provided in this application embodiment;

[0075] Figure 6 A schematic diagram illustrating another simulation result of the time-to-digital converter provided in the embodiments of this application;

[0076] Figure 7 A flowchart illustrating a time-to-digital conversion method provided in an embodiment of this application;

[0077] Figure 8 Another flowchart illustrating the time-to-digital conversion method provided in this application embodiment;

[0078] Figure 9 This is a schematic diagram of a time-to-digital conversion device provided in an embodiment of this application. Detailed Implementation

[0079] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art based on this application are within the scope of protection of this application.

[0080] This solution provides a device for correcting a time-to-digital converter. The device includes: a down-conversion circuit for down-converting a high-frequency clock signal and its inverted signal; a multi-stage delay unit for delaying a low-frequency signal; a delay comparison circuit for determining whether the delay of the multi-stage delay unit is greater than or less than half a clock cycle, and correcting the delay of the multi-stage delay unit based on the determination result; a delay chain for time measurement, wherein the delay units in the delay chain have the same circuit structure as the units within the multi-stage delay unit; a sampling circuit for recording the state of the delay chain; and an encoding circuit for encoding the state of the delay chain recorded by the sampling unit into binary to represent the measured time interval.

[0081] This solution provides a method for correcting a time-to-digital converter. The method includes: down-converting a high-frequency clock signal and its inverted signal to obtain a low-frequency signal CK_DIV (down-converted clock signal) and a down-converted signal CK_DIV_180 (down-converted inverted signal), with a delay of half a clock cycle between them; feeding the low-frequency signal CK_DIV into a multi-stage delay unit for delay, obtaining a delayed low-frequency signal CK_DIV_delay; comparing the delay of CK_DIV_delay with that of CK_DIV_180 to determine whether the delay of the multi-stage delay unit is greater than or less than half a clock cycle, and correcting the delay of the multi-stage delay unit based on the determination result; after dynamic correction reaches equilibrium, the total delay of the multi-stage delay unit is precisely equal to half a clock cycle; the delay units in the delay chain and the delay units in the multi-stage delay unit have the same delay, and the number of delay units in the delay chain is twice the number of units in the multi-stage delay unit, then the delay of the delay chain is precisely equal to one clock cycle.

[0082] This solution proposes a method and circuit for correcting a time-to-digital converter. It allows for delay correction using a down-frequency signal without increasing the number of delay units. After dynamic equilibrium is achieved, the delay chain's delay is precisely equal to one clock cycle. Therefore, this solution's correction circuit has low power consumption and good correction performance.

[0083] This application provides a time-to-digital converter, see [link]. Figure 1 It includes a time measurement circuit 101 and a correction circuit 102;

[0084] The correction circuit 102 is used to receive a clock signal and an inverted clock signal; input the clock signal and the inverted clock signal into the down-frequency module for down-frequency reduction to obtain a down-frequency clock signal and a down-frequency inverted clock signal; and generate a delay correction signal based on the down-frequency clock signal and the down-frequency inverted clock signal.

[0085] The time measurement circuit 101 is used to receive START and STOP signals; input the START signal into the delay chain for multiple delays; the delay chain includes multiple delay units; sample the signal after each delay using the STOP signal to obtain multiple delay signals; and measure the time based on the multiple delay signals using an encoding circuit.

[0086] In one example, see Figure 2 and Figure 3 The correction circuit consists of a frequency reduction circuit, a multi-stage delay unit, and a delay comparator circuit. During frequency reduction, both the clock signal CK and its inverted signal CK_180 are down-clocked, resulting in the down-clocked low-frequency signals CK_DIV and CK_180_DIV. The delay of CK_180_DIV relative to CK_DIV is 0.5*T. This delay originates from half a cycle of the clock signal and does not change with PVT. The delay of the multi-stage delay unit is controlled by the delay correction signal; the larger the voltage amplitude of the delay correction signal, the smaller the delay of the multi-stage delay unit.

[0087] In this scheme, the low-frequency signal CK_DIV is fed into a multi-stage delay unit (consisting of N / 2 delay units, only half the size of a delay chain) to obtain the delayed low-frequency signal CK_DIV_delay. A delay comparison circuit compares the time difference between CK_DIV_delay and the CK_180_DIV signal. If this time difference is greater than or less than zero, the delay provided by the multi-stage delay unit is greater than or less than 0.5*T. Based on the judgment result, the voltage of the delay correction signal will change, thereby reducing or increasing the delay size of the multi-stage delay unit.

[0088] In the above example, the delay chain is used to control the delay duration through a delay correction signal. The clock signal can be a high-frequency clock signal, and the waveform of the reverse clock signal can be the opposite of the clock signal waveform. When the clock signal is rising, the reverse clock signal is falling; when the clock signal is falling, the reverse clock signal is rising. The down-clocking module can down-clock both the clock signal and the reverse clock signal to obtain a down-clocked clock signal and a down-clocked reverse clock signal. The delay difference between the down-clocked clock signal and the down-clocked reverse clock signal is half a cycle. Multiple delays are applied to the down-clocked clock signal to obtain a delayed clock signal. The delayed clock signal and the down-clocked reverse clock signal are compared, and a delay correction signal is generated based on the comparison result. This delay correction signal adjusts the delay duration of the multiple delays applied to the down-clocked clock signal, ensuring that the delay duration of each delay is half a cycle. For example, see... Figure 3 During frequency downsampling, both the clock signal CK and its inverted signal CK_180 are down-frequencyd, resulting in the down-frequency signals CK_DIV and CK_180_DIV. The delay of CK_180_DIV relative to CK_DIV is 0.5*T. Multiple delay stages are applied to the down-frequency signals to obtain the delayed clock signal CK_DIV_delay. Through adjustment of the delay correction signal, the total delay duration of the multiple delay stages is 0.5*T.

[0089] In one example, one of the START or STOP signals can be a high-frequency clock signal, and the other is the event signal to be measured. For instance, the STOP signal mentioned above is a high-frequency clock signal, and the START signal is the event signal to be measured. The rising edge of the STOP signal can drive the sampling circuit to record the propagation state of the signal after each delay, resulting in multiple delayed signals. The encoding circuit then measures the time based on these multiple delayed signals.

[0090] As can be seen, the time-to-digital converter provided in this application embodiment can generate a delay correction signal by down-frequency reduction of the clock signal through the correction circuit, and then use the generated delay correction signal to correct the delay duration in the delay chain, and then perform time measurement. Compared with direct correction using a high-frequency clock signal, the time-to-digital converter in this application embodiment can not only significantly reduce the power consumption of the correction circuit, but also improve the PVT (Process Voltage Temperature) stability of the time measurement circuit.

[0091] Optionally, the correction circuit 102 is specifically used to input the down-frequency clock signal into the multi-stage delay unit to obtain the delayed clock signal; input the delayed clock signal and the down-frequency inverted clock signal into the delay comparison circuit for delay comparison, and calculate the delay correction signal based on the delay comparison result. The delay correction signal is used to feed back to the multi-stage delay unit so that the delay duration of the multi-stage delay unit is half a cycle.

[0092] Optionally, a correction circuit is used to input the delayed clock signal and the down-frequency inverted clock signal into a delay comparison circuit for delay comparison. When the delay duration of the delayed clock signal and the down-frequency inverted clock signal is greater than half a cycle, the voltage of the delay correction signal is reduced. When the delay duration of the delayed clock signal and the down-frequency inverted clock signal is less than half a cycle, the voltage of the delay correction signal is increased to obtain a corrected delay correction signal. The corrected delay correction signal is fed back to a multi-stage delay unit, and the down-frequency clock signal is corrected by the multi-stage delay unit so that the delay duration of the delayed clock signal and the down-frequency inverted clock signal is half a cycle.

[0093] In one example, see Figure 4 , Figure 4The correction circuit internally employs a frequency reduction circuit, which can correct the delay using a low-frequency signal without increasing the number of delay units N, thus obtaining an accurate delay. Here, START and STOP represent the START and STOP signals, respectively, and CK1 and CK2 represent CK_DIV and CK_180_DIV, respectively. The rising edge of the STOP signal drives the sampling circuit to record the propagation state of the START signal in the delay chain. The encoding circuit encodes this propagation state to obtain the time difference between the START and STOP signals. One of the START or STOP signals can be a high-frequency clock signal, and the other can be the event signal to be measured. The correction circuit of this scheme can guarantee that under different PVT conditions, the delay of the delay chain is precisely equal to one cycle of the clock signal, i.e., the delay of each delay unit is T / N. The delay of the multi-stage delay units is controlled by the delay correction signal; the larger the voltage amplitude of the delay correction signal, the smaller the delay of the multi-stage delay units. The low-frequency signal CK_DIV is fed into a multi-stage delay unit to obtain the delayed low-frequency signal CK_DIV_delay. A delay comparison circuit compares the time difference between CK_DIV_delay and the CK_180_DIV signal. If this time difference is greater than or less than zero, the delay duration provided by the multi-stage delay unit is greater than or less than 0.5*T. Specifically, when the delay duration of the delayed clock signal and the down-frequency inverted clock signal is greater than half a cycle, the voltage of the delay correction signal is reduced; when the delay duration of the delayed clock signal and the down-frequency inverted clock signal is less than half a cycle, the voltage of the delay correction signal is increased, and the down-frequency clock signal is corrected through the multi-stage delay unit to ensure that the delay duration of the delayed clock signal and the down-frequency inverted clock signal is half a cycle. For example, when the delay is greater than 0.5*T, the delay can be reduced by increasing the voltage of the delay correction signal through a multi-stage delay unit. When the delay is less than 0.5*T, the delay can be increased by decreasing the voltage of the delay correction signal through a multi-stage delay unit. After correction, when in a stable state, the delay duration of the multi-stage delay unit is half a cycle.

[0094] Optionally, the number of delay units in the delay chain is twice the number of delay units in a multi-level delay chain.

[0095] In one example, the circuitry of each unit in the multi-stage delay unit within the correction circuit is identical to that of the delay unit in the delay chain within the time measurement circuit, but the number of units in the multi-stage delay unit is half the number of units in the delay chain. Therefore, when the delay duration of the multi-stage delay unit is half a cycle, the delay duration of the delay chain is precisely equal to one clock cycle, and the delay of each delay unit is T / N. This not only increases the robustness of the circuit but also improves the accuracy of time measurement, resulting in a precise delay that can be used for time measurement. Furthermore, the signals directly involved in the correction process in the correction circuit are all low-frequency signals after frequency reduction, and the correction circuit uses N / 2 delay units, only half the number of units in the delay chain. Therefore, the power consumption and area footprint of the correction circuit are relatively low.

[0096] Optionally, the time measurement circuit includes a sampling circuit and an encoding circuit;

[0097] The sampling circuit is used to input the STOP signal into the sampling circuit; the sampling circuit samples the signal after each delay based on the STOP signal to obtain multiple delayed signals; the multiple delayed signals are stored in multiple registers;

[0098] The encoding circuit is used to read the delayed signals from multiple registers and measure the time based on the multiple delayed signals;

[0099] The sampling circuit is specifically used to drive the signal by the rising edge of the STOP signal, record the propagation state of the signal after each delay, and obtain multiple delayed signals.

[0100] The encoding circuit is specifically used to read the delayed signals in multiple registers and calculate the time difference between the STOP signal and the signal after each delay based on the multiple delayed signals; and to measure the time based on the time difference.

[0101] The process involves using the rising edge of the STOP signal to drive the sampling circuit and record the signal propagation state after each delay. The rising edge of the STOP signal drives the sampling circuit to record the propagation state after each delay, and the encoding circuit measures the time based on this propagation state. For example, the rising edge of the STOP signal drives the sampling circuit to record the signal state after each delay of the START signal. Specifically, the signal state after each delay of the START signal can be stored in a register, and the encoding circuit reads the signal from each register to calculate the time. For instance, the number of states 1 and 0 in each register can be read, and the time can be calculated based on the number of states 1 in the registers. For example, the current time can be calculated by multiplying the number of states 1 in the registers by the duration corresponding to the period.

[0102] In this embodiment, the delay duration of the delay chain is required to be greater than or equal to one clock cycle. Let N be the number of delay units in the delay chain, and let delay be the delay duration of each delay unit. If the clock signal period is T, then delay >= T / N. However, in this embodiment, to improve time measurement accuracy, the number of delay units in the delay chain is set to twice the number of delay units in a multi-stage delay chain. By using a delay correction signal to make the delay duration of the multi-stage delay units half a cycle, the delay duration of the delay chain can be made to be one cycle T, i.e., N*delay = T, delay = T / N. By ensuring the delay of the delay chain is precisely equal to one clock signal cycle, not only is the power consumption of the correction circuit low, but the correction effect is also good, achieving high-precision time measurement.

[0103] To illustrate the beneficial effects of the embodiments of this application, the following description is provided in conjunction with specific embodiments.

[0104] This solution uses CMOS 180nm process to build the circuit and simulates its function. See [link / reference] Figure 5a and Figure 5b The simulation describes the delay and changes in the delay correction signal of the multi-stage delay unit during the correction process. In the simulation, the clock signal frequency was selected as 500MHz with a period of 2ns. The frequency reduction factor was 32 times. The initial voltage amplitude of the delay correction signal was approximately 900mV.

[0105] from Figure 5a and Figure 5b As can be seen, the delays provided by the multi-stage delay units differ in the initial state under different process corners. Here, typ, ss, and ff represent different signals. After a period of time, the delays of the multi-stage delay units are all corrected to half a clock signal cycle, i.e., 1ns, and reach dynamic equilibrium. After dynamic equilibrium, the voltage amplitudes of the delay correction signals are 788mV (typ), 991mV (ss), and 301mV (ff), respectively. Due to the dynamic adjustment characteristics of the correction circuit, the delays provided by the multi-stage delay units will jitter around 1ns after dynamic equilibrium. Simulations show that, under different process corners, the delay jitter (RMS) after dynamic equilibrium is 0.86ps (typ), 0.91ps (ss), and 0.74ps (ff), respectively. The magnitude of the jitter is much smaller than the magnitude of the delay, so the jitter will not affect the accuracy of time measurement. The correction circuit has four multi-stage delay units, so each delay unit provides a delay of 250ps.

[0106] See Figure 6 A comparison of power consumption between circuits that perform correction without frequency reduction and those that perform correction using the frequency reduction method described in this paper. It can be seen that after a 32-fold frequency reduction, the power consumption of the correction circuit is significantly reduced, from 704uW to 52.8uW. The power consumption of the multi-stage delay unit is reduced by approximately 32 times.

[0107] A second aspect of this application provides a time-to-digital conversion method, see [link to previous section]. Figure 7 ,include:

[0108] Step S71: Receive clock signal and reverse clock signal;

[0109] Step S72: Down-clock the clock signal and the reverse clock signal to obtain the down-clocked clock signal and the down-clocked reverse clock signal.

[0110] Step S73: Generate a delay correction signal based on the down-frequency clock signal and the down-frequency inverted clock signal;

[0111] Step S74: Receive the START signal and the STOP signal;

[0112] Step S75: Delay the START signal multiple times according to the delay correction signal, and sample the signal after each delay using the STOP signal to obtain multiple delayed signals;

[0113] Step S76: Measure the time based on multiple delay signals.

[0114] Optionally, a delay correction signal is generated based on the down-clocked clock signal and the down-clocked inverse clock signal, including:

[0115] The down-frequency clock signal is delayed through multiple stages to obtain a delayed clock signal;

[0116] The delayed clock signal and the down-frequency reverse clock signal are compared for delay. The delay correction signal is calculated based on the delay comparison result. The delay correction signal is used to make the delay duration of the multi-stage delay unit half a cycle.

[0117] Optional, see details of the correction process. Figure 8 After the final adjustment reaches dynamic equilibrium, the delay provided by the multi-stage delay unit is precisely equal to 0.5*T, and the delay of each delay unit is T / N. The circuitry of each unit in the multi-stage delay unit within the correction circuit is identical to that of the delay unit in the delay chain within the time measurement circuit, but the number of units in the multi-stage delay unit is half the number of units in the delay chain. Therefore, the delay of the delay chain is precisely equal to one clock cycle, and the delay of each delay unit is T / N. In this way, we obtain a precise delay that can be used for time measurement. The signals directly involved in the correction process in the correction circuit are all low-frequency signals after frequency reduction. Furthermore, the correction circuit uses N / 2 delay units, only half the number of units in the delay chain, thus resulting in lower power consumption and area footprint.

[0118] Optionally, a delay comparison is performed between the delayed clock signal and the down-clocked inverse clock signal, and a delay correction signal is calculated based on the delay comparison result, including:

[0119] The delayed clock signal and the down-frequency inverted clock signal are input into the delay comparison circuit for delay comparison. When the delay duration of the delayed clock signal and the down-frequency inverted clock signal is greater than half a cycle, the voltage of the delay correction signal is reduced. When the delay duration of the delayed clock signal and the down-frequency inverted clock signal is less than half a cycle, the voltage of the delay correction signal is increased to obtain the corrected delay correction signal.

[0120] The corrected delay correction signal is fed back to the multi-stage delay unit, and the down-frequency clock signal is corrected by the multi-stage delay unit so that the delay duration of the delayed clock signal and the down-frequency inverse clock signal is half a cycle.

[0121] In one example, the number of times the START signal is delayed is twice the number of times the down-clocked clock signal is delayed.

[0122] Optionally, the START signal is delayed multiple times based on the delay correction signal, and the signal after each delay is sampled using the STOP signal to obtain multiple delayed signals, including:

[0123] The START signal is delayed multiple times based on the delay correction signal;

[0124] The signal after each delay of the START signal is sampled using the STOP signal to obtain multiple delayed signals, which are then buffered.

[0125] Time measurement of multiple delayed signals;

[0126] Read multiple cached delay signals and measure their time.

[0127] Optionally, the signal after each delay of the START signal is sampled using the STOP signal to obtain multiple delayed signals, which are then buffered, including:

[0128] The rising edge of the STOP signal is used as the sampling start signal. The propagation state of the signal after each delay of the START signal is recorded to obtain multiple delayed signals.

[0129] Read multiple buffered delay signals and measure their time, including:

[0130] Read multiple delayed signals and calculate the time difference between the STOP and START signals based on the multiple delayed signals;

[0131] Time is measured based on the time difference.

[0132] As can be seen, the time-to-digital conversion method provided in this application can generate a delay correction signal by down-converting the clock signal, and then use the generated delay correction signal to correct the delay duration in the delay chain, and then measure the time. Compared with direct correction using a high-frequency clock signal, the method in this application can not only significantly reduce the power consumption of the correction circuit, but also improve the PVT stability of the time measurement circuit.

[0133] A third aspect of the embodiments of this application, see [link to embodiment]. Figure 9 A time-to-digital conversion device is provided, comprising:

[0134] The clock signal receiving module 901 is used to receive clock signals and reverse clock signals;

[0135] The signal down-frequency module 902 is used to down-frequency the clock signal and the reverse clock signal to obtain the down-frequency clock signal and the down-frequency reverse clock signal.

[0136] The signal correction module 903 is used to generate a delay correction signal based on the down-frequency clock signal and the down-frequency inverse clock signal;

[0137] The start / stop signal receiving module 904 is used to receive START and STOP signals;

[0138] The signal delay module 905 is used to delay the START signal multiple times according to the delay correction signal, and to sample the signal after each delay through the STOP signal to obtain multiple delayed signals;

[0139] The time measurement module 906 is used to measure time based on multiple delay signals.

[0140] Optionally, the signal correction module 903 includes:

[0141] The multi-level delay submodule is used to perform multi-level delay on the down-frequency clock signal to obtain a delayed clock signal;

[0142] The delay comparison submodule is used to compare the delay clock signal and the down-frequency reverse clock signal, and calculate the delay correction signal based on the delay comparison result. The delay correction signal is used to make the delay duration of the multi-level delay unit half a cycle.

[0143] Optional, the delay comparison submodule includes:

[0144] The correction signal generation submodule is used to input the delayed clock signal and the down-frequency inverted clock signal into the delay comparison circuit for delay comparison. When the delay duration of the delayed clock signal and the down-frequency inverted clock signal is greater than half a cycle, the voltage of the delay correction signal is reduced. When the delay duration of the delayed clock signal and the down-frequency inverted clock signal is less than half a cycle, the voltage of the delay correction signal is increased to obtain the corrected delay correction signal.

[0145] The correction signal correction submodule is used to feed back the corrected delay correction signal to the multi-level delay unit, and to correct the down-frequency clock signal through the multi-level delay unit so that the delay duration of the delayed clock signal and the down-frequency inverse clock signal is half a cycle.

[0146] Optionally, the number of times the START signal is delayed is twice the number of times the down-frequency clock signal is delayed.

[0147] Optionally, the signal delay module 905 includes:

[0148] The delay correction submodule is used to delay the START signal multiple times based on the delay correction signal.

[0149] The signal sampling submodule is used to sample the signal after each delay of the START signal using the STOP signal, obtain multiple delayed signals, and buffer them.

[0150] The time measurement module is specifically used to read multiple buffered delay signals and measure their time.

[0151] Optional, the signal sampling submodule includes:

[0152] The state recording unit is used to take the rising edge of the STOP signal as the sampling start signal, record the propagation state of the signal after each delay of the START signal, and obtain multiple delayed signals.

[0153] Time measurement module 906 includes:

[0154] The time difference calculation submodule is used to read multiple delayed signals and calculate the time difference between the STOP signal and the START signal based on the multiple delayed signals;

[0155] The time measurement submodule is used to measure time based on time differences.

[0156] As can be seen, the time-to-digital converter provided in this application can reduce the frequency of the clock signal to generate a delay correction signal, and then use the generated delay correction signal to correct the delay duration in the delay chain, and then measure the time. Compared with direct correction using a high-frequency clock signal, the method in this application can not only significantly reduce the power consumption of the correction circuit, but also improve the PVT stability of the measurement accuracy of the time measurement circuit.

[0157] Another aspect of the embodiments of this application also provides an electronic device, including:

[0158] Any of the above time-to-digital converters.

[0159] In the above embodiments, implementation can be achieved entirely or partially through software, hardware, firmware, or any combination thereof. When implemented using software, it can be implemented entirely or partially in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, all or part of the processes or functions described in the embodiments of this application are generated. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, the computer instructions can be transmitted from one website, computer, server, or data center to another website, computer, server, or data center via wired (e.g., coaxial cable, fiber optic, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) means. The computer-readable storage medium can be any available medium that a computer can access or a data storage device such as a server or data center that integrates one or more available media. The available medium can be a magnetic medium (e.g., floppy disk, hard disk, magnetic tape), an optical medium (e.g., DVD), or a semiconductor medium (e.g., solid state disk (SSD)).

[0160] It should be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0161] The various embodiments in this specification are described in a related manner. Similar or identical parts between embodiments can be referred to mutually. Each embodiment focuses on describing the differences from other embodiments. In particular, the method embodiments are basically similar to the method embodiments, so the description is relatively simple; relevant parts can be referred to the descriptions of the method embodiments.

[0162] The above description is merely a preferred embodiment of this application and is not intended to limit the scope of protection of this application. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application are included within the scope of protection of this application.

Claims

1. A time-to-digital converter, characterized by, The time measurement circuit and the correction circuit are included. The correction circuit is configured to receive a clock signal and a reverse clock signal, input the clock signal and the reverse clock signal into a frequency reduction module to reduce the frequency, obtain a reduced clock signal and a reduced reverse clock signal, input the reduced clock signal into a multi-stage delay unit to obtain a delay clock signal, input the delay clock signal and the reduced reverse clock signal into a delay comparison circuit to perform delay comparison, and calculate a delay correction signal according to a delay comparison result, wherein the delay correction signal is used for feedback to the multi-stage delay unit, so that a delay time length of the delay clock signal and the reduced reverse clock signal is half a period. The time measurement circuit is configured to receive a START signal and a STOP signal, input the START signal into a delay chain, perform multiple times of delay according to the delay correction signal, the delay chain includes multiple delay units, sample a signal after each time of delay by the STOP signal to obtain multiple delay signals, and perform time measurement according to the multiple delay signals by an encoding circuit.

2. The time-to-digital converter of claim 1, wherein The correction circuit is specifically configured to input the delay clock signal and the reduced reverse clock signal into a delay comparison circuit to perform delay comparison, when a delay time length of the delay clock signal and the reduced reverse clock signal is greater than half a period, reduce a voltage of the delay correction signal, when the delay time length of the delay clock signal and the reduced reverse clock signal is less than half a period, increase the voltage of the delay correction signal, obtain a corrected delay correction signal, feedback the corrected delay correction signal to the multi-stage delay unit, and correct the reduced clock signal by the multi-stage delay unit, so that the delay time length of the delay clock signal and the reduced reverse clock signal is half a period.

3. The time-to-digital converter of claim 1, wherein A number of delay units in the delay chain is twice a number of delay units in the multi-stage delay unit.

4. The time-to-digital converter of claim 1, wherein The time measurement circuit includes a sampling circuit and an encoding circuit. The sampling circuit is configured to input the STOP signal into the sampling circuit, sample a signal after each time of delay by the sampling circuit according to the STOP signal to obtain multiple delay signals, and store the multiple delay signals in multiple registers. The encoding circuit is configured to read the delay signals in the multiple registers, and perform time measurement according to the multiple delay signals. The sampling circuit is specifically configured to drive by a rising edge of the STOP signal, record a propagation state of the signal after each time of delay to obtain the multiple delay signals. The encoding circuit is specifically configured to read the delay signals in the multiple registers, calculate a time difference between the STOP signal and the signal after each time of delay according to the multiple delay signals, and perform time measurement according to the time difference.

5. A time-to-digital conversion method, characterized by, The time-to-digital converter includes receive a clock signal and a reverse clock signal; down-clock the clock signal and the reverse clock signal to obtain a down-clocked clock signal and a down-clocked reverse clock signal; perform multi-stage delay on the down-clocked clock signal to obtain a delayed clock signal; perform delay comparison on the delayed clock signal and the down-clocked reverse clock signal, and calculate a delay correction signal according to a delay comparison result, wherein the delay correction signal is used to make the delay time of the multi-stage delay unit half a period; receive a START signal and a STOP signal; delay the START signal multiple times according to the delay correction signal, and sample each delayed signal of the START signal by the STOP signal to obtain multiple delay signals; measure time according to the multiple delay signals.

6. The method of claim 5, wherein, The delay comparison on the delayed clock signal and the down-clocked reverse clock signal, and the calculation of the delay correction signal according to the delay comparison result, comprises: input the delayed clock signal and the down-clocked reverse clock signal into a delay comparison circuit to perform delay comparison, when the delay time of the delayed clock signal and the down-clocked reverse clock signal is greater than half a period, decrease the voltage of the delay correction signal, when the delay time of the delayed clock signal and the down-clocked reverse clock signal is less than half a period, increase the voltage of the delay correction signal, and obtain a corrected delay correction signal; feedback the corrected delay correction signal to the multi-stage delay unit, and correct the down-clocked clock signal by the multi-stage delay unit, so that the delay time of the delayed clock signal and the down-clocked reverse clock signal is half a period.

7. The method of claim 5, wherein: the number of times of delaying the START signal is twice the number of times of multi-stage delaying the down-clocked clock signal.

8. The method of claim 5, wherein, The delaying the START signal multiple times according to the delay correction signal, and sampling each delayed signal of the START signal by the STOP signal to obtain multiple delay signals, comprises: delaying the START signal multiple times according to the delay correction signal; sampling each delayed signal of the START signal by the STOP signal to obtain multiple delay signals and cache them; The measuring time according to the multiple delay signals, comprises: reading the cached multiple delay signals and measuring time.

9. The method of claim 8, wherein, The sampling each delayed signal of the START signal by the STOP signal to obtain multiple delay signals and cache them, comprises: taking the rising edge of the STOP signal as a sampling start signal, and recording the propagation state of each delayed signal of the START signal to obtain multiple delay signals; The reading the cached multiple delay signals and measuring time, comprises: reading the multiple delay signals, and calculating the time difference between the STOP signal and the START signal according to the multiple delay signals; The time difference is used to measure time.

10. A time-to-digital conversion apparatus, characterized by comprising: The method comprises the steps of: receiving a clock signal and a reverse clock signal; reducing the frequency of the clock signal and the reverse clock signal to obtain a reduced clock signal and a reduced reverse clock signal; correcting the reduced clock signal by using a multi-stage delay sub-module and a delay comparison sub-module to obtain a delay clock signal and a delay correction signal, wherein the delay correction signal is used to make the delay time of the multi-stage delay unit half a period; receiving a START signal and a STOP signal; delaying the START signal multiple times according to the delay correction signal, and sampling the signal after each delay by using the STOP signal to obtain multiple delay signals; measuring time according to the multiple delay signals.

11. The apparatus of claim 10, wherein, The delay comparison sub-module comprises: a correction signal generation sub-module configured to input the delay clock signal and the reduced reverse clock signal into a delay comparison circuit for delay comparison, decrease the voltage of the delay correction signal when the delay time of the delay clock signal and the reduced reverse clock signal is greater than half a period, and increase the voltage of the delay correction signal when the delay time of the delay clock signal and the reduced reverse clock signal is less than half a period to obtain a corrected delay correction signal; a correction signal correction sub-module configured to feed back the corrected delay correction signal to the multi-stage delay unit, and correct the reduced clock signal by using the multi-stage delay unit to make the delay time of the delay clock signal and the reduced reverse clock signal half a period.

12. The apparatus of claim 10, wherein the number of times of delaying the START signal is twice the number of times of delaying the reduced clock signal.

13. The apparatus of claim 10, wherein, The signal delay module comprises: a correction delay sub-module configured to delay the START signal multiple times according to the delay correction signal; a signal sampling sub-module configured to sample the signal after each delay of the START signal by using the STOP signal to obtain multiple delay signals and store the multiple delay signals; The time measurement module is specifically configured to read the stored multiple delay signals and measure time.

14. The apparatus of claim 13, wherein, The signal sampling sub-module comprises: a state recording unit configured to record the propagation state of the signal after each delay of the START signal by using the rising edge of the STOP signal as a sampling start signal to obtain multiple delay signals; The time measurement module comprises: a time difference calculation sub-module configured to read the multiple delay signals and calculate the time difference between the STOP signal and the START signal according to the multiple delay signals. a time measurement sub-module for measuring time according to the time difference.

15. An electronic device, comprising: comprising: a time-to-digital converter according to any of claims 1-4.

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