Voltage suppression circuit

Abstract

The application provides a voltage suppression circuit, comprising a signal processing module, a power tube, a feedback module, a load module, a first clamping circuit and a second clamping circuit, the output end of the signal processing module is electrically connected with the gate electrode of the power tube, the drain electrode of the power tube is electrically connected with the input end of the feedback module, the output end of the feedback module is electrically connected with the first input end of the signal processing module, the second input end of the signal processing module inputs a reference voltage, the grounding end of the feedback module is grounded, the drain electrode of the power tube is also electrically connected with a voltage output end, one end of the load module is electrically connected with the drain electrode of the power tube, the other end of the load module is grounded, one end of the first clamping circuit and the second clamping circuit is electrically connected with the drain electrode of the power tube, the other end of the first clamping circuit and the source electrode of the power tube are both connected with an input power supply, and the other end of the second clamping circuit is grounded. The application can effectively suppress the overshoot and undershoot of the voltage and improve the stability of the output voltage.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of chip circuit design, and particularly relates to a voltage suppression circuit. BACKGROUND

[0002] Low-dropout regulator (LDO) is a very common power management module, which can provide stable voltage to a system or a module. However, when the LDO load current changes, the output voltage will have overshoot (when the current load changes from large to small) and undershoot (when the current load changes from small to large). If the overshoot voltage is too high, the system may be damaged, and if the overshoot voltage is too low, the system may not work, so how to suppress the overshoot and undershoot caused by the change of the current load is one of the key indicators of LDO design.

[0003] The mainstream methods of LDO power supply suppression enhancement at present include the following: the first method is to increase the output capacitor, use the charge sharing principle to reduce the overshoot and undershoot voltage, but this will affect the LDO stability or reduce the LDO bandwidth and slow down the response, and a large capacitor is needed, which wastes the chip area; the second method is to increase the discharge capacity of the feedback network to reduce the overshoot, but this will increase the LDO power consumption; the third method is to increase the bandwidth of the LDO to enable it to respond quickly, but this will not have obvious effect when the load changes quickly, such as nS level change, because the LDO bandwidth is in the order of MHz, and the change is not large; and this will increase the power consumption and affect the stability; the fourth method is to use NMOS power tube, which can help to improve the undershoot of the negative pulse signal, but this requires higher voltage to drive the NMOS gate, which may cause trouble to the system design.

[0004] Therefore, it is necessary to provide a new type of voltage suppression circuit to solve the above problems in the prior art. SUMMARY

[0005] The present application relates to the technical field of chip circuit design, and particularly relates to a voltage suppression circuit.

[0006] In order to achieve the above object, the voltage suppression circuit comprises a signal processing module, a power tube, a feedback module, a load module, a first clamping circuit and a second clamping circuit, the output end of the signal processing module is electrically connected with the gate of the power tube, the drain of the power tube is electrically connected with the input end of the feedback module, the output end of the feedback module is electrically connected with the first input end of the signal processing module, the second input end of the signal processing module inputs a reference voltage, and the ground end of the feedback module is grounded, the drain of the power tube is also electrically connected with a voltage output end, one end of the load module is electrically connected with the drain of the power tube, the other end of the load module is grounded, one end of the first clamping circuit and the second clamping circuit is electrically connected with the drain of the power tube, the other end of the first clamping circuit and the source of the power tube are both connected with an input power supply, and the other end of the second clamping circuit is grounded.

[0007] The voltage suppression circuit has the beneficial effects that the first clamping circuit and the second clamping circuit are added between the voltage output end and the drain of the power tube to suppress negative overshoot voltage and overshoot voltage respectively, so that the voltage output end of the whole circuit outputs stable voltage, and the first clamping circuit and the second clamping circuit do not work when the whole circuit normally works, so that the power consumption is not increased and the stability of the whole circuit is not affected.

[0008] Optionally, the first clamping circuit comprises a first resistor, a first capacitor and a PMOS tube, one end of the first resistor and one end of the first capacitor are both electrically connected with the gate of the PMOS tube, the other end of the first resistor and the source of the PMOS tube are both connected with the input power supply, and the other end of the first capacitor and the drain of the PMOS tube are both electrically connected with the drain of the power tube.

[0009] Optionally, the second clamping circuit comprises a second resistor, a second capacitor and an NMOS tube, one end of the second resistor and one end of the second capacitor are both electrically connected with the gate of the NMOS tube, the other end of the second resistor and the source of the NMOS tube are grounded, and the other end of the second capacitor and the drain of the NMOS tube are both electrically connected with the drain of the power tube.

[0010] Optionally, the load module comprises a load capacitor and a load resistor, one end of the load capacitor and one end of the load resistor are both grounded, and the other end of the load capacitor and the other end of the load resistor are both electrically connected with the drain of the power tube.

[0011] Optionally, the signal processing module is an error signal amplifier, the positive input end of the error signal amplifier is electrically connected with the output end of the feedback module, the negative input end of the error signal amplifier inputs the reference voltage, and the power supply end of the error signal amplifier is connected with the input power supply.

[0012] Optionally, the signal processing module comprises an operational amplifier or a filter. BRIEF DESCRIPTION OF DRAWINGS

[0013] Figure 1 Circuit diagram of LDO in prior art.

[0014] Figure 2 Voltage and current waveform diagram of overshoot and undershoot in LDO in prior art.

[0015] Figure 3 State diagram when undershoot occurs in LDO in prior art.

[0016] Figure 4 State diagram when overshoot occurs in LDO in prior art.

[0017] Figure 5 Overall structure block diagram of voltage suppression circuit according to the present application.

[0018] Figure 6 Circuit diagram of voltage suppression circuit according to the present application.

[0019] Figure 7 Voltage and current waveform diagram of overshoot and undershoot in voltage suppression circuit according to the present application. DETAILED DESCRIPTION

[0020] In order to make the objects, technical solutions and advantages of the present application clearer, the technical solutions in the embodiments of the present application will be described below in connection with the drawings of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without any creative work fall within the protection scope of the present application. Unless otherwise defined, the technical terms or scientific terms used herein should be understood as the common meanings by those of ordinary skill in the art to which the present application belongs. The words such as “comprise” and the like used herein mean that the elements or objects before the words cover the elements or objects listed after the words and their equivalents, without excluding other elements or objects.

[0021] In prior art, a conventional low-dropout linear regulator (LDO) has a circuit diagram as shown in Figure 1 , which comprises an error signal amplifier A, a power transistor Mp, a feedback module F, a resistor R L and a capacitor C L , wherein the negative input end of the error signal amplifier A inputs a reference voltage V refThe power supply terminal is connected to the input power supply, and its output terminal is electrically connected to the gate of the power transistor Mp to output voltage V1. The drain of the power transistor Mp is electrically connected to the input terminal and voltage output terminal Vout of the feedback module F. The output terminal of the feedback module F is electrically connected to the positive input terminal of the error signal amplifier A to output voltage V1. fb The input is to the error signal amplifier A, the source of the power transistor Mp is connected to the input power supply, and the resistor R... L One end and capacitor C L One end is grounded, and the resistance is R. L The other end and capacitor C L The other end is electrically connected to the voltage output terminal Vout.

[0022] However, regarding Figure 1 The circuit in the middle, but when the LDO load current I L When the current load changes, the output voltage may experience overshoot (when the current load decreases) and undershoot (when the current load increases). (Refer to...) Figure 2 If the overshoot voltage is too high, it may damage the system; if the overshoot voltage is too low, the system may not work.

[0023] Specifically, when the load current of an LDO changes, the rate of change is typically very fast, on the order of nanoseconds. Since the bandwidth of an LDO is generally in the MHz range, its response time cannot keep up with the instantaneous load change. Figure 1 When a negative impulse occurs in the circuit, refer to Figure 3 When the load current has a step change, from I L1 Instantly rose to I L2 Because the LDO's response speed cannot keep up, the current Ic1 provided by the power transistor Mp is insufficient to compensate for the change in load current (I L2 -I L1 A transient undershoot will occur, and at the same time, charge sharing will occur in the load capacitor, resulting in a current I. C2 According to the principle of charge sharing, the larger the capacitance, the smaller the negative voltage. And when... Figure 1 When an overshoot occurs in the circuit, refer to Figure 4 When the load current has a step change, from I L2 Instantly dropped to I L1 Because the LDO's response speed cannot keep up, and the feedback module F has limited leakage capacity, it can only handle a portion of the current I. D1 And excess current I D2 It will be injected into the load capacitor C L This results in an overshoot phenomenon. According to the principle of charge sharing, the larger the capacitance value, the smaller the overshoot voltage value.

[0024] Embodiments of the present application provide a voltage suppression circuit to solve the problems in the prior art Figure 5 , comprising a signal processing module 51, a power tube 52, a feedback module 53, a load module 54, a first clamping circuit 55 and a second clamping circuit 56, an output end of the signal processing module 51 is electrically connected with a gate of the power tube 52, a drain of the power tube 52 is electrically connected with an input end of the feedback module 53, an output end of the feedback module 53 is electrically connected with a first input end of the signal processing module 51 to output a voltage V fb , a second input end of the signal processing module 51 inputs a reference voltage V ref , and a ground end of the feedback module 53 is grounded Gnd, the drain of the power tube 52 is also electrically connected with a voltage output end Vout, one end of the load module 54 is electrically connected with the drain of the power tube 52, the other end of the load module 54 is grounded Gnd, one end of the first clamping circuit 55 and the second clamping circuit 56 is electrically connected with the drain of the power tube 52, the other end of the first clamping circuit 55 and a source of the power tube 52 are both connected with an input power Vin, and the other end of the second clamping circuit 56 is grounded Gnd.

[0025] In the embodiment, by connecting the first clamping circuit 55 and the second clamping circuit 56 between the power output end Vout and the ground and the input power Vin respectively, the normal work and stability of the whole circuit are not affected, the static power consumption is not increased, and only when overvoltage and negative voltage occur, the circuit works, so that the overvoltage and negative voltage of the circuit are effectively suppressed, and the stability of the final output voltage is improved.

[0026] In some embodiments, referring to FIG. Figure 6, the first clamping circuit 55 includes a first resistor 551, a first capacitor 552 and a PMOS tube 553, one end of the first resistor 551 and one end of the first capacitor 552 are electrically connected to the gate of the PMOS tube 553, the other end of the first resistor 551 and the source of the PMOS tube 553 are connected to the input power Vin, the other end of the first capacitor 552 and the drain of the PMOS tube 553 are electrically connected to the drain of the power tube 52; the second clamping circuit 56 includes a second resistor 561, a second capacitor 562 and an NMOS tube 563, one end of the second resistor 561 and one end of the second capacitor 562 are electrically connected to the gate of the NMOS tube 563, the other end of the second resistor 561 and the source of the NMOS tube 563 are connected to the ground Gnd, the other end of the second capacitor 562 and the drain of the NMOS tube 563 are electrically connected to the drain of the power tube 52, the load module 54 includes a load capacitor 541 and a load resistor 542, one end of the load capacitor 541 and one end of the load resistor 542 are connected to the ground Gnd, the other end of the load capacitor 541 and the other end of the load resistor 542 are electrically connected to the drain of the power tube 52.

[0027] In some embodiments, the signal processing module 51 is an error signal amplifier, the positive input end of the error signal amplifier is electrically connected to the output end of the feedback module 53, the negative input end of the error signal amplifier inputs the reference voltage V ref , the power supply end of the error signal amplifier is connected to the input power Vin, thereby forming a low dropout linear regulator LDO to output a stable voltage.

[0028] For example, the LDO with the signal processing module 51 as an error signal amplifier is described, the first clamping circuit 55 includes a first resistor 551, a first capacitor 552 and a PMOS tube 553, and the second clamping circuit 56 includes a second resistor 561, a second capacitor 562 and an NMOS tube 563, wherein the resistance and capacitance determine the response speed and working time of the clamping circuit, and the PMOS tube 553 and the NMOS tube 563 generate compensation current when the load current step changes.

[0029] When the LDO works normally, that is, the load current does not change, at this time, because Vout does not change, the first capacitor 552 and the second capacitor 562 in the clamping circuit are both in the off state, the PMOS tube 553 and the NMOS tube 563 are connected to the power supply and the ground by the first resistor 551 and the second resistor 561, the gate-source voltage is 0, which is equivalent to the off state, that is, the circuit has no any effect and no extra power consumption.

[0030] Reference Figure 7 When the load current I LWhen the voltage jumps, the negative impulse at the voltage output terminal Vout decreases, at which point the first clamping circuit 55 starts to operate. Because it is a transient signal, the first capacitor 552 in the first clamping circuit 55 is approximately short-circuited, and the gate voltage V of the PMOS transistor 553... CH Following the change in Vout, a negative gate-source voltage is generated across the PMOS transistor 553. At this time, the PMOS transistor 553 turns on, and the output current compensates for the sudden increase in load current, thereby suppressing the negative voltage surge. Afterwards, the voltage V... CH The voltage will recover to the power supply voltage according to the time constant formed by the first resistor 551 and the first capacitor 552. The PMOS transistor 553 will return to the off state and there will be no current output. During the period when the first clamping circuit 55 is working until it is turned off, the LDO reacts and ultimately undertakes the modulation of the output voltage.

[0031] When the load current I L When the voltage drops by a step, the voltage output Vout overshoots and goes high, at which point the second clamping circuit 56 starts working. Because it is a transient signal, the second capacitor 562 in the second clamping circuit 56 is approximately short-circuited, and the gate voltage V of the NMOS transistor 563... CL Following the change in Vout, a positive gate-source voltage is generated on NMOS transistor 563. At this time, NMOS transistor 563 conducts, pulling down the current to compensate for the sudden decrease in load current, thereby suppressing overshoot voltage. Afterwards, NMOS transistor 563 recovers to the supply voltage according to the time constant formed by the second resistor 561 and the second capacitor 562, and NMOS transistor 563 returns to the off state without pulling down the current. During the period from the operation to the shutdown of the second clamping circuit 56, the LDO reacts simultaneously and ultimately undertakes the modulation of the output voltage. Moreover, due to the conduction principle of PMOS and NMOS, the first clamping circuit 55 and the second clamping circuit 56 will not operate simultaneously.

[0032] In some embodiments, the signal processing module 51 includes an operational amplifier or a filter to suppress overshoot and undershoot at the output of the operational amplifier or filter, thereby improving the stability of the output result.

[0033] This invention adds a first clamping circuit and a second clamping circuit between the voltage output terminal and the drain of the power transistor to suppress negative and overshoot voltages respectively, resulting in a stable voltage output at the entire circuit. Moreover, the first and second clamping circuits do not operate during normal circuit operation, thus avoiding unnecessary power consumption and maintaining the stability of the entire circuit. Based on the traditional LDO architecture, overshoot and negative suppression are achieved by adding a first clamping circuit 55 and a second clamping circuit 56. The circuit structure is simple and can effectively improve overshoot and negative suppression.

[0034] While the embodiments of the application have been illustrated and described in detail, it will be readily apparent to those skilled in the art that various modifications and changes can be made to the embodiments without departing from the scope and spirit of the application, as described in the claims. Moreover, the application described is not limited in its application to the details set forth in the description or illustrated in the drawings. The application is capable of other embodiments and of being practiced or carried out in various ways.

Claims

1. A voltage suppression circuit, characterized by, The circuit comprises a signal processing module, a power tube, a feedback module, a load module, a first clamping circuit and a second clamping circuit, an output end of the signal processing module is electrically connected with a gate electrode of the power tube, a drain electrode of the power tube is electrically connected with an input end of the feedback module, an output end of the feedback module is electrically connected with a first input end of the signal processing module, a second input end of the signal processing module inputs a reference voltage, and a grounding end of the feedback module is grounded, the drain electrode of the power tube is also electrically connected with a voltage output end, one end of the load module is electrically connected with the drain electrode of the power tube, the other end of the load module is grounded, one end of the first clamping circuit and the second clamping circuit is electrically connected with the drain electrode of the power tube, the other end of the first clamping circuit and a source electrode of the power tube are both connected with an input power supply, and the other end of the second clamping circuit is grounded. The first clamping circuit comprises a first resistor, a first capacitor and a PMOS tube, one end of the first resistor and one end of the first capacitor are both electrically connected with a gate electrode of the PMOS tube, the other end of the first resistor and a source electrode of the PMOS tube are both connected with the input power supply, and the other end of the first capacitor and a drain electrode of the PMOS tube are both electrically connected with the drain electrode of the power tube. The second clamping circuit comprises a second resistor, a second capacitor and an NMOS tube, one end of the second resistor and one end of the second capacitor are both electrically connected with a gate electrode of the NMOS tube, the other end of the second resistor and a source electrode of the NMOS tube are grounded, and the other end of the second capacitor and a drain electrode of the NMOS tube are both electrically connected with the drain electrode of the power tube. The load module comprises a load capacitor and a load resistor, one end of the load capacitor and one end of the load resistor are both grounded, and the other end of the load capacitor and the other end of the load resistor are both electrically connected with the drain electrode of the power tube.

2. The voltage suppression circuit of claim 1, wherein, The signal processing module is an error signal amplifier, a positive input end of the error signal amplifier is electrically connected with the output end of the feedback module, a negative input end of the error signal amplifier inputs the reference voltage, and a power supply end of the error signal amplifier is connected with the input power supply.

3. The voltage suppression circuit of claim 1, wherein, The signal processing module comprises an operational amplifier or a filter.

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