LDO circuit with high-voltage start-up suitable for at_af protocol chip

Abstract

The application provides an LDO circuit with high-voltage starting suitable for an AT_AF protocol chip, which comprises a band gap comparator for monitoring an input voltage and generating an enable signal when the voltage exceeds a first predetermined value; a clamping circuit combined with a current limiting resistor for clamping a gate voltage alone when the input voltage is less than the first predetermined value, so that a power supply voltage inside the chip is kept at a second predetermined value; and a low-dropout linear regulator (LDO) for precisely controlling the power supply voltage inside the chip by controlling the gate voltage under the action of the enable signal and improving the power supply rejection ratio performance and dynamic response performance of the power supply. The circuit of the application can effectively reduce the whole machine standby power consumption and reduce the circuit complexity, and can provide a higher power supply rejection ratio and higher precision and fast response power supply for the chip inside while meeting the low power consumption and high precision voltage monitoring requirements of the AT_AF system.

Description

Technical Field

[0001] This invention belongs to the field of Ethernet chip technology, specifically relating to an LDO circuit with high-voltage startup suitable for AT_AF protocol chips. Background Technology

[0002] Ethernet chips are one of the most important components of Ethernet. Figure 1 This is the voltage waveform of the PSE (Power Sourcing Equipment) supplying power to the PD (Powered Device) in accordance with the IEEE 802.3af / at standard for PoE (Power Over Ethernet) systems. When the supply voltage is less than 10.1V, the PD device should start operating with extremely low current consumption, typically much less than 10uA. When the supply voltage is higher than 11.5V, the chip should be able to immediately recognize and start operating.

[0003] To achieve Ethernet functionality, traditional chips typically employ methods such as... Figure 2 Architecture. In Figure 2 The circuit requires at least two power supplies to power the reference and comparator separately, increasing circuit size and power consumption. The power supply accuracy of the first stage is uncontrollable, and the power supply ripple rejection ratio (PSRR) is poor, especially in PoE systems where power supply fluctuations are significant, making load noise easily transmitted to the reference. Furthermore, both the first and second stage power supply modules need to be started in advance to monitor the 10.1V threshold of the power supply in real time, increasing standby power consumption and circuit size. Adopting a low-power design for this purpose, however, degrades the anti-interference performance and dynamic response capability of the reference and LDO. Summary of the Invention

[0004] To address the aforementioned problems in the prior art, this invention provides an LDO with high-voltage startup suitable for AT_AF protocol chips. The technical problem to be solved by this invention is achieved through the following technical solution:

[0005] This invention provides an LDO circuit with high-voltage startup suitable for AT_AF protocol chips, comprising: a bandgap comparator, a clamping circuit, a current-limiting resistor, and a low-dropout linear regulator (LDO).

[0006] A bandgap comparator is used to monitor the input voltage and generate an enable signal when the input voltage exceeds a first predetermined value.

[0007] The clamping circuit, in conjunction with the current-limiting resistor, is used to clamp the gate voltage separately when the input voltage is less than a first predetermined value, so that the power supply voltage inside the chip is maintained at a second predetermined value.

[0008] Low dropout linear regulators (LDOs) are used to precisely control the internal power supply voltage of a chip by controlling the gate voltage under the action of an enable signal.

[0009] Optionally, the bandgap comparator includes: transistors: QN1, QN2; MOSFETs: PM1, PM2; resistors: R3, R4, R5, R6;

[0010] In this configuration, the bases of QN1 and QN2, the first terminal of R3, and the first terminal of R4 are connected, and the second terminal of R3 is connected to the input voltage VIN. The collector of QN1 is connected to the drain and gate of PM1 and the gate of PM2. The emitter of PM1 is connected to the first terminal of R5. The second terminal of R5 and the first terminal of R6 are connected to the emitter of QN2. The collector of QN2 is connected to the drain of PM2 and outputs the enable signal EN. The source of PM1 is connected to the source of PM2 and connected to the power supply VDD. The second terminals of R4 and R6 are both grounded (GND).

[0011] Optionally, the clamping circuit includes: diode: Z0; switch: K1; inverter: A0;

[0012] The A0 input terminal is connected to the enable signal EN, the output terminal is connected to the control terminal of K1, the first terminal of K1 is grounded, the second terminal is connected to the input terminal of Z0, the output terminal of Z0 is connected to the first terminal of the current limiting resistor R0, and the second terminal of the current limiting resistor R0 is connected to the second terminal of R3.

[0013] Optionally, the low dropout linear regulator (LDO) includes: a bandgap reference module; MOSFETs: PM3, PM4, NM1, NM2, NM3, NM4, PM5, and PM6; a bias current source: IBIAS; a voltage conversion MOSFET: HVNMOS; and a switch: K2.

[0014] In this configuration, the drain of the HVNMOS is connected to the input voltage VIN, and its gate is connected to the first terminal of the current-limiting resistor R0, the output terminal of Z0, the drain of PM6, and the drain of NM4. The source of the HVNMOS is connected to the power supply VDD and the first terminal of R1. The second terminal of R1 is connected to the gate of PM3 and the first terminal of R2. The sources of PM3 and PM4 are connected to IBIAS. The drain of PM3 is connected to the drain and gate of NM2 and the gate of NM1. The drain of NM1 is connected to the drain and gate of PM5 and the gate of PM5 and PM6. The sources of PM5 and PM6 are connected together. The input voltage VIN is connected; the drain of PM6 is connected to the drain of NM4 and the gate of HVNMOS, and the gate of NM4 is connected to the gate and drain of NM3 and the drain of PM4; the gate of PM4 is connected to the reference voltage vref; the second end of R2 is connected to the first end of K2, the control end of K2 is connected to the enable signal EN, and the second end of K2, the source of NM1, the source of NM3, the source of NM4 and the source of NM4 are all grounded to GND; the first end of the bandgap reference module is connected to the enable signal EN, the second end is connected to the power supply VDD, the third end is connected to the bias current source, and the fourth end is connected to the reference voltage vref.

[0015] Optionally, the first predetermined value is 10.1V, and the second predetermined value is VZ0-VGS, where VZ0 is the predetermined voltage of Z0 and VGS is the gate-source voltage of the HVNMOS.

[0016] Beneficial effects:

[0017] This invention provides an LDO circuit with high-voltage startup suitable for AT_AF protocol chips, comprising: a bandgap comparator for monitoring the input voltage and generating an enable signal when the voltage exceeds a first predetermined value; a clamping circuit combined with a current-limiting resistor for clamping the gate voltage separately when the input voltage is less than the first predetermined value, so that the power supply voltage inside the chip is maintained at a second predetermined value; and a low-dropout linear regulator (LDO) for precisely controlling the power supply voltage inside the chip by controlling the gate voltage under the action of the enable signal, thereby improving the power supply rejection ratio (PSRR) and dynamic response performance of the power supply. This circuit can effectively reduce the standby power consumption of the entire system and reduce circuit complexity. While meeting the requirements of the AT_AF system for low power consumption and high-precision voltage monitoring, it can provide the chip with a higher PSRR, higher precision, and faster response power supply.

[0018] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments. Attached Figure Description

[0019] Figure 1 This is the voltage waveform of the power supply from the PSE to the PD terminal of the electrical device in the existing technology;

[0020] Figure 2This is a schematic diagram of the structure of a traditional chip;

[0021] Figure 3 This invention provides an LDO circuit with high-voltage startup suitable for AT_AF protocol chips. Detailed Implementation

[0022] The present invention will be further described in detail below with reference to specific embodiments, but the implementation of the present invention is not limited thereto.

[0023] like Figure 3 As shown, this invention provides an LDO circuit with high-voltage startup suitable for AT_AF protocol chips, comprising:

[0024] Bandgap comparator, clamping circuit, current limiting resistor, and low dropout linear regulator (LDO);

[0025] A bandgap comparator is used to monitor the input voltage and generate an enable signal when the input voltage exceeds a first predetermined value.

[0026] The clamping circuit, in conjunction with the current-limiting resistor, is used to clamp the gate voltage separately when the input voltage is less than a first predetermined value, so that the power supply voltage inside the chip is maintained at a second predetermined value.

[0027] Low dropout linear regulators (LDOs) are used to precisely control the internal power supply voltage of a chip by controlling the gate voltage under the action of an enable signal.

[0028] Continued reference Figure 3 The bandgap comparator includes: transistors QN1 and QN2; MOSFETs PM1 and PM2; resistors R3, R4, R5, and R6; the bases of QN1 and QN2, the first terminal of R3, and the first terminal of R4 are connected, and the second terminal of R3 is connected to the input voltage VIN; the collector of QN1 is connected to the drain and gate of PM1 and the gate of PM2; the emitter of PM1 is connected to the first terminal of R5; the second terminal of R5 and the first terminal of R6 are connected to the emitter of QN2; the collector of QN2 is connected to the drain of PM2 and outputs an enable signal EN; the source of PM1 is connected to the source of PM2 and connected to the power supply VDD; the second terminals of R4 and R6 are both grounded (GND).

[0029] The clamping circuit includes: diode: Z0; switch: K1; inverter: A0;

[0030] The A0 input terminal is connected to the enable signal EN, the output terminal is connected to the control terminal of K1, the first terminal of K1 is grounded, the second terminal is connected to the input terminal of Z0, the output terminal of Z0 is connected to the first terminal of the current limiting resistor R0, and the second terminal of the current limiting resistor R0 is connected to the second terminal of R3.

[0031] The low dropout linear regulator (LDO) includes: a bandgap reference module; MOSFETs: PM3, PM4, NM1, NM2, NM3, NM4, PM5, and PM6; a bias current source: IBIAS; a voltage conversion MOSFET: HVNMOS; and a switch: K2.

[0032] In this configuration, the drain of the HVNMOS is connected to the input voltage VIN, and its gate is connected to the first terminal of the current-limiting resistor R0, the output terminal of Z0, the drain of PM6, and the drain of NM4. The source of the HVNMOS is connected to the power supply VDD and the first terminal of R1. The second terminal of R1 is connected to the gate of PM3 and the first terminal of R2. The sources of PM3 and PM4 are connected to IBIAS. The drain of PM3 is connected to the drain and gate of NM2 and the gate of NM1. The drain of NM1 is connected to the drain and gate of PM5 and the gate of PM5 and PM6. The sources of PM5 and PM6 are connected together. The input voltage VIN is connected; the drain of PM6 is connected to the drain of NM4 and the gate of HVNMOS, and the gate of NM4 is connected to the gate and drain of NM3 and the drain of PM4; the gate of PM4 is connected to the reference voltage vref; the second end of R2 is connected to the first end of K2, the control end of K2 is connected to the enable signal EN, and the second end of K2, the source of NM1, the source of NM3, the source of NM4 and the source of NM4 are all grounded to GND; the first end of the bandgap reference module is connected to the enable signal EN, the second end is connected to the power supply VDD, the third end is connected to the bias current source, and the fourth end is connected to the reference voltage vref.

[0033] It is worth noting that: the first predetermined value is 10.1V, the second predetermined value is VZ0-VGS, where VZ0 is the predetermined voltage of Z0, VGS is the gate-source voltage of HVNMOS, and the third predetermined value is VZ0.

[0034] The working principle of the low-dropout linear regulator of the present invention is explained below.

[0035] In this invention, PM1, PM2, QN1, QN2, R3, R4, R5, and R6 together constitute a bandgap comparator, such as... Figure 3 As shown, its function is to generate a logic enable signal when HV_VIN exceeds 10.1V, which enables subsequent modules such as the bandgap reference BANDGAP to start working.

[0036] PM3, PM4, NM1, NM2, NM3, NM4, PM5, PM6, IBIAS, and HVNMOS form an LDO. After BANGAP startup, this LDO precisely modulates the gate voltage of the HVNMOS transistor, thereby precisely controlling the VDD voltage and maintaining it at a set threshold value regardless of dynamic changes in the power supply or internal modules. This VDD power supply can power all modules within the chip.

[0037] R0 and Z0 are used by the HVNMOS to convert high voltage to low voltage to generate the VDD power supply. The HVNMOS is a high-voltage NMOS, R0 is a current-limiting resistor, and the Z0 circuit acts as a clamp to limit the gate voltage of the HVNMOS to a preset VZ0 voltage. VGS is the gate-source voltage of the HVNMOS device. Before the VIN power supply is less than 10.1V, switch K1 is turned on, and the VDD voltage is maintained between VZ0 and VGS, which is sufficient for the bandgap comparator to operate normally. When VIN exceeds 10.1V, switch K1 is turned off, and the gate voltage of the HVNMOS is controlled by a low-dropout linear regulator (LDO).

[0038] The bandgap comparator of this invention has a simple structure. Extremely low current loss can be achieved simply by increasing the resistance value, fully meeting the low power consumption requirements of AF / AT systems. Furthermore, after enabling the LDO, the LDO provides power to the reference and other core modules, leveraging its high PSRR performance to enhance the anti-interference capability of the core modules and the dynamic response capability of the chip.

[0039] This invention provides an LDO circuit with high-voltage startup suitable for AT_AF protocol chips, comprising: a bandgap comparator for monitoring the input voltage and generating an enable signal when the voltage exceeds a first predetermined value; a clamping circuit combined with a current-limiting resistor for clamping the gate voltage separately when the input voltage is less than the first predetermined value, so that the power supply voltage inside the chip is maintained at a second predetermined value; and a low-dropout linear regulator (LDO) for precisely controlling the power supply voltage inside the chip by controlling the gate voltage under the action of the enable signal, thereby improving the power supply rejection ratio (PSRR) and dynamic response performance of the power supply. This circuit can effectively reduce the standby power consumption of the entire system and reduce circuit complexity. While meeting the requirements of the AT_AF system for low power consumption and high-precision voltage monitoring, it can provide the chip with a higher PSRR, higher precision, and faster response power supply.

[0040] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified.

[0041] Although this application has been described herein in conjunction with various embodiments, those skilled in the art will understand and implement other variations of the disclosed embodiments by reviewing the accompanying drawings, the disclosure, and the appended claims in carrying out the claimed application. In the claims, the word "comprising" does not exclude other components or steps, and "a" or "an" does not exclude a plurality.

[0042] The above description, in conjunction with specific preferred embodiments, provides a further detailed explanation of the present invention. It should not be construed that the specific implementation of the present invention is limited to these descriptions. For those skilled in the art, various simple deductions or substitutions can be made without departing from the concept of the present invention, and all such modifications and substitutions should be considered within the scope of protection of the present invention.

Claims

1. An LDO circuit with high-voltage startup suitable for AT_AF protocol chips, characterized in that, include: Bandgap comparator, clamping circuit, current limiting resistor, and low dropout linear regulator (LDO); The bandgap comparator is used to monitor the input voltage and generate an enable signal when the input voltage exceeds a first predetermined value; The clamping circuit, in conjunction with the current-limiting resistor, is used to clamp the gate voltage separately when the input voltage is less than a first predetermined value, so that the power supply voltage inside the chip is maintained at a second predetermined value. Low dropout linear regulators (LDOs) are used to precisely control the internal power supply voltage of a chip by controlling the gate voltage under the action of an enable signal. The bandgap comparator includes: transistors: QN1, QN2; MOSFETs: PM1, PM2; resistors: R3, R4, R5, R6; In this configuration, the bases of QN1 and QN2, the first terminal of R3, and the first terminal of R4 are connected, and the second terminal of R3 is connected to the input voltage (VIN). The collector of QN1 is connected to the drain and gate of PM1 and the gate of PM2. The emitter of PM1 is connected to the first terminal of R5. The second terminal of R5 and the first terminal of R6 are connected to the emitter of QN2. The collector of QN2 is connected to the drain of PM2 and outputs an enable signal (EN). The source of PM1 is connected to the source of PM2 and connected to the power supply (VDD). The second terminals of R4 and R6 are both grounded (GND). The clamping circuit includes: diode: Z0; switch: K1; inverter: A0; The A0 input terminal is connected to the enable signal (EN), the output terminal is connected to the control terminal of K1, the first terminal of K1 is grounded, the second terminal is connected to the input terminal of Z0, the output terminal of Z0 is connected to the first terminal of the current limiting resistor (R0), and the second terminal of the current limiting resistor (R0) is connected to the second terminal of R3.

2. The LDO circuit with high-voltage startup suitable for AT_AF protocol chips according to claim 1, characterized in that, The low dropout linear regulator (LDO) includes: a bandgap reference module; MOSFETs: PM3, PM4, NM1, NM2, NM3, NM4, PM5, and PM6; a bias current source: IBIAS; a voltage conversion MOSFET: HVNMOS; and a switch: K2. In this configuration, the drain of the HVNMOS is connected to the input voltage (VIN), and its gate is connected to the first terminal of the current-limiting resistor (R0), the output terminal of Z0, the drain of PM6, and the drain of NM4. The source of the HVNMOS is connected to the power supply (VDD) and the first terminal of R1. The second terminal of R1 is connected to the gate of PM3 and the first terminal of R2. The sources of PM3 and PM4 are connected to IBIAS. The drain of PM3 is connected to the drain and gate of NM2 and the gate of NM1. The drain of NM1 is connected to the drain, gate of PM5, and gate of PM6. The sources of PM5 and PM6 are connected together and connected to the input voltage. Input voltage (VIN); The drain of PM6 is connected to the drain of NM4 and the gate of HVNMOS, and the gate of NM4 is connected to the gate and drain of NM3 and the drain of PM4; The gate of PM4 is connected to the reference voltage (vref); The second terminal of R2 is connected to the first terminal of K2, and the control terminal of K2 is connected to the enable signal (EN). The second terminal of K2, the source of NM1, the source of NM3, the source of NM4, and the source of NM4 are all grounded (GND); The first terminal of the bandgap reference module is connected to the enable signal (EN), the second terminal is connected to the power supply (VDD), the third terminal is connected to the bias current source, and the fourth terminal is connected to the reference voltage (vref).

3. The LDO circuit with high-voltage startup suitable for AT_AF protocol chips according to claim 1, characterized in that, The first predetermined value is 10.1V, and the second predetermined value is VZ0-VGS, where VZ0 is the predetermined voltage of Z0 and VGS is the gate-source voltage of the HVNMOS.

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