A linear voltage regulator applied to three-dimensional memory

Abstract

This invention provides a linear regulator for a three-dimensional memory, comprising: an LDO main circuit module and a bias module; the LDO main circuit module generates an output voltage; the bias module is connected to the output of the LDO main circuit module and generates a bias voltage for the LDO main circuit module; wherein, when the output voltage of the LDO main circuit module increases or decreases, the LDO main circuit module can restore the output voltage to a static stable value. This invention improves transient response performance and reduces the size of the power transistor.

Description

Technical Field

[0001] This invention relates to the field of integrated circuits, and more specifically to a linear regulator for use in three-dimensional memory. Background Technology

[0002] With the continuous advancement of integrated circuit technology, traditional non-volatile memories, such as flash memory, are experiencing serious reliability issues as feature sizes shrink. New types of memories, including phase-change memory (PCM), resistive random access memory (RRAM), and magnetic random access memory (MRRAM), offer significant advantages in speed, power consumption, and 3D integration capability. Chips such as 3D phase-change memory (3D-PCM) and 3D resistive random access memory (3D-RRAM) achieve 4F (four-dimensional) integration thanks to their 3D structures. 2 The ultra-high density of 3D memory has become a popular research direction for breaking through the bottleneck of Moore's Law, and has broad application prospects in fields such as replacing traditional non-volatile memory, in-memory computing, and information security. Because the gating devices used in 3D memory, such as bidirectional threshold switches, are bidirectional, special biasing methods such as V / 2 are required to achieve correct read and write operations in 3D memory. The V / 2 biasing method, for example... Figure 1 As shown, taking a read operation as an example, when the memory performs a read operation, all bit lines and word lines are biased at V before the read pulse arrives. read / 2, When the read pulse arrives, quickly switch the selected bit line or word line to V. read Alternatively, if 0 is selected, the offset of the unselected character line and bit line remains unchanged. To ensure faster reading speed and higher reading accuracy, V is provided. read Circuit modules with a / 2 bias voltage must have excellent transient characteristics when facing extremely fast load current switching speeds.

[0003] Low-dropout linear regulators (LDOs) offer advantages such as low ripple, low noise, and small size, making them suitable for implementing special biases in 3D memory. Currently, traditional LDOs are mainly divided into two categories: those with and without external capacitors. While the former has excellent transient characteristics, it requires additional pins in the SoC chip to connect to external capacitors, significantly reducing chip integration density. LDOs without external capacitors are currently a popular research direction, but traditional LDO structures generate large overshoots when the load current changes rapidly, making them unsuitable for the transient characteristics required by 3D memory. To improve the transient characteristics of LDOs, FVF (Flipped Voltage Follower) structure LDO circuits without external capacitors have been proposed. Many of these circuits utilize large on-chip capacitors of several hundred picofarads, using the output node as the dominant pole to achieve loop stability and high transient characteristics. This severely degrades the chip area and significantly limits the range of load capacitance. Some other FVFs set the output terminal as a non-dominant pole of the loop, saving a significant amount of on-chip capacitor area, but resulting in weak load capacitance and poor transient characteristics. Existing technologies for providing V / 2 bias for three-dimensional vertical memory suffer from problems such as poor transient characteristics, inability to be integrated on-chip, large area, and poor load-carrying capacity.

[0004] Therefore, it is necessary to provide a novel linear regulator for three-dimensional memory to solve the above-mentioned problems in the prior art. Summary of the Invention

[0005] The purpose of this invention is to propose a linear regulator for three-dimensional memory, which solves the problems of poor transient characteristics, inability to be integrated on-chip, and large area of ​​existing technologies.

[0006] To achieve the above objectives, the present invention provides a linear regulator for use in a three-dimensional memory, comprising:

[0007] LDO main circuit module and bias module;

[0008] The LDO main circuit module is used to generate the output voltage;

[0009] The bias module is connected to the output of the LDO main circuit module and is used to generate a bias voltage for the LDO main circuit module.

[0010] Specifically, when the output voltage of the LDO main circuit module increases or decreases, the LDO main circuit module can restore the output voltage to a static stable value.

[0011] In an optional embodiment, the LDO main circuit module includes: a first MOSFET, a second MOSFET, a third MOSFET, a fourth MOSFET, a fifth MOSFET, a sixth MOSFET, a seventh MOSFET, an eighth MOSFET, a ninth MOSFET, a tenth MOSFET, an eleventh MOSFET, a twelfth MOSFET, a first resistor, a second resistor, a third resistor, a first capacitor, a second capacitor, and a third capacitor;

[0012] In this configuration, the source terminal of the first MOSFET is connected to a set voltage, and its gate terminal is connected to its own drain terminal, while also being connected to the gate terminals of the second and third MOSFETs. The gate terminal of the third MOSFET is connected to the second bias voltage of the bias module, and its source terminal is connected to the drain terminal of the fourth MOSFET. The gate terminal of the fourth MOSFET is connected to the first bias voltage of the bias module, and its source terminal is grounded. The source terminal of the second MOSFET is connected to the source terminal of the twelfth MOSFET (MP), and also connected to one end of the third resistor, which serves as the output terminal of the LDO main circuit module. The drain terminal of the second MOSFET is connected to the drain terminal of the tenth MOSFET, which serves as the feedback terminal of the LDO main circuit module. The other end of the third resistor is connected to one end of the third capacitor. The other end of the third capacitor is connected to ground.

[0013] The gate of the tenth MOS transistor is connected to the second bias voltage of the bias module, and the source terminal is connected to the drain terminal of the eleventh MOS transistor; the gate of the eleventh MOS transistor is connected to the first bias voltage of the bias module, and the source terminal is connected to ground.

[0014] The drain terminal of the twelfth MOSFET is connected to the input voltage, and the gate terminal is connected to one end of the second resistor, and simultaneously connected to the drain terminals of the fifth MOSFET, the sixth MOSFET, and the ninth MOSFET; the other end of the second resistor is connected to one end of the second capacitor, and the other end of the second capacitor is connected to ground;

[0015] The source terminal of the fifth MOSFET is connected to the input voltage, and its gate terminal is connected to one end of the first resistor and one end of the first capacitor; the other end of the first resistor is connected to the third bias voltage of the bias module; the other end of the first capacitor is connected to the output terminal of the LDO main circuit module; the gate terminal of the sixth MOSFET is connected to the feedback terminal of the LDO main circuit module, and its source terminal is connected to the gate terminal of the ninth MOSFET, and also connected to the drain terminal of the seventh MOSFET; the gate terminal of the seventh MOSFET is connected to the second bias voltage of the bias module, and its source terminal is connected to the drain terminal of the eighth MOSFET; the gate terminal of the eighth MOSFET is connected to the first bias voltage of the bias module, and its source terminal is connected to ground; the source terminal of the ninth MOSFET is connected to ground.

[0016] The first, second, and fifth MOS transistors are all PMOS transistors; the third, fourth, sixth, seventh, eighth, ninth, tenth, eleventh, and twelfth MOS transistors are all NMOS transistors.

[0017] In the optional solution, the setting voltage V SET The generation circuit includes: a low-power amplifier and a thirteenth MOS transistor; the negative input terminal of the low-power amplifier is connected to a reference voltage, and the positive input terminal is connected to the drain terminal of the thirteenth MOS transistor, which is the set voltage; the output terminal of the low-power amplifier is connected to the gate terminal of the thirteenth MOS transistor; the source terminal of the thirteenth MOS transistor is connected to the input voltage; the thirteenth MOS transistor is a PMOS transistor.

[0018] In an optional embodiment, the bias circuit module includes: a fourteenth MOSFET, a fifteenth MOSFET, a sixteenth MOSFET, a seventeenth MOSFET, an eighteenth MOSFET, a first current source, and a fourth capacitor;

[0019] In this configuration, the source terminal of the fourteenth MOSFET is connected to the input voltage, and its gate terminal is designated as the third bias voltage of the bias module. This point is connected to its own source terminal and simultaneously connected to the drain and gate terminals of the fifteenth MOSFET. The source terminal of the fifteenth MOSFET is connected to the drain and gate terminals of the sixteenth MOSFET. The drain and gate terminals of the sixteenth MOSFET are designated as the second bias voltage of the bias module. The source terminal of the sixteenth MOSFET is connected to the drain terminal of the seventeenth MOSFET. The gate terminal of the seventeenth MOSFET is designated as the first bias voltage of the bias module. This point is connected to one end of the fourth capacitor and simultaneously connected to the gate and drain terminals of the eighteenth MOSFET and the output terminal of the first current source. The other end of the fourth capacitor is connected to the output terminal of the LDO main circuit module. The source terminal of the eighteenth MOSFET is connected to ground. The input terminal of the first current source is connected to the input voltage.

[0020] The fourteenth MOS transistor is a PMOS transistor; the fifteenth, sixteenth, seventeenth, and eighteenth MOS transistors are all NMOS transistors.

[0021] The beneficial effects of this invention are as follows:

[0022] 1) This invention improves transient response performance and reduces the size and area of ​​the power transistor.

[0023] 2) The LDO circuit of this invention has excellent transient characteristics, and can achieve a small overshoot voltage and a short recovery time in a very short load switching time.

[0024] 3) The LDO circuit of this invention does not require off-chip capacitors and can achieve full on-chip integration.

[0025] 4) The LDO circuit described in this invention has excellent load capacitance capability and can drive a wide range of load capacitances. Attached Figure Description

[0026] The above and other objects, features and advantages of the present invention will become more apparent from the accompanying drawings, in which like reference numerals generally denote like parts.

[0027] Figure 1 This is a schematic diagram of the V / 2 bias method for three-dimensional memory in the prior art.

[0028] Figure 2 This is a circuit diagram of a linear regulator applied to a three-dimensional memory in one embodiment of the present invention.

[0029] Figure 3 This is a circuit diagram of a voltage generation circuit in one embodiment of the present invention.

[0030] Figure 4 This is a simulation curve of the amplitude-frequency characteristic under different load currents in one embodiment of the present invention.

[0031] Figure 5 This is a simulation curve of phase margin under different load capacitances in one embodiment of the present invention.

[0032] Figure 6 This is a simulation curve of transient characteristic response in one embodiment of the present invention. Detailed Implementation

[0033] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become clearer from the following description and drawings. However, it should be noted that the concept of the technical solution of the present invention can be implemented in many different forms and is not limited to the specific embodiments described herein. The accompanying drawings are all in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of the present invention.

[0034] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this invention, the first element, component, area, layer, or portion discussed below may be referred to as the second element, component, area, layer, or portion.

[0035] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below” or “under” the other element or feature will be oriented “above” the other element or feature. Therefore, the exemplary terms “below” and “under” can include both upper and lower orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.

[0036] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the invention. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising” and / or “including,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0037] Example 1

[0038] Reference Figures 1 to 6 This embodiment provides a linear regulator for use in a three-dimensional memory, comprising:

[0039] LDO main circuit module 1 and bias module 2;

[0040] The LDO main circuit module 1 is used to generate a stable output voltage VOUT with good transient response characteristics;

[0041] The bias module 2 is connected to the output of the LDO main circuit module 1 and is used to generate a bias voltage for the LDO main circuit module 1.

[0042] When the output voltage of the LDO main circuit module 1 increases or decreases, the LDO main circuit module 1 can restore the output voltage to a static stable value.

[0043] Specifically, in this embodiment, the LDO main circuit module includes: a first MOSFET M1, a second MOSFET M2, a third MOSFET M3, a fourth MOSFET M4, a fifth MOSFET M5, a sixth MOSFET M6, a seventh MOSFET M7, an eighth MOSFET M8, a ninth MOSFET M9, and a tenth MOSFET M1. 10 11th MOSFET M 11 12th MOSFET M P The components are: first resistor R1, second resistor R2, third resistor R3, first capacitor C1, second capacitor C2, and third capacitor C3.

[0044] The source terminal of the first MOS transistor M1 is connected to a voltage V. SET The gate terminal is connected to its own drain terminal, and is also connected to the gate terminal of the second MOS transistor M2 and the gate terminal of the third MOS transistor M3; the gate terminal of the third MOS transistor M3 is connected to the second bias voltage V of the bias module. B2 The source terminal is connected to the drain terminal of the fourth MOS transistor M4; the gate terminal of the fourth MOS transistor M4 is connected to the first bias voltage V of the bias module. B1 The source terminal of the second MOSFET M2 is grounded; the source terminal of the second MOSFET M2 is connected to the twelfth MOSFET M... P The source terminal is also connected to one end of the third resistor R3, and this point serves as the output terminal V of the LDO main circuit module. OUT The drain terminal of the second MOSFET M2 is connected to the tenth MOSFET M. 10 The drain terminal, which serves as the feedback terminal V of the LDO main circuit module. F The other end of the third resistor R3 is connected to one end of the third capacitor C3; the other end of the third capacitor C3 is connected to ground; the tenth MOSFET M 10 The gate terminal is connected to the second bias voltage V of the bias module. B2 The source terminal is connected to the eleventh MOS transistor M. 11 The drain terminal; the eleventh MOS transistor M 11 The gate terminal is connected to the first bias voltage V of the bias module. B1 The source terminal is connected to ground; the twelfth MOS transistor M P The drain terminal is connected to the input voltage V. IN The gate voltage is denoted as Vgate of the power transistor. GThe gate terminal is connected to one end of the second resistor R2, and simultaneously connected to the drain terminals of the fifth MOSFET M5, the sixth MOSFET M6, and the ninth MOSFET M9; the other end of the second resistor R2 is connected to one end of the second capacitor C2, and the other end of the second capacitor C2 is connected to ground; the source terminal of the fifth MOSFET M5 is connected to the input voltage V. IN The gate terminal is connected to one end of the first resistor R1 and one end of the first capacitor C1; the other end of the first resistor R1 is connected to the third bias voltage V of the bias module. B3 The other end of the first capacitor C1 is connected to the output terminal V of the LDO main circuit module. OUT The gate of the sixth MOS transistor M6 is connected to the feedback terminal V of the LDO main circuit module. F The source terminal is connected to the gate terminal of the ninth MOS transistor M9, and simultaneously connected to the drain terminal of the seventh MOS transistor M7; the gate terminal of the seventh MOS transistor M7 is connected to the second bias voltage V of the bias module. B2 The source terminal is connected to the drain terminal of the eighth MOS transistor M8; the gate terminal of the eighth MOS transistor M8 is connected to the first bias voltage V of the bias module. B1 The source terminal of the ninth MOSFET M9 is connected to ground; the source terminal of the first MOSFET M1, the second MOSFET M2, and the fifth MOSFET M5 are all PMOS transistors; the third MOSFET M3, the fourth MOSFET M4, the sixth MOSFET M6, the seventh MOSFET M7, the eighth MOSFET M8, the ninth MOSFET M9, and the tenth MOSFET M... 10 11th MOSFET M 11 and the twelfth MOSFET M P All are NMOS transistors.

[0045] In this embodiment, the bias circuit module includes: the fourteenth MOS transistor M B1 The fifteenth MOSFET M B2 The sixteenth MOSFET M B3 The seventeenth MOSFET M B4 The eighteenth MOSFET M B5 First current source I BIAS The fourth capacitor C4; wherein, the fourteenth MOS transistor M B1 The source terminal is connected to the input voltage V. IN The gate terminal is denoted as the third bias voltage V of the bias module. B3 This point is connected to its own source terminal and is also connected to the fifteenth MOS transistor M. B2 The drain and gate terminals; the fifteenth MOS transistor M B2The source terminal is connected to the sixteenth MOS transistor M. B3 The drain and gate terminals; the sixteenth MOS transistor M B3 The drain and gate terminals are denoted as the second bias voltage V of the bias module. B2 The sixteenth MOS transistor M B3 The source terminal is connected to the seventeenth MOS transistor M. B4 The drain terminal; the seventeenth MOS transistor M B4 The gate terminal is denoted as the first bias voltage V of the bias module. B1 This point is connected to one end of the fourth capacitor C4, and also to the eighteenth MOSFET M. B5 The gate terminal, drain terminal and the first current source I BIAS The output terminal of the fourth capacitor C4 is connected to the output terminal V of the LDO main circuit module; the other end of the fourth capacitor C4 is connected to the output terminal V of the LDO main circuit module. OUT The eighteenth MOS transistor M B5 The source terminal is connected to ground; the first current source I BIAS The input terminal is connected to the input voltage V. IN The fourteenth MOS transistor M B1 It is a PMOS transistor; the fifteenth MOS transistor M B2 The sixteenth MOSFET M B3 The seventeenth MOSFET M B4 and the eighteenth MOSFET M B5 All are NMOS transistors.

[0046] In this embodiment, the set voltage V SET The generation circuit includes: a low-power amplifier EA and a thirteenth MOSFET M. SET The negative input terminal of the low-power amplifier EA is connected to the reference voltage V. REF The positive input terminal is connected to the thirteenth MOS transistor M. SET The drain terminal, at which the set voltage V is located. SET The output terminal of the low-power amplifier EA is connected to the gate terminal of the thirteenth MOS transistor; the thirteenth MOS transistor M SET The source terminal is connected to the input voltage V. IN The thirteenth MOS transistor is a PMOS transistor. The set voltage V... SET The generation circuit has very low power consumption, and since it only requires a few microamps of drive current, the size of the PMOS transistor does not need to be very large.

[0047] The input voltage V IN and output voltage V OUT The difference is large, and the input voltage V IN When denoted as V, the output voltage VOUT The voltage is typically between 1 / 3V and 2 / 3V, with a typical value of 1 / 2V.

[0048] In this embodiment, the first capacitor C1 and the fourth capacitor C4 enhance the transient characteristics of the circuit through capacitive coupling. In the static state, the first capacitor C1 and the fourth capacitor C4 are not conducting, and the fifth MOSFET M5 and the fourteenth MOSFET M... B1 The seventeenth MOS transistor M B4 and the eighteenth MOSFET M B5 This ensures the normal operation of the current mirror structure. When the output current instantly changes from a small current load to a large current load, the gate voltage of the power transistor does not change immediately due to its large size, resulting in a lower output voltage V. OUT When the capacitor is coupled, the voltage across it decreases along with the output voltage, increasing the current flowing through the fifth MOSFET M5 and decreasing the current flowing through the eighth MOSFET M8 and the eleventh MOSFET M1. 11 The voltage across the terminals accelerates the twelfth MOSFET M P Gate voltage V G The charging process causes the output voltage V to be increased. OUT It quickly recovers to its static stable value.

[0049] In this embodiment, the second resistor R2 and the second capacitor C2 are used to compensate for the loop stability of the circuit; the third resistor R3 and the third capacitor C3 are used to enhance the transient characteristics of the circuit and improve the loop stability. Specifically, the second resistor R2 and the second capacitor C2 generate a left-half-plane zero point to compensate for the loop's phase margin; the third resistor R3 and the third capacitor C3, in addition to improving the circuit's transient characteristics, can also compensate for the loop's phase margin under heavy load conditions.

[0050] The output resistance of the LDO main circuit module in this embodiment is very small, and it has a good load capacitance capability, enabling it to drive a wide range of load capacitances.

[0051] The operation of the LDO circuit applied to the three-dimensional memory is as follows: When the output voltage increases, the drain voltage of the second MOSFET M2 increases. The fifth MOSFET M5, the sixth MOSFET M6, the seventh MOSFET M7, the eighth MOSFET M8, and the ninth MOSFET M9 form a high-output-resistance, high-bandwidth inverting amplifier, which increases the output voltage V. OUT The change is amplified in reverse and fed back to the twelfth MOSFET M P The gate terminal of the gate is used to form negative feedback, which restores the output voltage to the static stable value.

[0052] Figure 4The simulation curves of amplitude-frequency characteristics under 10mA and 0 load current in this embodiment of the invention are shown. It can be seen that under heavy load, the low-frequency loop gain is 40dB, the GBW is 400MHz, and the phase margin is 109°; under heavy load, the low-frequency loop gain is 38dB, the GBW is 10MHz, and the phase margin is 91°. The simulation results show that the LDO circuit applied to the three-dimensional memory can achieve good switching stability under various load conditions and has a large loop bandwidth under heavy load conditions.

[0053] Figure 5 The simulation curves show the phase margin under different load capacitances in this embodiment of the invention. The LDO circuit has a very low resistance at the output node, thus exhibiting excellent load resistance capability. It can be seen that within a wide load capacitance range of 0-10nF, the phase margin of the LDO circuit is above 50° in both light and heavy load scenarios, meeting the loop stability requirements. Simulation results show that the LDO circuit applied to the three-dimensional memory has the ability to drive a wide range of load capacitances.

[0054] Figure 6 The simulation curves for transient response in this embodiment of the invention are shown. It can be seen that the simulation conditions were set such that the load current transitions within the range of 0 to 10 mA with a margin time of 10 ps. Without a load capacitor, the maximum undershoot voltage at the output terminal when the load current switches from light load to heavy load is 144 mV, with a recovery time of approximately 50 ns; the maximum overshoot voltage at the output terminal when the load current switches from heavy load to light load is 121 mV, with a recovery time of approximately 400 ns. With a 100 pF load capacitor, the maximum undershoot voltage at the output terminal when the load current switches from light load to heavy load is 102 mV, with a recovery time of approximately 55 ns; the maximum overshoot voltage at the output terminal when the load current switches from heavy load to light load is 76 mV, with a recovery time of approximately 1 μs. The simulation results show that the LDO circuit applied to the three-dimensional memory has excellent transient characteristics.

[0055] Therefore, the LDO circuit for three-dimensional memory described in this invention has the following beneficial effects: 1) This invention improves transient response performance and reduces the size and area of ​​the power transistor; 2) The LDO circuit described in this invention has excellent transient characteristics, achieving small overshoot voltage and short recovery time in a very short load switching time; 3) The LDO circuit described in this invention does not require off-chip capacitors and can achieve full on-chip integration; 4) This invention uses a 5 picofarad compensation capacitor and a 40 picofarad output capacitor, resulting in a smaller area compared to traditional FVF-LDO circuits; 5) The LDO circuit described in this invention has excellent load capacitance capability and can drive a wide range of load capacitances. This invention uses SMIC 110nm process. Simulation results show that the LDO circuit of this invention has an input voltage of 3.3V, an output voltage of 1.65V, a quiescent current of 70μA under no-load conditions, and a load switching range of 0-10mA. In a 10ps load switching time, the output voltage overshoot voltage is 144mV, and the recovery time is 50ns. In addition, this LDO circuit can drive load capacitors of 0-10nF.

[0056] The above description is merely a description of preferred embodiments of the present invention and is not intended to limit the scope of the present invention in any way. Any changes or modifications made by those skilled in the art based on the above disclosure shall fall within the protection scope of the claims.

Claims

1. A linear regulator for use in a three-dimensional memory, characterized in that, include: LDO main circuit module and bias module; The LDO main circuit module is used to generate the output voltage; The bias module is connected to the output of the LDO main circuit module and is used to generate a bias voltage for the LDO main circuit module. When the output voltage of the LDO main circuit module increases or decreases, the LDO main circuit module can restore the output voltage to a static stable value. The LDO main circuit module includes: a first MOSFET, a second MOSFET, a third MOSFET, a fourth MOSFET, a fifth MOSFET, a sixth MOSFET, a seventh MOSFET, an eighth MOSFET, a ninth MOSFET, a tenth MOSFET, an eleventh MOSFET, a twelfth MOSFET, a first resistor, a second resistor, a third resistor, a first capacitor, a second capacitor, and a third capacitor; In this configuration, the source terminal of the first MOSFET is connected to a set voltage, and its gate terminal is connected to its own drain terminal, while also being connected to the gate terminal of the second MOSFET and the drain terminal of the third MOSFET. The gate terminal of the third MOSFET is connected to the second bias voltage of the bias module, and its source terminal is connected to the drain terminal of the fourth MOSFET. The gate terminal of the fourth MOSFET is connected to the first bias voltage of the bias module, and its source terminal is grounded. The source terminal of the second MOSFET is connected to the source terminal of the twelfth MOSFET MP, and is also connected to one end of the third resistor, which serves as the output terminal of the LDO main circuit module. The drain terminal of the second MOSFET is connected to the drain terminal of the tenth MOSFET, which serves as the feedback terminal of the LDO main circuit module. The other end of the third resistor is connected to one end of the third capacitor. The other end of the third capacitor is connected to ground. The gate of the tenth MOS transistor is connected to the second bias voltage of the bias module, and the source terminal is connected to the drain terminal of the eleventh MOS transistor; the gate of the eleventh MOS transistor is connected to the first bias voltage of the bias module, and the source terminal is connected to ground. The drain terminal of the twelfth MOSFET is connected to the input voltage, and the gate terminal is connected to one end of the second resistor, and simultaneously connected to the drain terminals of the fifth MOSFET, the sixth MOSFET, and the ninth MOSFET; the other end of the second resistor is connected to one end of the second capacitor, and the other end of the second capacitor is connected to ground; The source terminal of the fifth MOSFET is connected to the input voltage, and its gate terminal is connected to one end of the first resistor and one end of the first capacitor; the other end of the first resistor is connected to the third bias voltage of the bias module; the other end of the first capacitor is connected to the output terminal of the LDO main circuit module; the gate terminal of the sixth MOSFET is connected to the feedback terminal of the LDO main circuit module, and its source terminal is connected to the gate terminal of the ninth MOSFET, and also connected to the drain terminal of the seventh MOSFET; the gate terminal of the seventh MOSFET is connected to the second bias voltage of the bias module, and its source terminal is connected to the drain terminal of the eighth MOSFET; the gate terminal of the eighth MOSFET is connected to the first bias voltage of the bias module, and its source terminal is connected to ground; the source terminal of the ninth MOSFET is connected to ground. The first, second, and fifth MOS transistors are all PMOS transistors; the third, fourth, sixth, seventh, eighth, ninth, tenth, eleventh, and twelfth MOS transistors are all NMOS transistors.

2. The linear regulator for a three-dimensional memory as described in claim 1, characterized in that, The set voltage V SET The generation circuit includes: A low-power amplifier and a thirteenth MOS transistor; the negative input terminal of the low-power amplifier is connected to a reference voltage, and the positive input terminal is connected to the drain terminal of the thirteenth MOS transistor, which is the set voltage; the output terminal of the low-power amplifier is connected to the gate terminal of the thirteenth MOS transistor; the source terminal of the thirteenth MOS transistor is connected to the input voltage; the thirteenth MOS transistor is a PMOS transistor.

3. The linear regulator for a three-dimensional memory as described in claim 1, characterized in that, The bias circuit module includes: a fourteenth MOSFET, a fifteenth MOSFET, a sixteenth MOSFET, a seventeenth MOSFET, an eighteenth MOSFET, a first current source, and a fourth capacitor; In this configuration, the source terminal of the fourteenth MOSFET is connected to the input voltage, and its gate terminal is designated as the third bias voltage of the bias module. This point is connected to its own drain terminal and simultaneously connected to the drain and gate terminals of the fifteenth MOSFET. The source terminal of the fifteenth MOSFET is connected to the drain and gate terminals of the sixteenth MOSFET. The drain and gate terminals of the sixteenth MOSFET are designated as the second bias voltage of the bias module. The source terminal of the sixteenth MOSFET is connected to the drain terminal of the seventeenth MOSFET. The gate terminal of the seventeenth MOSFET is designated as the first bias voltage of the bias module. This point is connected to one end of the fourth capacitor and simultaneously connected to the gate, drain, and output terminals of the eighteenth MOSFET and the first current source. The other end of the fourth capacitor is connected to the output terminal of the LDO main circuit module. The source terminal of the eighteenth MOSFET is connected to ground. The input terminal of the first current source is connected to the input voltage. The fourteenth MOS transistor is a PMOS transistor; the fifteenth, sixteenth, seventeenth, and eighteenth MOS transistors are all NMOS transistors.

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