An FPGA that supports storage and computing

Abstract

The present application discloses an FPGA supporting storage and calculation, and relates to the field of FPGA technology. The resource modules and interconnection resources in the same sub-area of ​​the FPGA are implemented as a storage and calculation unit. The local storage units in each storage and calculation unit transmit data with the outside of the FPGA chip through a global read-write channel. Since the processor of each storage and calculation unit only needs to read and write instructions and data in the adjacent local storage unit during execution, the wiring resources and interconnection resources consumed by transmitting data are reduced, and the data transmission delay and energy loss are reduced, which is conducive to improving the data processing efficiency of the FPGA. In addition, the FPGA can realize multi-core parallel storage and calculation operations through multiple storage and calculation units, and the processors of each storage and calculation unit will not cause conflicts with each other, avoiding the constraints brought by the storage bandwidth during multi-core operations, thereby further improving the overall data processing efficiency and operation speed of the FPGA.

Description

Technical Field

[0001] The present application relates to the field of FPGA technology, and in particular to an FPGA supporting storage and computing. Background Art

[0002] With the development of high-tech technologies such as the Internet of Things, cloud computing, and artificial intelligence, various data-intensive applications based on hardware platforms have also grown dramatically. FPGA (Field Programmable Gate Array) is a commonly used hardware platform due to its advantages of parallelism and reconfigurability.

[0003] The existing FPGA, like most traditional hardware platforms, adopts the von Neumann architecture. The FPGA contains a large number of resource modules such as CLB, DSP and BRAM. These resource modules are connected by highly configurable interconnects to form the processor and memory in the FPGA. BRAM is an important on-chip memory. The on-chip data is mainly stored in BRAM, and the on-chip data must be transferred to the processor during calculation.

[0004] Therefore, existing FPGAs, like other hardware platforms that use the von Neumann architecture, need to repeatedly transfer large amounts of data between the memory and the processor when performing various computing tasks. Frequent and large-scale data movement not only consumes a large amount of wiring resources and interconnection resources, but also causes huge delays and energy losses, thereby limiting the data processing efficiency of the FPGA. Summary of the invention

[0005] In response to the above problems and technical requirements, the applicant has proposed an FPGA that supports storage and computing. The technical solution of this application is as follows:

[0006] An FPGA supporting storage and computing, the FPGA internally includes a plurality of resource modules arranged according to a predetermined structure, interconnection resources arranged around the resource modules, and a global read-write channel realized by additional hardware resources, the resource modules located in the same sub-area are connected through the interconnection resources inside the FPGA to realize a storage and computing unit, the local storage unit in each storage and computing unit is used to store instructions and data of the storage and computing unit, and the processor in the storage and computing unit is connected to the local storage unit in the same storage and computing unit via the interconnection resources and is used to perform operations according to the instructions and data stored in the local storage unit;

[0007] The resource modules in multiple different sub-areas correspond to the implementation of multiple storage and computing units, and the local storage unit in each storage and computing unit transmits data with the outside of the FPGA chip through a global read and write channel.

[0008] A further technical solution is that a storage and calculation operation implemented by FPGA through multiple storage and calculation units includes:

[0009] The parameters of each storage and computing unit are written from outside the FPGA chip into the local storage unit of the corresponding storage and computing unit via the global read and write channel. The parameters written to the local storage unit of each storage and computing unit include the instructions and / or data of the storage and computing unit.

[0010] Start each storage and computing unit to perform parallel operations simultaneously, and the processor in each storage and computing unit performs operations according to the instructions and data in the local storage unit of the storage and computing unit, and stores the operation results in the local storage unit of the storage and computing unit;

[0011] The calculation results in the local storage unit of each storage and calculation unit are read out to the outside of the FPGA chip through the global read and write channel.

[0012] A further technical solution is that the FPGA implements multiple storage and calculation operations in sequence through the storage and calculation units implemented internally, and when the FPGA implements any storage and calculation operation:

[0013] Write corresponding parameters to the local storage units of all storage and computing units from outside the FPGA chip, or write corresponding parameters to the local storage units of some storage and computing units;

[0014] Start all or part of the storage and calculation units to perform parallel operations simultaneously;

[0015] The calculation results in the local storage units of all storage and computing units or the calculation results in the local storage units of some storage and computing units are read out to the outside of the FPGA chip.

[0016] Its further technical solution is that the local storage unit in a storage and computing unit includes an instruction local storage unit and a data local storage unit, the instruction local storage unit is used to store the instructions of the storage and computing unit, and the data local storage unit is used to store the data of the storage and computing unit, the instruction local storage unit is implemented by at least one BRAM module, and the data local storage unit is implemented by at least one BRAM module.

[0017] A further technical solution is that the instruction local storage unit and the data local storage unit in a storage and computing unit both transmit data via a global read-write channel;

[0018] Alternatively, the instruction local storage unit in a storage and computing unit transmits instructions via the instruction global read and write channel, and the data local storage unit transmits data via the data global read and write channel.

[0019] A further technical solution is that the storage sizes of instruction local storage units of any two storage and computing units are the same or different, and the storage sizes of data local storage units of any two storage and computing units are the same or different.

[0020] Its further technical solution is to implement a local storage unit in a storage and computing unit, and several BRAM modules located in the same column are connected to an on-chip read-write interface of the FPGA through the same global read-write channel to transmit data with the outside of the FPGA, and different global read-write channels are respectively connected to different on-chip read-write interfaces of the FPGA.

[0021] Its further technical solution is to realize the local storage unit in the storage and computing unit, and several BRAM modules located in the same column are connected to an active end of the multiplexer through the same global read-write channel, and the fixed end of the multiplexer is connected to the on-chip read-write interface of the FPGA.

[0022] Its further technical solution is that the types and quantities of resource modules contained in any two sub-areas are the same or there is at least one difference; the instruction sets used by the two storage and computing units implemented by the resource modules in any two sub-areas are the same or different, and the bit widths of the two storage and computing units using the same instruction set are the same or different.

[0023] Its further technical solution is that the resource module in each sub-area is also used to implement the control signal and status signal of a corresponding storage and computing unit, the control signal is used to control the operating status of the storage and computing unit, and the status signal is used to display the operating status of the storage and computing unit; the control signal and status signal of the storage and computing unit are connected to other circuit structures inside the FPGA, or the control signal and status signal of the storage and computing unit are connected to the outside of the FPGA.

[0024] A further technical solution is that the control signals of any two storage and computing units are the same or different, and the control signal includes at least one of an enable signal, a clock signal, a reset signal and an interrupt signal.

[0025] A further technical solution is that a local storage unit in a storage and computing unit is connected to other BRAM modules via the interconnection resources of the FPGA.

[0026] The beneficial technical effects of this application are:

[0027] The present application discloses an FPGA supporting storage and calculation, in which resource modules located in the same sub-area of ​​the FPGA are connected through interconnection resources inside the FPGA to realize a storage and calculation unit, and the local storage unit in each storage and calculation unit transmits data with the outside of the FPGA through a global read-write channel, and the processor and local storage unit of each storage and calculation unit are in the same sub-area. When executing, the processor only needs to read and write instructions and data in the adjacent local storage unit, which reduces the wiring resources and interconnection resources consumed by transmitting data between the processor and the local storage unit, reduces data transmission delay and energy loss, and improves the data processing efficiency of the FPGA. In addition, the FPGA can realize multi-core parallel storage and calculation operations through multiple storage and calculation units, and the processors of each storage and calculation unit will not cause conflicts with each other. Each storage and calculation unit can perform operations at full speed, which is not affected by the storage bandwidth, and can further improve the overall data processing efficiency and operation speed of the FPGA. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 It is a schematic diagram of the arrangement of resource modules inside the FPGA in an example of the present application and a schematic diagram of the eight sub-areas obtained by division.

[0029] Figure 2 yes Figure 1 A circuit structure diagram of a storage and computing unit implemented by a resource module in each sub-area in the example shown.

[0030] Figure 3 yes Figure 1 A circuit structure diagram of a storage and computing unit implemented by a resource module in each sub-area in the example shown.

[0031] Figure 4 yes Figure 1 A circuit structure diagram of a storage and computing unit implemented by a resource module in each sub-area in the example shown.

[0032] Figure 5 yes Figure 1 A circuit structure diagram of a storage and computing unit implemented by a resource module in each sub-area in the example shown. DETAILED DESCRIPTION

[0033] The specific implementation of the present application is further described below in conjunction with the accompanying drawings.

[0034] The present application discloses an FPGA that supports storage and computing. The FPGA of the present application is the same as a conventional FPGA, and includes a number of resource modules arranged in a predetermined structure and interconnection resources arranged around the resource modules. The predetermined structure can be arranged according to actual conditions. For example, taking the currently mainstream Column-Based structure as an example, the resource modules are arranged in a row and column structure to form a two-dimensional array architecture. The same type of resource modules are arranged in each column, and interconnection resources are arranged around each resource module. The types of resource modules included in the FPGA include configurable logic modules CLB, configurable storage modules BRAM, and configurable multiplication and addition modules DSP. The configurable logic module CLB contains units such as lookup tables and registers, which can be configured to implement various logical functions. The configurable multiplication and addition module DSP contains arithmetic units that can perform multiple operations such as multiplication, addition, and multi-bit logic gates. The configurable storage module BRAM contains block storage units that can implement single-port and dual-port storage and FIFO storage of various widths and depths. Please refer to Figure 1 The schematic diagram of the resource module inside the FPGA shown is a schematic diagram of the resource module inside the FPGA. This part of the structure follows the structure inside the existing FPGA and will not be elaborated in this application.

[0035] All resource modules arranged in a predetermined structure in the FPGA of the present application are divided into several sub-areas, each of which contains a certain number of resource modules. Resource modules in the same sub-area are connected through interconnection resources inside the FPGA to realize a storage and computing unit, and resource modules in multiple different sub-areas correspondingly realize multiple storage and computing units.

[0036] Each storage and computing unit includes its own processor and local storage unit. The processor in each storage and computing unit is connected to the local storage unit in the storage and computing unit via interconnection resources. The local storage unit in each storage and computing unit is used to store the instructions and data of the storage and computing unit, and the processor in each storage and computing unit is used to operate according to the instructions and data stored in the connected local storage unit.

[0037] In one embodiment, the instruction sets used by the two storage and computing units implemented by the resource modules in any two sub-areas are the same or different, and the bit widths of the two storage and computing units using the same instruction set are the same or different. In the present application, the storage and computing units formed inside the FPGA can form various typical general-purpose 8-bit processors including RISC, 8051 and 6802.

[0038] In one embodiment, the number and type of resource modules contained in any two sub-areas obtained by division are the same, or in another embodiment, the number and type of resource modules contained in any two sub-areas obtained by division are at least one different, that is, the multiple sub-areas obtained by division may be completely the same or not necessarily the same. In addition, each resource module in the FPGA belongs to a sub-area, all resource modules in the FPGA are divided into corresponding sub-areas, or some resource modules in the FPGA are divided into corresponding sub-areas, that is, the FPGA can be divided into sub-areas globally or locally. For example, Figure 1 In the example shown, the resource modules inside the FPGA are divided into 8 sub-areas, each of which contains the same number and type of resource modules, and each area framed by a dotted box represents a sub-area obtained by the division.

[0039] This application does not limit the number and type of resource modules contained in each sub-area, but the number and type of resource modules contained in each sub-area must be sufficient to implement the processor and local storage unit in a storage and computing unit. The processor in a storage and computing unit is mainly implemented based on DSP, and the storage unit in a storage and computing unit is mainly implemented based on BRAM. In addition, a certain number of CLBs are also required.

[0040] In addition to resource modules and interconnection resources, the FPGA of the present application also adds additional hardware resources to implement global read and write channels compared to conventional FPGAs. The local storage unit in each storage unit transmits data to the FPGA chip through the global read and write channels. Figure 1 The resource modules in each sub-area shown implement a storage and computing unit. Figure 1 The schematic diagram of the implemented storage and computing unit is as follows Figure 2 shown.

[0041] The FPGA of this architecture of the present application forms multiple storage and computing units inside, and each storage and computing unit supports independent storage and computing operations in the form of a soft core. Therefore, the FPGA can jointly realize a multi-core storage and computing operation through multiple storage and computing units formed inside. Since the processor and local storage unit of each storage and computing unit are in the same sub-area, the processor only needs to read and write instructions and data in the adjacent local storage unit during execution, thereby reducing the wiring resources and interconnection resources consumed by transmitting data between the processor and the local storage unit, reducing data transmission delays and energy losses, and improving the data processing efficiency of the FPGA. In addition, in a multi-core scenario, if multiple computing cores read and write the same main memory at the same time, the read and write bandwidth of the main memory forms a bottleneck, restricting the data processing efficiency. This problem will be particularly obvious in high-performance computing. For FPGAs that support artificial intelligence or machine learning applications, the FPGA generally has a large number of relatively simple computing cores inside, and the number of computing cores will exceed 100. The demand for the read and write bandwidth of the main memory is greater, and the problem is more prominent. The FPGA of the present application is also a multi-core scenario. Since the processors in each storage and computing unit read and write the local storage unit, instead of all processors reading and writing the same memory, the processors of each storage and computing unit will not conflict with each other. Each storage and computing unit can perform operations at full speed, which is not affected by the storage bandwidth, which is conducive to improving the overall data processing efficiency and operation speed. This makes the FPGA of the present application applicable to scenarios with a large number of storage and computing units, and even if the number of storage and computing units exceeds 100, it can have a high operation rate, so as to better support artificial intelligence and machine learning scenarios.

[0042] Based on this structure, the FPGA of the present application implements a storage-computation operation through multiple storage-computation units, including: first, the parameters of each storage-computation unit are written from outside the FPGA chip to the local storage unit of the corresponding storage-computation unit via the global read-write channel, and the parameters written to the local storage unit of each storage-computation unit include the instructions and / or data of the storage-computation unit, that is, only instructions or data can be written to the storage-computation unit, or instructions and data can be written at the same time. Start each storage-computation unit to operate in parallel at the same time, and the processor in each storage-computation unit performs operations according to the instructions and data in the local storage unit of the storage-computation unit, and stores the operation results in the local storage unit of the storage-computation unit. Then, the operation results in the local storage units of each storage-computation unit can be read out of the FPGA chip via the global read-write channel. In addition, according to actual needs, the local storage unit in a storage-computation unit can also be connected to other BRAM modules inside the FPGA via the interconnection resources of the FPGA to realize data exchange.

[0043] On this basis, according to actual needs, the FPGA can sequentially implement multiple storage and calculation operations through the internal storage and calculation units until all operations are completed. And when the FPGA implements any storage and calculation operation, the corresponding parameters are written from outside the FPGA chip to the local storage units of all storage and calculation units, or to the local storage units of some storage and calculation units. Similarly, the parameters here include the instructions and / or data of the storage and calculation units. All storage and calculation units or some storage and calculation units are started to perform parallel operations at the same time. Then the calculation results in the local storage units of all storage and calculation units or the calculation results in the local storage units of some storage and calculation units are read out to the outside of the FPGA chip. That is, when multiple storage and calculation operations are implemented, each storage and calculation operation can use all the storage and calculation units formed inside the FPGA, or only use some storage and calculation units and skip other storage and calculation units. When using some storage and calculation units, the same or different storage and calculation units can also be used multiple times. In addition, each storage and calculation operation can adjust the parameters written to each storage and calculation unit. Each storage and calculation operation can read the calculation results of all or some storage and calculation units. That is, the processes of executing multiple storage and computing operations are basically similar, but each storage and computing operation can flexibly adjust the data reading and writing of each storage and computing unit, without the need to perform the same data reading and writing operations on the local storage units in all storage and computing units every time.

[0044] In one embodiment, when the predetermined structure adopted by the resource module arrangement inside the FPGA is a Column-Based structure, the BRAM module occupies one or more columns, and the local storage units in each storage and computing unit are implemented based on the BRAM module. Therefore, the BRAM module used to implement the local storage unit in each storage and computing unit is located in one or more columns, and the local storage unit in the storage and computing unit and several BRAM modules located in the same column are used to implement data transmission with the FPGA chip outside via the same global read-write channel. The FPGA chip can exchange data with any local storage unit connected to the global read-write channel via each global read-write channel. Based on this, the present application provides the following two methods to implement data transmission between the local storage unit in each storage and computing unit and the FPGA chip outside:

[0045] In one embodiment, several BRAM modules located in the same column and used to implement local storage units in the storage and computing units are connected to an on-chip read / write interface of the FPGA through the same global read / write channel to perform data transmission with the outside of the FPGA, and different global read / write channels are connected to different on-chip read / write interfaces of the FPGA. Figure 2In the example shown, 8 storage and computing units are formed inside the FPGA. The local storage units in storage and computing units 1 to 4 are implemented by BRAM modules located in the same column. The local storage units of these 4 storage and computing units are connected to the on-chip read-write interface 1 of the FPGA through the global read-write channel 1 to realize data transmission with the outside of the FPGA. The local storage units in storage and computing units 5 to 8 are implemented by BRAM modules located in the same column. The local storage units of these 4 storage and computing units are connected to the on-chip read-write interface 2 of the FPGA through the global read-write channel 2 to realize data transmission with the outside of the FPGA.

[0046] The method provided in the above embodiment often needs to occupy multiple on-chip read / write interfaces of the FPGA, and the on-chip read / write interface resources of the FPGA are relatively precious. Therefore, in another embodiment, only one on-chip read / write interface of the FPGA is needed to realize the local storage unit in the soft-core processor, and several BRAM modules located in the same column are connected to an active end of the multiplexer MUX through the same global read / write channel, and the fixed end of the multiplexer MUX is connected to the on-chip read / write interface of the FPGA. By selecting each active end of the multiplexer MUX, each global read / write channel can be selected, so that data can be exchanged with any local storage unit connected to the global read / write channel outside the FPGA chip via the selected global read / write channel. For example, in Figure 3 In the structure diagram shown, it corresponds to Figure 2 , the local storage units in storage and computing units 1 to 4 are connected to an active end of the multiplexer MUX through the global read-write channel 1, the local storage units in storage and computing units 5 to 8 are connected to the other active end of the multiplexer MUX through the global read-write channel 2, and the fixed end of the multiplexer MUX is connected to the on-chip read-write interface of the FPGA to realize data transmission with the outside of the chip, then compared with Figure 2 The method of this embodiment only needs to occupy one on-chip read / write interface of the FPGA.

[0047] According to the traditional von Neumann architecture, the instructions and data in each storage unit are mixed and stored. However, in order to improve the data processing efficiency, in one embodiment, according to the Harvard structure, the instructions and data of each storage unit are stored separately and independently. Then the local storage unit in a storage and computing unit includes an instruction local storage unit and a data local storage unit. The instruction local storage unit is used to store the instructions of the storage and computing unit, and the data local storage unit is used to store the data of the storage and computing unit, so that the instructions and data do not interfere with each other when the processor operates, thereby improving the data processing efficiency. The instruction local storage unit is implemented by at least one BRAM module, and the data local storage unit is implemented by at least one BRAM module. Therefore, based on this, a common sub-area includes at least one DSP, two BRAMs, and 300 CLBs.

[0048] When the local storage unit in each storage and computing unit includes an instruction local storage unit and a data local storage unit, the storage size of the instruction local storage units of any two storage and computing units is the same or different, and the storage size of the data local storage units of any two storage and computing units is the same or different.

[0049] When the local storage unit in each storage unit includes an instruction local storage unit and a data local storage unit: (1) In one embodiment, the instruction local storage unit and the data local storage unit in a storage unit share the global read / write channel for data transmission, and the instruction local storage unit and the data local storage unit in the storage unit and the data local storage unit in the same column are used to transmit data with the FPGA chip via the same global read / write channel. In this embodiment, the global read / write channel can be used as follows Figure 2 The method of the embodiment shown is connected to the on-chip read / write interface of the FPGA, or according to Figure 3 The method of the embodiment shown is connected to an active terminal of the multiplexer MUX. Figure 2 Taking the structure shown in the figure as an example, Figure 4 As shown, the instruction local storage units and data local storage units in storage and computing units 1 to 4 are connected to the global read-write channel 1, and the instruction local storage units and data local storage units in storage and computing units 5 to 8 are connected to the global read-write channel 2. (2) Or in another embodiment, the instruction local storage units and data local storage units use their own global read-write channels respectively, and the instruction local storage units in a storage and computing unit transmit instructions via the instruction global read-write channel, and the data local storage units transmit data via the data global read-write channel. Then, the instruction local storage units in the storage and computing units and several BRAM modules in the same column transmit data with the outside of the FPGA chip via the same instruction global read-write channel, and the data local storage units in the storage and computing units and several BRAM modules in the same column transmit data with the outside of the FPGA chip via the same data global read-write channel. Similarly, in this embodiment, each instruction global read-write channel and data global read-write channel can be configured as follows: Figure 2 The method of the embodiment shown is connected to the on-chip read / write interface of the FPGA, or according to Figure 3 The method of the embodiment shown is connected to an active terminal of the multiplexer MUX. Figure 3 Taking the structure shown in the figure as an example, Figure 5The instruction local storage units in storage and computing units 1 to 4 are all connected to the instruction global read and write channel 1, the data local storage units in storage and computing units 1 to 4 are all connected to the data global read and write channel 1, the instruction local storage units in storage and computing units 5 to 8 are all connected to the instruction global read and write channel 2, the data local storage units in storage and computing units 5 to 8 are all connected to the data global read and write channel 2, the instruction global read and write channel 1, the data global read and write channel 1, the instruction global read and write channel 2 and the data global read and write channel 2 are respectively connected to an active end of the multiplexer MUX.

[0050] In another embodiment, the resource module in each sub-area is also used to implement the control signal and status signal of a corresponding storage and computing unit, the control signal is used to control the operating status of the storage and computing unit, and the status signal is used to display the operating status of the storage and computing unit. The control signal and status signal of the storage and computing unit are connected to other circuit structures inside the FPGA, or the control signal and status signal of the storage and computing unit are connected to the outside of the FPGA. That is, the control signal and status signal required by each storage and computing unit when performing storage and computing are implemented by the resource module in the corresponding sub-area.

[0051] The control signal of each storage and computing unit includes at least one of an enable signal, a clock signal, a reset signal and an interrupt signal. The enable signal is used to control the corresponding storage and computing unit to execute instructions or stop executing instructions. The reset signal is used to reset the storage and computing unit. The interrupt signal provides external interrupt capability. The control signals of any two storage and computing units are the same or different.

[0052] The above is only a preferred embodiment of the present application, and the present application is not limited to the above embodiments. It is understood that other improvements and changes directly derived or associated by those skilled in the art without departing from the spirit and concept of the present application should be considered to be included in the protection scope of the present application.

Claims

1. An FPGA supporting storage and computing, characterized in that: The FPGA includes a plurality of resource modules arranged in a predetermined structure, interconnection resources arranged around the resource modules, and a global read / write channel realized by additional hardware resources. The resource modules located in the same sub-area are connected through the interconnection resources inside the FPGA to realize a storage and computing unit. The local storage unit in each storage and computing unit is used to store instructions and data of the storage and computing unit. The processor in the storage and computing unit is connected to the local storage unit in the same storage and computing unit via the interconnection resources and is used to perform operations according to the instructions and data stored in the local storage unit. Resource modules in multiple different sub-areas correspondingly implement multiple storage and computing units, and the local storage unit in each storage and computing unit transmits data with the FPGA chip outside through a global read and write channel; The FPGA implements a storage-computation operation through multiple storage-computation units, including: writing the parameters of each storage-computation unit from outside the FPGA chip to the local storage unit of the corresponding storage-computation unit via a global read-write channel, and the parameters written to the local storage unit of each storage-computation unit include the instructions and / or data of the storage-computation unit; starting each storage-computation unit to perform operations in parallel at the same time, and the processor in each storage-computation unit performs operations according to the instructions and data in the local storage unit of the storage-computation unit, and stores the operation results in the local storage unit of the storage-computation unit; reading the operation results in the local storage unit of each storage-computation unit to outside the FPGA chip via the global read-write channel; The FPGA implements multiple storage-computing operations in sequence through the storage-computing units implemented internally, and when the FPGA implements any storage-computing operation: writes corresponding parameters to the local storage units of all storage-computing units from outside the FPGA chip, or writes corresponding parameters to the local storage units of some storage-computing units; starts all storage-computing units or some storage-computing units to perform parallel operations at the same time; and reads the operation results in the local storage units of all storage-computing units or the operation results in the local storage units of some storage-computing units to outside the FPGA chip.

2. The FPGA supporting storage and computing according to claim 1, characterized in that: A local storage unit in the storage and computing unit includes an instruction local storage unit and a data local storage unit. The instruction local storage unit is used to store the instructions of the storage and computing unit, and the data local storage unit is used to store the data of the storage and computing unit. The instruction local storage unit is implemented by at least one BRAM module, and the data local storage unit is implemented by at least one BRAM module.

3. The FPGA supporting storage and computing according to claim 2, characterized in that: The instruction local storage unit and the data local storage unit in one of the storage and computing units both transmit data via the global read and write channel; Alternatively, the instruction local storage unit in one of the storage and computing units transmits instructions via the instruction global read-write channel, and the data local storage unit transmits data via the data global read-write channel.

4. The FPGA supporting storage and computing according to claim 2, characterized in that: The storage sizes of the instruction local storage units of any two storage and computing units are the same or different, and the storage sizes of the data local storage units of any two storage and computing units are the same or different.

5. The FPGA supporting storage and computing according to claim 1, characterized in that: Several BRAM modules located in the same column, which are used to implement local storage units in the storage and computing units, are connected to an on-chip read-write interface of the FPGA through the same global read-write channel to perform data transmission with the outside of the FPGA, and different global read-write channels are respectively connected to different on-chip read-write interfaces of the FPGA.

6. The FPGA supporting storage and computing according to claim 1, characterized in that: Several BRAM modules located in the same column and used to realize local storage units in storage and computing units are connected to an active end of a multiplexer through a global read-write channel, and the fixed end of the multiplexer is connected to the on-chip read-write interface of the FPGA.

7. The FPGA supporting storage and computing according to claim 1, characterized in that: The types and quantities of resource modules contained in any two sub-areas are the same or there is at least one difference; the instruction sets used by the two storage and computing units implemented by the resource modules in any two sub-areas are the same or different, and the bit widths of the two storage and computing units using the same instruction set are the same or different.

8. The FPGA supporting storage and computing according to claim 1, characterized in that: The resource module in each sub-area is also used to implement the control signal and status signal of a corresponding storage and computing unit, wherein the control signal is used to control the operating status of the storage and computing unit, and the status signal is used to display the operating status of the storage and computing unit; the control signal and status signal of the storage and computing unit are connected to other circuit structures inside the FPGA, or the control signal and status signal of the storage and computing unit are connected to the outside of the FPGA.

9. The FPGA supporting storage and computing according to claim 8, characterized in that: The control signals of any two storage and computing units are the same or different, and the control signal includes at least one of an enable signal, a clock signal, a reset signal and an interrupt signal.

10. The FPGA supporting storage and computing according to claim 1, characterized in that: The local storage unit in a storage and computing unit is connected to other BRAM modules via the interconnection resources of the FPGA.

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