A method, device and electronic equipment for screening SerDes chips

Abstract

This invention provides a method, apparatus, and electronic device for screening SerDes chips. The method includes: obtaining the bit error rate (BER) of the target coordinate points in the digital eye diagram corresponding to the SerDes chip based on the target coordinate points of a predetermined BER boundary contour; the BER boundary contour is predetermined based on the boundary coordinate points with a BER of zero in the digital eye diagram corresponding to a qualified SerDes chip; if a first proportion of the target coordinate points with a BER of zero is greater than a preset proportion threshold, the SerDes chip is determined to be a qualified chip. In this application, judging the SerDes chip by obtaining the BER of the target coordinate points in the digital eye diagram corresponding to the SerDes chip based on the predetermined BER boundary contour can reduce misjudgments of SerDes chips and improve the yield of SerDes chips. Furthermore, only the BER of the target coordinate points of the predetermined BER boundary contour in the digital eye diagram of the SerDes chip needs to be obtained, which shortens the screening time and improves the screening efficiency of SerDes chips compared to obtaining the complete digital eye diagram.

Description

Technical Field

[0001] This invention relates to the field of communication technology, and in particular to a method, apparatus, and electronic device for screening SerDes chips. Background Technology

[0002] SerDes (Serializer / Deserializer) is the entry point and gateway of a network communication chip, playing a crucial role in the chip and serving as a prerequisite for normal data exchange.

[0003] The SerDes chip screening process can be understood as a process of selecting qualified SerDes chips, and it is a crucial step. If an inappropriate screening method is chosen, defective chips may enter the market, causing direct economic losses and increased maintenance costs; conversely, qualified SerDes chips may be judged as defective, leading to misjudgment and a decrease in chip yield. Therefore, finding suitable screening criteria for SerDes chips is extremely important.

[0004] Since SerDes is a complex mixed-signal module, it is impossible to perform comprehensive simulation and verification during the chip development stage. Therefore, the SLT (System Level Test) stage after chip delivery becomes a critical link.

[0005] Existing SerDes chip screening methods mainly rely on bit error rate or the eye height and eye width of digital eye diagrams for judgment.

[0006] Specifically, the SerDes chips to be screened are placed on an SLT testing machine. A test stream is sent from the TX (Transport) end of the SerDes chip, and then the test stream is checked at the RX (Receive) end. If the bit error rate of the SerDes chip meets the requirements within a specific test time, the SerDes chip is deemed qualified. To reduce the false positive rate, this screening method requires maximizing the test time. Therefore, it often occupies a considerable amount of time on the SLT testing machine, resulting in high operating costs.

[0007] Alternatively, during SerDes chip testing, a digital eye diagram (DEM) for the corresponding SerDes chip can be generated, and the pass / fail status of the SerDes chip can be determined based on the eye height and eye width in the DEM. However, screening SerDes chips solely based on the eye height and eye width of the DEM is prone to misjudgment. For example, usable chips may be identified as unqualified chips, resulting in a low chip yield; or unqualified chips may be identified as qualified chips, allowing defective chips to enter the market. Furthermore, screening based on eye height and eye width requires obtaining the complete DEM of the SerDes chip, and acquiring the complete DEM consumes a significant amount of time on the SLT testing equipment, leading to high operating costs for the testing equipment. Summary of the Invention

[0008] The purpose of this invention is to provide a method, apparatus, and electronic device for screening SerDes chips, thereby solving the problems of misjudgment and low screening efficiency in SerDes chip screening. The specific technical solution is as follows:

[0009] In a first aspect of this invention, a method for screening SerDes chips is provided, the method comprising:

[0010] Based on the target coordinates of the error boundary contour in the predetermined digital eye diagram, the bit error rate of the target coordinates in the digital eye diagram corresponding to the serializer / deserializer SerDes chip is obtained; wherein, the error boundary contour is determined in advance based on the boundary coordinates of the zero bit error rate in the digital eye diagram corresponding to the qualified SerDes chip;

[0011] If the first proportion of the target coordinate points with a bit error rate of zero is greater than a preset proportion threshold, the SerDes chip is determined to be a qualified chip.

[0012] Optionally, the error boundary profile can be determined in the following manner:

[0013] Obtain digital eye diagrams corresponding to multiple qualified SerDes chips;

[0014] For each digital eye diagram, determine the boundary coordinates of the digital eye diagram with a bit error rate of zero, and determine the eye diagram profile formed by the boundary coordinates.

[0015] The minimum eye diagram contour is determined from the eye diagram contours and used as the error boundary contour.

[0016] Optionally, the method further includes:

[0017] Identify the abnormal chips with an abnormal bit error rate among the qualified chips;

[0018] Obtain the digital eye diagram corresponding to the abnormal chip, and based on the boundary coordinate points with zero bit error rate in the digital eye diagram, determine the eye diagram contour formed by the boundary coordinate points as the first contour.

[0019] The largest first contour is determined from the first contour, and a new error boundary contour is obtained by enlarging the largest first contour by a preset ratio.

[0020] Optionally, the method further includes:

[0021] If the first proportion of the target coordinate points with a bit error rate of zero is not greater than a preset proportion threshold, the SerDes chip is determined to be an abnormal chip.

[0022] In a second aspect of the present invention, a qualification screening device for SerDes chips is also provided, the device comprising:

[0023] The acquisition module is used to acquire the bit error rate of the target coordinate point in the digital eye diagram corresponding to the serializer / deserializer SerDes chip, based on the target coordinate point of the bit error boundary contour in the predetermined digital eye diagram; wherein, the bit error boundary contour is determined in advance according to the boundary coordinate point with a bit error rate of zero in the digital eye diagram corresponding to the qualified SerDes chip;

[0024] The first determining module is used to determine that the SerDes chip is a qualified chip if the first proportion of the target coordinate points with a bit error rate of zero is greater than a preset proportion threshold.

[0025] Optionally, the device further includes:

[0026] The second determining module is used to determine the error boundary profile in the following manner:

[0027] Obtain digital eye diagrams corresponding to multiple qualified SerDes chips;

[0028] For each digital eye diagram, determine the boundary coordinates of the digital eye diagram with a bit error rate of zero, and determine the eye diagram profile formed by the boundary coordinates.

[0029] The minimum eye diagram contour is determined from the eye diagram contours and used as the error boundary contour.

[0030] Optionally, the device further includes:

[0031] The third determining module is used to determine the abnormal chips among the qualified chips that have abnormal bit error rates;

[0032] The fourth determining module is used to obtain the digital eye diagram corresponding to the abnormal chip, and based on the boundary coordinate points with zero bit error rate in the digital eye diagram, determine the eye diagram contour formed by the boundary coordinate points as the first contour.

[0033] The contour adjustment module is used to determine the largest first contour from the first contour, and to enlarge the largest first contour by a preset ratio to obtain a new error boundary contour.

[0034] Optionally, the device further includes:

[0035] The fifth determining module is used to determine that the SerDes chip is an abnormal chip if the first proportion of the target coordinate points with a bit error rate of zero is not greater than a preset proportion threshold.

[0036] In a third aspect of the present invention, an electronic device is also provided, including a processor, a communication interface, a memory, and a communication bus, wherein the processor, the communication interface, and the memory communicate with each other through the communication bus.

[0037] Memory, used to store computer programs;

[0038] When the processor executes a program stored in memory, it implements any of the above-described methods for screening SerDes chips.

[0039] In a fourth aspect of the present invention, a computer-readable storage medium is also provided, wherein a computer program is stored therein, and when executed by a processor, the computer program implements any of the above-described methods for screening a SerDes chip.

[0040] Beneficial effects of the embodiments of the present invention:

[0041] The SerDes chip screening method, apparatus, and electronic device provided in this invention can obtain the bit error rate (BER) of the target coordinate points in the digital eye diagram corresponding to the SerDes chip based on the target coordinate points of the BER boundary contour in a pre-determined digital eye diagram. If a first proportion of the target coordinate points with a BER of zero is greater than a preset proportion threshold, the SerDes chip is determined to be a qualified chip. The BER boundary contour is pre-determined based on the boundary coordinate points with a BER of zero in the digital eye diagram corresponding to the qualified SerDes chip. Therefore, when the proportion of target coordinate points with a BER of zero is greater than the preset proportion threshold, the BER performance of the SerDes chip to be screened is considered superior to that of a qualified chip, and it can be determined as a qualified chip.

[0042] As can be seen, by simply obtaining the bit error rate of the target coordinate point in the digital eye diagram corresponding to the SerDes chip, the SerDes chip can be qualified for screening. Compared with generating the entire digital eye diagram and then screening the SerDes chip based on the eye height and eye width indicators, this method can significantly shorten the testing time, reduce the occupation of the testing equipment, and improve the screening efficiency.

[0043] Furthermore, the error boundary profile can accurately measure the error performance of SerDes chips. By selecting an appropriate error boundary profile, the false rejection rate during chip screening can be significantly reduced. Adjusting the error boundary profile also allows for adjusting the stringency of chip screening.

[0044] Of course, implementing any product or method of the present invention does not necessarily require achieving all of the advantages described above at the same time. Attached Figure Description

[0045] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other embodiments can be obtained based on these drawings.

[0046] Figure 1 A flowchart illustrating a method for screening SerDes chips according to an embodiment of the present invention;

[0047] Figure 2 An exemplary digital eye diagram is provided for an embodiment of the present invention;

[0048] Figure 3 A schematic diagram illustrating chip screening based on error boundary contours provided in an embodiment of the present invention;

[0049] Figure 4 A flowchart illustrating another method for screening SerDes chips provided in an embodiment of the present invention;

[0050] Figure 5 A flowchart illustrating another method for screening SerDes chips provided in an embodiment of the present invention;

[0051] Figure 6 This is a schematic diagram of a screening device for a SerDes chip provided in an embodiment of the present invention;

[0052] Figure 7 A schematic structural diagram of an electronic device provided by an embodiment of the present invention. Detailed Implementation

[0053] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art based on this application are within the scope of protection of the present invention.

[0054] To address the problems of misidentification of SerDes chips and the long screening time and low efficiency in existing technologies, this application provides a method for screening SerDes chips, such as... Figure 1 As shown, Figure 1 A flowchart of a SerDes chip screening method provided in this embodiment of the invention includes:

[0055] Step S101: Based on the target coordinate points of the error boundary contour in the predetermined digital eye diagram, obtain the bit error rate of the target coordinate points in the digital eye diagram corresponding to the SerDes chip. The error boundary contour is determined in advance based on the boundary coordinate points with a bit error rate of zero in the digital eye diagram corresponding to the qualified SerDes chip.

[0056] For ease of understanding, the execution subject in the embodiments of the present invention may be a detection device or an electronic device connected to the detection device.

[0057] The SerDes chip mentioned in the embodiments of the present invention can be a chip that only contains the SerDes circuit structure, or it can be a chip that contains the SerDes circuit structure and other circuit structures.

[0058] In this embodiment of the invention, the qualified SerDes chip is a predetermined SerDes chip whose bit error rate meets a preset condition, wherein the preset condition can be determined according to actual needs.

[0059] For example, the SerDes chip is placed on a testing machine to test the bit error rate. If the bit error rate measured within a specific time period is zero, then the SerDes chip is determined to be a qualified SerDes chip.

[0060] Alternatively, the SerDes chip can be placed on a testing machine and its bit error rate (BER) tested under various specific environments. If the BER measured under different specific environments is zero, the SerDes chip is determined to be a qualified SerDes chip. Specific environments may include specific temperatures, humidity levels, temperature change rates, humidity change rates, etc.

[0061] The above are merely examples, and the specific methods for determining qualified SerDes chips are not limited in the embodiments of the present invention.

[0062] Those skilled in the art will understand that the digital eye diagram can be determined based on the test bitstream transmitted via the SerDes chip. The test bitstream can be a PRBS (Pseudo Random Bit Sequence) bitstream.

[0063] Specifically, the SerDes chip is placed on an SLT test bench, a test stream is sent from the TX end of the SerDes chip, and then the test stream is verified at the RX end. During this process, a digital eye diagram is generated.

[0064] Those skilled in the art will understand that digital eye diagrams are generated based on bit error rate information. Specifically, in digital eye diagram collection mode, the sampling points are moved relative to the optimal decision position, and the sampling voltage is shifted to obtain the estimated bit error rate at different coordinate points. In these coordinate points, the horizontal axis represents the offset at the sampling time, which can also be understood as Phase Offset; the vertical axis represents the offset of the sampling voltage, which can also be understood as Voltage Offset.

[0065] To further illustrate the digital eye diagram, this application provides a schematic diagram of a digital eye diagram, such as... Figure 2 As shown, each pixel (i.e., coordinate point) in a digital eye diagram corresponds to a BER (Bit Error Ratio), which can also be understood as the bit error rate. In the digital eye diagram, the horizontal axis represents the offset at the sampling time, and the vertical axis represents the offset of the sampling voltage. The digital eye diagram test circuit calculates the BER for each coordinate point by shifting the signal amplitude vertically and the sampling position horizontally, ultimately obtaining the correspondence between each coordinate point and the bit error rate. By plotting this correspondence, the digital eye diagram can be obtained.

[0066] The eye depth of a digital eye diagram represents the order of magnitude of the maximum bitstream sampled for BER calculation at the same coordinate point. A greater depth results in a more accurate digital eye diagram, but also requires more time. This embodiment of the invention does not limit the eye depth of the digital eye diagram.

[0067] In this embodiment of the invention, the error boundary contour in the digital eye diagram can be predetermined, that is, the target coordinate points contained in the error boundary contour can be determined in advance. Accordingly, when screening the SerDes chip, only the bit error rate of the target coordinate points in the digital eye diagram needs to be obtained.

[0068] In this embodiment of the invention, the pre-determined error boundary contour in the digital eye diagram can be determined based on the boundary coordinates of the zero-error rate in the digital eye diagrams corresponding to one or more qualified SerDes chips. As an example, if a SerDes chip has been determined to be a qualified chip, its digital eye diagram can be obtained, and then the contour formed by the boundary coordinates of the zero-error rate can be determined based on the digital eye diagram as the error boundary contour. Alternatively, digital eye diagrams of multiple qualified SerDes chips can be obtained, and the contour formed by multiple boundary coordinates of the zero-error rate can be determined based on these digital eye diagrams. The average contour is then taken as the error boundary contour.

[0069] Among them, the boundary coordinate points with a bit error rate of zero can be represented by the set {(X,Y)}. For example, the set contains n boundary coordinate points (X1,Y1), (X2,Y2), (X3,Y3), ..., (Xn,Yn). These boundary coordinate points constitute the bit error boundary profile, and the target coordinate points contained in the bit error boundary profile are the above n coordinate points.

[0070] Step S102: If the first proportion of the target coordinate points with a bit error rate of zero is greater than the preset proportion threshold, the SerDes chip is determined to be a qualified chip.

[0071] In this embodiment, if the proportion of zero-error-rate coordinate points in the target coordinate diagram of the SerDes chip to be screened is greater than a preset proportion threshold, it indicates that the contour formed by the boundary coordinate points with zero error rate in the digital eye diagram of the SerDes chip basically encompasses the error boundary contour. This can also be understood as the SerDes chip to be screened having more zero-error-rate coordinate points in its digital eye diagram. This is because the error boundary contour is predetermined based on the boundary coordinate points with zero error rate in the digital eye diagram of a qualified SerDes chip, and the SerDes chip to be screened has a larger number of zero-error-rate coordinate points in its digital eye diagram. Therefore, it can be determined that the performance of the SerDes chip to be screened is superior to that of a qualified SerDes chip.

[0072] As an example, the preset percentage threshold is set to 95%. Based on the predetermined error boundary profile, the bit error rate of the target coordinate points in the corresponding digital eye diagram of SerDes chip A is collected. After calculation, the proportion of coordinate points with a bit error rate of zero is 98%, which is greater than 95%, thus determining that SerDes chip A is a qualified chip.

[0073] The SerDes chip screening method provided in this invention can obtain the bit error rate (BER) of the target coordinate points in the digital eye diagram corresponding to the SerDes chip based on the target coordinate points of the BER boundary contour in a pre-determined digital eye diagram. If the proportion of coordinate points with a BER of zero in the target coordinate points is greater than a preset proportion threshold, the SerDes chip is determined to be a qualified chip. The BER boundary contour is pre-determined based on the boundary coordinate points with a BER of zero in the digital eye diagram corresponding to the qualified SerDes chip. Therefore, when the first proportion of coordinate points with a BER of zero in the target coordinate points is greater than the preset proportion threshold, the BER performance of the SerDes chip to be screened is considered superior to that of the qualified chip, and it can be determined as a qualified chip.

[0074] As can be seen, by simply obtaining the bit error rate of the target coordinate point in the digital eye diagram corresponding to the SerDes chip, the SerDes chip can be qualified for screening. Compared with generating the entire digital eye diagram and then screening the SerDes chip based on the eye height and eye width indicators, this method can significantly shorten the testing time, reduce the occupation of the testing equipment, and improve the screening efficiency.

[0075] Furthermore, the error boundary profile can accurately measure the error performance of SerDes chips. By selecting an appropriate error boundary profile, the false rejection rate during chip screening can be significantly reduced. Adjusting the error boundary profile also allows for adjusting the stringency of chip screening.

[0076] In this embodiment of the invention, SerDes chips are screened based on a pre-determined error boundary profile. Therefore, the pre-determined error boundary profile directly affects the subsequent screening of SerDes chips. If the set chip qualification conditions are too stringent, it may lead to usable chips being judged as unqualified chips. Therefore, in order to avoid this situation as much as possible, in one embodiment of the invention, the error boundary profile can be determined in the following way:

[0077] Step 11: Obtain the digital eye diagrams corresponding to multiple qualified SerDes chips.

[0078] Specifically, digital eye diagrams can be pre-collected for multiple qualified SerDes chips to obtain the digital eye diagram corresponding to each SerDes chip.

[0079] Step 12: For each digital eye diagram, determine the boundary coordinates of the point with zero bit error rate in the digital eye diagram, and determine the eye diagram profile formed by the boundary coordinates.

[0080] Each digital eye diagram has boundary coordinates with a bit error rate of zero, and the boundary coordinates with a bit error rate of zero in each digital eye diagram constitute an eye diagram profile.

[0081] Specifically, when determining the boundary coordinates of a zero-error-rate point in a digital eye diagram, if a coordinate point A with a zero-error-rate is surrounded by coordinate points with a zero-error-rate, then coordinate point A is not a boundary coordinate point. If a coordinate point B with a zero-error-rate is surrounded by coordinate points with a non-zero error rate, then coordinate point B is a boundary coordinate point.

[0082] Step 13: Determine the minimum eye diagram profile from the eye diagram profile as the error boundary profile.

[0083] As an example, the size of an eye diagram outline can be measured by the number of coordinate points contained within the eye diagram outline. That is, for each eye diagram outline, the number of coordinate points located inside the eye diagram outline is determined to measure the size of the eye diagram outline.

[0084] As another example, to simplify the calculation, the size of the eye diagram outline can also be measured by the product of the eye height and the eye width.

[0085] Each of the above eye diagram contours corresponds to a qualified SerDes chip, and the size of the eye diagram contour can reflect the bit error rate performance of the SerDes chip. Therefore, in this embodiment of the invention, the smallest eye diagram contour is used as the bit error boundary contour, and the qualified screening of SerDes chips is performed based on the bit error boundary contour. This avoids the situation where the qualified screening conditions are too strict, which would lead to the unqualified chips being judged as unqualified chips, resulting in a low chip yield.

[0086] See Figure 3 , Figure 3 This is a schematic diagram illustrating chip screening based on error boundary contours, provided by an embodiment of the present invention. Figure 3 The coordinates marked with the '#' symbol represent points where the bit error rate is not zero. All other coordinates represent points where the bit error rate is zero. Figure 3 The curve in the diagram represents the determined minimum eye diagram profile, which is also the error boundary profile. For Figure 3 The digital eye diagram corresponding to the SerDes chip shown in the figure shows that the bit error rate of the target coordinate points corresponding to the bit error boundary contour is zero. Therefore, it can be determined that the SerDes chip is a qualified SerDes chip.

[0087] In this embodiment, since all acquired SerDes chips are qualified SerDes chips, the eye diagram contours formed by the boundary coordinates of the zero bit error rate in the digital eye diagrams corresponding to these qualified chips can all be used as error boundary contours. Determining the smallest eye diagram contour as the error boundary contour based on multiple eye diagram contours can further reduce misjudgments of SerDes chips and improve SerDes chip yield during subsequent chip screening.

[0088] In this embodiment of the invention, the pre-determined error boundary profile may not be the most suitable. In the subsequent chip screening process, the error boundary profile can be re-determined.

[0089] For details, see Figure 4 , Figure 4 A flowchart of another SerDes chip screening method provided in this embodiment of the invention includes:

[0090] Step S101: Based on the target coordinate points of the error boundary contour in the predetermined digital eye diagram, obtain the bit error rate of the target coordinate points in the digital eye diagram corresponding to the SerDes chip. The error boundary contour is determined in advance based on the boundary coordinate points with a bit error rate of zero in the digital eye diagram corresponding to the qualified SerDes chip.

[0091] This step is the same as S101 above, and you can refer to the relevant description of S101 above, so it will not be repeated here.

[0092] Step S102: If the first proportion of the target coordinate points with a bit error rate of zero is greater than the preset proportion threshold, the SerDes chip is determined to be a qualified chip.

[0093] This step is the same as S102 above, and you can refer to the relevant description of S102 above, so it will not be repeated here.

[0094] Step S201: Identify the abnormal chips among the qualified chips that have abnormal bit error rates.

[0095] In this embodiment, an abnormal chip refers to a chip that was initially determined to be a qualified chip but exhibits an abnormal bit error rate during subsequent use. Specifically, the usage of publicly released qualified SerDes chips can be tracked. If a SerDes chip confirmed as qualified is found to have an abnormal bit error rate, that chip is identified as an abnormal chip.

[0096] For example, by tracking the usage of publicly released qualified SerDes chips A, B, and C, and identifying chip A as an abnormal chip when it experiences an abnormal bit error rate during subsequent use.

[0097] Step S202: Obtain the digital eye diagram corresponding to the abnormal chip, and determine the eye diagram contour formed by the boundary coordinate points with a bit error rate of zero in the digital eye diagram, as the first contour.

[0098] The abnormal chip is a SerDes chip that was pre-judged as a qualified chip based on the error boundary profile. Therefore, the subsequent identification of the abnormal chip indicates that the pre-determined error boundary profile was not accurate enough, which led to the unusable chip being judged as a qualified chip.

[0099] For example, for an abnormal chip A, obtain the digital eye diagram of chip A. Then, based on the boundary coordinates of the zero bit error rate in the digital eye diagram, determine the eye diagram contour formed by the boundary coordinates, which is used as the first contour.

[0100] Step S203: Determine the largest first contour from the first contour, and enlarge the largest first contour by a preset ratio to obtain a new error boundary contour.

[0101] In this embodiment of the invention, in order to accurately identify the abnormal chip by the new error boundary contour, if there are multiple abnormal chips, the corresponding digital eye diagram can be obtained for each abnormal chip, and the boundary coordinate point with a zero bit error rate in the digital eye diagram can be determined to form a first contour. Then, the largest first contour is determined from the first contour, and the new error boundary contour is obtained by enlarging it by a preset ratio based on the largest first contour.

[0102] As another example, the range of the new error boundary contour can cover the first contour corresponding to any abnormal chip.

[0103] Therefore, when using the new error boundary profile to identify the above-mentioned abnormal chips, these chips can be identified as unqualified chips.

[0104] As can be seen, in this embodiment of the invention, after identifying an abnormal chip with an abnormal bit error rate among qualified chips, the digital eye diagram of the abnormal chip is obtained. The boundary coordinates of the abnormal chip's digital eye diagram with a bit error rate of zero are determined, and the eye diagram contour formed by the boundary coordinates of the zero bit error rate boundary is used as the first contour. A maximum first contour is determined from the first contour, and a new bit error boundary contour is obtained by scaling up the maximum first contour by a preset ratio. This further improves the accuracy of SerDes chip screening and reduces the subsequent maintenance costs of chip misjudgment.

[0105] In this embodiment of the invention, if the first proportion of target coordinate points with a zero bit error rate is not greater than a preset proportion threshold, the SerDes chip is determined to be an abnormal chip. Because the predetermined bit error rate boundary profile is determined by the boundary coordinate point profile of the digital eye diagram of a chip that can be used normally but has poor performance, if the first proportion of target coordinate points with a non-zero bit error rate is not greater than the preset proportion threshold, it indicates that there are too many coordinate points with a non-zero bit error rate in the digital eye diagram of the SerDes chip. Therefore, the SerDes chip is determined to be unqualified.

[0106] For example, the preset ratio threshold is set to 95%. For SerDes chip D, based on the predetermined error boundary profile, the bit error rate of the target coordinate point in the digital eye diagram of SerDes chip D is obtained. After calculation, the first proportion of coordinate points with a bit error rate of zero is 90%, which is less than the preset ratio threshold of 95%, and SerDes chip D is determined to be a defective chip.

[0107] To further illustrate the method for selecting SerDes chips, this application provides an exemplary method for selecting SerDes chips, such as... Figure 5 As shown, Figure 5 A flowchart illustrating another method for screening SerDes chips provided in this embodiment of the invention may specifically include the following steps:

[0108] Step S301, Begin.

[0109] Step S302, preset TX terminal parameters.

[0110] A set of preset parameters for the TX end is determined through manual testing. These preset parameters can be understood as SerDes parameters, which typically include pre-emphasis parameters and pre-equalization parameters.

[0111] Step S303: Send the test stream.

[0112] Place the SerDes chip to be screened on the SLT test machine and send the test bit stream at the TX end of the SerDes chip.

[0113] Step S304: The RX end checks for bit errors.

[0114] At the RX end, check the test bitstream for errors. If errors are found, proceed to step S305 to adjust the parameters. If not, proceed to step S306.

[0115] Step S305: Adjust the parameters.

[0116] Specifically, the aforementioned preset parameters need to be adjusted. It must be ensured that, based on the adjusted parameters and under sufficient testing conditions, the PRBS bitstream sent from the TX end has no errors during verification at the RX end. At this point, these parameters can be fixed as the optimal parameters in the screening environment configuration.

[0117] Step S306: Collect eye diagram data.

[0118] Specifically, digital eye diagrams corresponding to multiple qualified SerDes chips are collected through sampling.

[0119] Step S307: Determine the eye diagram to identify the contour.

[0120] Based on the digital eye diagrams corresponding to multiple qualified SerDes chips, and combined with the theoretical eye diagram model, the minimum eye diagram judgment contour (i.e., the aforementioned error boundary contour) is determined. The specific method for determining the eye diagram judgment contour is the same as the method for determining the error boundary contour described above, and will not be repeated here. Figure 3 As shown, Figure 3 The curve in the diagram is the obtained eye diagram judgment contour.

[0121] Step S308: Does the eye diagram need to be corrected to determine the contour?

[0122] Determine whether the eye diagram's judgment contour is the smallest contour formed by boundary coordinate points with a zero bit error rate. If yes, execute S309; ​​otherwise, execute S306.

[0123] Step S309: Correct the eye diagram to determine the contour.

[0124] If the eye diagram judgment contour is not the minimum boundary contour formed by boundary coordinate points with zero bit error rate, then the eye diagram judgment contour is corrected.

[0125] Step S310: Establish the database.

[0126] Specifically, the usage of publicly released qualified SERDES chips can be tracked, and a database can be established to retain relevant data on all tested qualified SERDES chips.

[0127] Step S311: Determine the SerDes chip to be screened.

[0128] Step S312: Collect pixel bit error rate based on the determined eye diagram to determine the contour.

[0129] The obtained target pixel positions (i.e., the aforementioned target coordinates) are applied to the SLT sieve system to collect the bit error rate of the target pixels at the corresponding positions in the digital eye diagram of the SerDes chip under test.

[0130] Step S313: Compare whether the bit error rate of the eye diagram contour pixels to be screened is 0.

[0131] Based on the target pixel location, compare whether the bit error rate of the target pixels corresponding to these locations in the digital eye diagram of the SerDes chip to be screened is 0. Alternatively, slight changes in the shape of the digital eye diagram can be allowed, such as judging whether the proportion of target pixels with a bit error rate of zero is greater than a preset proportion threshold, for example, the preset proportion threshold can be 95%. If yes, proceed to step S314; if no, proceed to step S317.

[0132] Step S314: Determine that the SerDes chip is normal.

[0133] If the bit error rate of all pixels corresponding to the target pixel position in the digital eye diagram of the SerDes chip to be screened is zero, or the proportion of target pixels with a bit error rate of zero is greater than a preset proportion threshold, then the SerDes chip is judged to be normal and a qualified chip.

[0134] Step S315: Track the subsequent use of the SerDes chip.

[0135] Since the initial eye diagram used to determine the contour may not be the most suitable, in order to prevent errors in the selection, it is necessary to follow up and determine whether the SerDes chip can be used normally.

[0136] Step S316: Is there any abnormality?

[0137] If yes, it indicates that the chip malfunctioned during subsequent use, and the eye diagram used to screen the SerDes chip was not suitable. Therefore, the eye diagram used during screening needs to be corrected, and step S309 is executed. If no, it indicates that the chip is normal, the tracking of the chip ends, and step S318 is executed.

[0138] Step S317: Determine that the SerDes chip is abnormal.

[0139] If the bit error rate of the pixel corresponding to the target pixel position in the digital eye diagram of the SerDes chip to be screened is not zero, or the proportion of the number of target pixels with a bit error rate of zero is not greater than a preset proportion threshold, then the SerDes chip is determined to be abnormal.

[0140] Step S318, End.

[0141] In this embodiment, the optimal SerDes parameters are first determined. Then, based on the optimal parameters, digital eye diagrams of multiple qualified SerDes chips are obtained to determine the eye diagram judgment contour, i.e., the aforementioned bit error rate boundary contour. The target pixel positions determined based on the eye diagram judgment contour are applied to the SLT chip screening system to obtain the bit error rate of the corresponding pixels in the digital eye diagram of the SerDes chip to be screened. The bit error rate of the corresponding pixels in the digital eye diagram of the SerDes chip to be screened is compared to see if it is zero. If it is, the SerDes chip is determined to be a normal chip, i.e., a qualified chip. If not, the SerDes chip is determined to be an abnormal chip. The subsequent usage of the SerDes chip is tracked. If an abnormality occurs, the process returns to the step of correcting the eye diagram judgment contour, adjusting the eye diagram judgment contour, and continuing the SerDes chip screening step based on the adjusted eye diagram judgment contour. In this embodiment, the selection is performed by identifying key points in the eye diagram acquisition, i.e., the eye diagram judgment contour. Compared to existing technologies that rely on bit error rate (BER) or the eye height and width of the digital eye diagram for selection, this reduces false positives and improves chip yield. Furthermore, compared to acquiring a complete digital eye diagram, this embodiment only acquires the BER for pixels corresponding to the target pixel location, significantly shortening the selection time and improving the selection efficiency of the SerDes chip. Additionally, by establishing a database in this embodiment, the subsequent maintenance costs for chip anomalies can be reduced.

[0142] Based on the same inventive concept, this application correspondingly provides a screening device for SerDes chips, such as... Figure 6 As shown, Figure 6 A schematic diagram of a screening device for a SerDes chip provided in an embodiment of the present invention includes:

[0143] The acquisition module 601 is used to acquire the bit error rate of the target coordinate point in the digital eye diagram corresponding to the SerDes chip based on the target coordinate point of the bit error boundary contour in the predetermined digital eye diagram; wherein, the bit error boundary contour is determined in advance based on the boundary coordinate point with a bit error rate of zero in the digital eye diagram corresponding to the qualified SerDes chip;

[0144] The first determining module 602 is used to determine the SerDes chip as a qualified chip if the first proportion of the target coordinate points with a bit error rate of zero is greater than a preset proportion threshold.

[0145] The SerDes chip screening method provided in this invention can obtain the bit error rate (BER) of the target coordinate points in the digital eye diagram corresponding to the SerDes chip based on the target coordinate points of the BER boundary contour in a pre-determined digital eye diagram. If the first proportion of the target coordinate points with a BER of zero is greater than a preset proportion threshold, the SerDes chip is determined to be a qualified chip. The BER boundary contour is pre-determined based on the boundary coordinate points with a BER of zero in the digital eye diagram corresponding to the qualified SerDes chip. Therefore, when the first proportion of the target coordinate points with a BER of zero is greater than the preset proportion threshold, the BER performance of the SerDes chip to be screened is considered superior to that of the qualified chip, and it can be determined as a qualified chip.

[0146] As can be seen, by simply obtaining the bit error rate of the target coordinate point in the digital eye diagram corresponding to the SerDes chip, the SerDes chip can be qualified for screening. Compared with generating the entire digital eye diagram and then screening the SerDes chip based on the eye height and eye width indicators, this method can significantly shorten the testing time, reduce the occupation of the testing equipment, and improve the screening efficiency.

[0147] Furthermore, the error boundary profile can accurately measure the error performance of SerDes chips. By selecting an appropriate error boundary profile, the false rejection rate during chip screening can be significantly reduced. Adjusting the error boundary profile also allows for adjusting the stringency of chip screening.

[0148] In one possible embodiment, the device further includes:

[0149] The second determining module is used to determine the error boundary profile in the following manner:

[0150] Obtain digital eye diagrams corresponding to multiple qualified SerDes chips;

[0151] For each digital eye diagram, determine the boundary coordinates of the digital eye diagram with a bit error rate of zero, and determine the eye diagram profile formed by the boundary coordinates.

[0152] The minimum eye diagram contour is determined from the eye diagram contour and used as the error boundary contour.

[0153] In one possible embodiment, the device further includes:

[0154] The third determination module is used to identify abnormal chips among qualified chips that have abnormal bit error rates;

[0155] The fourth determination module is used to obtain the digital eye diagram corresponding to the abnormal chip, and based on the boundary coordinate points with zero bit error rate in the digital eye diagram, determine the eye diagram contour formed by the boundary coordinate points as the first contour.

[0156] The contour adjustment module is used to determine the largest first contour from the first contour, and to enlarge the largest first contour by a preset ratio to obtain a new error boundary contour.

[0157] In one possible embodiment, the device further includes:

[0158] The fifth determination module is used to determine that the SerDes chip is an abnormal chip if the first proportion of the target coordinate points with a bit error rate of zero is not greater than a preset proportion threshold.

[0159] This invention also provides an electronic device, such as... Figure 7 As shown, it includes a processor 701, a communication interface 702, a memory 703, and a communication bus 704, wherein the processor 701, the communication interface 702, and the memory 703 communicate with each other through the communication bus 704.

[0160] Memory 703 is used to store computer programs;

[0161] When processor 701 executes a program stored in memory 703, it performs the following steps:

[0162] Based on the target coordinates of the error boundary contour in the predetermined digital eye diagram, the bit error rate of the target coordinates in the digital eye diagram corresponding to the SerDes chip is obtained. The error boundary contour is determined in advance based on the boundary coordinates of the qualified SerDes chip corresponding to the digital eye diagram with a bit error rate of zero.

[0163] If the proportion of the target coordinate points with a bit error rate of zero is greater than the preset proportion threshold, the SerDes chip is determined to be a qualified chip.

[0164] The communication bus mentioned in the above electronic devices can be a Peripheral Component Interconnect (PCI) bus or an Extended Industry Standard Architecture (EISA) bus, etc. This communication bus can be divided into address bus, data bus, control bus, etc. For ease of illustration, only one thick line is used to represent it in the diagram, but this does not mean that there is only one bus or one type of bus.

[0165] The communication interface is used for communication between the aforementioned electronic devices and other devices.

[0166] The memory may include random access memory (RAM) or non-volatile memory (NVM), such as at least one disk storage device. Optionally, the memory may also be at least one storage device located remotely from the aforementioned processor.

[0167] The processors mentioned above can be general-purpose processors, including central processing units (CPUs), network processors (NPs), etc.; they can also be digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components.

[0168] In another embodiment of the present invention, a computer-readable storage medium is also provided, which stores a computer program that, when executed by a processor, implements the steps of any of the above-described SerDes chip screening methods.

[0169] In another embodiment of the present invention, a computer program product containing instructions is also provided, which, when run on a computer, causes the computer to execute any of the SerDes chip screening methods described in the above embodiments.

[0170] In the above embodiments, implementation can be achieved entirely or partially through software, hardware, firmware, or any combination thereof. When implemented using software, it can be implemented entirely or partially in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, all or part of the processes or functions described in the embodiments of the present invention are generated. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, the computer instructions can be transmitted from one website, computer, server, or data center to another website, computer, server, or data center via wired (e.g., coaxial cable, fiber optic, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) means. The computer-readable storage medium can be any available medium that a computer can access or a data storage device such as a server or data center that integrates one or more available media. The available medium can be a magnetic medium (e.g., floppy disk, hard disk, magnetic tape), an optical medium (e.g., DVD), or a semiconductor medium (e.g., solid state disk (SSD)).

[0171] It should be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0172] The various embodiments in this specification are described in a related manner. Similar or identical parts between embodiments can be referred to mutually. Each embodiment focuses on describing the differences from other embodiments. In particular, the embodiments of apparatus, electronic devices, computer-readable storage media, and computer program products are basically similar to the method embodiments, and therefore the descriptions are relatively simple; relevant parts can be referred to the descriptions of the method embodiments.

[0173] The above description is merely a preferred embodiment of the present invention and is not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention are included within the scope of protection of the present invention.

Claims

1. A method for screening SerDes chips, characterized in that, The method includes: Based on the target coordinates of the error boundary contour in the predetermined digital eye diagram, the bit error rate of the target coordinates in the digital eye diagram corresponding to the serializer / deserializer SerDes chip is obtained; wherein, the error boundary contour is determined in advance based on the boundary coordinates of the zero bit error rate in the digital eye diagram corresponding to the qualified SerDes chip; If the first proportion of the target coordinate points with a bit error rate of zero is greater than a preset proportion threshold, the SerDes chip is determined to be a qualified chip.

2. The method according to claim 1, characterized in that, The error boundary profile is determined as follows: Obtain digital eye diagrams corresponding to multiple qualified SerDes chips; For each digital eye diagram, determine the boundary coordinates of the digital eye diagram with a bit error rate of zero, and determine the eye diagram profile formed by the boundary coordinates. The minimum eye diagram contour is determined from the eye diagram contours and used as the error boundary contour.

3. The method according to claim 1, characterized in that, The method further includes: Identify the abnormal chips with an abnormal bit error rate among the qualified chips; Obtain the digital eye diagram corresponding to the abnormal chip, and based on the boundary coordinate points with zero bit error rate in the digital eye diagram, determine the eye diagram contour formed by the boundary coordinate points as the first contour. The largest first contour is determined from the first contour, and a new error boundary contour is obtained by enlarging the largest first contour by a preset ratio.

4. The method according to claim 1, characterized in that, The method further includes: If the first proportion of the target coordinate points with a bit error rate of zero is not greater than a preset proportion threshold, the SerDes chip is determined to be an abnormal chip.

5. A qualification screening device for SerDes chips, characterized in that, The device includes: The acquisition module is used to acquire the bit error rate of the target coordinate point in the digital eye diagram corresponding to the serializer / deserializer SerDes chip, based on the target coordinate point of the bit error boundary contour in the predetermined digital eye diagram; wherein, the bit error boundary contour is determined in advance according to the boundary coordinate point with a bit error rate of zero in the digital eye diagram corresponding to the qualified SerDes chip; The first determining module is used to determine that the SerDes chip is a qualified chip if the first proportion of the target coordinate points with a bit error rate of zero is greater than a preset proportion threshold.

6. The apparatus according to claim 5, characterized in that, The device further includes: The second determining module is used to determine the error boundary profile in the following manner: Obtain digital eye diagrams corresponding to multiple qualified SerDes chips; For each digital eye diagram, determine the boundary coordinates of the digital eye diagram with a bit error rate of zero, and determine the eye diagram profile formed by the boundary coordinates. The minimum eye diagram contour is determined from the eye diagram contours and used as the error boundary contour.

7. The apparatus according to claim 5, characterized in that, The device further includes: The third determining module is used to determine the abnormal chips among the qualified chips that have abnormal bit error rates; The fourth determining module is used to obtain the digital eye diagram corresponding to the abnormal chip, and based on the boundary coordinate points with zero bit error rate in the digital eye diagram, determine the eye diagram contour formed by the boundary coordinate points as the first contour. The contour adjustment module is used to determine the largest first contour from the first contour, and to enlarge the largest first contour by a preset ratio to obtain a new error boundary contour.

8. The apparatus according to claim 5, characterized in that, The device further includes: The fifth determining module is used to determine that the SerDes chip is an abnormal chip if the first proportion of the target coordinate points with a bit error rate of zero is not greater than a preset proportion threshold.

9. An electronic device, characterized in that, It includes a processor, a communication interface, a memory, and a communication bus, wherein the processor, the communication interface, and the memory communicate with each other through the communication bus; Memory, used to store computer programs; A processor, when executing a program stored in memory, implements the steps of the method described in any one of claims 1-4.

10. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program that, when executed by a processor, implements the steps of the method described in any one of claims 1-4.

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