A display panel and display device

Abstract

The application discloses a display panel and a display device, the display panel comprising: a pixel circuit and a light emitting element; the pixel circuit comprising a light modulation module, a driving module and a biasing module; the driving module is used for providing a driving current for the light emitting element, and the driving module comprises a driving transistor; the biasing module is connected between a biasing signal end and a first end of the driving transistor, a control end of the biasing module is connected to a biasing control end, the biasing module is used for biasing and adjusting the driving transistor, and the biasing signal end provides a biasing signal; the pixel circuit comprises a plurality of working stages, the plurality of working stages at least comprising a first working stage and a second working stage, the light emitting time of the light emitting element is different in the first working stage and the second working stage, and the biasing signal voltage provided by the biasing signal end is different in the first working stage and the second working stage. In the application, the biasing signal voltage provided by the biasing signal end is different in the first working stage and the second working stage, and the display uniformity can be improved.

Description

Technical Field

[0001] This invention relates to the field of display technology, and more particularly to a display panel and a display device. Background Technology

[0002] In a display panel, the pixel circuit provides the driving current required for the light-emitting elements of the display panel and controls whether the light-emitting elements enter the light-emitting stage. It is an indispensable component in most self-emissive display panels.

[0003] In existing display panels, the image exhibits poor uniformity at low frequencies, affecting the display effect. Summary of the Invention

[0004] The present invention provides a display panel and a display device to solve the problem of poor uniformity in existing display panels.

[0005] According to one aspect of the present invention, a display panel is provided, comprising:

[0006] Pixel circuits and light-emitting elements;

[0007] The pixel circuit includes a dimming module, a driving module, and a bias module, wherein the dimming module and the driving module are both connected to the light-emitting element.

[0008] The control terminal of the dimming module is connected to the dimming control terminal, and the dimming module is used to adjust the light emission duration of the light-emitting element;

[0009] The driving module is used to provide driving current to the light-emitting element, and the driving module includes a driving transistor;

[0010] The bias module is connected between the bias signal terminal and the first terminal of the driving transistor. The control terminal of the bias module is connected to the bias control terminal. The bias module is used to adjust the bias of the driving transistor. The bias signal terminal provides a bias signal.

[0011] The pixel circuit includes multiple operating stages, including at least a first operating stage and a second operating stage. The light-emitting element emits light for different durations in the first operating stage and the second operating stage, and the bias signal terminal provides different bias signal voltages in the first operating stage and the second operating stage.

[0012] According to another aspect of the present invention, a display device is provided, comprising a display panel as described above.

[0013] In this invention, the pixel circuit includes a dimming module, a driving module, and a bias module. The driving module provides driving current to the light-emitting element, and the bias module is connected between the bias signal terminal and the first terminal of the driving transistor. The bias module adjusts the bias of the driving transistor, and the bias signal terminal provides a bias signal. Since the light-emitting duration of the light-emitting element is different in the first and second working stages, the threshold voltage offset of the driving transistor is different in the first and second working stages. In the non-light-emitting stage, by setting the bias signal voltage provided by the bias signal terminal to be different in the first and second working stages, the bias adjustment can be performed separately for the threshold voltage offset phenomenon of the driving transistor in the first and second working stages, reducing the difference in the threshold voltage offset of the driving transistor in the first and second working stages, and making the bias state of the driving transistor in each working stage with different light-emitting durations tend to be consistent, thereby improving display uniformity.

[0014] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of the present invention, nor is it intended to limit the scope of the invention. Other features of the invention will become readily apparent from the following description. Attached Figure Description

[0015] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0016] Figure 1 This is a schematic diagram of a pixel circuit of a display panel provided in an embodiment of the present invention;

[0017] Figure 2 This is a schematic diagram of the working stages of a pixel circuit provided in an embodiment of the present invention;

[0018] Figure 3 This is a schematic diagram of the drift of the Id-Vg curve of the driving transistor;

[0019] Figure 4 This is a schematic diagram of another pixel circuit operation stage provided in an embodiment of the present invention;

[0020] Figure 5 This is a schematic diagram of another pixel circuit operation stage provided in an embodiment of the present invention;

[0021] Figure 6 This is a schematic diagram of another pixel circuit operation stage provided in an embodiment of the present invention;

[0022] Figure 7This is a schematic diagram of another pixel circuit operation stage provided in an embodiment of the present invention;

[0023] Figure 8 This is a schematic diagram of another pixel circuit operation stage provided in an embodiment of the present invention;

[0024] Figure 9 This is a schematic diagram of another pixel circuit operation stage provided in an embodiment of the present invention;

[0025] Figure 10 This is a schematic diagram of another pixel circuit operation stage provided in an embodiment of the present invention;

[0026] Figure 11 This is a schematic diagram of another pixel circuit operation stage provided in an embodiment of the present invention;

[0027] Figure 12 yes Figure 1 The timing diagram of the pixel circuit shown is shown.

[0028] Figure 13 yes Figure 1 Another timing diagram of the pixel circuit shown;

[0029] Figure 14 yes Figure 1 Another timing diagram of the pixel circuit shown;

[0030] Figure 15 This is a schematic diagram of another pixel circuit provided in an embodiment of the present invention;

[0031] Figure 16 yes Figure 15 The timing diagram of the pixel circuit shown is shown.

[0032] Figure 17 This is a timing diagram of another pixel circuit provided in an embodiment of the present invention;

[0033] Figure 18 This is a timing diagram of another pixel circuit provided in an embodiment of the present invention;

[0034] Figure 19 This is a schematic diagram of a display device provided in an embodiment of the present invention. Detailed Implementation

[0035] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0036] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0037] Figure 1 This is a schematic diagram of a pixel circuit for a display panel provided in an embodiment of the present invention. Figure 2 This is a schematic diagram of the working stages of a pixel circuit provided in an embodiment of the present invention. The display panel provided in this embodiment includes: a light-emitting element 10 and a pixel circuit 20; the pixel circuit 20 includes a dimming module 21, a driving module 22 and a bias module 23, both of which are connected to the light-emitting element 10; the control terminal of the dimming module 21 is connected to the dimming control terminal EM, and the dimming module 21 is used to adjust the light-emitting duration of the light-emitting element 10; the driving module 22 is used to provide driving current to the light-emitting element 10, and the driving module 22 includes a driving transistor M0; the bias module 23 is connected between the bias signal terminal DVI and the first terminal N1 of the driving transistor M0, and the control terminal of the bias module 23 is connected to the bias control terminal SPI, and the bias module 23 is used to adjust the bias of the driving transistor M0, and the bias signal terminal DVI provides a bias signal; the pixel circuit 20 includes multiple operating stages, and the multiple operating stages include at least a first operating stage W1 and a second operating stage W2, the light-emitting duration of the light-emitting element 10 is different in the first operating stage W1 and the second operating stage W2, and the bias signal voltage provided by the bias signal terminal DVI is different in the first operating stage W1 and the second operating stage W2.

[0038] It is important to note that Figure 1 and Figure 2The above embodiments only illustrate key structures and do not include all the structures and timing of the pixel circuit. Other circuit structures, all or part of the pixel circuit, will be gradually shown in the following description of this embodiment.

[0039] In this embodiment, the pixel circuit 20 includes a driving module 22, which includes a control terminal N3, a first terminal N1, and a second terminal N2. Optionally, the first terminal N1 of the driving module 22 is connected to the output terminal of the bias module 23, and simultaneously, the first terminal N1 of the driving module 22 is coupled to the first power supply terminal PVDD; the second terminal N2 of the driving module 22 is coupled to the light-emitting element 10. The driving module 22 includes a driving transistor M0, the gate of which is connected to the control terminal N3 of the driving module 22, and the first terminal of the driving transistor M0 is connected to the first terminal N1 of the driving module 22, i.e., the output terminal of the bias module 23. When the control terminal N3 of the driving module 22 receives a valid pulse signal, the driving transistor M0 is turned on, and the driving module 22 provides driving current to the light-emitting element 10; when the control terminal N3 of the driving module 22 receives an invalid pulse signal, the driving transistor M0 is turned off.

[0040] If the driving transistor M0 is a P-type transistor, then the input terminal (source) of the driving transistor M0 is connected to the output terminal of the bias module 23, and the output terminal (drain) of the driving transistor M0 is coupled to the light-emitting element 10. Here, N1 can also be represented as the first terminal of the driving transistor M0. It is understood that the source and drain of the transistor are not constant but change with the driving state of the transistor. If the driving transistor M0 is a P-type transistor, then the effective pulse signal received by the control terminal N3 of the driving module 22 is a low voltage to turn on the driving transistor M0, and the invalid pulse signal received by the control terminal N3 of the driving module 22 is a high voltage to turn off the driving transistor M0. In other embodiments, those skilled in the art can reasonably design the first terminal of the driving module to be connected to the output terminal of the bias module according to the product requirements, and simultaneously, the first terminal of the driving module is coupled to the light-emitting element; the second terminal of the driving module is coupled to the first power supply terminal PVDD. In the following text, ... Figure 1 The pixel circuit shown is used as an example for explanation.

[0041] The pixel circuit 20 includes a dimming module 21. The control terminal of the dimming module 21 is connected to the dimming control terminal EM. The dimming module 21 is used to adjust the light emission duration of the light-emitting element 10. By controlling the on / off state of the dimming module 21, the driving current supplied to the light-emitting element 10 can be controlled. When the dimming control terminal EM outputs a valid pulse signal, the dimming module 21 is turned on, driving the light-emitting element 10 into the light emission stage, and the driving module 22 is turned on to allow the driving current to flow into the light-emitting element 10. When the dimming control terminal EM outputs an invalid pulse signal, the dimming module 21 is turned off, disconnecting the path for the driving current to flow into the light-emitting element 10.

[0042] The optional dimming module 21 includes a first dimming unit 21a and a second dimming unit 21b. The first dimming unit 21a includes a first dimming transistor M1, and the second dimming unit 21b includes a second dimming transistor M2. The control terminal of the first dimming transistor M1 is connected to the dimming control terminal EMa, and the first dimming transistor M1 is connected between the first power supply terminal PVDD and the driving module 22. The control terminal of the second dimming transistor M2 is connected to the dimming control terminal EMb, and the second dimming transistor M2 is connected between the driving module 22 and the light-emitting element 10. The optional dimming control terminal EMa and the dimming control terminal EMb are connected to the same light-emitting control signal line. When the light-emitting control signal line outputs a valid pulse signal, the first dimming transistor M1 and the second dimming transistor M2 are simultaneously turned on, driving the light-emitting element 10 into the light-emitting stage, and driving current flows into the light-emitting element 10. When the light-emitting control signal line outputs an invalid pulse signal, the first dimming transistor M1 and the second dimming transistor M2 are simultaneously turned off, disconnecting the path of driving current flowing into the light-emitting element 10. In other embodiments, those skilled in the art can design the dimming control terminal EMa and the dimming control terminal EMb to be connected to different light emission control signal lines according to the product requirements; this is not limited to this. By adjusting the duty cycle of the first dimming transistor M1 and the second dimming transistor M2, the light emission duration of the light-emitting element 10 is changed, thereby achieving dimming of the pixel circuit 20.

[0043] The pixel circuit 20 includes a bias module 23, which is connected between the bias signal terminal DVI and the first terminal N1 of the driving transistor M0. The control terminal of the bias module 23 is connected to the bias control terminal SPI. The bias module 23 is used to adjust the bias of the driving transistor M0, and the bias signal terminal DVI provides a bias signal. The bias signal terminal DVI provides a bias signal, and the pulse signal provided by the bias control terminal SPI controls the bias module 23 to be turned on or off. When the bias control terminal SPI provides a valid pulse signal, the bias module 23 is turned on, and the bias signal provided by the bias signal terminal DVI is written to the first terminal N1 of the driving transistor M0. When the bias control terminal SPI provides an invalid pulse signal, the bias module 23 is turned off, disconnecting the path between the bias signal terminal DVI and the first terminal N1 of the driving transistor M0. If the bias signal provided by the bias signal terminal DVI is low voltage, then when the bias module 23 is turned on, the bias signal provided by the bias signal terminal DVI pulls down the potential of the first terminal N1 of the driving transistor M0; if the bias signal provided by the bias signal terminal DVI is high voltage, then when the bias module 23 is turned on, the bias signal provided by the bias signal terminal DVI pulls up the potential of the first terminal N1 of the driving transistor M0.

[0044] When the dimming control terminal EM outputs a valid pulse signal, the dimming module 21 is turned on, driving the light-emitting element 10 into the light-emitting stage. At this time, the driving transistor M0 is turned on. Figure 1As shown, for the PMOS type driving transistor M0, when the driving transistor M0 is turned on, its gate (N3) potential Vg is lower than its source (N1) potential. At this time, the driving transistor M0 is operating in a non-saturated state, and its drain (N2) voltage is often lower than its gate (N3) voltage. Therefore, during the light-emitting stage of the pixel circuit 20, there may be a phenomenon where the PMOS transistor is turned on but the drain voltage is lower than the gate voltage. Moreover, the voltage difference between the drain voltage and the gate voltage is often quite large, resulting in a large potential difference. Over time, this setting will lead to the polarization of ions inside the driving transistor M0, thereby forming a built-in electric field inside the driving transistor M0, causing the threshold voltage of the driving transistor M0 to continuously increase.

[0045] The pixel circuit 20 also includes a reset module 24 and a compensation module 25. The control terminal of the reset module 24 is connected to the reset control terminal S1N1, and the reset module 24 is connected between the reset signal terminal VREF and the control terminal N3 of the drive module 22. The control terminal of the compensation module 25 is connected to the compensation control terminal S2N1, and the compensation module 25 is connected between the control terminal N3 and the second terminal N2 of the drive module 22. Optionally, the reset module 24 includes a reset transistor M4, and the compensation module 25 includes a compensation transistor M5. The reset transistor M4 can be an NMOS, but is not limited to this; a high voltage provided by the reset control terminal S1N1 as a valid pulse signal can turn on the reset transistor M4; a low voltage provided by the reset control terminal S1N1 as an invalid pulse signal can turn off the reset transistor M4. Optionally, the compensation transistor M5 can be an NMOS, but is not limited to this; a high voltage provided by the compensation control terminal S2N1 as a valid pulse signal can turn on the compensation transistor M5; a low voltage provided by the compensation control terminal S2N1 as an invalid pulse signal can turn off the compensation transistor M5.

[0046] The pixel circuit 20 also includes a data writing module 26. The data writing module 26 is connected between the data signal terminal DATA and the first terminal N1 of the driving transistor M0. The control terminal of the data writing module 26 is connected to the write control terminal SP. The data writing module 26 is turned on during the data writing phase. Optionally, the data writing module 26 includes a data writing transistor M6, which may be a PMOS, but is not limited to this. The write control terminal SP provides a low voltage as a valid pulse signal to turn on the data writing transistor M6; the write control terminal SP provides a high voltage as an invalid pulse signal to turn off the data writing transistor M6.

[0047] The pixel circuit 20 also includes an initialization module 27; the initialization module 27 is connected between the initialization signal terminal VR2 and the anode of the light-emitting element 10, and the control terminal of the initialization module 27 is connected to the initialization control terminal SPIA. Optionally, the bias control terminal SPI can be multiplexed as the initialization control terminal SPIA. The optional initialization module 27 includes an initialization transistor M7, which is a PMOS, but not limited to it; the initialization control terminal SPIA provides a low voltage as a valid pulse signal to turn on the initialization transistor M7; the initialization control terminal SPIA provides a high voltage as an invalid pulse signal to turn off the initialization transistor M7.

[0048] Figure 3 This is a schematic diagram of the drift of the Id-Vg curve of the driving transistor, as shown below. Figure 3 As shown, a shift in the Id-Vg curve affects the driving current flowing into the light-emitting element, thus impacting display uniformity. In this embodiment, a bias module 23 is added to the pixel circuit 20. The bias module 23 addresses the hysteresis characteristics of the driving transistor M0. During the non-light-emitting phase, the bias module 23 is turned on, causing the pixel circuit 20 to enter the bias adjustment phase. In this phase, the bias signal provided by the bias signal terminal DVI can be written to the potentials of the first terminal N1 and the second terminal N2 of the driving transistor M0, applying a bias signal voltage to the driving transistor M0 to adjust the potential difference between its drain and gate. This improves the threshold voltage shift phenomenon of the driving transistor M0, reduces its hysteresis effect, and thus improves the brightness difference of each frame at low frequencies. If the driving transistor M0 is a PMOS, the bias signal provided by the bias signal terminal DVI can be selected as a high voltage. Specifically, during the bias adjustment stage, both the bias module 23 and the driving transistor M0 are turned on. The high voltage signal provided by the bias signal terminal DVI is written to the drain of the driving transistor M0 through the source of the driving transistor M0 to increase the drain potential of the driving transistor M0. This can reduce the potential difference between the gate potential and the drain potential of the driving transistor M0, thereby achieving voltage bias between the gate and drain of the driving transistor M0. This reduces the degree of ion polarization inside the driving transistor M0, thereby reducing the threshold voltage offset of the driving transistor M0 and improving display uniformity.

[0049] In this embodiment, the pixel circuit 20 includes multiple operating stages. If one frame refresh of the display panel only includes a data write frame, then one operating stage of the pixel circuit 20 is one frame refresh, and the first operating stage W1 and the second operating stage W2 in the pixel circuit 20 are different frame refreshes. If one frame refresh of the display panel includes multiple sub-frames, and the multiple sub-frames include one data write frame and at least one hold frame, then one operating stage of the pixel circuit 20 is one sub-frame, and the first operating stage W1 and the second operating stage W2 in the pixel circuit 20 can be two sub-frames from different frame refreshes, or the first operating stage W1 and the second operating stage W2 in the pixel circuit 20 can be different sub-frames from the same frame refresh.

[0050] The light-emitting element 10 emits light for different durations in the first working stage W1 and the second working stage W2. For example... Figure 2 As shown, the light-emitting element 10 emits light for a duration of T1 in the first operating stage W1, and for a duration of T2 in the second operating stage W2, where T1 is not equal to T2. As described above, during the light-emitting stage, the driving transistor M0 is turned on, but there is a phenomenon where the drain voltage is lower than the gate voltage. Over time, this will cause the threshold voltage of the driving transistor M0 to continuously increase. Clearly, as the light-emitting duration of the light-emitting element 10 changes during the operating stages, the degree of threshold voltage shift of the driving transistor M0 also changes. In this embodiment, T1 is not equal to T2, so the degree of threshold voltage shift of the driving transistor M0 in the first operating stage W1 is different from the degree of threshold voltage shift of the driving transistor M0 in the second operating stage W2.

[0051] It should be noted that the display panel uses EM dimming to change the non-light-emitting duration of the light-emitting element 10 in different operating stages, thereby changing the light-emitting duration of the light-emitting element 10 in different operating stages. The EM dimming methods of the display panel include EM forward dimming and EM backward dimming. EM forward dimming increases or decreases the time interval between the start of the non-light-emitting stage and the start of the bias adjustment stage, that is, moving the rising edge of the signal output by the dimming control terminal EM forward or backward. EM backward dimming increases or decreases the time interval between the end of the bias adjustment stage and the start of the light-emitting stage, that is, moving the falling edge of the signal output by the dimming control terminal EM forward or backward. The following will explain forward dimming and backward dimming separately. Figure 4 This is a schematic diagram of another pixel circuit operation stage provided in an embodiment of the present invention. Figure 5 This is a schematic diagram of the working stage of another pixel circuit provided in an embodiment of the present invention. Figure 6 This is a schematic diagram of the working stage of another pixel circuit provided in an embodiment of the present invention.

[0052] First, let's explain the situation of adjusting the brightness backwards, such as... Figure 2 and Figure 4 As shown, the phase where the SPI output at the bias control terminal is low is the bias adjustment phase. In the first operating phase W1, the time interval A between the start time of the non-light-emitting phase and the start time of the bias adjustment phase is A11, and the time interval B between the end time of the bias adjustment phase and the start time of the light-emitting phase is B11; in the second operating phase W2, the time interval A between the start time of the non-light-emitting phase and the start time of the bias adjustment phase is A11, and the time interval B between the end time of the bias adjustment phase and the start time of the light-emitting phase is B12. Figure 2 In the example shown, the first working stage W1 is the earlier stage, and the second working stage W2 is the later stage. The falling edge of the signal output by the dimming control terminal EM shifts forward, and B11 is greater than B12. Figure 4 In the example shown, the first working stage W1 is the later stage, and the second working stage W2 is the earlier stage. The falling edge of the signal output by the dimming control terminal EM is shifted backward, and B12 is less than B11.

[0053] Next, we will explain the situation of forward dimming, such as... Figure 5 and Figure 6 As shown, in the first working stage W1, the time interval A between the start time of the non-luminescent stage and the start time of the bias adjustment stage is A21, and the time interval B between the end time of the bias adjustment stage and the start time of the luminescent stage is B21; in the second working stage W2, the time interval A between the start time of the non-luminescent stage and the start time of the bias adjustment stage is A22, and the time interval B between the end time of the bias adjustment stage and the start time of the luminescent stage is B21. Figure 5 In the example shown, the first working stage W1 is the earlier stage, and the second working stage W2 is the later stage. The rising edge of the signal output by the dimming control terminal EM shifts backward, and A21 is greater than A22. Figure 6 In the example shown, the first working stage W1 is the later stage, and the second working stage W2 is the earlier stage. The rising edge of the signal output by the dimming control terminal EM moves forward, and A22 is less than A21.

[0054] During the bias adjustment phase in the non-light-emitting stage, the bias signal provided by the bias signal terminal DVI adjusts the potential of the first terminal N1 and the second terminal N2 of the driving transistor M0, thereby adjusting the potential difference between its drain and gate and improving the threshold voltage offset phenomenon of the driving transistor M0. As mentioned above, the light-emitting duration of the light-emitting element 10 is different in the first working stage W1 and the second working stage W2, which may lead to different degrees of threshold voltage offset of the driving transistor in the two working stages. Therefore, in this embodiment, by setting the bias signal voltage provided by the bias signal terminal DVI to different voltages in the first working stage W1 and the second working stage W2, the bias state of the driving transistor M0 can be adjusted based on different voltages in the first working stage W1 and the second working stage W2, reducing the difference in the degree of threshold voltage offset of the driving transistor in the two working stages, making the adjustment effect of the bias module on the bias state of the driving transistor M0 more consistent, thereby making the bias state of the driving transistor M0 more consistent, which is beneficial to improving display uniformity.

[0055] Furthermore, it should be noted that EM backward dimming involves changing the bias adjustment duration (B) between the end of the bias adjustment phase and the start of the emission phase during the operating phase. This change in the bias adjustment duration (B) significantly affects the bias state of the driving transistor. For example, in... Figure 2 In the example shown, after the bias adjustment phase of the first working stage W1 ends, the duration B11 of the bias adjustment effect is longer than the duration B12 after the bias adjustment phase of the second working stage W2 ends. This indicates a stronger bias adjustment effect in the first working stage W1, resulting in a difference in the bias adjustment effects between the two working stages. Therefore, by setting different bias signal voltages provided by the bias signal terminal DVI in the first and second working stages W1 and W2, the problem of the difference in bias adjustment effects between the two working stages caused by backward dimming can be resolved. This allows the bias state of the driving transistor M0 to become more consistent, which is beneficial for improving display uniformity.

[0056] In this setup, the bias signal voltage provided by the DVI terminal in the first operating phase (W1) is dva, and the bias signal voltage provided by the DVI terminal in the second operating phase (W2) is dvb. dva is not equal to dvb. It should be noted that in the laboratory, the display panel needs to achieve the same target brightness in different operating phases. Therefore, the required bias signal voltage of the DVI terminal in different operating phases is measured, and the relevant data is stored in the display panel's memory. Subsequent bias adjustments directly retrieve the relevant bias signal voltage from memory for control. Therefore, the values ​​of dva and dvb are not specifically limited. By adjusting the bias signal voltage in different operating phases, the uniformity of the image display in different operating phases is improved.

[0057] In this invention, the pixel circuit includes a dimming module, a driving module, and a bias module. The driving module provides driving current to the light-emitting element, and the bias module is connected between the bias signal terminal and the first terminal of the driving transistor. The bias module adjusts the bias of the driving transistor, and the bias signal terminal provides a bias signal. Since the light-emitting duration of the light-emitting element is different in the first and second working stages, the threshold voltage offset of the driving transistor is different in the first and second working stages. In the non-light-emitting stage, by setting the bias signal voltage provided by the bias signal terminal to be different in the first and second working stages, the bias adjustment can be performed separately for the threshold voltage offset phenomenon of the driving transistor in the first and second working stages, reducing the difference in the threshold voltage offset of the driving transistor in the first and second working stages, and making the bias state of the driving transistor in each working stage with different light-emitting durations tend to be consistent, thereby improving display uniformity.

[0058] Figure 7 This is a schematic diagram illustrating the working stages of another pixel circuit provided in an embodiment of the present invention. For example... Figure 7 As shown, the optional display panel includes S frames of refreshed images. Each refreshed image includes sub-images from the 1st to the Mth frames. In each refreshed image, the 1st sub-image is a data writing frame, and the 2nd to the Mth sub-images are all hold frames. S>1, M>1; the first working stage W1 is the xth sub-image of the i-th refreshed image, and the second working stage W2 is the xth sub-image of the j-th refreshed image. i≠j, M≥x≥1.

[0059] In this embodiment, a refreshed frame includes at least two sub-frames, numbered sequentially from frame 1 to frame M. The first sub-frame in a refreshed frame is a data writing frame, which includes a data writing phase where the pixel circuit writes new display data. The second through M sub-frames in a refreshed frame are hold frames; in hold frames, the pixel circuit does not write new display data and retains the display data from the previous sub-frame. Figure 7 The diagram shows the i-th frame refresh, its data writing frame (i.e., the first sub-frame), and the last holding frame (i.e., the M-th sub-frame). Multiple sub-frames between the first and M-th sub-frames are represented by ellipses. Similarly, the j-th frame refresh, its data writing frame (i.e., the first sub-frame), and the last holding frame (i.e., the M-th sub-frame) are also shown, with multiple sub-frames between them. A bias adjustment stage is set during the non-light-emitting phase of the first sub-frame. During this stage, both the bias module 23 and the drive module 22 are enabled. The bias signal from the bias signal terminal DVI is written from the source (N1) of the drive transistor M0 to the drain (N2) of the drive transistor M0, which can bias the voltage between the gate and drain of the drive transistor M0, improving the bias phenomenon of the pixel circuit 20.

[0060] The x=1 option is available. The first working stage W1 is the first sub-frame of the i-th refreshed image, i.e., the data writing frame. The second working stage W2 is the first sub-frame of the j-th refreshed image, i.e., the data writing frame. The light-emitting duration of the light-emitting element in the data writing frame of the i-th refreshed image is T1, and the light-emitting duration of the light-emitting element in the data writing frame of the j-th refreshed image is T2, where T1 is different from T2. During the non-light-emitting stage of the data writing frame of the i-th refreshed image, the bias signal terminal DVI provides a bias signal voltage dva; during the non-light-emitting stage of the data writing frame of the j-th refreshed image, the bias signal terminal DVI provides a bias signal voltage dvb, where dva is different from dvb. By properly adjusting dva and dvb, the difference in the threshold voltage offset of the driving transistors in the first working stage W1 and the second working stage W2 can be reduced, making the bias state of the driving transistors in each working stage with different light-emitting durations more consistent, thereby improving display uniformity. By adjusting the bias signal voltage of the same sub-frame in different refreshed images, the display uniformity of different refreshed images can be improved.

[0061] In other embodiments, the first working stage and the second working stage may also be selected as hold frames that refresh the screen at different times; specifically, Figure 8 This is a schematic diagram illustrating the working stages of another pixel circuit provided in an embodiment of the present invention. For example... Figure 8 As shown, x can be any number other than 1. The first working stage W1 is the Mth sub-frame of the refreshed image in the i-th frame, which is the last frame held. The second working stage W2 is the Mth sub-frame of the refreshed image in the j-th frame, which is the last frame held. However, it is not limited to this. The first working stage and the second working stage can also be the second sub-frame of the refreshed image in different frames or other frames. There are no specific restrictions.

[0062] Please see Figure 2 , Figure 4 , Figure 5 and Figure 6 The light-emitting duration T1 of the optional light-emitting element in the first working stage W1 is less than the light-emitting duration T2 of the light-emitting element in the second working stage W2, and the bias signal voltage dva corresponding to the first working stage W1 is less than the bias signal voltage dvb corresponding to the second working stage W2.

[0063] In this embodiment, the light-emitting duration T1 of the light-emitting element in the first working stage W1 is less than the light-emitting duration T2 of the light-emitting element in the second working stage W2. Therefore, the threshold voltage offset of the driving transistor in the first working stage W1 is lower than the threshold voltage offset of the driving transistor in the second working stage W2. Based on this, the bias signal terminal DVI can use a smaller bias signal voltage dva in the first working stage W1 to adjust the bias state of the driving transistor and reduce the threshold voltage offset of the driving transistor; the bias signal terminal DVI can use a larger bias signal voltage dvb in the second working stage W2 to adjust the bias state of the driving transistor and reduce the threshold voltage offset of the driving transistor. In this embodiment, setting the bias signal voltage dva corresponding to the first working stage W1 to be less than the bias signal voltage dvb corresponding to the second working stage W2 can make the bias state of the driving transistor in the first working stage W1 and the second working stage W2 more consistent, improving display uniformity.

[0064] refer to Figure 2 As shown, for the two operating stages W1 and W2, T1 is less than T2, and B11 is greater than B12. To verify the above, the inventors conducted tests using B12 as 10H and B11 as 70H (where H is the horizontal frequency) as an example. The experimental results show that when the bias adjustment effects of the first operating stage W1 and the second operating stage W2 tend to be consistent, the optimal bias signal voltage dva of the first operating stage W1 is less than the optimal bias signal voltage dvb of the second operating stage W2.

[0065] For example, the display panel is designed with a refresh rate of 10Hz and a brightness of 3 nits. The test results are as follows.

[0066] For the case where B12 is 10H, the test results for the bias signal voltage OBS and the flicker value FLK are as follows:

[0067] 1) OBS = 2V, FLK = -31.3V;

[0068] 2) OBS = 3V, FLK = -35.81V;

[0069] 3) OBS = 3.5V, FLK = -44.5V;

[0070] 4)OBS=3.6V, FLK=-48.89;

[0071] 5) OBS = 4V, FLK = -48.76;

[0072] 6) OBS = 5V, FLK = -36.31V;

[0073] As mentioned above, when the display panel is working in the second working stage W2, the flicker is weakest when FLK = -48.89. Therefore, the OBS corresponding to FLK = -48.89, which is 3.6V, is the optimal bias signal voltage for the second working stage W2.

[0074] For the case where B11 is 70H, the test results for the bias signal voltage OBS and the flicker value FLK are as follows:

[0075] 1) OBS = 1V, FLK = -33.16;

[0076] 2) OBS = 2V, FLK = -34.28;

[0077] 3) OBS = 3V, FLK = -44.48;

[0078] 4) OBS = 4V, FLK = -31.02V;

[0079] 5) OBS = 5V, FLK = -27.99;

[0080] As mentioned above, when the display panel is working in the first working stage W1, the flicker is weakest when FLK = -44.48. Therefore, the OBS corresponding to FLK = -44.48, which is 3V, is the optimal bias signal voltage for the first working stage W1.

[0081] This verifies that when the bias adjustment duration B of the two working stages is different, reducing the bias signal voltage of the working stage with the longer bias adjustment duration can reduce the difference in bias adjustment effect between the two working stages and improve the display effect. It should be noted that the inventors also conducted corresponding experiments on forward dimming and obtained the same results, which will not be detailed here.

[0082] Figure 9 This is a schematic diagram illustrating the working stages of another pixel circuit provided in an embodiment of the present invention. For example... Figure 9As shown, the optional display panel includes S frames of refresh frames. Each refresh frame includes sub-frames from the 1st to the Mth frame. The 1st sub-frame in a refresh frame is a data writing frame, and the 2nd to the Mth sub-frames are all hold frames. S>1, M>1. The first working stage W1 is the data writing frame of the i-th refresh frame, and the second working stage W2 is the data writing frame of the j-th refresh frame. i≠j. The multiple working stages also include a third working stage W3 and a fourth working stage W4. The third working stage W3 is the p-th sub-frame of the i-th refresh frame, and the fourth working stage W4 is the p-th sub-frame of the j-th refresh frame. 2≤p≤M. The light-emitting duration T3 of the light-emitting element in the third working stage W3 is different from the light-emitting duration T4 of the light-emitting element in the fourth working stage W4, and the bias signal voltage dvc corresponding to the third working stage W3 is different from the bias signal voltage dvd corresponding to the fourth working stage W4. Figure 9 In this embodiment, p = M can be selected. In other embodiments, the p-th frame sub-frame can also be any one of the frames from the 2nd to the (M-1)th frame that is held. It is not limited to this. By adjusting the bias signal voltage of the same frame sub-frame in different frame refreshes, the display uniformity of different frame refreshes is improved.

[0083] In this embodiment, the data writing frame of the i-th refresh frame is the first working stage W1, and the light-emitting element emits light for a duration of T1 during the first working stage W1. The M-th hold frame of the i-th refresh frame is the third working stage W3, and the light-emitting element emits light for a duration of T3 during the third working stage W3. The data writing frame of the j-th refresh frame is the second working stage W2, and the light-emitting element emits light for a duration of T2 during the second working stage W2. The M-th hold frame of the j-th refresh frame is the fourth working stage W4, and the light-emitting element emits light for a duration of T4 during the fourth working stage W4. However, this embodiment is not limited to this.

[0084] In this embodiment, the light emission duration T1 of the light-emitting element in the first working stage W1 is different from the light emission duration T2 of the light-emitting element in the second working stage W2, and the light emission duration T3 of the light-emitting element in the third working stage W3 is different from the light emission duration T4 of the light-emitting element in the fourth working stage W4. That is, when the light emission duration of the light-emitting element in the data writing frame changes, the light emission duration of the holding frame will change accordingly, so as to maintain the display uniformity of the data writing frame and the holding frame after dimming. Based on this, when the bias signal voltage of the data writing frame changes, that is, when the bias signal voltage dva of the bias signal terminal DVI in the first working stage W1 becomes the bias signal voltage dvb in the second working stage W2, the bias signal voltage corresponding to the hold frame also needs to be adjusted. That is, the bias signal voltage dvc of the bias signal terminal DVI in the third working stage W3 is set to be different from the bias signal voltage dvd in the fourth working stage W4. In this way, the bias state of the driving transistor in the data writing frame tends to be consistent in different refresh frames, and the bias state of the hold frame also tends to be consistent, thereby improving the uniformity of display.

[0085] The optional light-emitting element has an emission duration T1 in the first operating stage W1 that is shorter than the emission duration T2 in the second operating stage W2, and the bias signal voltage dva corresponding to the first operating stage W1 is shorter than the bias signal voltage dvb corresponding to the second operating stage W2. Furthermore, the emission duration T3 in the third operating stage W3 is shorter than the emission duration T4 in the fourth operating stage W4, and the bias signal voltage dvc corresponding to the third operating stage W3 is shorter than the bias signal voltage dvd corresponding to the fourth operating stage W4. In this embodiment, the bias signal voltage dva corresponding to the first operating stage W1 and the bias signal voltage dvc corresponding to the third operating stage W3 can be the same or different; the bias signal voltage dvb corresponding to the second operating stage W2 and the bias signal voltage dvd corresponding to the fourth operating stage W4 can be the same or different, and no limitation is made here.

[0086] In this embodiment, the first working stage W1 is the data writing frame of the i-th frame refresh, and the second working stage W2 is the data writing frame of the j-th frame refresh. The light emission duration T1 of the light-emitting element in the first working stage W1 is less than the light emission duration T2 of the light-emitting element in the second working stage W2, and the bias signal voltage dva corresponding to the first working stage W1 is less than the bias signal voltage dvb corresponding to the second working stage W2, so that the bias adjustment effect of the first working stage W1 and the second working stage W2 is close or tends to be consistent.

[0087] Figure 10 This is a schematic diagram illustrating the working stages of another pixel circuit provided in an embodiment of the present invention. For example... Figure 10As shown, the optional display panel includes S refresh frames, each refresh frame comprising sub-frames 1 to M. Within a refresh frame, the first sub-frame is a data write frame, and the second to M sub-frames are hold frames, where S>1 and M>1. The first working stage is the x-th sub-frame of the i-th refresh frame, and the second working stage is the y-th sub-frame of the i-th refresh frame, where M≥x≥1, M≥y≥1, and x≠y. By adjusting the bias signal voltages of different sub-frames within the same refresh frame, the display uniformity of different frames is improved.

[0088] In this embodiment, the first working stage W1 and the second working stage W2 can be two hold frames of the i-th refreshed frame. Optionally, the first working stage W1 can be the second sub-frame of the i-th refreshed frame and the second working stage W2 can be the M-th sub-frame of the i-th refreshed frame; however, it is not limited to this. In other embodiments, the first working stage can also be a data writing frame of the i-th refreshed frame, and the second working stage can be a hold frame of the i-th refreshed frame.

[0089] x can be less than y. In a 1-frame refresh, the data write frame writes display data, while the hold frame does not. This causes leakage current in the gate of the driving transistor, which increases over time. Therefore, at low frequencies, the brightness of sub-frames within a single refresh frame decreases. Based on this, in a 1-frame refresh, the illumination duration T2 of the y-th frame sub-frame can be designed to be greater than the illumination duration T1 of the x-th frame sub-frame. By extending the illumination duration of the y-th frame sub-frame, its brightness can be compensated, thus reducing the brightness difference between the y-th and x-th frames. Similarly, in a 1-frame refresh, brightness can be compensated by extending the illumination duration of the hold frame, addressing the issue of the hold frame brightness being lower than the data write frame brightness.

[0090] Furthermore, in a single-frame refresh, the bias signal voltage dvb of the bias signal terminal DVI in the second working stage W2 can be designed to be greater than the bias signal voltage dva in the first working stage W1. This allows the bias adjustment effect in each working stage of a single-frame refresh to be close to or consistent. Specifically, in a single-frame refresh, if the bias signal voltage of the data write frame is adjusted without adjusting the bias signal voltage of the hold frame, the bias adjustment effect of the data write frame and the hold frame in a single-frame refresh will differ significantly. However, if the bias signal voltage of the data write frame is adjusted, the bias signal voltage of the hold frame will change accordingly, making the bias adjustment effect of the data write frame and the hold frame in a single-frame refresh more consistent. Similarly, in a single-frame refresh, if the bias signal voltage of the earlier hold frame is adjusted, the bias signal voltage of the later hold frames will change accordingly, making the bias adjustment effect of multiple hold frames in a single-frame refresh more consistent.

[0091] As described above, in a 1-frame refresh, designing the illumination duration of the first x-frame sub-frame to be shorter than that of the last y-frame sub-frame can solve the brightness difference problem between different frames caused by leakage current in the driving transistor. Simultaneously, designing the bias signal voltage of the x-frame sub-frame to be lower than that of the y-frame sub-frame can solve the problem of inconsistent bias adjustment effects between different frames, thus improving the display uniformity of the 1-frame refresh. If the illumination duration of the first x-frame sub-frame is equal to that of the last y-frame sub-frame, then by making the bias signal voltage of the x-frame sub-frame lower than that of the y-frame sub-frame, the brightness of the later sub-frame can be compensated, further improving the display uniformity of the 1-frame refresh.

[0092] Figure 11 This is a schematic diagram illustrating the working stages of another pixel circuit provided in an embodiment of the present invention. For example... Figure 11 As shown, the optional multiple working stages also include a fifth working stage W5 and a sixth working stage W6. The fifth working stage W5 is the x-th sub-frame of the j-th frame refreshed image, and the sixth working stage W6 is the y-th sub-frame of the j-th frame refreshed image. The light-emitting duration T5 of the light-emitting element in the fifth working stage W5 is different from the light-emitting duration T1 of the light-emitting element in the first working stage W1, and the light-emitting duration T2 of the light-emitting element in the sixth working stage W6 is different from the light-emitting duration T2 of the light-emitting element in the second working stage T2. Furthermore, ΔTi 15 ≠ΔTi 26 ΔV 15 ≠ΔV 26 ; where ΔTi 15 ΔTi is the difference in the light-emitting duration between the first working stage W1 and the fifth working stage W5 of the light-emitting element. 26 ΔV is the difference in the light-emitting duration of the light-emitting element during the second working stage W2 and the sixth working stage W6. 15 ΔV is the difference between the bias signal voltage dva corresponding to the first operating stage W1 and the bias signal voltage dve corresponding to the fifth operating stage W5. 26 This is the difference between the bias signal voltage dvb corresponding to the second operating stage W2 and the bias signal voltage dvf corresponding to the sixth operating stage W6.

[0093] In this embodiment, x = 2 and y = M can be selected. Then, the second sub-frame of the j-th refreshed frame is the fifth working stage W5, and the M-th sub-frame of the j-th refreshed frame is the sixth working stage W6.

[0094] The light-emitting duration T5 of the light-emitting element in the fifth operating stage W5 is different from the light-emitting duration T1 of the light-emitting element in the first operating stage W1. Therefore, the bias signal voltage dve corresponding to the fifth operating stage W5 is different from the bias signal voltage dva corresponding to the first operating stage W1. Optionally, T1 can be less than T5, thus designing dva to be less than dve, which can improve the bias adjustment effect in both the first operating stage W1 and the fifth operating stage W5.

[0095] The light-emitting duration of the light-emitting element in the sixth operating stage W6 is different from the light-emitting duration T2 in the second operating stage. Therefore, the bias signal voltage dvf corresponding to the sixth operating stage W6 is different from the bias signal voltage dvb corresponding to the second operating stage W2. If T2 is chosen to be less than T6, then dvb can be designed to be less than dvf, which can improve the bias adjustment effect in both the second operating stage W2 and the sixth operating stage W6.

[0096] In a single frame refresh, the illumination duration of the x-th sub-frame is shorter than that of the y-th sub-frame. Therefore, the bias signal voltage corresponding to the x-th sub-frame is designed to be different from that corresponding to the y-th sub-frame. Optionally, T1 < T2, then dva < dvb; T5 < T6, then dve < dvf.

[0097] ΔTi 15 Let ΔTi be the time difference between T1 and T5. 26 Let ΔV be the time difference between T2 and T6. 15 Let ΔV be the pressure difference between dva and dve. 26 The voltage difference between DVB and DVF. The increment ΔTi between the illumination duration of the x-th sub-frame in the i-th refreshed frame and the illumination duration of the x-th sub-frame in the j-th refreshed frame. 15 Unlike the increase ΔTi of the illumination duration of the y-th sub-frame in the i-th refreshed frame and the illumination duration of the y-th sub-frame in the j-th refreshed frame, this time the illumination duration of the y-th sub-frame is different. 26 Then, the increment ΔV of the bias signal voltage of the x-th sub-frame in the i-th refreshed frame and the bias signal voltage of the x-th sub-frame in the j-th refreshed frame is... 15 Unlike the difference between the bias signal voltage of the y-th sub-frame in the i-th refreshed frame and the increment ΔV of the bias signal voltage of the y-th sub-frame in the j-th refreshed frame. 26 By adjusting the bias signal voltage of the same sub-frame of different frame refreshes, the display uniformity of different frame refreshes can be improved.

[0098] Specifically, at low frequencies, a single refresh frame contains multiple sub-frames, including one data write frame and multiple hold frames. Due to leakage current in the gate of the driving transistor, the brightness of the sub-frames within a single refresh frame gradually decreases. The illumination duration of later sub-frames in a single refresh frame can be set to be longer than that of earlier sub-frames to compensate for the brightness differences among the sub-frames within a single refresh frame and improve display uniformity.

[0099] For a single refresh frame, the increment of the illumination duration for the hold frame adjustment should differ from that for the data write frame adjustment to ensure consistent brightness. For example, in the first refresh frame of a low-frequency LTPS display panel, the illumination duration of the data write frame is 8 hours, the first hold frame is 12 hours, and the second hold frame is 16 hours. The second refresh frame is the dimmed frame. Assuming the illumination duration of the data write frame in the second refresh frame becomes 12 hours, the increment of the illumination duration of its first hold frame should exceed 4 hours of the data write frame's illumination duration to maintain consistent brightness as much as possible. For example, the illumination duration of the first hold frame in the second refresh frame becomes 18 hours. Furthermore, for the second hold frame in the second refresh frame, its illumination duration can increase by more than 6 hours compared to the first hold frame, for example, the illumination duration of the second hold frame becomes 24 hours, etc., without specific limitations.

[0100] Since the illumination duration of different sub-frames in a single frame refresh is different, the bias signal voltage of different sub-frames also needs to be adjusted to be inconsistent in order to ensure that each sub-frame has the best bias adjustment effect.

[0101] It should be noted that in two different refresh frames, the light emission duration increment of the corresponding hold frame is different from the light emission duration increment of the data write frame. Therefore, the amount / rate of the bias signal voltage change of the corresponding hold frame should also be different from the amount / rate of the bias signal voltage change of the data write frame. This can ensure that the display panel has the best bias adjustment effect.

[0102] For example, in the first refresh frame of a low-frequency LTPS display panel, the light emission duration of the data writing frame is 8 hours, the light emission duration of the first hold frame is 12 hours, and the light emission duration of the second hold frame is 16 hours. The second refresh frame is the frame after dimming; in the second refresh frame, the light emission duration of the data writing frame is 12 hours, the light emission duration of the first hold frame is 18 hours, and the light emission duration of the second hold frame is 24 hours. The bias signal voltage difference between the x-th sub-frame in the first and second refresh frames is different from the bias signal voltage difference between the y-th sub-frame in the first and second refresh frames, which ensures the best bias adjustment effect; x is less than y.

[0103] As mentioned above, in a 1-frame refresh frame, the illumination duration of the data write frame is different from that of the hold frame. To ensure that the brightness of the data write frame and the hold frame is the same after dimming, the increment of the illumination duration of the hold frame can be greater than that of the data write frame. Based on this, adjusting the amount of bias signal voltage change in the data write frame to be different from that in the hold frame within a 1-frame refresh frame can ensure optimal bias adjustment.

[0104] The optional display panel includes different light-emitting duration intervals from the 1st to the Nth and different bias signal voltages from the 1st to the Nth. The kth light-emitting duration interval corresponds to the kth bias signal voltage, where N ≥ k ≥ 1 and N > 1. The light-emitting duration of the light-emitting element in one working stage is within the kth light-emitting duration interval, and the bias signal provided by the bias signal terminal in this working stage is the kth bias signal voltage. The light-emitting duration value of the optional kth light-emitting duration interval is less than the light-emitting duration value of the (k+1)th light-emitting duration interval, and the kth bias signal voltage is less than or equal to the (k+1)th bias signal voltage.

[0105] In this embodiment, during the laboratory stage before shipment, the target brightness of the display panel is preset, and the light-emitting duration of the pixel circuit's operating phase is set to Z1. A bias signal voltage is then applied to the pixel circuit to make it display at the preset target brightness. This bias signal voltage value, DVA, is determined as the bias signal voltage corresponding to the light-emitting duration Z1. The light-emitting duration of the pixel circuit's operating phase is then adjusted to Z2, and a bias signal voltage is applied to the pixel circuit to make it display at the preset target brightness. This bias signal voltage value, DVB, is determined as the bias signal voltage corresponding to the light-emitting duration Z2. This process is repeated to obtain multiple different bias signal voltages, each corresponding to a light-emitting duration interval.

[0106] The emission duration of the first emission duration interval is less than the emission duration of the second emission duration interval, and the corresponding first bias signal voltage of the first emission duration interval is less than or equal to the corresponding second bias signal voltage of the second emission duration interval. Similarly, the emission duration of the kth emission duration interval is less than the emission duration of the (k+1)th emission duration interval, and the kth bias signal voltage is less than or equal to the (k+1)th bias signal voltage.

[0107] Figure 12 yes Figure 1 The timing diagram of the pixel circuit shown is as follows. Figure 13 yes Figure 1 Another timing diagram of the pixel circuit shown. Figure 14 yes Figure 1The diagram shows another timing sequence of the pixel circuit. The optional pixel circuit 20's operating stages include a pre-amplification stage Ta and a light-emitting stage Tb executed sequentially. The dimming module 21 is turned off in the pre-amplification stage Ta and turned on in the light-emitting stage Tb. The pre-amplification stage Ta includes a biasing stage, during which the biasing module 23 is turned on. The biasing stage includes a first biasing sub-stage Tc and / or a second biasing sub-stage Td. It should be noted that the first operating stage of the pixel circuit 20 includes the pre-amplification stage and the light-emitting stage executed sequentially, and the duration of the light-emitting stage is the light-emitting duration of the light-emitting element in the first operating stage. The second operating stage of the pixel circuit 20 includes the pre-amplification stage and the light-emitting stage executed sequentially, and the duration of the light-emitting stage is the light-emitting duration of the light-emitting element in the second operating stage.

[0108] The optional pre-stage Ta also includes the data writing stage Tg; such as Figure 12 As shown, the biasing stage only includes the first biasing sub-stage Tc, and the data writing stage Tg is located between the first biasing sub-stage Tc and the light emission stage Tb; or, as... Figure 13 As shown, the biasing stage only includes the second biasing sub-stage Td, which is located between the data writing stage Tg and the light emission stage Tb; or, as... Figure 14 As shown, the biasing stage includes a first biasing sub-stage Tc and a second biasing sub-stage Td, and the data writing stage Tg is located between the first biasing sub-stage Tc and the second biasing sub-stage Td.

[0109] In this embodiment, the optional bias module 23 includes a bias transistor M3, which may be a PMOS, but is not limited to this. The gate of the bias transistor M3 is connected to the bias control terminal SPI, and the bias transistor M3 is connected between the bias signal terminal DVI and the first terminal N1 of the driving transistor M0. If the bias transistor M3 is a PMOS, the bias control terminal SPI provides a low voltage as a valid pulse signal to turn on the bias transistor M3; the bias control terminal SPI provides a high voltage as an invalid pulse signal to turn off the bias transistor M3. Optionally, both the first dimming transistor M1 and the second dimming transistor M2 may be PMOS.

[0110] The working stages of a pixel circuit include the following:

[0111] During the pre-emitting stage Ta, EM provides a high voltage to disconnect M1 and M2; during the light-emitting stage Tb, EM provides a low voltage to turn on both M1 and M2.

[0112] In the first bias sub-stage Tc, SPI provides a low voltage to turn on M3, while the driving transistor M0 remains on. Then, the high voltage provided by DVI is written to the source and drain of the driving transistor M0.

[0113] During the reset phase (Te+Tf), the reset control terminal S1N1 provides a high voltage to turn on the reset transistor M4, and the low voltage provided by VREF is written to the control terminal of the drive transistor M0 to control the drive transistor M0 to turn on.

[0114] During the compensation phase (Tf+Tg+Th), the compensation control terminal S2N1 provides a high voltage to turn on the compensation transistor M5. Specifically, in the Tf phase, the reset transistor M4 remains on, and the low voltage provided by VREF is written to the gate, drain, and source of the driving transistor M0, keeping M0 on. In the Tg phase, the reset transistor M4 is turned off, the driving transistor M0 remains on, and the data writing transistor M6 is turned on, writing the data signal provided by DATA to the source, drain, and gate of the driving transistor M0. In the Th phase, the driving transistor M0 remains on, and the source, drain, and gate of the driving transistor M0 stabilize to form a data signal. The Tg phase is the data writing phase.

[0115] In the second bias sub-stage Td, SPI provides a low voltage to turn on M3, while the driving transistor M0 remains on. Then, the high voltage provided by DVI is written to the source and drain of the driving transistor M0 again.

[0116] In other embodiments, the pixel circuit may also have other structures, for example, Figure 15 This is a schematic diagram of another pixel circuit provided in an embodiment of the present invention. Figure 16 yes Figure 15 The timing diagram of the pixel circuit is shown. (Reference) Figure 15 and Figure 16 As shown, the optional bias module 23 is multiplexed as a data writing module, and the data signal terminal DATA is multiplexed as the bias signal terminal DVI. The bias module 23 is also enabled during the data writing phase (Tg). During the data writing phase, the data signal terminal DATA provides the data signal; during the bias phase, the data signal terminal DATA provides the bias signal voltage.

[0117] like Figure 16 As shown, the optional bias stage includes a first bias sub-stage Tc and a second bias sub-stage Td, and the data writing stage Tg is located between the first bias sub-stage Tc and the second bias sub-stage Td. In other embodiments, the optional bias stage may include only the first bias sub-stage or only the second bias sub-stage.

[0118] like Figure 16As shown, in the first bias sub-stage Tc, SPI provides a low voltage to turn on M3, and the driving transistor M0 remains on. DATA then provides a high voltage and writes to the source and drain of the driving transistor M0. In the data writing stage Tg, the reset transistor M4 is turned off, the driving transistor M0 remains on, SPI provides a low voltage to turn on M3, and DATA provides a data signal and writes to the source, drain, and gate of the driving transistor M0. In the second bias sub-stage Td, SPI provides a low voltage to turn on M3, and the driving transistor M0 remains on. DATA then provides a high voltage and again writes to the source and drain of the driving transistor M0.

[0119] The optional display panel includes an S-frame refresh screen. Each refresh screen includes sub-frames 1 to M. In a refresh screen, the first sub-frame is a data write frame and the second to M sub-frames are all hold frames, where S>1 and M>1. Within a refresh screen, a fixed voltage is provided at the bias signal terminal during the pre-processing stage of the data write frame and at the pre-processing stage of the hold frame.

[0120] In this embodiment, the pixel circuit 20 includes a data writing module 26 and a bias module 23. Within one frame refresh, the data writing frame normally writes display data, while the hold frame does not write display data. Therefore, the data signal terminal DATA provides a data signal during the data writing phase Tg of the data writing frame. The bias signal terminal DVI provides a fixed voltage signal during the working phase. For example, the bias signal terminal DVI provides a fixed voltage signal dva in the first working phase and a fixed voltage signal dvb in the second working phase, where dva is different from dvb.

[0121] The optional display panel includes an S-frame refresh screen, and each refresh screen includes sub-frames 1 to M. In a refresh screen, the first sub-frame is a data write frame and the second to M sub-frames are all hold frames, where S>1 and M>1. Within a refresh screen, in the pre-stage of the data write frame, the bias signal terminal DVI provides a data signal, and in the pre-stage of the hold frame, the bias signal terminal DVI provides a fixed voltage.

[0122] In this embodiment, the pixel circuit 20 includes a bias module 23, which is multiplexed as a data writing module 26. In other words, in this embodiment, the data writing module 26 and the bias module 23 are the same module; the data writing signal terminal and the bias signal terminal are the same signal terminal; and the signal line used to transmit the data signal and the data line used to transmit the bias signal are the same signal line. Within one frame of refresh, the data writing frame normally writes display data, while the hold frame does not write display data. Based on this, the bias signal terminal DVI provides a data signal during the data writing phase Tg of the data writing frame. The bias signal terminal DVI provides a fixed voltage signal during the bias phase.

[0123] Figure 17 This is a timing diagram of another pixel circuit provided in an embodiment of the present invention. For example... Figure 17 As shown, b1 can be the time interval between the data writing stage Tg and the second bias sub-stage Td executed sequentially in the working phase, and b2 can be the time interval between the second bias sub-stage Td and the light emission stage Tb executed sequentially in the working phase; 11 =b 12 b 21 ≠b 22 b 11 For the first working stage W1, b1, b 12 For the second working phase W2, b1, b 21 For the first working stage W1, b2, b 22 b2 is the second working stage W2; the bias signal voltage corresponding to the first working stage W1 is not equal to the bias signal voltage corresponding to the second working stage W2. The first working stage W1 and the second working stage W2 can be selected as data write frames for different refresh frames, but are not limited to this; in other embodiments, the first working stage and the second working stage can also be selected as the x-th frame hold frame for different refresh frames, or the first working stage and the second working stage can also be selected as hold frames within the same refresh frame, or the first working stage and the second working stage can also be selected as a data write frame and a hold frame within the same refresh frame.

[0124] In this embodiment, b 11 b is the time interval between the data writing phase Tg1 and the second bias sub-phase Td1 executed sequentially in the first working phase W1. 12 b is the time interval between the data writing phase Tg2 and the second bias sub-phase Td2, which are executed sequentially in the second working phase W2. 11 It can be equal to b 12 b 21 b is the time interval between the second bias sub-stage Td1 and the luminescence stage Tb1, which are executed sequentially in the first working stage W1. 22 This refers to the time interval between the second bias sub-stage Td2 and the luminescence stage Tb2, which are executed sequentially in the second working stage W2. In b 11 equals b 12 In this case, the time interval b2 between the second bias sub-stage and the light emission stage can be adjusted so that the duration of the light emission stage Tb1 in the first working stage W1 is not equal to the duration of the light emission stage Tb2 in the second working stage W2. Accordingly, the bias signal voltage corresponding to the first working stage W1 is not equal to the bias signal voltage corresponding to the second working stage W2.

[0125] If Tb1 is less than Tb2, then in b 11 equals b 12 In the case of design b21 Greater than b 22 This allows Tb1 to be less than Tb2, and the bias signal voltage corresponding to the first working stage W1 is less than the bias signal voltage corresponding to the second working stage W2.

[0126] Figure 18 This is a timing diagram of another pixel circuit provided in an embodiment of the present invention. For example... Figure 18 As shown, the optional multiple working stages also include a seventh working stage W7, in which the light-emitting duration Tb7 of the light-emitting element is different from that of the first working stage W1 and the second working stage W2; b 12 ≠b 17 b 22 =b 27 b 17 For the seventh working phase W7, b1, b 27 b2 is the seventh working stage W7; the bias signal voltage corresponding to the seventh working stage W7 is equal to the bias signal voltage corresponding to the second working stage W2. W1, W2, and W7 can be selected as data write frames for different refresh frames, but are not limited to this; in other embodiments, W1, W2, and W7 can also be selected as the x-th frame hold frame for different refresh frames, or W1, W2, and W7 can also be selected as hold frames within the same refresh frame, or W1, W2, and W7 can also be selected as a data write frame and two hold frames within the same refresh frame. The preceding stage of the seventh working stage W7 is Ta7.

[0127] In this embodiment, b 17 b is the time interval between the data writing phase Tg7 and the second bias sub-phase Td7, which are executed sequentially in the seventh working phase W7. 17 Not equal to b 12 b 11 =b 12 b 27 b is the time interval between the second bias sub-stage Td7 and the luminescence stage Tb7, which are executed sequentially in the seventh working stage W7. 21 Not equal to b 22 b 22 =b 27 In b 22 equals b 27 In this case, the same bias signal voltage can be provided to the seventh operating stage W7 and the second operating stage W2, which can reduce power consumption.

[0128] As mentioned above, taking the first working stage W1 as the normal working stage, the second working stage W2 and the seventh working stage W7 are two working stages after dimming based on the first working stage W1. Therefore, the first working stage W1 can be used as a comparison object. The light-emitting duration of the light-emitting element is different in W1, W2 and W7. Specifically, b 11 =b 12 b 21 Not equal to b 22 b 27 equals b 22 b 21 Not equal to b 27 .

[0129] In the seventh operating stage (W7), the bias signal voltage of the DVI bias signal terminal is equal to the bias signal voltage in the second operating stage (W2). However, the bias signal voltage in the first operating stage (W1) is not equal to the bias signal voltage in the second operating stage (W2). Based on this, the pixel circuit can adjust different emission durations, such as 4H, 8H, and 12H, and then adjust the bias signal voltage accordingly. The adjusted bias signal voltage will differ from that in the first operating stage (W1). Furthermore, the bias signal voltage can be kept constant by changing the timing of the bias adjustment stages. This reduces the need for the driver chip to pre-set too many voltages, thus saving IC resources.

[0130] Specifically, compared to the first working stage W1, both the seventh working stage W7 and the second working stage W2 use an EM backward dimming method. Although the emission duration of the seventh working stage W7 and the second working stage W2 are different, the bias adjustment duration b of the seventh working stage W7 is... 27 Equal to the bias adjustment time b of the second working stage W2 22 Therefore, under the same EM backward dimming method, the same bias adjustment duration for the seventh working stage W7 and the second working stage W2 ensures that the threshold voltage offset of the seventh working stage W7 is almost equal to that of the second working stage W2. Based on this, setting the bias signal voltage at the DVI terminal in the seventh working stage W7 to be equal to the bias signal voltage in the second working stage W2 allows the seventh working stage W7 and the second working stage W2 to have the best bias adjustment effect.

[0131] Based on the same inventive concept, embodiments of the present invention provide a display device, including a display panel as described in any of the above embodiments. When the display panel is dimmed using EM, if the duration of the non-light-emitting phase is increased, the voltage signal provided by the DVI is correspondingly reduced; if the duration of the non-light-emitting phase is decreased, the voltage signal provided by the DVI is correspondingly increased. This improves the display uniformity of the display panel and reduces screen flicker.

[0132] The display panel can be an organic light-emitting display panel or a micro LED display panel, but is not limited to these. Figure 19 This is a schematic diagram of a display device provided in an embodiment of the present invention, such as... Figure 19 As shown, this display device can be optionally applied to electronic devices 1 such as smartphones and tablets. It is understood that the above embodiments only provide a partial structure of the display panel and pixel circuitry; the display panel also includes other structures, which will not be described in detail here.

[0133] It should be understood that the various forms of processes shown above can be used, with steps reordered, added, or deleted. For example, the steps described in this invention can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution of this invention can be achieved, and this is not limited herein.

[0134] The specific embodiments described above do not constitute a limitation on the scope of protection of this invention. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this invention should be included within the scope of protection of this invention.

Claims

1. A display panel, characterized in that, include: Pixel circuits and light-emitting elements; The pixel circuit includes a dimming module, a driving module, and a bias module, wherein the dimming module and the driving module are both connected to the light-emitting element. The control terminal of the dimming module is connected to the dimming control terminal, and the dimming module is used to adjust the light emission duration of the light-emitting element; The driving module is used to provide driving current to the light-emitting element, and the driving module includes a driving transistor; The bias module is connected between the bias signal terminal and the first terminal of the driving transistor. The control terminal of the bias module is connected to the bias control terminal. The bias module is used to adjust the bias of the driving transistor. The bias signal terminal provides a bias signal. The pixel circuit includes multiple operating stages, including at least a first operating stage and a second operating stage. The light-emitting element emits light for different durations in the first operating stage and the second operating stage, and the bias signal terminal provides different bias signal voltages in the first operating stage and the second operating stage. The display panel includes S frames of refreshed images. Each refreshed image includes sub-images from the 1st to the Mth frames. In each refreshed image, the 1st sub-image is a data writing frame and the 2nd to the Mth sub-images are all hold frames. S>1, M>1. The display panel satisfies at least one of the following conditions: The first working stage is the data writing frame of the i-th frame refresh, the second working stage is the data writing frame of the j-th frame refresh, i≠j; the multiple working stages also include a third working stage and a fourth working stage, the third working stage is the p-th frame sub-frame of the i-th frame refresh, the fourth working stage is the p-th frame sub-frame of the j-th frame refresh, 2≤p≤M; the light emission duration of the light-emitting element in the third working stage is different from the light emission duration of the light-emitting element in the fourth working stage, and the bias signal voltage corresponding to the third working stage is different from the bias signal voltage corresponding to the fourth working stage; or, The first working stage is the x-th sub-frame of the i-th refreshed frame, and the second working stage is the y-th sub-frame of the i-th refreshed frame, where M≥x≥1, M≥y≥1, and x≠y; the plurality of working stages also includes a fifth working stage and a sixth working stage, where the fifth working stage is the x-th sub-frame of the j-th refreshed frame, and the sixth working stage is the y-th sub-frame of the j-th refreshed frame; the light-emitting duration of the light-emitting element in the fifth working stage is different from the light-emitting duration of the light-emitting element in the first working stage, and the light-emitting duration of the light-emitting element in the sixth working stage is different from the light-emitting duration of the light-emitting element in the second working stage; and... ≠ , ≠ ;in, The difference between the light-emitting duration of the light-emitting element in the first working stage and the fifth working stage. The difference between the light-emitting duration of the light-emitting element in the second working stage and the sixth working stage. This is the difference between the bias signal voltage corresponding to the first operating stage and the bias signal voltage corresponding to the fifth operating stage. It is the difference between the bias signal voltage corresponding to the second working stage and the bias signal voltage corresponding to the sixth working stage.

2. The display panel according to claim 1, characterized in that, The light-emitting duration of the light-emitting element in the first working stage is less than the light-emitting duration of the light-emitting element in the second working stage, and the bias signal voltage corresponding to the first working stage is less than the bias signal voltage corresponding to the second working stage.

3. The display panel according to claim 1, characterized in that, The light-emitting duration of the light-emitting element in the first working stage is less than the light-emitting duration of the light-emitting element in the second working stage, and the bias signal voltage corresponding to the first working stage is less than the bias signal voltage corresponding to the second working stage; furthermore, the light-emitting duration of the light-emitting element in the third working stage is less than the light-emitting duration of the light-emitting element in the fourth working stage, and the bias signal voltage corresponding to the third working stage is less than the bias signal voltage corresponding to the fourth working stage.

4. The display panel according to claim 1, characterized in that, The display panel includes different light emission duration intervals from the 1st to the Nth and different bias signal voltages from the 1st to the Nth. The kth light emission duration interval corresponds to the kth bias signal voltage, N≥k≥1, N>1; The light-emitting element emits light for a duration within the k-th light-emitting duration interval during one of the operating phases, and the bias signal provided by the bias signal terminal during this operating phase is the k-th bias signal voltage.

5. The display panel according to claim 4, characterized in that, The emission duration value of the kth emission duration interval is less than the emission duration value of the (k+1)th emission duration interval, and the kth bias signal voltage is less than or equal to the (k+1)th bias signal voltage.

6. The display panel according to claim 1, characterized in that, The operation phase of the pixel circuit includes a pre-stage and a light-emitting stage executed sequentially, wherein the dimming module is turned off in the pre-stage and turned on in the light-emitting stage. The pre-stage includes a bias stage, during which the bias module is activated. The bias stage includes a first bias sub-stage and / or a second bias sub-stage.

7. The display panel according to claim 6, characterized in that, The pre-processing stage also includes a data writing stage; The biasing stage includes only the first biasing sub-stage, and the data writing stage is located between the first biasing sub-stage and the light emission stage; Alternatively, the biasing stage may include only the second biasing sub-stage, which is located between the data writing stage and the light emission stage. Alternatively, the biasing phase may include a first biasing sub-phase and a second biasing sub-phase, with the data writing phase located between the first biasing sub-phase and the second biasing sub-phase.

8. The display panel according to claim 7, characterized in that, The bias module is reused as a data writing module, and the bias module is also enabled during the data writing phase.

9. The display panel according to claim 8, characterized in that, Within a single frame refresh, during the pre-processing phase of the data writing frame, the bias signal terminal provides a data signal; during the pre-processing phase of the holding frame, the bias signal terminal provides a fixed voltage.

10. The display panel according to claim 7, characterized in that, The pixel circuit also includes a data writing module; The data writing module is connected between the data signal terminal and the first terminal of the driving transistor. The control terminal of the data writing module is connected to the write control terminal. The data writing module is turned on during the data writing phase.

11. The display panel according to claim 10, characterized in that, Within a single frame refresh, during the pre-processing phase of the data writing frame, the bias signal terminal provides a fixed voltage; during the pre-processing phase of the holding frame, the bias signal terminal provides a fixed voltage.

12. The display panel according to claim 7, characterized in that, b1 is the time interval between the data writing stage and the second bias sub-stage executed sequentially in the working stage, and b2 is the time interval between the second bias sub-stage and the light emission stage executed sequentially in the working stage. b 11 =b 12 ,b 21 ≠b 22 ; b 11 For the first working stage, b1, b 12 For the second working stage, b1, b 21 For the first working stage, b2, b 22 This refers to b2 in the second working stage; The bias signal voltage corresponding to the first operating stage is not equal to the bias signal voltage corresponding to the second operating stage.

13. The display panel according to claim 12, characterized in that, The plurality of working stages also includes a seventh working stage, in which the light-emitting duration of the light-emitting element is different from that of the first working stage and the second working stage; b 12 ≠b 17 ,b 22 =b 27 ; b 17 For the seventh working stage, b1, b 27 For the seventh working stage, b2; The bias signal voltage corresponding to the seventh operating stage is equal to the bias signal voltage corresponding to the second operating stage.

14. A display device, characterized in that, Includes the display panel as described in any one of claims 1-13.

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