Adaptive cancellation LED ghosting and coupling method and related circuit product and medium

Abstract

Embodiments of this application provide an adaptive method for eliminating LED ghosting and coupling, as well as related circuit products and media. The method includes: controlling the discharge speed of row parasitic capacitors through a ghosting elimination circuit, increasing the falling edge slope of the row selection signal according to the discharge speed of the row parasitic capacitors, so that the row parasitic capacitors cannot drive LEDs on unselected rows, thereby eliminating the ghosting phenomenon in the LEDs; controlling the charging speed of column parasitic capacitors through a coupling elimination circuit, decreasing the rising edge slope of the column selection signal according to the charging speed of the column parasitic capacitors, so that the column parasitic capacitors cannot drive LEDs on unselected columns, thereby eliminating the coupling phenomenon in the LEDs, and thus significantly improving the overall display effect.

Description

Technical Field

[0001] This application relates to the field of LED technology, and in particular to adaptive methods for eliminating LED ghosting and coupling, as well as related circuit products and media. Background Technology

[0002] Current light-emitting diode (LED) display arrays consist of m rows and n columns of LEDs. Dynamic scanning is often used to scan the array before displaying the image. As integration density increases, the number of pixels per row and column increases, resulting in large parasitic capacitances on both row and column lines. When controlling the on / off state of LEDs in a specific row or column using column pull-down control, the charge on these parasitic capacitances flows through the off LEDs, causing them to conduct slightly and creating LED ghosting. Simultaneously, when controlling high-contrast brightness displays, the higher voltage across the brighter LEDs couples to the darker ones, making the column voltage on the darker side even higher, causing coupling. Summary of the Invention

[0003] This application provides an adaptive method for eliminating LED ghosting and coupling, as well as related circuit products and media, which can quickly and effectively eliminate ghosting and coupling phenomena in LEDs and improve display effects.

[0004] In a first aspect, embodiments of this application provide an adaptive method for eliminating LED ghosting and coupling, applied to an adaptive LED ghosting and coupling elimination circuit. The adaptive LED ghosting and coupling elimination circuit includes an LED display array and a driver chip that provides row selection signals and column selection signals for the LED display array. The LED display array includes m rows * n columns of LEDs, where m and n are both positive integers. Each row of LEDs is connected in parallel with a row parasitic capacitor and a series ghosting elimination circuit, and each column of LEDs is connected in parallel with a column parasitic capacitor and a series coupling elimination circuit.

[0005] The method includes:

[0006] The ghosting elimination circuit controls the first discharge speed, and the falling edge slope of the row selection signal is increased according to the first discharge speed so that the row parasitic capacitance cannot drive the LEDs on the unselected rows. The first discharge speed is the discharge speed of the row parasitic capacitance.

[0007] The first charging speed is controlled by the coupling elimination circuit. The rising edge slope of the column selection signal is reduced according to the first charging speed so that the column parasitic capacitance cannot drive the LEDs on the unselected column. The first charging speed is the charging speed of the column parasitic capacitance.

[0008] Secondly, this application provides an adaptive LED ghosting and coupling elimination circuit, which includes an LED display array and a driver chip that provides row selection signals and column selection signals for the LED display array. The LED display array includes m rows and n columns of LEDs, where m and n are both positive integers. Each row of LEDs is connected in parallel with a row parasitic capacitor and a series ghosting elimination circuit, and each column of LEDs is connected in parallel with a column parasitic capacitor and a series coupling elimination circuit.

[0009] The ghosting elimination circuit is used to control the first discharge speed. The falling edge slope of the row selection signal is increased according to the first discharge speed so that the row parasitic capacitance cannot drive the LED on the unselected row. The first discharge speed is the discharge speed of the row parasitic capacitance.

[0010] The coupling elimination circuit is used to control a first charging speed, and reduces the rising edge slope of the column selection signal according to the first charging speed, so that the column parasitic capacitance cannot drive the LEDs on the unselected column. The first charging speed is the charging speed of the column parasitic capacitance.

[0011] Thirdly, embodiments of this application provide an LED display screen, which includes the adaptive LED ghosting elimination and coupling circuit described in the second aspect.

[0012] Fourthly, embodiments of this application provide a display device, the display device including a processor, a memory, a communication interface and the LED display screen described in the third aspect above, the memory storing one or more programs, and the one or more programs being executed by the processor, the one or more programs including instructions for performing some or all of the steps described in the method described in the first aspect above.

[0013] Fifthly, embodiments of this application provide a computer-readable storage medium storing a computer program for electronic data interchange, wherein the computer program causes a computer to perform some or all of the steps described in the method described in the first aspect above.

[0014] Sixthly, embodiments of this application provide a computer program product, wherein the computer program product includes a non-transitory computer-readable storage medium storing a computer program, the computer program being operable to cause a computer to perform some or all of the steps described in the method described in the first aspect of embodiments of this application. The computer program product may be a software installation package.

[0015] Therefore, the adaptive LED ghosting and coupling elimination method proposed in this application controls the discharge speed of the row parasitic capacitor through a ghosting elimination circuit, and increases the falling edge slope of the row selection signal according to the discharge speed of the row parasitic capacitor, so that the row parasitic capacitor cannot drive the LEDs on the unselected row, thereby eliminating the ghosting phenomenon in the LEDs; and controls the charging speed of the column parasitic capacitor through a coupling elimination circuit, and decreases the rising edge slope of the column selection signal according to the charging speed of the column parasitic capacitor, so that the column parasitic capacitor cannot drive the LEDs on the unselected column, thereby eliminating the coupling phenomenon in the LEDs, thus significantly improving the overall display effect. Attached Figure Description

[0016] To more clearly illustrate the technical solutions in the embodiments of this application, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0017] Figure 1 This is a schematic diagram of the timing and circuit diagram of an LED display array provided in an embodiment of this application;

[0018] Figure 2 This is a schematic diagram of a circuit structure for a ghosting phenomenon provided in an embodiment of this application;

[0019] Figure 3 This is a schematic diagram of a circuit structure illustrating inter-coupling phenomena provided in an embodiment of this application;

[0020] Figure 4 This is a schematic diagram of an adaptive LED ghosting elimination and coupling circuit provided in an embodiment of this application;

[0021] Figure 5 This is a schematic diagram of the structure of a ghosting elimination circuit provided in an embodiment of this application;

[0022] Figure 6 This is a schematic diagram of a coupling elimination circuit provided in an embodiment of this application;

[0023] Figure 7 This is a flowchart illustrating an adaptive method for eliminating LED ghosting and coupling provided in an embodiment of this application;

[0024] Figure 8 This is a schematic diagram illustrating the effect of controlling the falling edge slope of a row selection signal according to an embodiment of this application;

[0025] Figure 9 This is a schematic diagram illustrating the effect of controlling the rising edge slope of a column select signal according to an embodiment of this application. Detailed Implementation

[0026] To help those skilled in the art better understand the technical solutions of this application, the technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the description of the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0027] The terms "first," "second," etc., in the specification, claims, and accompanying drawings of this application are used to distinguish different objects, not to describe a specific order. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion. For example, a process, method, software, product, or apparatus that includes a series of steps or units is not limited to the listed steps or units, but also includes steps or units not listed, or other steps or units inherent to such processes, methods, products, or apparatus.

[0028] In this document, the term "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0029] The embodiments of this application are described below with reference to the accompanying drawings. In the drawings, the intersection of intersecting wires is indicated by dots, and the absence of dots indicates that the wires are not connected.

[0030] Currently, displays are generally implemented using a scanning method. For example... Figure 1 As shown, the display array consists of m rows * n columns of LEDs and a driver chip. The driver chip sends m row selection signals and n column selection signals respectively. The m row selection signals are valid in a cycle, and each row selection signal corresponds to n LED control signals within its validity period.

[0031] When multiple row selection signals (m row selection signals) are cyclically valid, if the drive signal for row 1 has just ended (i.e., switch RS1 changes from closed to open), and the row selection signal for row 2 is already valid (i.e., switch RS2 changes from open to closed), theoretically there should be no row selection signal on row 1. However, due to the parasitic capacitance CR1 in row 1, when the row selection signal for row 2 is valid, CR1 will discharge to all LEDs on row 1. If the column selection signal is valid at this time, the LEDs in the corresponding column with the valid column selection signal will be dimly lit, causing a ghosting effect in the display. The same problem exists for switching between other rows, such as... Figure 2 As shown in the figure, time T2 is the time when the ghosting phenomenon occurs.

[0032] Furthermore, when a row select signal is activated, the valid column select signal will illuminate the LEDs on that row and the valid column select signal. However, due to the parasitic capacitance CC between the column select signals, the column select signal next to the valid column select signal will, due to the presence of the parasitic capacitance CC, weakly conduct through the parasitic capacitance CC, forming a brief loop. For example, as... Figure 3 As shown in the diagram, the row 2 signal is selected, meaning RS2 is closed. At this time, the column selection signal for column 2 is valid, i.e., when IS2 is closed, LED2-2 is lit. Conversely, the column selection signal for column 1 is invalid, meaning IS1 is open, and LED2-1 should be off. However, due to the parasitic capacitance CC1-2 between columns 1 and 2, and because the column selection signal for column 2 is generally a low voltage, the end of CC1-2 closest to column 2 is also at a low voltage. Therefore, the circuit forms a brief discharge loop through RS2->LED2-1->CC1-2, causing LED2-1 to be briefly and weakly lit, resulting in inter-column coupling in the display.

[0033] Ghosting and coupling are common and difficult-to-eradicate phenomena in LED dynamic scanning displays. To address this issue, this application proposes an adaptive method for eliminating LED ghosting and coupling. A ghosting elimination circuit is connected in series with each row of LEDs. By increasing the falling edge slope of the row selection signal through the ghosting elimination circuit, the parasitic capacitance of the row cannot drive the LEDs in the unselected row, thereby eliminating the ghosting phenomenon. A coupling elimination circuit is connected in series with each column of LEDs. By decreasing the rising edge slope of the column selection signal through the coupling elimination circuit, the parasitic capacitance of the column cannot drive the LEDs in the unselected column, thereby eliminating the inter-column coupling phenomenon and thus effectively improving the overall display effect.

[0034] Please see Figure 4 , Figure 4 This is a schematic diagram of an adaptive LED ghosting elimination and coupling circuit provided in an embodiment of this application. Figure 4 As shown, the adaptive LED ghosting and coupling elimination circuit includes an LED display array 100, a driver chip 200, m row parasitic capacitors CR 300, n column parasitic capacitors CC 400, m ghosting elimination circuits 500, and n coupling elimination circuits 600.

[0035] The aforementioned LED display array 100 comprises m rows and n columns of LEDs. The aforementioned driver chip 200 provides row selection signals RCTL and column selection signals CCTL to the LED display array 100. The aforementioned m ghosting elimination circuits 500 are connected in series with each row of LEDs, and the aforementioned n coupling elimination circuits 600 are connected in series with each column of LEDs. Each row of LEDs is also connected in parallel with a row parasitic capacitor CR 300, and each column of LEDs is also connected in parallel with a column parasitic capacitor CC 400.

[0036] In the specific implementation, due to the presence of the row parasitic capacitor CR 300, when the row selection signal RCTL of the i-th row is valid, the row parasitic capacitor CR 300 connected in parallel to the (i-1)-th row will discharge to all the LEDs in the (i-1)-th row, thus weakly lighting the LEDs in the columns where the column selection signal CCTL of the (i-1)-th row is valid, causing a ghosting phenomenon in the display. To solve this problem, this application connects a ghosting elimination circuit 500 in series with each row of LEDs. This ghosting elimination circuit 500 can effectively control the discharge rate of the row parasitic capacitor CR 300, that is, adjust the falling edge slope of the row selection signal according to the discharge rate of the row selection signal CR 300, so that before the row selection signal RCTL of the i-th row becomes valid, the charge of the row parasitic capacitor CR 300 of the (i-1)-th row has been reduced to the point that it cannot drive the LEDs in the (i-1)-th row, where i is a positive integer less than or equal to M.

[0037] When the row selection signal RCTL of row i is active, the column selection signal CTLL of column j, which is also active at this time, will light up the LED in row i, column j. At this time, due to the presence of the column parasitic capacitance CC 400, column j-1 will form a brief loop through the weak conduction of the column parasitic capacitance CC 400 when the column selection signal CTLL is inactive, causing the LED in row i, column j-1 to be briefly and weakly lit, resulting in inter-column coupling. To solve this problem, this application connects a coupling cancellation circuit 600 in series with each column of LEDs. This coupling cancellation circuit 600 can control the charging speed of the column parasitic capacitance CC 400 and adaptively adjust the rising edge slope of the column selection signal CTLL, so that the low-voltage pulse when the column selection signal CTLL of column j is active will not cause the column parasitic capacitance CC 400 in column j-1 to enter a fast charging state, thereby weakening the charge of the column parasitic capacitance in column j-1 to the point that it cannot drive the LED in column j-1.

[0038] For example, please read Figure 5 , Figure 5 This is a schematic diagram of the structure of a ghosting elimination circuit 500 provided in an embodiment of this application. Figure 5 As shown, the ghosting elimination circuit 500 includes a first transistor Q1, a second transistor Q2, a first resistor R1, a comparator U1, and an AND gate.

[0039] In this configuration, the source of the first transistor Q1 is connected to the power supply VLED, and the drain of the first transistor Q1 is connected to the positive input terminal of the comparator U1, the drain of the second transistor Q2, one end of the horizontal parasitic capacitance CR, and the output terminal of the ghost cancellation circuit 500. The gate of the first transistor Q1 is connected to the input terminal of the ghost cancellation circuit 500 and the first input terminal of the AND gate. The inverting input terminal of the comparator U1 is connected to the reference voltage VREF, and the output terminal of the comparator U1 is connected to the second input terminal of the AND gate. The output terminal of the AND gate is connected to the gate of the second transistor Q2, and the source of the second transistor Q2 is connected to one end of the first resistor R1. The other end of the first resistor R1 is connected to the other end of the horizontal parasitic capacitance CR and grounded.

[0040] The ghosting elimination circuit 500 of this application adopts the principle of fast current pulling and clamping. The first transistor Q1 is a P-channel MOS transistor, which is used to control the output voltage Vrout of the ghosting elimination circuit 500. The second transistor Q2 is an N-channel MOS transistor, which is used to control whether to drive a new falling edge for slope adjustment.

[0041] Specifically, when the row selection signal RCTL changes from high to low (i.e., when RCTL is at its falling edge), the first transistor Q1 is turned on, the voltage at the positive input of comparator U1 is Vrout, and a reference voltage VREF lower than the output voltage Vrout is connected to the negative input of comparator U1. At this time, the output of comparator U1 is high. However, since the row selection signal RCTL is low, the AND gate output is low, and the second transistor Q2 is turned off. The output voltage Vrout of the ghosting elimination circuit 500 is always approximately equal to the power supply VLED that powers the LED display array, and during this period, the parasitic horizontal capacitance CR is charged. When the row selection signal RCTL becomes high, the first transistor Q1 is turned off, the parasitic horizontal capacitance CR discharges, and the output voltage Vrout of the ghosting elimination circuit 500 is approximately the voltage of the parasitic horizontal capacitance CR. When the output voltage Vrout of the ghost cancellation circuit 500 is greater than or equal to the reference voltage VREF, the comparator U1 outputs a high level, therefore the AND gate outputs a high level and drives the second transistor Q2 to conduct. The horizontal parasitic capacitance CR begins to discharge rapidly through the path of comparator U1 -> AND gate -> second transistor Q2 -> first resistor R1 -> ground. As the charge of the horizontal parasitic capacitance CR continues to decrease, when the output voltage Vrout of the ghost cancellation circuit 500 is less than the reference voltage VREF, the comparator U1 outputs a low level, the second transistor Q2 is in the off state, the discharge path of the horizontal parasitic capacitance CR is broken, and the horizontal parasitic capacitance CR no longer discharges.

[0042] In this embodiment of the application, in order to accurately and effectively control the discharge speed of the horizontal parasitic capacitor CR, that is, to control the falling edge slope of the horizontal selection signal RCTL, the ghost cancellation circuit 500 can calculate the preset value of the output voltage Vrout of the ghost cancellation circuit 500, and then achieve different slopes by using the resistance value of the first resistor R1.

[0043] For an example, please refer to Figure 6 , Figure 6 This is a schematic diagram of a coupling elimination circuit 600 provided in an embodiment of this application. Figure 6 As shown, the coupling elimination circuit 600 includes a third transistor Q3, a fourth transistor Q4, a fifth transistor Q5, an adjustable constant current source, a current configuration circuit, and n sixth transistors Q6.

[0044] In this configuration, the gate of the third transistor Q3 is connected to the input terminal of the coupling elimination circuit 600 and the gate of the fifth transistor Q5. The source of the third transistor Q3 is connected to VCC and the sources of the n sixth transistors Q6. The drain of the third transistor Q3 is connected to the gate of the fourth transistor Q4, the drain of the fifth transistor Q5, one end of the column parasitic capacitance CC, and the drains of the n sixth transistors Q6. The other end of the column parasitic capacitance CC is grounded. The source of the fourth transistor Q4 is connected to the output terminal of the coupling elimination circuit 600. The drain of the fourth transistor Q4 is connected to the first output terminal of the adjustable constant current source. The second output terminal of the adjustable constant current source is connected to the source of the fifth transistor Q5 and grounded. The current configuration circuit is connected to the control terminal of the adjustable constant current source and the gates of the n sixth transistors Q6.

[0045] In this application, in order to better eliminate ghosting and coupling phenomena in LED display arrays, a variable slope signal processing mechanism is adopted. By controlling the falling edge slope of the row selection signal RCTL and the rising edge slope of the column selection signal CCTL, the ghosting and coupling phenomena in LED display arrays are quickly eliminated, thereby improving the display effect.

[0046] The slope adjustment of the column select signal CCTL differs from that of the row select signal RCTL. In this application, the slope adjustment of the column select signal CCTL primarily relies on the weak conduction of n sixth transistors Q6 to adjust the rising edge slope of the final column select signal CCTL. The third transistor Q3 is a P-channel MOS transistor, the fourth transistor is an N-channel MOS transistor, the fifth transistor Q5 is an N-channel MOS transistor, and all n sixth transistors Q6 are P-channel MOS transistors. Furthermore, all n sixth transistors Q6 are weakly conducted, meaning that the turn-on voltages of the third transistor Q3, the fourth transistor Q4, and the fifth transistor Q5 are significantly higher than the turn-on voltages of these n sixth transistors Q6.

[0047] Specifically, when the column select signal CCTL is high, the third transistor Q3 and the fourth transistor Q4 are in the off state, and the column parasitic capacitance CC discharges, driving the fifth transistor Q5 to be in the on state. When the column select signal CCTL is low, both the third transistor Q3 and the fourth transistor Q4 are in the on state. At this time, a constant current source path is formed, and the column parasitic capacitance CC is charged. This constant current source can output current according to the output current capability configured by the current configuration circuit. In this state, the current configuration circuit simultaneously configures different currents to control the conduction of n sixth transistors Q6. The number of sixth transistors Q6 that are turned on can be controlled according to the configured current, and thus the charging capability of the column parasitic capacitance CC is adjusted according to the number of sixth transistors Q6 that are turned on. As the number of sixth transistors Q6 that are turned on increases, the voltage on the gate of the fourth transistor Q4 also increases slowly, resulting in different conduction levels of the fourth transistor Q4, which in turn causes different rising slopes of the rising edge of the column select signal CCTL.

[0048] In the embodiments of this application, the larger the current configured by the current configuration circuit, the smaller the rising edge slope of the column select signal CCTL; the smaller the current configured by the current configuration circuit, the larger the rising edge slope of the column select signal CCTL, so that the rising edge slope of the column select signal CCTL can be adaptively adjusted according to the size of the configured current.

[0049] As can be seen, the adaptive LED ghosting elimination and coupling circuit provided in this application embodiment, with each row of LEDs connected in series with the ghosting elimination circuit 500 and each column of LEDs connected in series with the coupling elimination circuit 600, increases the falling edge slope of the row selection signal through the ghosting elimination circuit 500, so that the row parasitic capacitance CR cannot drive the LEDs on the unselected row, thereby eliminating the ghosting phenomenon; and decreases the rising edge slope of the column selection signal through the coupling elimination circuit 600, so that the column parasitic capacitance CC cannot drive the LEDs on the unselected column, thereby eliminating the inter-column coupling phenomenon, and thus effectively improving the overall display effect.

[0050] Please see Figure 7 , Figure 7 This application provides a flowchart illustrating an adaptive method for eliminating LED ghosting and coupling, applicable to, for example... Figures 4-6 The adaptive LED ghosting cancellation and coupling circuit shown is illustrated. Figure 7 As shown, the method includes the following steps.

[0051] S710. The first discharge speed is controlled by the ghost cancellation circuit, and the falling edge slope of the row selection signal is increased according to the first discharge speed so that the row parasitic capacitance cannot drive the LED on the unselected row. The first discharge speed is the discharge speed of the row parasitic capacitance.

[0052] In this process, when the row selection signal RCTL is cyclically active, the parasitic capacitance CR on the unselected rows (i.e., when the row selection signal is inactive) discharges to the LEDs on those rows, causing the LEDs in the selected columns of those rows to be faintly illuminated. Therefore, this application increases the falling edge slope of the row selection signal RCTL by controlling its discharge rate, preventing the parasitic capacitance from driving the LEDs on the unselected rows, thereby eliminating ghosting and improving the display effect.

[0053] Optionally, controlling the first discharge rate through the ghosting elimination circuit and increasing the falling edge slope of the row selection signal according to the first discharge rate includes: when the row selection signal is low, turning on the first transistor through the row selection signal and charging the row parasitic capacitor through the power supply; when the row selection signal is high, turning off the first transistor through the row selection signal and driving the second transistor to conduct through the discharge of the row parasitic capacitor within a first time period, the first time period being the time when the charge of the row parasitic capacitor is greater than or equal to the VREF; determining the falling edge slope of the row selection signal corresponding to the first time period based on the mapping relationship between time and falling edge slope.

[0054] When the row selection signal RCTL transitions from high to low (i.e., at its falling edge), the first transistor Q1 is on and the second transistor Q2 is off. The output voltage Vrout of the ghosting elimination circuit 500 remains approximately equal to the power supply VLED, charging the parasitic horizontal capacitance CR during this period. When the row selection signal RCTL goes high, the first transistor Q1 is off, and the output voltage Vrout of the ghosting elimination circuit 500 is approximately equal to the voltage of the parasitic horizontal capacitance CR. The parasitic horizontal capacitance CR discharges, driving the second transistor Q2 to turn on until its voltage is less than the reference voltage VREF.

[0055] Wherein, the aforementioned first time is the discharge time of the horizontal parasitic capacitance CR, and the magnitude of this first time is mapped to the falling edge slope of the horizontal selection signal RCTL, such as... Figure 8 As shown, the ghosting elimination circuit 500 can effectively increase the rising and falling edge slopes of the row selection signal RCTL. However, due to the presence of the row parasitic capacitance CR, the rising and falling edges of the row selection signal RCTL become slow and unpredictable. Therefore, by selecting an appropriate value for the first resistor, the falling edge slope of the row selection signal RCTL can be effectively increased, allowing the row parasitic capacitance CR to discharge quickly when the row selection signal RCTL changes from high to low, thus preventing the LEDs on the unselected rows from being driven.

[0056] In this embodiment, the falling edge slope of the row selection signal RCTL is controlled by the ghost cancellation circuit 500, that is, the falling edge slope of the row selection signal RCTL is increased to ensure that when the row selection signal RCTL of the i-th row is in the validity period, the charge of the row parasitic capacitor CR on the i-th row has been reduced to the point that it cannot drive the LED on the row.

[0057] S720. The first charging speed is controlled by the coupling elimination circuit. The rising edge slope of the column selection signal is reduced according to the first charging speed so that the column parasitic capacitance cannot drive the LEDs on the unselected column. The first charging speed is the charging speed of the column parasitic capacitance.

[0058] In this application, a low-voltage pulse in the column select signal CCTL of column j causes the adjacent column parasitic capacitor CC (the column parasitic capacitor CC on column j-1) to enter a fast charging state. This causes LEDs on columns near column j that should not be lit to suddenly light up weakly due to the rapid charging of the column parasitic capacitor CC, where j is a positive integer less than or equal to N. Therefore, this application reduces the charging rate of the column parasitic capacitor CC by adjusting the rising edge slope of the column select signal CCTL, thereby eliminating inter-column coupling and improving the display effect.

[0059] Optionally, controlling the first charging speed through the coupling elimination circuit and reducing the rising edge slope of the column select signal according to the first charging speed includes: when the row select signal is high, turning on the fifth transistor by discharging the column parasitic capacitance; when the column select signal is low, turning on both the third and fourth transistors through the column select signal, and charging the column parasitic capacitance through VCC in a second time period, the second time period being determined by the number of sixth transistors turned on among the n sixth transistors; and determining the rising edge slope of the column select signal corresponding to the second time period according to the mapping relationship between time and rising edge slope.

[0060] Among them, the n sixth transistors are all weakly conducting transistors.

[0061] Specifically, when the column select signal CCTL is low, both the third transistor Q3 and the fourth transistor Q4 are in the on state, forming a constant current source path to charge the column parasitic capacitance CC. During the charging process of the column parasitic capacitance CC, the current configuration circuit can configure different currents to control the conduction of n sixth transistors Q6 respectively. The number of sixth transistors Q6 that are turned on can be controlled according to the configured current, thereby adjusting the charging capability of the column parasitic capacitance CC based on the number of sixth transistors Q6 that are turned on. As the number of sixth transistors Q6 that are turned on increases, the voltage on the gate of the fourth transistor Q4 also gradually increases, resulting in different levels of conduction of the fourth transistor Q4, which in turn causes different rising slopes of the column select signal CCTL.

[0062] Furthermore, the aforementioned second time is the charging time of the column parasitic capacitance CC, which is mapped to the rising edge slope of the column select signal CCTL. For example... Figure 9 As shown, before slope adjustment (left waveform), due to the presence of column parasitic capacitance CC between column j and column j+1, when the column select signal CCTL of column j is active while that of column j+1 is inactive, a sudden low pulse on column j will couple column j to a brief low level state through the column parasitic capacitance CC on column j+1. This causes the LED in row i, column j+1, which should not be lit, to be weakly lit. After slope adjustment (right waveform), the rising edge of the column select signal CCTL on column j+1 is slowed down. At this time, due to the slow coupling of column parasitic capacitance CC between column j and column j+1, the low signal on column j+1 does not reach the low level needed to light up the LED in row i, column j+1, and quickly becomes the voltage after the LED voltage drop. Therefore, the inter-column coupling problem is effectively solved.

[0063] As can be seen, this application proposes an adaptive method for eliminating LED ghosting and coupling. Each row of LEDs is connected in series with a ghosting elimination circuit 500, and each column of LEDs is connected in series with a coupling elimination circuit 600. The ghosting elimination circuit 500 increases the falling edge slope of the row selection signal RCTL, preventing the row parasitic capacitance CR from driving the LEDs in the unselected row, thus eliminating the ghosting phenomenon. The coupling elimination circuit 600 decreases the rising edge slope of the column selection signal CCTL, preventing the column parasitic capacitance CC from driving the LEDs in the unselected column, thus eliminating inter-column coupling and effectively improving the overall display effect.

[0064] It should be understood that "at least one" in the embodiments of this application refers to one or more, and "more than one" refers to two or more. "And / or" describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A alone, A and B simultaneously, or B alone, where A and B can be singular or plural. The character " / " generally indicates that the preceding and following related objects are in an "or" relationship. "At least one of the following" or similar expressions refer to any combination of these items, including any combination of single or plural items. For example, at least one of a, b, or c can represent: a, b, c, ab, ac, bc, or abc, where a, b, and c can be single or multiple.

[0065] This application embodiment also provides an LED display screen, which includes the above-described components. Figures 4-6 The adaptive LED ghosting cancellation and coupling circuit shown is illustrated.

[0066] This application embodiment also provides a display device, which includes a processor, a memory, a communication interface and the LED display screen. The memory stores one or more programs, and the one or more programs are executed by the processor. The one or more programs include instructions for performing some or all of the steps of any of the methods described in the above method embodiments.

[0067] This application also provides a computer storage medium storing a computer program for electronic data interchange, which causes a computer to perform some or all of the steps of any of the methods described in the above method embodiments.

[0068] This application also provides a computer program product, which includes a non-transitory computer-readable storage medium storing a computer program operable to cause a computer to perform some or all of the steps of any of the methods described in the above method embodiments. This computer program product can be a software installation package.

[0069] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.

[0070] In the several embodiments provided in this application, it should be understood that the disclosed adaptive LED ghosting cancellation and coupling circuit can be implemented in other ways. For example, the embodiments of adaptive LED ghosting cancellation and coupling circuit described above are merely illustrative, and the components in the above circuit can also be other components with the same function. Furthermore, the mutual coupling or direct coupling or communication connection shown or discussed can be indirect coupling or communication connection through some interface, circuit, or component, and can be electrical or other forms.

[0071] In addition, the circuits in the various embodiments of this application can be integrated into a single circuit board, or each circuit can exist as a separate entity, or two or more circuits can be integrated into a single circuit board.

[0072] The embodiments of this application have been described in detail above. Specific examples have been used to illustrate the principles and implementation methods of this application. The description of the above embodiments is only for the purpose of helping to understand this application and its core ideas. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of this application. Therefore, the content of this specification should not be construed as a limitation of this application.

Claims

1. An adaptive method for eliminating LED ghosting and coupling, characterized in that, An adaptive LED ghosting and coupling elimination circuit is applied to the LED display array and a driver chip that provides row selection signals and column selection signals for the LED display array. The LED display array includes m rows × n columns of LEDs, where m and n are both positive integers. The LEDs in the i-th row are connected in parallel with a row parasitic capacitor and a series ghosting elimination circuit, and the LEDs in the j-th row and column are connected in parallel with a column parasitic capacitor and a series coupling elimination circuit. The m row selection signals are valid cyclically, and each row selection signal corresponds to n LED control signals within its validity period. Wherein, the LED in the i-th row is one of the LEDs in the m-row LEDs; Wherein, the LED in column j is one of the LEDs in column n; The method includes: The ghosting elimination circuit controls the first discharge speed, and the falling edge slope of the row selection signal is increased according to the first discharge speed so that the row parasitic capacitance cannot drive the LEDs on the unselected rows. The first discharge speed is the discharge speed of the row parasitic capacitance. The first charging speed is controlled by the coupling elimination circuit, and the rising edge slope of the column selection signal is reduced according to the first charging speed so that the column parasitic capacitance cannot drive the LEDs on the unselected column. The first charging speed is the charging speed of the column parasitic capacitance. in, The ghosting elimination circuit includes: a first transistor, a second transistor, a first resistor, a comparator, and an AND gate; The source of the first transistor is connected to the power supply. The drain of the first transistor is connected to the positive input terminal of the comparator, the drain of the second transistor, one end of the row parasitic capacitance, and the output terminal of the ghost cancellation circuit. The gate of the first transistor is connected to the input terminal of the ghost cancellation circuit and the first input terminal of the AND gate. The inverting input terminal of the comparator is connected to the reference voltage VREF. The output terminal of the comparator is connected to the second input terminal of the AND gate. The output terminal of the AND gate is connected to the gate of the second transistor. The source of the second transistor is connected to one end of the first resistor. The other end of the first resistor is connected to the other end of the row parasitic capacitance and grounded. The coupling elimination circuit includes: a third transistor, a fourth transistor, a fifth transistor, an adjustable constant current source, a current configuration circuit, and n sixth transistors; The gate of the third transistor is connected to the input terminal of the coupling elimination circuit and the gate of the fifth transistor. The source of the third transistor is connected to VCC and the sources of the n sixth transistors. The drain of the third transistor is connected to the gate of the fourth transistor, the drain of the fifth transistor, one end of the column parasitic capacitance, and the drains of the n sixth transistors. The other end of the column parasitic capacitance is grounded. The source of the fourth transistor is connected to the output terminal of the coupling elimination circuit. The drain of the fourth transistor is connected to the first output terminal of the adjustable constant current source. The second output terminal of the adjustable constant current source is connected to the source of the fifth transistor and grounded. The current configuration circuit is connected to the control terminal of the adjustable constant current source and the gates of the n sixth transistors.

2. The method according to claim 1, characterized in that, The step of controlling the first discharge speed through the ghosting elimination circuit and increasing the falling edge slope of the row selection signal according to the first discharge speed includes: When the row selection signal is low, the first transistor is turned on by the row selection signal, and the row parasitic capacitor is charged by the power supply. When the row selection signal is high, the first transistor is turned off by the row selection signal, and the second transistor is turned on by discharging the row parasitic capacitor within a first time. The first time is the time when the charge of the row parasitic capacitor is greater than or equal to the VREF. Based on the mapping relationship between time and falling edge slope, the falling edge slope of the row selection signal corresponding to the first time is determined.

3. The method according to claim 1, characterized in that, The step of controlling the first charging speed through the coupling cancellation circuit and reducing the rising edge slope of the column select signal according to the first charging speed includes: When the row selection signal is high, the fifth transistor is turned on by discharging the column parasitic capacitance; When the column select signal is low, the third transistor and the fourth transistor are both turned on by the column select signal, and the column parasitic capacitance is charged by VCC in the second time period, which is determined by the number of sixth transistors turned on among the n sixth transistors; Based on the mapping relationship between time and rising edge slope, the rising edge slope of the column selection signal corresponding to the second time is determined.

4. An adaptive LED ghosting and coupling elimination circuit, characterized in that, The adaptive LED ghosting elimination and coupling circuit includes an LED display array and a driver chip that provides row selection signals and column selection signals for the LED display array. The LED display array includes m rows × n columns of LEDs, where m and n are both positive integers. The LEDs in the i-th row are connected in parallel with a row parasitic capacitor and a series ghosting elimination circuit, and the LEDs in the j-th column are connected in parallel with a column parasitic capacitor and a series coupling elimination circuit. Among them, the m row selection signals are valid cyclically, and each row selection signal corresponds to n LED control signals within its validity period. Wherein, the LED in the i-th row is one of the LEDs in the m-row LEDs; Wherein, the LED in column j is one of the LEDs in column n; The ghosting elimination circuit is used to control the first discharge speed. The falling edge slope of the row selection signal is increased according to the first discharge speed so that the row parasitic capacitance cannot drive the LED on the unselected row. The first discharge speed is the discharge speed of the row parasitic capacitance. The coupling elimination circuit is used to control the first charging speed and reduce the rising edge slope of the column selection signal according to the first charging speed so that the column parasitic capacitance cannot drive the LEDs on the unselected column. The first charging speed is the charging speed of the column parasitic capacitance. The ghosting elimination circuit includes: a first transistor, a second transistor, a first resistor, a comparator, and an AND gate; The source of the first transistor is connected to the power supply. The drain of the first transistor is connected to the positive input terminal of the comparator, the drain of the second transistor, one end of the row parasitic capacitance, and the output terminal of the ghost cancellation circuit. The gate of the first transistor is connected to the input terminal of the ghost cancellation circuit and the first input terminal of the AND gate. The inverting input terminal of the comparator is connected to the reference voltage VREF. The output terminal of the comparator is connected to the second input terminal of the AND gate. The output terminal of the AND gate is connected to the gate of the second transistor. The source of the second transistor is connected to one end of the first resistor. The other end of the first resistor is connected to the other end of the row parasitic capacitance and grounded. The coupling elimination circuit includes: a third transistor, a fourth transistor, a fifth transistor, an adjustable constant current source, a current configuration circuit, and n sixth transistors; The gate of the third transistor is connected to the input terminal of the coupling elimination circuit and the gate of the fifth transistor. The source of the third transistor is connected to VCC and the sources of the n sixth transistors. The drain of the third transistor is connected to the gate of the fourth transistor, the drain of the fifth transistor, one end of the column parasitic capacitance, and the drains of the n sixth transistors. The other end of the column parasitic capacitance is grounded. The source of the fourth transistor is connected to the output terminal of the coupling elimination circuit. The drain of the fourth transistor is connected to the first output terminal of the adjustable constant current source. The second output terminal of the adjustable constant current source is connected to the source of the fifth transistor and grounded. The current configuration circuit is connected to the control terminal of the adjustable constant current source and the gates of the n sixth transistors.

5. An LED display screen, characterized in that, The LED display screen includes the adaptive LED ghosting elimination and coupling circuit as described in claim 4.

6. A display device, characterized in that, The display device includes a processor, a memory, a communication interface, and an LED display screen as described in claim 5, wherein the memory stores one or more programs, and the one or more programs are executed by the processor, the one or more programs including instructions for performing the steps of the method as described in any one of claims 1-3.

7. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program for electronic data interchange, wherein the computer program causes a computer to perform the steps of the method as described in any one of claims 1-3.

8. A computer program product, characterized in that, The computer program product causes a computer to perform the steps of the method as described in any one of claims 1-3.

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