Array substrate and display device

Abstract

The present disclosure provides an array substrate and a display device. The array substrate comprises: a gate driving unit configured to output a write switch signal to a refresh control unit in response to a determination result of whether pixel units in a column need to write pixel data of a current row before displaying each frame of image; a data driving unit configured to output a preset level signal to the refresh control unit in response to the determination result; the refresh control unit configured to output a refresh control signal when receiving the write switch signal and the preset level signal; the refresh control signal is configured to control the pixel units in the column to write the pixel data of the current row; and the data driving unit is configured to output the pixel data of the current row to a data line in the current row when determining that the pixel units in the column write the pixel data of the current row. The embodiment can avoid repeatedly refreshing the pixel data, thereby reducing the power consumption of the data driving unit.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the field of display, and in particular to an array substrate and a display device. BACKGROUND

[0002] OLED (Organic Light-Emitting Diode) display technology has the advantages of high contrast, fast response, low power consumption, etc., and is more and more widely used.

[0003] The OLED device in the OLED display device is a current type organic light-emitting device. Holes generated by an anode and electrons generated by a cathode are combined to generate an energy excimer, so as to excite light-emitting molecules to finally generate visible light. The light-emitting intensity is proportional to the injected current.

[0004] In the related art, LTPO display technology combining LTPS technology and IGZO technology is used to reduce driving power consumption by reducing repeated refreshing of static pictures.

[0005] In the related art, when updating a picture, the LTPO display technology needs to initialize and write all pixels within one frame time. However, in some scenarios such as watching a video in a horizontal screen, there are pixels in the frame image that do not need to update the voltage. However, the related art solution updates the voltage of these pixels, which increases the power consumption of the driving chip. SUMMARY

[0006] The present disclosure provides an array substrate and a display device to solve the above technical problems.

[0007] According to a first aspect of the present disclosure, an array substrate is provided, comprising a gate driving unit, a data driving unit, a refresh control unit and a row-column distributed pixel unit; the data driving unit is electrically connected with the refresh control unit, the gate driving unit is electrically connected with the refresh control unit, and the refresh control unit is electrically connected with the pixel unit in the column;

[0008] The gate driving unit is configured to output a write switch signal to the refresh control unit in response to a determination result of whether the pixel unit in the column needs to write pixel data of the current row before displaying each frame image;

[0009] The data driving unit is configured to determine whether the pixel unit in the column needs to write pixel data of the current row before displaying each frame image, and output a write switch signal and a preset level signal to the refresh control unit;

[0010] The refresh control unit is configured to output a refresh control signal when receiving the write switch signal and the preset level signal; the refresh control signal is configured to control the pixel unit in the column to write pixel data of the current row.

[0011] The data driving unit is configured to output pixel data of a current row to a data line of the current row when determining that a pixel unit of a current column writes the pixel data of the current row.

[0012] The pixel unit is configured to drive the light emitting device to emit light when writing the pixel data of the current row.

[0013] Optionally, the refresh control unit is arranged in a non-display area of the array substrate and close to a display area of the array substrate.

[0014] Optionally, the refresh control unit comprises a control signal writing module, a control signal maintaining module and a control signal output module; the control signal writing module is electrically connected with the gate driving unit and a signal node; the control signal maintaining module is electrically connected with the signal node and a power line respectively; the control signal output module is electrically connected with the signal node, a first level line, a second level line and a refresh control line respectively; the refresh control line is electrically connected with a pixel unit of a current column.

[0015] The control signal writing module is configured to write a first preset level to the signal node when the switch signal is a write-on signal and the preset level signal is the first preset level.

[0016] The control signal maintaining module is configured to maintain the preset level signal of the signal node.

[0017] The control signal output module is configured to electrically connect the second level line and the refresh control line when the preset level is the first preset level, so as to write the level signal of the second level line as a refresh enable signal to the refresh control line.

[0018] Optionally, the control signal writing module comprises a first refresh transistor; a first electrode of the first refresh transistor is electrically connected with a data line of a current column; a second electrode of the first refresh transistor is electrically connected with the signal node; a control electrode of the first refresh transistor is electrically connected with the gate driving unit.

[0019] The first refresh transistor is configured to write the preset level signal received by the data line of the current column to the signal node when the write-on switch signal is a write-on signal.

[0020] Optionally, the control signal maintaining module comprises a maintaining capacitor; a first electrode of the maintaining capacitor is electrically connected with the power line; a second electrode of the maintaining capacitor is electrically connected with the signal node.

[0021] The maintaining capacitor is configured to maintain the preset level signal of the signal node.

[0022] Optionally, the control signal output module includes a second refresh transistor and a third refresh transistor;

[0023] A first electrode of the third refresh transistor is electrically connected to the first level line, a second electrode of the third refresh transistor is electrically connected to the first electrode of the second refresh transistor and the refresh control line respectively, and a control electrode of the third refresh transistor is electrically connected to the signal node;

[0024] The second electrode of the second refresh transistor is electrically connected to the second level line, and the control electrode of the second refresh transistor is electrically connected to the signal node;

[0025] The second refresh transistor is configured to write the level signal of the second level line as a refresh enable signal into the refresh control line when the level of the signal node is a first preset level;

[0026] The third refresh transistor is configured to write the level signal of the first level line as a refresh prohibition signal into the refresh control line when the level of the signal node is a second preset level.

[0027] Optionally, the pixel unit includes a pixel driving circuit and a light-emitting device, the pixel driving circuit is used to provide a current driving signal to the light-emitting device; the pixel driving circuit includes a current control module, a current adjustment module, a refresh control module and a driving module; the refresh control module is electrically connected to the current control module, the current adjustment module and the driving module respectively; the current adjustment module is electrically connected to the driving module; and the current control module is electrically connected to a power line;

[0028] The refresh control module is used to determine whether to write pixel data of the current row into the pixel unit according to the refresh control signal;

[0029] The current adjustment module is used for writing the pixel data in the data writing phase when the refresh control module determines to write the pixel data of the current row into the pixel unit;

[0030] The current control module is used to maintain the pixel data of the driving module;

[0031] The driving module is used to output a current driving signal matching the pixel data to the light emitting device during a light emitting phase, so as to make the light emitting device emit light.

[0032] Optionally, the refresh control module includes a first transistor; a first electrode of the first transistor is electrically connected to the current control module and the driving module respectively; a second electrode of the first transistor is electrically connected to the current adjustment module; and a control electrode of the first transistor is electrically connected to a refresh control line;

[0033] The first transistor is used to turn on the current adjustment module, the current control module and the driving module when the refresh control line is at a level signal of the second level line, so that the pixel data of the current row at the current adjustment module is written into the current control module and the driving module;

[0034] The first transistor is further configured to disconnect the current adjustment module and the driving module when the refresh control line has a level signal of a first level line, so that the current control module retains pixel data of a previous row for the driving module.

[0035] Optionally, the current adjustment module includes a second transistor; a first electrode of the second transistor is electrically connected to the refresh control module, a first electrode of the second transistor is electrically connected to the driving module and the light-emitting device respectively, and a control electrode of the second transistor is electrically connected to a gate signal line;

[0036] The second transistor is used to conduct the refresh control module and the driving module when the gate signal line transmits a first level signal, so that the pixel data output by the driving module is written into the refresh control module;

[0037] The refresh control module writes the pixel data into the current control module.

[0038] According to a second aspect of the present disclosure, a display device is provided, comprising the array substrate according to any one of the first aspects.

[0039] The technical solutions provided by the embodiments of the present disclosure may have the following beneficial effects:

[0040] The array substrate provided in this embodiment includes a gate driving unit, a data driving unit, a refresh control unit, and pixel units distributed in rows and columns; the data driving unit is electrically connected to the refresh control unit, the gate driving unit is electrically connected to the refresh control unit, and the refresh control unit is electrically connected to the pixel units in the column; the gate driving unit is configured to output a write switch signal to the refresh control unit in response to a determination result of whether the pixel units in the column need to write pixel data of the current row before displaying each frame of image; the data driving unit is configured to output a preset level signal to the refresh control unit in response to a determination result of whether the pixel units in the column need to write pixel data of the current row before displaying each frame of image; the refresh control unit is configured to output a refresh control signal upon receiving the write switch signal and the preset level signal; the refresh control signal is configured to control the pixel units in the column to write pixel data of the current row; the data driving unit is configured to output the pixel data of the current row to the data line of the row when determining that the pixel units in the column need to write pixel data of the current row; and the pixel units are configured to drive the light-emitting devices to emit light when the pixel data of the current row is written. In this way, in this embodiment, the data driving unit outputs pixel data only when pixel data of the current row needs to be written, which can avoid repeated refreshing of pixel data and achieve the effect of reducing power consumption of the data driving unit.

[0041] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] Figure 1 This is a block diagram of an array substrate according to an embodiment of the present disclosure.

[0043] Figure 2 The present invention is a block diagram of a refresh control unit according to an embodiment of the present invention.

[0044] Figure 3 This is a circuit diagram of a refresh control unit according to an embodiment of the present disclosure.

[0045] Figure 4 This is a circuit diagram of another refresh control unit according to an embodiment of the present disclosure.

[0046] Figure 5 This is a block diagram of a pixel unit according to an embodiment of the present disclosure.

[0047] Figure 6 This is a circuit diagram of a pixel unit according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0048] Exemplary embodiments will be described in detail herein, examples of which are illustrated in the accompanying drawings. In the following description, when referring to the drawings, identical numerals in different figures represent identical or similar elements unless otherwise indicated. The embodiments described in the following exemplary embodiments are not intended to represent all embodiments consistent with the present disclosure. Rather, they are merely examples of devices consistent with certain aspects of the present disclosure, as detailed in the appended claims.

[0049] The present disclosure provides a display device, which may include but is not limited to mobile phones, computers, tablets, e-books, watches, three-dimensional display screens, all-in-one conference machines, electronic whiteboards and other devices with display functions. The display device includes an array substrate. The present disclosure provides an array substrate suitable for the above display device. Figure 1 FIG1 is a block diagram of an array substrate according to an embodiment of the present disclosure. Figure 1 The array substrate includes a data driving unit 10, a refresh control unit 20, a gate driving unit 40 and pixel units 30 arranged in a matrix.

[0050] The data driving unit 10 is electrically connected to the refresh control unit 20 , the gate driving unit 40 is electrically connected to the refresh control unit 20 , and the refresh control unit 20 is electrically connected to the pixel unit 30 in the column;

[0051] The gate driving unit 40 is configured to output a write switch signal to the refresh control unit 20 in response to a determination result of whether the pixel unit 30 in the column needs to write pixel data of the current row before displaying each frame of image;

[0052] The data driving unit 10 is configured to output a preset level signal to the refresh control unit 20 in response to a determination result of whether the pixel units in the column need to write the pixel data of the current row before displaying each frame of image;

[0053] The refresh control unit 20 is used to output a refresh control signal when receiving the write switch signal and the preset level signal; the refresh control signal is used to control the pixel unit 30 in the column to write the pixel data of the current row;

[0054] The data driving unit 10 is configured to output the pixel data of the current row to the data line Dm of the row when the pixel unit 30 in the column where the data driving unit 10 is located is determined to write the pixel data of the current row;

[0055] The pixel unit 30 is used to drive the light emitting device to emit light when the pixel data of the current row is written.

[0056] In one embodiment, see Figure 1The refresh control unit 20 is disposed in the non-display area of ​​the array substrate and close to the display area (Active Area, AA) of the array substrate. In other words, the refresh control unit 20 is disposed in the edge area of ​​the non-display area before the display area pixel units are disposed.

[0057] It should be noted that in this embodiment, the refresh control unit 20 controls each column of pixel units to achieve the effect of controlling the refreshing of pixel data for each column of pixel units. In some possible embodiments, the refresh control unit can control each pixel unit to achieve the effect of refreshing pixel data for a single pixel.

[0058] It should be noted that in this embodiment, the write switch signal GOA1 can be provided by the gate driver unit 40. This embodiment uses the write switch signal GOA1 to write a preset level signal indicating whether each column needs to refresh its pixel data before displaying an image. In other words, this embodiment is equivalent to adding a row of pixel cells before the first row of pixel cells. However, the pixel data in this row of pixel cells is used to indicate the result of determining whether the pixel data in that column should be refreshed, rather than to indicate the brightness of the light-emitting device. Furthermore, this row of pixel cells is located in the non-display area rather than the display area, which ensures the size of the display area.

[0059] In one embodiment, see Figure 2 The refresh control unit 20 includes a control signal writing module 21, a control signal holding module 22, and a control signal output module 23. The control signal writing module 21 is electrically connected to the data driving unit 10 and is electrically connected to the signal node N0; the control signal holding module 22 is electrically connected to the signal node N0 and the power line VDD respectively; the control signal output module 23 is electrically connected to the signal node N0, the first level line VGH, the second level line VGL, and the refresh control line Data_En respectively; the refresh control line Data_En is electrically connected to the pixel unit 30 in the column.

[0060] The control signal writing module 21 is configured to write a first preset level into the signal node N0 when the switch signal is a write-on signal and the preset level signal is a first preset level (eg, +7V).

[0061] The control signal holding module 22 is configured to hold the preset level signal of the signal node N0 .

[0062] The control signal output module 23 is used to electrically connect the second level line VGL and the refresh control line Data_En when the preset level is a first preset level number, so as to write the level signal of the second level line VGL as the refresh enable signal VData_En into the refresh control line Data_En.

[0063] In this embodiment, the control signal writing module 21 is further configured to write the second preset level to the signal node N0 when the switch signal is a write-on signal and the preset level signal is at a second preset level (e.g., -7V). At this time, the control signal holding module 22 is configured to maintain the second preset level at the signal node N0. The control signal output module 23 is configured to electrically connect the first level line VGH and the refresh control line Data_En when the preset level is the second preset level, so as to write the level signal of the first level line VGH as the refresh disable signal Vdisabled to the refresh control line Data_En.

[0064] In this embodiment, the control signal writing module 21 is further configured to prohibit writing the level signal of the data line Dm into the signal node N0 when the switch signal is a write-off signal, so as to ensure reliable operation of the refresh control unit 20 .

[0065] In one embodiment, see Figure 3 The control signal writing module 21 includes a first refresh transistor SWT1, a first electrode of the first refresh transistor SWT1 ( Figure 3 The upper electrode shown in FIG) is electrically connected to the data line Dm of the column, and the second electrode ( Figure 3 The lower electrode shown in the figure is electrically connected to the signal node N0, and the control electrode of the first refresh transistor SWT1 is electrically connected to the data driving unit 10 through the control line GOA1; the first refresh transistor SWT1 is used to write the preset level signal received by the data line Dm of the column to the signal node N0 when the write switch signal is a write-on signal.

[0066] It should be noted that the first refresh transistor SWT1 can be implemented using either a P-type transistor or an N-type transistor, depending on the actual situation. For ease of describing the solutions of each embodiment, the first refresh transistor SWT1 is implemented using an N-type transistor, that is, a high-level signal is used to control the N-type transistor to be turned on and a low-level signal is used to control the N-type transistor to be turned off.

[0067] In one embodiment, see Figure 3 The control signal holding module 22 includes a holding capacitor C1. The first electrode ( Figure 3 The upper electrode of C1 shown in FIG. 1 is electrically connected to the power supply line VDD. The second electrode of the holding capacitor C1 ( Figure 3 The lower electrode of capacitor C1 is electrically connected to signal node N0. Thus, when the voltage at the second electrode of capacitor C1 changes, the voltage at the first electrode of capacitor C1 remains unchanged, so the voltage difference between the two electrodes of capacitor C1 changes, thereby maintaining the signal at signal node N0.

[0068] In one embodiment, see Figure 3, the control signal output module 23 includes a second refresh transistor SWT2 and a third refresh transistor SWT3.

[0069] A first electrode of the third refresh transistor SWT3 is electrically connected to the first level line VGH, a second electrode of the third refresh transistor SWT3 is electrically connected to the first electrode of the second refresh transistor SWT2 and the refresh control line Data_En, and a control electrode of the third refresh transistor SWT3 is electrically connected to the signal node N0;

[0070] The second electrode of the second refresh transistor SWT2 is electrically connected to the second level line VGL, and the control electrode of the second refresh transistor SWT3 is electrically connected to the signal node N0;

[0071] The second refresh transistor SWT2 is used for writing the level signal of the second level line VGL as the refresh enable signal VData_En into the refresh control line Data_En when the level of the signal node N0 is a first preset level (such as +7V);

[0072] The third refresh transistor SWT3 is used for writing the level signal of the first level line VGH as the refresh disable signal Vdisabled into the refresh control line Data_En when the level of the signal node N0 is a second preset level (eg, −7V).

[0073] It should be noted that the second refresh transistor SWT2 can be implemented by a P-type transistor or an N-type transistor, and can be selected according to actual conditions. The third refresh transistor SWT3 can be implemented by a P-type transistor or an N-type transistor, and can be selected according to actual conditions. For the convenience of describing the solutions of each embodiment, the second refresh transistor SWT1 is implemented by an N-type transistor, that is, a high-level signal is used to control the N-type transistor to be turned on and a low-level signal is used to control the N-type transistor to be turned off. The third refresh transistor SWT3 is implemented by a P-type transistor, that is, a low-level signal is used to control the P-type transistor to be turned on and a high-level signal is used to control the P-type transistor to be turned off.

[0074] It should also be noted that the first level line and the second level line are used to provide signals of different levels. It is understood that the high-level signal and low-level signal described above refer to logic-level signals that can switch transistors in the pixel unit, respectively. The level signals output by the first level line and the second level line can be set according to the type of transistor controlled by the pixel unit. Considering that the controlled transistors of the pixel unit in subsequent embodiments are implemented using N-type transistors, the first level line VGH provides a high-level signal and the second level line VGL provides a low-level signal, for the convenience of describing the solution.

[0075] Based on the circuits of the control signal writing module 21, the control signal holding module 22 and the control signal output module 23, a circuit implementation of the refresh control unit can be obtained, such as Figure 4 See Figure 4 , the refresh control unit 20 is set in the AA area of ​​the array substrate.

[0076] In one example, the gate drive unit 40 can obtain pixel data of two adjacent rows (the current row and the previous row) of pixel units in each column and determine the differences and similarities in the pixel data. When the pixel data of two adjacent rows of pixel units in the same column are different, it can be determined that the pixel units in the current column need to be refreshed; when the pixel data of all pixel units in the same column are the same, it can be determined that the pixel units in the current row do not need to be refreshed, that is, maintaining the pixel data of the previous frame can ensure normal light emission of the light-emitting device, and the gate drive unit 40 can obtain the above judgment result.

[0077] In another example, the processor of the display device (such as AP) can obtain the pixel data of the pixel units in each column of the image to be displayed, and determine the differences and similarities of the pixel data. When it is determined that the pixel data of at least two pixel units in the same column of pixel units are different, it can be determined that the pixel units in the current column need to refresh the pixels; when it is determined that the pixel data of all pixel units in the same column of list units are the same, it can be determined that the pixel units in the current column do not need to refresh the pixel data, that is, maintaining the pixel data of the previous row can ensure that the light-emitting device emits light normally, that is, the processor can obtain the above judgment result. The data driving unit 10 can communicate with the processor to obtain the judgment result of whether the pixel units in the current column need to refresh the pixel data. The gate driving unit 40 can communicate with the processor to obtain the judgment result of whether the pixel units in the current column refresh the pixel data.

[0078] In this example, when the data driving unit 10 determines that the pixel unit of the current column needs to refresh the pixel data, the data driving unit 10 can output a first preset level (such as +7V), and the data driving unit 10 can output a write-on signal. At this time, the first refresh transistor SWT1 can be turned on and write the first preset level to the signal node N0. The first preset level can be maintained by the holding capacitor C1 for a preset time. The preset time can exceed the frame period. The frame period refers to the time required to scan the entire screen. Since the signal node N0 is at the first preset level, the second refresh transistor SWT2 is turned on at this time, thereby providing a low-level signal to the second level line VGL and outputting it to the pixel unit 30 in the column. The pixel unit 30 can refresh the pixel data, that is, maintain the current row pixel data to drive the light-emitting device to emit light.

[0079] In the example, when the data driving unit 10 determines that the pixel unit of the current column does not need to refresh the pixel data, the data driving unit 10 can output a second preset level (for example, -7V), and the data driving unit 10 can output a write-on signal, at this time, the first refresh transistor SWT1 can be turned on and write the second preset level to the signal node N0, and the second preset level can be maintained by the holding capacitor C1 for a preset time. Since the signal node N0 is at the second preset level, the third refresh transistor SWT3 is turned on at this time, so that the first level line VGH provides a high level signal output to the pixel unit 30 of the column, and the pixel unit 30 cannot refresh the pixel data, that is, the previous row of pixel data driving light emitting device emits light.

[0080] Referring to Figure 5 Each pixel unit 30 includes a light emitting device and a pixel driving circuit for driving the light emitting device to emit light. The pixel driving circuit is used to provide a current driving signal to the light emitting device to make the light emitting device emit light.

[0081] In an example, the structure of the light emitting device of the pixel unit includes a plurality of structures, such as OLED, quantum dot light emitting diode (QLED) or micro light emitting diode (Micro LED), etc., which can be selected and set according to actual needs, which is not limited here.

[0082] In another example, continuing to refer to Figure 5 The pixel driving circuit includes a refresh control module 51, a current adjustment module 52, a driving module 53 and a current control module 54. The refresh control module 51 is electrically connected with the current control module 54, the current adjustment module 52 and the driving module 53 respectively; the current adjustment module 52 is electrically connected with the driving module 53; the current control module 54 is electrically connected with the power line VDD. Among them,

[0083] The refresh control module 51 is used to determine whether to write the pixel data of the current row to the pixel unit according to the refresh control signal;

[0084] The current adjustment module 52 is used to write the pixel data in the data writing stage when the refresh control module 51 determines to write the pixel data of the current row to the pixel unit 30;

[0085] The current control module 54 is used to maintain the pixel data of the driving module 53;

[0086] The driving module 53 is used to output a current driving signal matched with the pixel data to the light emitting device D in the light emitting stage, so as to make the light emitting device D emit light.

[0087] In one embodiment, the refresh control module 51 includes a first transistor T1; a first electrode of the first transistor T1 is electrically connected to the current control module 54 and the driver module 53, respectively; a second electrode of the first transistor T1 is electrically connected to the current adjustment module 52; and a control electrode of the first transistor T1 is electrically connected to the refresh control line Data_En. The first transistor T1 is configured to conduct the current adjustment module 52, the current control module 54, and the driver module 53 when the refresh control line Data_En is at the level of the second level line VGL, so that the pixel data of the current row at the current adjustment module 52 is written into the current control module 54 and the driver module 53. The first transistor T1 is also configured to disconnect the current adjustment module 52 and the driver module 53 when the refresh control line Data_En is at the level of the first level line VGH, so that the current control module 54 retains the pixel data of the previous row for the driver module 53.

[0088] It should be noted that the first transistor T1 can be implemented by a P-type transistor or an N-type transistor, and the selection can be made according to actual conditions. In this example, the first transistor T1 is implemented by a PP-type transistor.

[0089] In one embodiment, the current adjustment module 52 includes a second transistor T2; the first electrode of the second transistor T2 is electrically connected to the refresh control module 51, the first electrode of the second transistor T2 is electrically connected to the driving module 53 and the light-emitting device D respectively, and the control electrode of the second transistor T2 is electrically connected to ( Figure 1 The second transistor T2 is used to turn on the refresh control module 51 and the driving module 53 when the gate signal line transmits a first level signal, so that the pixel data output by the driving module 53 is written to the refresh control module 51; the refresh control module 51 writes the pixel data to the current control module 54.

[0090] It should be noted that the circuit of the pixel unit 30 can be implemented using circuits such as 7T1C, 8T1C, 10T3C, 13T3C and 16T3C. When the current adjustment module 52 is present between the gate and drain of the driving transistor, the corresponding pixel unit circuit can be selected according to the specific scenario. In one example, the pixel unit 30 is implemented using an 8T1C pixel circuit, and combined with the above-mentioned refresh control unit 20, its circuit is as follows: Figure 6 shown.

[0091] It should be noted that the various transistors in the pixel drive circuit of the pixel unit using 8T1C can be implemented using P-type transistors or N-type transistors. In other words, the solution provided in this embodiment can be applied to the Pgate circuit (normally high) or to the Ngate circuit and EM GOA circuit (normally low), and can be selected according to actual conditions. For the convenience of describing the solutions of each embodiment, in the 8T1C pixel drive circuit of the present disclosure embodiment, except for the second transistor T2 which is implemented as an N-type transistor, the other transistors are implemented as P-type transistors, that is, a low-level signal is used to control the P-type transistor to be turned on and a high-level signal is used to control the P-type transistor to be turned off. In other words, each embodiment takes Pgate as an example.

[0092] Combine Figure 6 The circuit shown in FIG. 1 and the array substrate operation process may include:

[0093] (1) Before displaying each frame of image

[0094] The processor of the display device (such as AP) can obtain the pixel data of the pixel units in each column of the image to be displayed and determine the differences and similarities of the pixel data. When it is determined that the pixel data of at least two pixel units in the same column of pixel units are different, it can be determined that the pixel units in the current column need to refresh the pixels; when it is determined that the pixel data of all pixel units in the same column of list units are the same, it can be determined that the pixel units in the current column do not need to refresh the pixel data, that is, maintaining the pixel data of the previous row can ensure that the light-emitting device emits light normally. The data driving unit 10 can communicate with the processor to obtain the judgment result of whether the pixel units in the current column need to refresh the pixel data. The gate driving unit 40 also communicates with the processor to obtain the above judgment result.

[0095] In this example, when the gate driving unit 40 determines that the pixel units in the current column need to refresh pixel data, the gate driving unit 40 can output a write-on signal; when the data driving unit 10 determines that the pixel units in the current column need to refresh pixel data, it can output a first preset level (such as +7V).

[0096] At this point, the first refresh transistor SWT1 can be turned on and write a first preset level to the signal node N0. This first preset level can be maintained by the holding capacitor C1 for a preset time, which can exceed the frame period (the time required to scan the entire screen). Because the signal node N0 is at the first preset level, the second refresh transistor SWT2 is turned on, thereby providing a low-level signal to the second level line VGL and outputting it to the pixel unit 30 in the corresponding column. The pixel unit 30 can refresh the pixel data, that is, maintain the pixel data of the current row and drive the light-emitting device to emit light.

[0097] In this example, when the gate drive unit 40 determines that the pixel unit of the current column does not need to refresh the pixel data, the gate drive unit 40 can output a write-on signal; when the data drive unit 10 determines that the pixel unit of the current column needs to refresh the pixel data, it can output a second preset level (such as -7V). At this time, the first refresh transistor SWT1 can be turned on and write the second preset level to the signal node N0, and the second preset level can be maintained by the capacitor C1 for a preset time. Since the signal node N0 is at the second preset level, the third refresh transistor SWT3 is turned on at this time, thereby providing a high-level signal to the first level line VGH and outputting it to the pixel unit 30 in the column. The pixel unit 30 cannot refresh the pixel data, that is, it maintains the pixel data of the previous row to drive the light-emitting device to emit light.

[0098] (2) Display each frame of image

[0099] The pixel drive circuit controls a preset control timing, operating in various phases, including initialization, data writing, and light-emitting. The operation of each phase is similar to that of related art solutions, differing in that during the data writing phase, the data drive unit outputs pixel data to columns requiring refresh, while not outputting pixel data to columns requiring refresh. Because the number of columns for which the data drive unit outputs pixel data is reduced, power consumption of the data drive unit can be reduced.

[0100] For example, when watching a video, if there are borders, objects of the same color covering the entire screen, black and white stripes, etc. in the video, the pixel data for these repeated contents may not be refreshed, thereby reducing the power consumption of the data driving unit.

[0101] An embodiment of the present disclosure further provides a display device, comprising the above array substrate.

[0102] The terms used in this disclosure are for the purpose of describing specific embodiments only and are not intended to limit the disclosure. Unless otherwise defined, technical or scientific terms used in this disclosure should have the ordinary meaning understood by a person of ordinary skill in the art to which this disclosure belongs. The use of "a" or "an," and similar terms in this disclosure and the claims does not indicate a limitation of quantity, but rather indicates the presence of at least one. "Multiple" means at least two. "Include" or "comprising," and similar terms mean that the elements or objects preceding "include" or "comprise" include the elements or objects listed after "include" or "comprise," and their equivalents, and do not exclude other elements or objects. "Connected" or "connected," and similar terms are not limited to physical or mechanical connections and may include electrical connections, whether direct or indirect. As used in this disclosure and the appended claims, the singular forms "a," "the," and "the" are intended to include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the term "and / or" as used herein refers to and encompasses any and all possible combinations of one or more of the associated listed items.

[0103] As for the method embodiment, since it basically corresponds to the apparatus embodiment, the relevant parts can be referred to the partial description of the apparatus embodiment. The method embodiment and the apparatus embodiment complement each other.

[0104] The above description is only a preferred embodiment of the present disclosure and is not intended to limit the present disclosure. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present disclosure should be included in the scope of protection of the present disclosure.

Claims

1. An array substrate, characterized in that: It includes a gate driving unit, a data driving unit, a refresh control unit and pixel units distributed in columns; the data driving unit is electrically connected to the refresh control unit, the gate driving unit is electrically connected to the refresh control unit, and the refresh control unit is electrically connected to the pixel units in the column; The gate driving unit is configured to output a write switch signal to the refresh control unit in response to a determination result of whether the pixel units in the column need to write pixel data of the current row before displaying each frame of image; The data driving unit is configured to output a preset level signal to the refresh control unit in response to a determination result of whether the pixel units in the column need to write pixel data of the current row before displaying each frame of image; The refresh control unit is configured to output a refresh control signal when receiving the write switch signal and the preset level signal; The refresh control signal is used to control the pixel units in the column to write pixel data of the current row; The data driving unit is configured to output the pixel data of the current row to the data line of the row when it is determined that the pixel units in the column are writing the pixel data of the current row; The pixel unit is used to drive the light emitting device to emit light when writing pixel data of the current row.

2. The array substrate according to claim 1, wherein: The refresh control unit is disposed in the non-display area of ​​the array substrate and close to the display area of ​​the array substrate.

3. The array substrate according to claim 1, wherein: The refresh control unit includes a control signal writing module, a control signal holding module and a control signal output module; the control signal writing module is electrically connected to the gate driving unit and to the signal node; the control signal holding module is electrically connected to the signal node and the power line respectively; the control signal output module is electrically connected to the signal node, the first level line, the second level line and the refresh control line respectively; the refresh control line is electrically connected to the pixel unit in the column; The control signal writing module is configured to write the first preset level into the signal node when the switch signal is a write-on signal and the preset level signal is a first preset level; The control signal holding module is used to hold the preset level signal of the signal node; The control signal output module is used to electrically connect the second level line and the refresh control line when the preset level is a first preset level number, so as to write the level signal of the second level line as a refresh enable signal into the refresh control line.

4. The array substrate according to claim 3, wherein: The control signal writing module includes a first refresh transistor, wherein a first electrode of the first refresh transistor is electrically connected to the data line of the column, a second electrode of the first refresh transistor is electrically connected to the signal node, and a control electrode of the first refresh transistor is electrically connected to the gate driving unit; The first refresh transistor is configured to write a preset level signal received by the data line of the column to the signal node when the write switch signal is a write-on signal.

5. The array substrate according to claim 3, wherein: The control signal holding module includes a holding capacitor; a first electrode of the holding capacitor is electrically connected to the power line, and a second electrode of the holding capacitor is electrically connected to the signal node; The holding capacitor is used to hold the preset level signal of the signal node.

6. The array substrate according to claim 3, wherein: The control signal output module includes a second refresh transistor and a third refresh transistor; A first electrode of the third refresh transistor is electrically connected to the first level line, a second electrode of the third refresh transistor is electrically connected to the first electrode of the second refresh transistor and the refresh control line respectively, and a control electrode of the third refresh transistor is electrically connected to the signal node; The second electrode of the second refresh transistor is electrically connected to the second level line, and the control electrode of the second refresh transistor is electrically connected to the signal node; The second refresh transistor is configured to write the level signal of the second level line as a refresh enable signal into the refresh control line when the level of the signal node is a first preset level; The third refresh transistor is configured to write the level signal of the first level line as a refresh prohibition signal into the refresh control line when the level of the signal node is a second preset level.

7. The array substrate according to any one of claims 1 to 6, wherein: The pixel unit includes a pixel driving circuit and a light-emitting device, wherein the pixel driving circuit is used to provide a current driving signal to the light-emitting device; the pixel driving circuit includes a current control module, a current adjustment module, a refresh control module and a driving module; the refresh control module is electrically connected to the current control module, the current adjustment module and the driving module respectively; the current adjustment module is electrically connected to the driving module; and the current control module is electrically connected to a power line; The refresh control module is used to determine whether to write pixel data of the current row into the pixel unit according to the refresh control signal; The current adjustment module is used for writing the pixel data in the data writing phase when the refresh control module determines to write the pixel data of the current row into the pixel unit; The current control module is used to maintain the pixel data of the driving module; The driving module is used to output a current driving signal matching the pixel data to the light emitting device during a light emitting phase, so as to make the light emitting device emit light.

8. The array substrate according to claim 7, wherein: The refresh control module includes a first transistor; a first electrode of the first transistor is electrically connected to the current control module and the driving module respectively; a second electrode of the first transistor is electrically connected to the current adjustment module; and a control electrode of the first transistor is electrically connected to a refresh control line; The first transistor is used to turn on the current adjustment module, the current control module and the driving module when the refresh control line is at a level signal of the second level line, so that the pixel data of the current row at the current adjustment module is written into the current control module and the driving module; The first transistor is further configured to disconnect the current adjustment module and the driving module when the refresh control line has a level signal of a first level line, so that the current control module retains pixel data of a previous row for the driving module.

9. The array substrate according to claim 7, wherein: The current adjustment module includes a second transistor; a first electrode of the second transistor is electrically connected to the refresh control module, a first electrode of the second transistor is electrically connected to the driving module and the light-emitting device respectively, and a control electrode of the second transistor is electrically connected to the gate signal line; The second transistor is used to conduct the refresh control module and the driving module when the gate signal line transmits a first level signal, so that the pixel data output by the driving module is written into the refresh control module; The refresh control module writes the pixel data into the current control module.

10. A display device, characterized in that: The invention comprises the array substrate according to any one of claims 1 to 9.

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