Autonomous entry and exit of low-latency data paths in PCIE applications

Abstract

The present disclosure relates to autonomous entry and exit of a low-latency data path in PCIe applications. A PCIe retimer includes a read-only vendor register with low-latency mode entry and exit values. In-band low-latency switching logic monitors the output of the elastic buffer for vendor register read commands. When such a read command is received, it reads the corresponding address and switches a multiplexer between the link training data path and the low-latency data path based on the return value of the read operation. Control of the read command, and therefore the data path switch, is handled entirely in-band. The return value of the read operation indicates the success or failure of the mode switch to the root complex.

Description

Technical Field

[0001] Embodiments of the inventive concepts disclosed herein are generally directed to retimers, and more particularly, to PCIe retimers with in-band low-latency switching. Background Art

[0002] Where the Peripheral Component Interface Express (PCIe) bus is routed through a connector to a cable or printed circuit board (PCB) (i.e., a midplane or backplane layout), interconnect and PCB / cable variations create discontinuities, and those discontinuities react and increase intersymbol interference that degrades the PCIe signal. Without active circuitry, a receiver may be unable to read the degraded signal. The PCIe base specification allows for the implementation of up to two retimers (active circuitry that regenerates the PCIe signal) in series to extend the reach of the physical bus.

[0003] Retimers require a complete PCIe physical layer stack to fully participate in and manipulate the bits in ordered sets during link training. Incoming packets traversing the physical layer stack first traverse the receiver-side serial-to-parallel logic, descrambler, decoding, elastic buffers, alignment decoder, deskew buffers, and other receiver logic before traversing the transmitter-side encoding, scrambling, and parallel-to-serial logic. Existing PCIe retimers have a one-way delay in the range of 30 to 50 nanoseconds for traffic flowing through the retimer in each direction, for a round-trip delay in the range of 60 to 100 nanoseconds through a single retimer. In a system with two retimers, the round-trip delay can be as much as 120 to 200 nanoseconds. Some applications see performance degradation due to the increased latency. Summary of the Invention

[0004] In one aspect, embodiments of the inventive concepts disclosed herein are directed to a PCIe retimer with a read-only vendor register containing low-latency mode entry and exit values. In-band low-latency switching logic monitors the output of an elastic buffer for vendor register read commands. When such a read command is received, it reads the corresponding address and switches a multiplexer between the link training data path and the low-latency data path based on the return value of the read operation. Control of the read command, and therefore the datapath switching, is handled entirely in-band.

[0005] On the other hand, the return value of the read operation indicates the success or failure of the mode switch to the root complex.

[0006] It should be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and should not limit the scope of the claims. The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate exemplary embodiments of the inventive concepts disclosed herein and, together with the general description, serve to explain the principles. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Those skilled in the art may better understand the numerous advantages of the embodiments of the inventive concepts disclosed herein by referring to the accompanying drawings, in which:

[0008] Figure 1A A block diagram showing the retimer data path;

[0009] Figure 1B A perspective environmental view showing a PCIe retimer suitable for use with an exemplary embodiment;

[0010] Figure 2 Show link paths with 0, 1, or 2 retimers; and

[0011] Figure 3 A block diagram showing a retimer data path according to an exemplary embodiment of the present disclosure is shown. DETAILED DESCRIPTION

[0012] Before explaining in detail at least one embodiment of the inventive concepts disclosed herein, it should be understood that the inventive concepts should not be limited in their application to the construction details and arrangements of the components or steps or methodologies set forth in the following description or illustrated in the drawings. In the following detailed description of the embodiments of the inventive concepts, numerous specific details are set forth in order to provide a more detailed understanding of the inventive concepts. However, a person of ordinary skill in the art having the benefit of this disclosure will appreciate that the inventive concepts disclosed herein may be practiced without these specific details. In other examples, well-known features may not be described in detail to avoid unnecessarily complicating the disclosure. The inventive concepts disclosed herein are capable of other embodiments or can be practiced or implemented in various ways. Furthermore, it should be understood that the wording and terminology used herein are for descriptive purposes and should not be considered restrictive.

[0013] As used herein, a letter following a reference number is intended to reference an embodiment of a feature or element that may be similar, but not necessarily identical, to a previously described element or feature having the same reference number (e.g., 1, 1a, 1b). Such shorthand notation is used for convenience only and should not be construed as limiting the inventive concepts disclosed herein in any way unless expressly stated to the contrary.

[0014] Furthermore, unless expressly stated to the contrary, "or" refers to an inclusive or and not to an exclusive or. For example, condition A or B is satisfied by any of the following: A is true (or exists) and B is false (or does not exist), A is false (or does not exist) and B is true (or exists), and both A and B are true (or exist).

[0015] In addition, the use of "a" or "an" is used to describe elements and components of embodiments of the present inventive concept. This is done merely for convenience and to give a general sense of the inventive concept, and unless it is obvious that the meaning is to the contrary, "a" and "an" are intended to include one or at least one and the singular also includes the plural.

[0016] Also, while various components may be depicted as directly connected, such direct connection is not required. Components may be in data communication with intervening components not illustrated or described.

[0017] Finally, as used herein, any reference to "one embodiment" or "some embodiments" means that a particular element, feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the inventive concepts disclosed herein. The appearances of the phrase "in some embodiments" in various places in this specification are not necessarily all referring to the same embodiment, and embodiments of the disclosed inventive concepts may include one or more of the features expressly described or inherently present herein, or any combination or subcombination of two or more such features, as well as any other features that may not necessarily be expressly described or inherently present in this disclosure.

[0018] Broadly speaking, embodiments of the inventive concepts disclosed herein are directed to a PCIe retimer having in-band, read-only vendor registers with low-latency mode entry and exit values. In-band low-latency switching logic monitors the output of the elastic buffer for a vendor register read command and, when such a read command is received, reads the corresponding address and switches a multiplexer between a link training data path and a low-latency data path based on the return value of the read operation. The read command, and therefore the control of the data path switch, is handled entirely in-band. It should be understood that handling the data path switch in-band refers to the signal or data packet that initiates the switch between the link training data path and the low-latency data from within the link training data path. The return value of the read operation indicates the success or failure of the mode switch to the PCIe hierarchical elements of the root complex, the interfacing central processing unit (CPU), and the memory subsystem.

[0019] refer to Figure 1A and 1B, showing a block diagram of a retimer data path and an environmental view of the retimer. Existing retimers include a receiver 102 for receiving and transmitting data between two devices (e.g., a first component 122 and a second component 124, each having a PCIe interface) via a transmitter 118. Receiver 102 and transmitter 118 are coupled via a first data path for protocol-specific training (e.g., link training). Protocol-specific training enables transmitter 118 and receiver 102 to transmit data between the two devices according to the protocol of the link between them. Retimer 100 receives signals in both directions, extracts digital data components, and regenerates the signals as a separately trained link. As a result, noise and other artifacts, such as jitter, are eliminated.

[0020] Protocol-specific training includes link training and initialization. This link training includes executing an equalization program that generates transmitter equalization coefficients to control the equalization performed by the transmitter 118, such as, for example, cursor coefficients used to determine the level of de-emphasis and preshoot. Similarly, the equalization program generates receiver equalization coefficients for receive-side equalization in the form of continuous time linear equalization (CTLE) and decision feedback equalization (DFE).

[0021] During link training, signals from receiver 102 are converted to parallel data or bit registers via serial-to-parallel logic 104. Based on the protocol associated with the data, the parallel data may undergo bit alignment, decoding, and descrambling via aligner / decoder / descrambler 106. Furthermore, due to the speed at which the data is received, the data may need to be unscrambled. Furthermore, bits may need to be decoded; for example, the data may need to undergo 8b / 10b decoding or another type of decoding. Finally, aligner / decoder / descrambler 106 may align the data bits to determine when a symbol begins in the bit stream. In at least one embodiment, depending on the protocol, one or more functions of aligner / decoder / descrambler 106 may not be necessary. The resulting data is stored in elastic buffer 108.

[0022] Elastic buffer 108 can act as a drift buffer for protocols such as, for example, UPI, USB, Thunderbolt, and the like. Elastic buffer 108 compensates for bitstreams transmitted based on a clock that does not match the domain of transmitter 118. Data from elastic buffer 108 is sent to segment buffers 110 and at least one link training and status state machine (LTSSM) 112, each configured according to a known protocol. LTSSM 112 performs bitstream detection, ordered set generation, and bitstream modification associated with PCIe.

[0023] The LTSSM 112 is a state machine that defines link connectivity and link power management between the host and target devices. The training process includes checking and storing the power load capacity to determine what should and can be transmitted on each channel (handshaking). Once the handshake is complete, the host and target devices can freely send and receive information.

[0024] Data for transmission from LTSSM 112 and data from elastic buffer 108 are received by segmentation buffer 110, which outputs either LTSSM 112 data or elastic buffer 108 data depending on control signals. Data for transmission from segmentation buffer 110 undergoes scrambling and encoding via scrambler / encoder 114, as dictated by the protocol being used, and is converted to a serial format via parallel-to-serial logic 116. The serial data is output to transmitter 118. In at least one embodiment, LTSSM 112 may be stored in memory and implemented by a general-purpose processor.

[0025] The retimer 100 boosts the signal across the PCIe interconnect, but introduces significant latency. Multiple retimers 100 can exacerbate latency. Figure 2 , showing link paths with zero, one, or two retimers 204, 206. In a first configuration 212, upstream component 200 is directly connected to downstream component 202, with no added delay. However, if signal degradation from the interconnect requires it, a first retimer 204 can be inserted between upstream component 200 and downstream component 202 to regenerate the signal between the upstream component transmitter and the downstream component receiver, and vice versa. Additionally, in some configurations, a second retimer 206 can be inserted between the first retimer 204 and downstream component 202 to further extend the signal range via secondary signal regeneration.

[0026] Each signal regeneration introduces the same level of latency. Retimers 100, 204, 206 introduce latency due to the processing necessary to train during each signal regeneration. If processing steps can be bypassed after training for a particular protocol and upstream component 200 / downstream component 202 combination, latency can be reduced or substantially eliminated.

[0027] refer to Figure 3, shows a block diagram of the data path of a retimer 300 according to an exemplary embodiment of the present disclosure. During an initial training phase, such as when a first signal requiring regeneration is received, the signal from receiver 302 is converted via serial-to-parallel logic 304; bits are aligned, decoded, and descrambled via aligner / decoder / descrambler 306; and the resulting data is stored in elastic buffer 308. Data from elastic buffer 308 is sent to segmentation buffer 310 and at least one LTSSM 312. Data for transmission from LTSSM 312 and data from elastic buffer 308 are received by segmentation buffer 310, which outputs either LTSSM 312 data or elastic buffer 308 data for scrambling and encoding via scrambler / encoder 314 and conversion to serial format via parallel-to-serial logic 316. The serial data is output to transmitter 318.

[0028] Once initial link training is complete, in-band low-latency switching logic 320 controls the switching of multiplexer 322. Multiplexer 322 switches the data flow to low-latency data path 324, which bypasses any training components and sends the data directly to transmitter 318. In at least one embodiment, in-band low-latency switching logic 320 includes a vendor register configured with a bit that is configured to signal in-band low-latency switching logic 320 to switch multiplexer 322 to low-latency data path 324, thereby bypassing link training elements and corresponding delays.

[0029] In the current embodiment, the retimer registers are 8 bits wide and are accessed via 8-bit addresses. The PCIe Base Specification reserves addresses between 0xA0 and 0xFF for vendor-defined functions. In at least one embodiment, a lane margin read command (a PCIe specification command for reading information from the receiver 302) can be targeted to the upstream Rx port of the first retimer or the upstream Rx port of the second retimer, respectively (see FIG. Figure 2 ). However, there are no channel margin commands for retimer register writes. The vendor registers are therefore read-only and cannot support write operations to set the low latency bit register. Embodiments of the present disclosure allow in-band switching between full and low latency data paths without having to write or overwrite registry entries to record the current state. It should be understood that "in-band" switching refers to switching signals received in the data stream from receiver 302 without external control signals.

[0030] In-band low-latency switching logic 320 is configured to identify data in the signal received from elastic buffer 308 indicating that low-latency data path 324 is appropriate. In-band low-latency switching logic 320 then reads the vendor register that returns a read-only bit value and, using the returned value, sets multiplexer 322 to low-latency data path 324. Low-latency data path 324 then passes all signals from receiver 302 directly to transmitter 318 until multiplexer 322 is switched.

[0031] All signals are still processed through the training logic while the signals continue to utilize the low latency data path 324. As each signal reaches the elastic buffer 308, the in-band low latency switching logic 320 is configured to recognize data indicating that new link training is necessary.

[0032] In at least one embodiment, the in-band low-latency switching logic 320 includes a second vendor register that indicates that the low-latency data path 324 is inappropriate. The in-band low-latency switching logic 320 then reads the return read-only bit value to set the multiplexer 322 to the second vendor register of the standard link training data path. While the multiplexer 322 is in low-latency mode, the in-band low-latency switching logic 320 continuously monitors the data stream (e.g., via the elastic buffer 308) for a read vendor address signal. Upon identifying this read vendor address signal, the in-band low-latency switching logic 320 reads the second vendor address and applies a signal to the multiplexer 322, thereby switching the multiplexer 322 to the standard data path.

[0033] In-band low-latency switching logic 320 can be embodied in solid-state logic or implemented as a general-purpose processor configured to read data from elastic buffer 308. Elastic buffer 308 may contain data from a stream that would otherwise be discarded for link training purposes, but when read by in-band low-latency switching logic 320, triggers a read of a vendor register. The return code from the read operation instructs multiplexer 322 to switch between the standard data path and the low-latency data path 324. For example, PCIe includes functionality including commands such as "Access Retimer Registers," which allow in-band read-only access to internal retimer registers. Upon receiving this read command, in-band low-latency switching logic 320 reads the indicated read-only registers and uses the read value to set multiplexer 322 to both the standard data path and the low-latency data path 324. PCIe components can thereby instruct the retimer 300 to enter the low-latency data path 324 without requiring any out-of-band control signals.

[0034] In at least one embodiment, two read-only virtual registers are defined in the retimer vendor address space: Low Latency Mode Set (LLM_SET) and Low Latency Mode Clear (LLM_CLR). These virtual registers are used to set and clear the physical low-latency mode register bits in the in-band low-latency switching logic 320, which controls the multiplexer 322 via read side effects. When the root complex issues a lane margin read of LLM_SET, the in-band low-latency switching logic 320 sets a bit to instruct the multiplexer 322 to enter low-latency mode and returns 0x01 in the read data to indicate a successful request. Reporting successful or unsuccessful completion to the root complex is important to allow the root complex to manage the PCIe hierarchy and, if necessary, issue subsequent switching commands to the retimer 300. When the root complex issues a lane margin read of LLM_CLR, the in-band low-latency switching logic 320 clears the bit to instruct the multiplexer 322 to exit low-latency mode and returns 0x00 in the read data. In at least one embodiment, the in-band low latency switching logic 320 includes a set of registers, each defined by the same register address as the corresponding vendor register address (ie, overloaded). The overloaded vendor registers may be writable, while the legacy vendor registers are not.

[0035] In at least one embodiment, an upstream component (e.g. Figure 2 The upstream component 200 in the 300) inserts a data packet or other such signal (low latency mode entry signal) into the stream via the receiver 302 to request a switch between the standard data path and the low latency data path 324. A return code generated by the in-band low latency switch logic 320 may be reported to the root complex to indicate the success or failure of such a switch. In at least one embodiment, the dual timer configuration ( Figure 2 These in-band requests and responses are made by two retimers 300 (retimers 204, 206 in FIG).

[0036] In at least one embodiment, the low-latency data path 324 may be used during a common clock mode of operation, and the legacy data path may be used during a non-common clock mode of operation and during training.

[0037] In at least one embodiment, downstream components (e.g. Figure 2 The downstream component 202 in the IO can identify or report a threshold latency tolerance specific to the downstream component. The upstream component and the in-band low-latency switching logic 320 can prioritize the low-latency data path 324 based on this threshold.

[0038] From the out-of-band backend bus perspective, low latency mode is controlled by registers that are read / writeable and allow the external host to directly enter and exit low latency mode.

[0039] Embodiments of the present disclosure implement heretofore unknown improvements to the operation of devices that include PCIe retimers. Such devices include computing devices with PCIe-based graphics cards, solid-state drives, cards implementing Redundant Array of Independent Disks (RAID), Wi-Fi cards, and any other primary or peripheral component that utilizes PCIe.

[0040] It is believed that the inventive concepts disclosed herein and many of their attendant advantages will be understood through the foregoing description of the embodiments of the disclosed inventive concepts, and it will be apparent that various changes can be made in the form, construction, and arrangement of its components without departing from the broad scope of the inventive concepts disclosed herein or sacrificing all of its material advantages; and that individual features from various embodiments can be combined to obtain other embodiments. The forms previously described herein are merely illustrative embodiments thereof, and the appended claims are intended to cover and encompass such variations. In addition, any of the features disclosed with respect to any of the individual embodiments may be incorporated into any other embodiment.

Claims

1. A PCIe retimer, comprising: elastic buffer; Link training and status state machine; Multiplexer; and a switching logic for performing data communication with the elastic buffer and the multiplexer, the switching logic comprising: a first register configured with a first bit value; a second register configured with a second bit value; and Processing logic configured to: identifying a read signal from the elastic buffer, the read signal configured to instruct the switching logic to read one of the first register or the second register; reading the register indicated by the read signal; and applying a signal corresponding to the first bit value or the second bit value to the multiplexer depending on which of the first register or the second register is read, in: The first bit value places the multiplexer in a configuration that utilizes the link training and status state machine; and The second bit value places the multiplexer in a configuration that bypasses the link training and status state machine, Wherein the PCIe retimer is configured to receive a first signal and enhance the first signal by regenerating the first signal into a second signal.

2. The PCIe retimer of claim 1 , wherein the switching logic further comprises: a first overload register having a register address corresponding to the first register; and A second overload register has a register address corresponding to the second register.

3. The PCIe retimer of claim 1 , wherein the processing logic is further configured to: receiving a signal from an upstream component instructing the PCIe retimer to enter a low latency mode; and The elastic buffer is populated with the received signal to instruct the switching logic to place the multiplexer in the configuration that bypasses the link training and status state machine. 4 . The PCIe retimer of claim 3 , wherein the received signal comprises a lane margin read command.

5. The PCIe retimer of claim 1 , wherein the processing logic is further configured to pass a return code back to a root complex based on success or failure of applying the signal to the multiplexer.

6. The PCIe retimer of claim 1 , wherein the processing logic is further configured to: continuously monitoring the elastic buffer for a read signal when the multiplexer is in a low latency mode; identifying a read signal configured to instruct the switching logic to read the first register; and applying a signal corresponding to the first bit value to the multiplexer, Therein the read signal is delivered entirely in-band.

7. The PCIe retimer of claim 1 , wherein the signal to the multiplexer includes a read value returned when a vendor address corresponding to a vendor address signal is read.

8. A PCIe device comprising a retimer configured to receive a first signal and enhance the first signal by regenerating the first signal into a second signal, the retimer comprising: Receiver; transmitter; and PCIe retimer, which includes: elastic buffer; Link training and status state machine; multiplexers; and a switching logic for performing data communication with the elastic buffer and the multiplexer, the switching logic comprising: a first register configured with a first bit value; a second register configured with a second bit value; and Processing logic configured to: receiving a low-latency mode entry / exit signal via the receiver; filling the elastic buffer with the low latency mode entry / exit signal; identifying a low-latency mode entry / exit signal from the elastic buffer, the low-latency mode entry / exit signal configured to instruct the switching logic to read one of the first register or the second register; reading a register indicated by the low-latency mode entry / exit signal; applying a signal corresponding to the first bit value or the second bit value to the multiplexer based on the low latency mode entry / exit, in: The first bit value places the multiplexer in a configuration that utilizes the link training and status state machine; and The second bit value places the multiplexer in a configuration that utilizes a low-latency data path linking the receiver directly to the transmitter.

9. The PCIe device of claim 8, wherein the switching logic further comprises: a first overload register having a register address corresponding to the first register; and A second overload register has a register address corresponding to the second register.

10. The PCIe device of claim 8, wherein the low-latency mode entry / exit signal comprises a lane margin read command.

11. The PCIe device of claim 8, wherein the processing logic is further configured to pass a return code back to a root complex based on a success or failure of applying the signal to the multiplexer.

12. The PCIe device of claim 8, wherein the processing logic is further configured to: When the multiplexer is in a low-latency mode, continuously monitoring the elastic buffer for a low-latency mode entry / exit signal; identifying a low latency mode entry / exit signal corresponding to the first register; and applying a signal corresponding to the first bit value to the multiplexer, Wherein the low latency mode entry / exit signal is delivered entirely in-band.

13. The PCIe device of claim 8, wherein the signal to the multiplexer includes a read value returned when a vendor address corresponding to a vendor address signal is read.

14. A system comprising: A first device comprising a PCIe interface; a second device comprising a PCIe interface; and a PCIe retimer electronically interposed between the first device and the second device, the PCIe retimer configured to receive a first signal from the first device and enhance the first signal by regenerating the first signal into a second signal, the second signal being output to the second device, the PCIe retimer comprising: elastic buffer; Link training and status state machine; multiplexers; and a switching logic for performing data communication with the elastic buffer and the multiplexer, the switching logic comprising: a first register configured with a first bit value; a second register configured with a second bit value; and Processing logic configured to: identifying a read signal from the elastic buffer, the read signal configured to instruct the switching logic to read one of the first register or a second vendor address; Reading the register indicated by the read signal; applying a signal corresponding to the first bit value or the second bit value to the multiplexer based on the read signal, in: The first bit value places the multiplexer in a configuration that utilizes the link training and status state machine; and The second bit value places the multiplexer in a configuration that bypasses the link training and status state machine.

15. The system of claim 14, wherein the switching logic further comprises: a first overload register address corresponding to the first register; and A second overload register address corresponding to the second register.

16. The system of claim 14, wherein the processing logic is further configured to: receiving a signal from the first device instructing the PCIe retimer to enter a low latency mode; and The elastic buffer is filled with the received signal. The system of claim 16 , wherein the low latency mode entry signal comprises a channel margin read command.

18. The system of claim 14, wherein the processing logic is further configured to pass a return code back to a root complex based on a success or failure of applying the signal to the multiplexer.

19. The system of claim 14, wherein the processing logic is further configured to: continuously monitoring the elastic buffer for a read signal when the multiplexer is in a low latency mode; identifying a read signal corresponding to the first register; and applying a signal corresponding to the first bit value to the multiplexer, Therein the read signal is delivered entirely in-band.

20. The system of claim 14, wherein the signal to the multiplexer comprises a read value returned when the register address corresponding to the read signal is read.

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