Logical arrangement prediction model training method, logical arrangement method and device

Abstract

The application relates to a logic arrangement prediction model training method, a logic arrangement method and device, computer equipment, a storage medium and a computer program product, and relates to the technical field of computers and can be used in the field of financial technology and other related fields. The method comprises the following steps: constructing a syntax tree of a sample logic for each sample logic in a low-code platform; determining a logic sequence vector of the sample logic based on the syntax tree; performing sliding window processing on the logic sequence vector to obtain at least one logic sequence subvector of the sample logic; confirming a component corresponding to a next vector element of the logic sequence subvector in the logic sequence vector as a target component of the logic sequence subvector; and training a logic arrangement prediction model to be trained by taking the logic sequence subvector as input information and taking the target component of the logic sequence subvector as supervision information, so as to obtain a trained logic arrangement prediction model. The method can improve the logic arrangement efficiency in the low-code platform.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of computers, and in particular to a logic arrangement prediction model training method, a logic arrangement method, a device, a computer device, a storage medium, and a computer program product. BACKGROUND

[0002] Low code is a visual application development method; logic arrangement is a business function development method under low code, for example, a developer arranges visual graphical components in order to form logic with certain business functions, and realizes corresponding business functions by means of the logic.

[0003] However, in the logic arrangement process based on low code, it is still necessary to rely on the subjective selection of the developer on the visual graphical components, which easily leads to the fact that non-professional developers are difficult to concentrate on creative programming activities, thereby making the efficiency of logic arrangement in the low code platform lower. SUMMARY

[0004] Therefore, it is necessary to provide a logic arrangement prediction model training method, a logic arrangement method, a device, a computer device, a computer readable storage medium, and a computer program product, which can improve the efficiency of logic arrangement in a low code platform.

[0005] In a first aspect, the present application provides a logic arrangement prediction model training method. The method comprises:

[0006] For each sample logic in the low code platform, a syntax tree of the sample logic is constructed; each node in the syntax tree corresponds to each variable that constitutes the sample logic, and the variable is an instantiation object of a component;

[0007] Based on the syntax tree, a logic sequence vector of the sample logic is determined; one vector element in the logic sequence vector corresponds to one variable that constitutes the sample logic;

[0008] The logic sequence vector is subjected to sliding window processing to obtain at least one logic sequence sub-vector of the sample logic;

[0009] The component corresponding to the next vector element of the logic sequence sub-vector in the logic sequence vector is confirmed as the target component of the logic sequence sub-vector;

[0010] The logic sequence sub-vector is taken as input information, and the target component of the logic sequence sub-vector is taken as supervision information, and a logic arrangement prediction model to be trained is trained to obtain a trained logic arrangement prediction model.

[0011] In one of the embodiments, the determining, based on the syntax tree, a logic sequence vector of the sample logic comprises:

[0012] determining, based on the syntax tree, component type features, component identification features, and component nesting features of each node in the syntax tree; the component nesting features are used to represent the nesting relationship between components;

[0013] determining a node type of each node in the syntax tree according to the component nesting features;

[0014] performing word vector mapping processing on the component type features, the component identification features, and the component nesting features of each node in the syntax tree according to the node type, to obtain the logic sequence vector of the sample logic.

[0015] In one of the embodiments, the performing word vector mapping processing on the component type features, the component identification features, and the component nesting features of each node in the syntax tree according to the node type comprises:

[0016] in the case that the node is a first node without nested child nodes, performing word vector mapping processing on the component type features, the component identification features, and the component nesting features of the first node respectively, to obtain a component type feature vector, a component identification feature vector, and a component nesting feature vector of the first node;

[0017] in the case that the node is a second node with nested child nodes, performing word vector mapping processing on the component type features and the component identification features of the second node respectively, to obtain a component type feature vector and a component identification feature vector of the second node, and performing word vector mapping processing on the component nesting features of the second node based on the nested child nodes of the second node, to obtain a component nesting feature vector of the second node.

[0018] In one of the embodiments, the training, by taking the logic sequence sub-vector as input information and taking the target component of the logic sequence sub-vector as supervision information, a to-be-trained logical arrangement prediction model to obtain a trained logical arrangement prediction model comprises:

[0019] extracting features of the logic sequence sub-vector by a long short-term memory artificial neural network in the to-be-trained logical arrangement prediction model, to obtain a target vector corresponding to the logic sequence sub-vector;

[0020] classifying the target vector by an attention mechanism network in the to-be-trained logical arrangement prediction model, to obtain a predicted component corresponding to the logic sequence sub-vector;

[0021] Train the to-be-trained logical arrangement prediction model based on the difference information between the prediction component and the target component, to obtain the trained logical arrangement prediction model.

[0022] In one of the embodiments, the attention mechanism network in the to-be-trained logical arrangement prediction model is obtained by the following way:

[0023] Obtain the context feature vector of each variable in the low-code platform that constitutes each sample logic;

[0024] Obtain the attention mechanism network in the to-be-trained logical arrangement prediction model based on the context feature vector of each variable.

[0025] In one of the embodiments, the obtaining the context feature vector of each variable in the low-code platform that constitutes each sample logic comprises:

[0026] For each variable, determine the current position of the variable in the syntax tree of the corresponding sample logic;

[0027] Based on the current position, determine the variable frequency feature and the variable distance feature of the variable; the variable frequency feature is used to represent the number of times the variable appears before the current position in the syntax tree; the variable distance feature is used to represent the distance between the current position and the last position where the variable appears in the syntax tree;

[0028] Based on the variable frequency feature and the variable distance feature of the variable, obtain the context feature vector of the variable.

[0029] In a second aspect, the present application also provides a logical arrangement method. The method comprises:

[0030] Identify a to-be-predicted node in a logical arrangement interface, and determine a target logic to which the to-be-predicted node belongs;

[0031] Based on the target logic, determine a logical sequence sub-vector corresponding to the to-be-predicted node;

[0032] Input the logical sequence sub-vector corresponding to the to-be-predicted node into the trained logical arrangement prediction model, to obtain at least one predicted component associated with the to-be-predicted node, and the association degree between each predicted component and the to-be-predicted node; the trained logical arrangement prediction model is the trained logical arrangement prediction model in the logical arrangement prediction model training method;

[0033] According to the association degree, display the at least one predicted component in the logical arrangement interface, and arrange the target logic based on the at least one predicted component.

[0034] In one embodiment, the determining of the logic sequence sub-vector corresponding to the to-be-predicted node based on the target logic comprises:

[0035] constructing a syntax tree of the target logic based on the target logic;

[0036] determining a logic sequence vector of the target logic according to the component type feature, the component identifier feature and the component nesting feature of each node in the syntax tree of the target logic;

[0037] extracting, as the logic sequence sub-vector corresponding to the to-be-predicted node, a sub-vector with a preset length corresponding to a last element of the logic sequence sub-vector corresponding to the to-be-predicted node in the logic sequence vector of the target logic, the last element being a vector element of a previous node of the to-be-predicted node in the logic sequence vector of the target logic.

[0038] In a third aspect, the present application also provides a logic arrangement prediction model training device. The device comprises:

[0039] a syntax construction module configured to construct a syntax tree of each sample logic in a low-code platform; each node in the syntax tree corresponds to a variable constituting the sample logic, and the variable is an instantiation object of a component;

[0040] a sequence determination module configured to determine a logic sequence vector of the sample logic based on the syntax tree; one vector element in the logic sequence vector corresponds to one variable constituting the sample logic;

[0041] a sliding window processing module configured to perform sliding window processing on the logic sequence vector to obtain at least one logic sequence sub-vector of the sample logic;

[0042] a component determination module configured to confirm a component corresponding to a next vector element of the logic sequence sub-vector in the logic sequence vector as a target component of the logic sequence sub-vector;

[0043] a model training module configured to train a to-be-trained logic arrangement prediction model by taking the logic sequence sub-vector as input information and taking the target component of the logic sequence sub-vector as supervision information, to obtain a trained logic arrangement prediction model.

[0044] In a fourth aspect, the present application also provides a logic arrangement device. The device comprises:

[0045] a logic determination module configured to identify a to-be-predicted node in a logic arrangement interface and determine a target logic to which the to-be-predicted node belongs;

[0046] a vector determination module configured to determine a logical sequence sub-vector corresponding to the to-be-predicted node based on the target logic;

[0047] a component prediction module configured to input the logical sequence sub-vector corresponding to the to-be-predicted node into a trained logical arrangement prediction model to obtain at least one predicted component associated with the to-be-predicted node and an association degree between each predicted component and the to-be-predicted node; the trained logical arrangement prediction model is the trained logical arrangement prediction model in the logical arrangement prediction model training method;

[0048] a logical arrangement module configured to display the at least one predicted component in the logical arrangement interface according to the association degree and arrange the target logic based on the at least one predicted component.

[0049] In a fifth aspect, the present application further provides a computer device. The computer device includes a memory and a processor, the memory stores a computer program, and the processor implements the following steps when executing the computer program:

[0050] constructing a syntax tree of each sample logic in the low-code platform; each node in the syntax tree corresponds to a variable of the sample logic, and the variable is an instantiation object of a component;

[0051] determining a logical sequence vector of the sample logic based on the syntax tree; one vector element in the logical sequence vector corresponds to one variable of the sample logic;

[0052] performing sliding window processing on the logical sequence vector to obtain at least one logical sequence sub-vector of the sample logic;

[0053] confirming a component corresponding to a next vector element of the logical sequence sub-vector in the logical sequence vector as a target component of the logical sequence sub-vector;

[0054] training a to-be-trained logical arrangement prediction model by taking the logical sequence sub-vector as input information and the target component of the logical sequence sub-vector as supervision information, to obtain a trained logical arrangement prediction model.

[0055] In a sixth aspect, the present application further provides a computer readable storage medium. The computer readable storage medium stores a computer program, and the computer program is executed by a processor to implement the following steps:

[0056] constructing a syntax tree of each sample logic in the low-code platform; each node in the syntax tree corresponds to a variable of the sample logic, and the variable is an instantiation object of a component;

[0057] determining a logic sequence vector of the sample logic based on the syntax tree; one vector element in the logic sequence vector corresponds to a variable constituting the sample logic;

[0058] performing sliding window processing on the logic sequence vector to obtain at least one logic sequence sub-vector of the sample logic;

[0059] confirming, as a target component of the logic sequence sub-vector, a component corresponding to a next vector element in the logic sequence vector of the logic sequence sub-vector;

[0060] training a logic arrangement prediction model to be trained by taking the logic sequence sub-vector as input information and the target component of the logic sequence sub-vector as supervision information, to obtain a trained logic arrangement prediction model.

[0061] In a seventh aspect, the present application also provides a computer program product. The computer program product comprises a computer program which, when executed by a processor, implements the following steps:

[0062] constructing a syntax tree of each sample logic in the low-code platform; each node in the syntax tree corresponds to a variable constituting the sample logic, and the variable is an instantiation object of a component;

[0063] determining a logic sequence vector of the sample logic based on the syntax tree; one vector element in the logic sequence vector corresponds to a variable constituting the sample logic;

[0064] performing sliding window processing on the logic sequence vector to obtain at least one logic sequence sub-vector of the sample logic;

[0065] confirming, as a target component of the logic sequence sub-vector, a component corresponding to a next vector element in the logic sequence vector of the logic sequence sub-vector;

[0066] training a logic arrangement prediction model to be trained by taking the logic sequence sub-vector as input information and the target component of the logic sequence sub-vector as supervision information, to obtain a trained logic arrangement prediction model.

[0067] The aforementioned logic orchestration prediction model training, logic orchestration method, device, computer equipment, storage medium, and computer program product first construct a syntax tree for each sample logic in the low-code platform; each node in the syntax tree corresponds to a variable that makes up the sample logic, and the variable is an instantiated object of the component; then, based on the syntax tree, the logic sequence vector of the sample logic is determined; one vector element in the logic sequence vector corresponds to a variable that makes up the sample logic; next, the logic sequence vector is processed by sliding window to obtain at least one logic sequence sub-vector of the sample logic; then, the component corresponding to the next vector element in the logic sequence vector is identified as the target component of the logic sequence sub-vector; finally, the logic orchestration prediction model to be trained is trained using the logic sequence sub-vector as input information and the target component of the logic sequence sub-vector as supervision information, to obtain the trained logic orchestration prediction model. In this way, the syntax tree built based on the sample logic in the low-code platform can obtain the logic sequence vector of the sample logic. Then, through sliding window processing of the logic sequence vector, at least one logic sequence sub-vector of the sample logic can be obtained. Thus, the logic orchestration prediction model to be trained can be supervised and trained using the logic sub-sequence vector as input information and the target component of the logic sub-sequence vector as supervision information. This results in a trained logic orchestration prediction model that can predict the next component to be inserted based on the preceding information in the logic being orchestrated. The logic orchestration prediction model training method based on the above process can free developers from the tedious selection of visual graphical components, allowing them to better focus their energy on creative programming activities, thereby improving the efficiency of logic orchestration in the low-code platform. Attached Figure Description

[0068] Figure 1 This is a flowchart illustrating the training method for a logic orchestration prediction model in one embodiment;

[0069] Figure 2 This is a schematic diagram of the syntax tree for sample logic in one embodiment;

[0070] Figure 3 This is a flowchart illustrating the steps of determining the logical sequence vector of sample logic based on a syntax tree in one embodiment.

[0071] Figure 4 This is a flowchart illustrating the steps of training a logic orchestration prediction model to be trained, as shown in one embodiment, to obtain a trained logic orchestration prediction model.

[0072] Figure 5 This is a schematic diagram of the structure of a logic orchestration prediction model to be trained in one embodiment;

[0073] Figure 6A flowchart of a logic arrangement prediction model training method in another embodiment;

[0074] Figure 7 A flowchart of a logic arrangement method in an embodiment;

[0075] Figure 8 A schematic diagram of a low-code logic arrangement intelligent assistance method based on a visual language in an embodiment;

[0076] Figure 9 A structural block diagram of a logic arrangement prediction model training device in an embodiment;

[0077] Figure 10 A structural block diagram of a logic arrangement device in an embodiment;

[0078] Figure 11 An internal structure diagram of a computer device in an embodiment. DETAILED DESCRIPTION

[0079] In order to make the purposes, technical solutions and advantages of the present application clearer, the present application will be further described in detail below with reference to the drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and not to limit the present application.

[0080] It should be noted that the user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data for analysis, stored data, displayed data, etc.) involved in the present application are all information and data authorized by the user or authorized by all parties, and the collection, use and processing of related data need to comply with relevant laws, regulations and standards of relevant countries and regions.

[0081] It should also be noted that the logic arrangement prediction model training method, logic arrangement method, device, computer device, storage medium and computer program product provided by the present application can be applied in the field of financial technology, such as assisting the developers of banks to develop and apply the business systems of banks; it can also be applied in other related fields, such as in the field of computer technology, through the logic arrangement prediction model training method and the logic arrangement method provided by the present application, intelligent component recommendation in the low-code development process for non-professional developers is realized.

[0082] In an exemplary embodiment, as Figure 1As shown, a logical arrangement prediction model training method is provided, and the embodiment takes the method applied to a server as an example; it can be understood that the method can also be applied to a terminal, and can also be applied to a system including a server and a terminal, and is realized through interaction between the server and the terminal. The server can be realized by an independent server or a server cluster composed of multiple servers; the terminal can be, but is not limited to, various personal computers, notebook computers, smart phones and tablet computers. In the embodiment, the method includes the following steps:

[0083] In step S102, a syntax tree of each sample logic in the low-code platform is constructed.

[0084] In the field of code development, logic refers to a set of processes that can achieve corresponding functions; in the low-code platform, a logic will eventually be converted into a function in the code to achieve the corresponding function.

[0085] In the low-code platform, a logic is composed of multiple variables, and each variable is an instantiation object of a component; a component is an abstraction of multiple variables with common characteristics, and the relationship between the component and the variable can be understood as the relationship between the class and the object in the object-oriented language.

[0086] It can be understood that in the visual application development low-code platform, the developer can realize the arrangement of logic by dragging the visual graphical component.

[0087] The sample logic refers to the standard logic provided by the low-code platform, and can also include custom logic created by the developer and historical logic created by the developer.

[0088] Each node in the syntax tree corresponds to each variable that constitutes the sample logic.

[0089] Specifically, the server constructs the syntax tree of each sample logic in the low-code platform according to the component characteristics corresponding to each variable that constitutes the sample logic and the nesting relationship between the components to which each variable belongs.

[0090] For example, the low-code platform arrangement logic provides more than 30 components including logic components, arithmetic operation components, comparison operation components and the like for the developer, each component is described by component type characteristics, component identification characteristics and component nesting characteristics; wherein the component type characteristics are used to represent the type of the component in the six categories, the component identification characteristics are used to represent the identification of the component in the more than 30 components, and the component nesting characteristics are used to represent the nesting relationship between the components. For example, Figure 2A schematic diagram of the syntax tree of the sample logic, wherein the component corresponding to the first variable is the assignment component in the logic component, and the two nested variables are the variable component in the system component and the data query component in the logic component, respectively, the variable corresponding to the variable component is not further nested with other variables, and the variable corresponding to the data query component is further nested with other variables. It can be understood that, Figure 2 Only a part of the syntax tree of the sample logic is shown.

[0091] It should be noted that, for the component nesting feature, "empty" means that the node does not have a nested child node, and "submodule" means that the node has a nested child node.

[0092] In step S104, the logic sequence vector of the sample logic is determined based on the syntax tree.

[0093] In the logic sequence vector, one vector element corresponds to one variable that constitutes the sample logic, i.e., one node in the syntax tree.

[0094] Specifically, the server converts the word representation of each node in the syntax tree of the sample logic into the vector representation of the node through the word vector model to obtain the word vector of each node, and then obtains the logic sequence vector of the sample logic based on the word vector of each node.

[0095] For example, referring to Figure 2 , the server converts the component type feature "logic component", the component identification feature "assignment component", and the component nesting feature "submodule" of the first node into vector patterns through the word2vec model (word to vector, a model for converting words into vector form), to obtain the word vector X1 of the node = {X 11 , X 12 , X 13}, and similarly, the server can also obtain the word vector X2 of the second node (the node corresponding to the variable component) = {X 21 , X 22 , X 23}, and the word vector X3 of the third node (the node corresponding to the data query component) = {X 31 , X 32 , X 33}; then, the server combines X1, X2, and X3 to obtain the logic sequence vector {X1, X2, X3} of the sample logic.

[0096] In step S106, the logic sequence vector is subjected to sliding window processing to obtain at least one logic sequence sub-vector of the sample logic.

[0097] The sliding window processing refers to a truncation operation on the logical sequence vector with a preset sliding window step and a preset sliding window width.

[0098] Specifically, the server performs sliding window processing on the logical sequence vector of the sample logic with a preset sliding window step and a preset sliding window width to obtain at least one logical sequence sub-vector of the sample logic. In a case where the length of the logical sequence vector is less than the preset sliding window width, the server pads zeros at the beginning of the logical sequence vector to obtain one logical sequence sub-vector of the sample logic.

[0099] For example, assuming that the logical sequence vector of the sample logic obtained by the server is {X1, X2, X3, X4, X5, X6, X7, X8}, and the preset sliding window step is 1 and the preset sliding window width is 3, then the logical sequence sub-vectors obtained by the server are {X1, X2, X3}, {X2, X3, X4}, {X3, X4, X5}, {X4, X5, X6}, {X5, X6, X7}, and {X6, X7, X8}. If the logical sequence vector is {X1, X2}, then the server takes {0, X1, X2} as the logical sequence sub-vector of the logical sequence vector.

[0100] In step S108, the component corresponding to the next vector element of the logical sequence sub-vector in the logical sequence vector is determined as the target component of the logical sequence sub-vector.

[0101] Specifically, for each logical sequence sub-vector, the server determines the component corresponding to the next vector element of the logical sequence sub-vector in the logical sequence vector according to the component identification feature of the next vector element, and determines the component corresponding to the next vector element as the target component of the logical sequence sub-vector.

[0102] For example, taking the logical sequence sub-vector {X2, X3, X4} as an example, in the logical sequence vector, the next vector element of the logical sequence sub-vector {X2, X3, X4} is X5. Therefore, the server determines the component identification feature of the variable corresponding to the vector element X5 according to the word vector corresponding to the vector element X5, thereby obtaining the specific component to which the variable belongs, and determines the specific component as the target component of the logical sequence sub-vector {X2, X3, X4}. For example, if the component identification feature of the variable corresponding to the vector element X5 is “logical component”, then the server determines the target component of the logical sequence sub-vector {X2, X3, X4} as the logical component.

[0103] In step S110, the logical sequence sub-vector is taken as input information, and the target component of the logical sequence sub-vector is taken as supervision information to train the logic arrangement prediction model to be trained, thereby obtaining a trained logic arrangement prediction model.

[0104] Among them, the logic orchestration prediction model to be trained is a long short-term memory artificial neural network model with an attention mechanism network.

[0105] Specifically, the server takes logical sequence sub-vectors as input information and target components of logical sequence sub-vectors as supervision information. Through the logical orchestration prediction model to be trained, it obtains the predicted components of logical sequence sub-vectors. Then, based on the difference information between the predicted components and the target components, the server performs supervised training on the logical orchestration prediction model to be trained, and obtains a trained logical orchestration prediction model that can be used to predict the components that developers need to add to the current logic.

[0106] In the logic orchestration prediction model training method provided in the above embodiments, the server first constructs a syntax tree for each sample logic in the low-code platform; then, based on the syntax tree, it determines the logic sequence vector of the sample logic; next, it performs sliding window processing on the logic sequence vector to obtain at least one logic sequence sub-vector of the sample logic; then, it identifies the component corresponding to the next vector element in the logic sequence vector as the target component of the logic sequence sub-vector; finally, it trains the logic orchestration prediction model to be trained using the logic sequence sub-vector as input information and the target component of the logic sequence sub-vector as supervision information, thus obtaining a trained logic orchestration prediction model. In this way, the server, based on the syntax tree constructed from the sample logic in the low-code platform, can obtain the logic sequence vector of the sample logic, and further obtain at least one logic sequence sub-vector of the sample logic. Therefore, it can use the logic sub-sequence vector as input information and the target component of the logic sub-sequence vector as supervision information to perform supervised training on the logic orchestration prediction model to be trained, obtaining a trained logic orchestration prediction model that can predict the next component to be inserted based on the preceding information in the logic being orchestrated. The logic orchestration prediction model training method based on the above process can free developers from the tedious selection of visual graphical components, allowing them to better focus their energy on creative programming activities, thereby improving the efficiency of logic orchestration in low-code platforms.

[0107] like Figure 3 As shown, in an exemplary embodiment, step S104 above, which determines the logical sequence vector of the sample logic based on the syntax tree, specifically includes the following steps:

[0108] Step S302: Based on the syntax tree, determine the component type characteristics, component identification characteristics, and component nesting characteristics of each node in the syntax tree.

[0109] Step S304: Determine the node type of each node based on the component nesting characteristics.

[0110] In step S306, the component type feature, the component identification feature, and the component nesting feature of each node are mapped to a word vector according to the node type, to obtain a logic sequence vector of the sample logic.

[0111] The component nesting feature is used to represent the nesting relationship between components.

[0112] The node type is divided according to whether the node has nested child nodes.

[0113] Specifically, the server first determines the component type feature, the component identification feature, and the component nesting feature of each node in the syntax tree based on the syntax tree. Then, the server divides the nodes into first nodes without nested child nodes and second nodes with nested child nodes according to the component nesting feature of each node. Next, the server respectively performs word vector mapping processing on the component type feature, the component identification feature, and the component nesting feature of the first nodes and the second nodes, to obtain the word vector of each node and further obtain the logic sequence vector of the logic sequence.

[0114] For example, referring to Figure 2 The component nesting feature of the node corresponding to the variable component is empty, so the node is a first node. The nodes corresponding to the assignment component and the data query component both have nested child nodes, so the two nodes are second nodes.

[0115] In this embodiment, the server divides the nodes into first nodes without nested child nodes and second nodes with nested child nodes through the nesting relationship, so that the word mapping processing can be performed on the nodes according to the type of the nodes, to obtain the logic sequence vector that can accurately reflect the overall structure and internal nesting relationship of the logic, thereby providing a material basis for the training of the subsequent logic arrangement prediction model, and further improving the efficiency of the logic arrangement in the low-code platform.

[0116] In an exemplary embodiment, step S306, which involves performing word vector mapping processing on the component type features, component identifier features, and component nesting features of each node according to the node type, specifically includes the following: when the node is a first node without nested child nodes, word vector mapping processing is performed on the component type features, component identifier features, and component nesting features of the first node to obtain the component type feature vector, component identifier feature vector, and component nesting feature vector of the first node; when the node is a second node with nested child nodes, word vector mapping processing is performed on the component type features and component identifier features of the second node to obtain the component type feature vector and component identifier feature vector of the second node; and, based on the nested child nodes of the second node, word vector mapping processing is performed on the component nesting features of the second node to obtain the component nesting feature vector of the second node.

[0117] Specifically, when the node is the first node without nested child nodes, the server performs word vector mapping processing on the component type feature, component identifier feature, and component nesting feature of the first node respectively, to obtain the component type feature vector, component identifier feature vector, and component nesting feature vector of the first node. Then, the server combines the above component type feature vector, component identifier feature vector, and component nesting feature vector to obtain the word vector of the first node. For example, see Figure 2 The node corresponding to the variable component is the first node. Therefore, the server uses word vector mapping to process the component type feature "system component", component identifier feature "variable component", and component nesting feature "empty" of this node to obtain the component type feature vector of this node. Component Identifier Feature Vector and component nested feature vectors Based on the component type feature vector, component identifier feature vector, and component nesting feature vector mentioned above, the server obtains the word vector X2 = {X... 21 X 22 X 23 It is understandable that, since the first node does not have nested child nodes, the component nesting feature vector of the first node can be represented by X. 23 The eigenvectors are represented as {0, 0, 0...0}. Here, k represents the length of the eigenvector.

[0118] When the server encounters a second node with nested child nodes, it first performs word vector mapping on the component type feature and component identifier feature of the second node, respectively, to obtain the component type feature vector and component identifier feature vector of the second node. Next, based on the word vectors of the nested child nodes of the second node, it performs word vector mapping on the component nesting feature of the second node, to obtain the component nesting feature vector of the second node. Finally, the server obtains the word vector of the second node based on the aforementioned component type feature vector, component identifier feature vector, and component nesting feature vector. For example, see [link to relevant documentation]. Figure 2 The node corresponding to the assignment component is the second node. Therefore, the server first processes the component type feature vector of this node through word vector mapping, targeting both the component type feature "logical component" and the component identifier feature "assignment component". and component identifier feature vector Then, the server performs convolution processing on the word vectors of the node's child nodes (corresponding to the variable component and the data query component) using Formula 1, thereby achieving word vector mapping of the node's component nesting features and obtaining the node's component nesting feature vector.

[0119]

[0120] Where W is the weight vector of the convolution. Finally, based on the component type feature vector, component identifier feature vector, and component nesting feature vector mentioned above, the server obtains the word vector X1 = {X... 11 X 12 X 13}

[0121] In this embodiment, the server can obtain a logical sequence vector that fully reflects the overall structure and internal nesting relationship of the logic by mapping the word vectors of the first node and the second node. This facilitates the training of the logic orchestration prediction model and improves the efficiency of logic orchestration in the low-code platform.

[0122] like Figure 4 As shown, in an exemplary embodiment, step S110, which uses logical sequence sub-vectors as input information and target components of the logical sequence sub-vectors as supervision information to train the logical orchestration prediction model to obtain the trained logical orchestration prediction model, specifically includes the following steps:

[0123] Step S402: The long short-term memory artificial neural network in the logic arrangement prediction model to be trained is used to perform feature extraction processing on the logic sequence sub-vectors to obtain the target vector corresponding to the logic sequence sub-vectors.

[0124] Step S404, the attention mechanism network in the logic editing prediction model to be trained is used to classify the target vector, so as to obtain a prediction component corresponding to the logic sequence sub-vector.

[0125] Step S406, based on the difference information between the prediction component and the target component, the logic arrangement prediction model to be trained is trained to obtain a trained logic arrangement prediction model.

[0126] Specifically, as shown in Figure 5 The structure diagram of the logic arrangement prediction model to be trained is shown. The server uses the long short-term memory artificial neural network in the logic arrangement prediction model to be trained to perform feature extraction processing on the logic sequence sub-vector, so as to obtain a target vector corresponding to the logic sequence sub-vector. Then, the attention mechanism network in the logic editing prediction model to be trained is used to classify the target vector based on more than 30 components provided by the low-code platform, so as to obtain the correlation degree between the target vector and the more than 30 components. Then, the server confirms the component with the highest correlation degree as the target component of the logic sequence sub-vector. Finally, the server calculates the loss value between the prediction component and the target component according to the loss function, and updates the training parameters of the logic arrangement prediction model to be trained in the case that the loss value is greater than the preset loss threshold, so as to retrain the logic arrangement prediction model to be trained, until the corresponding loss value is less than the preset loss threshold, so as to obtain the trained logic arrangement prediction model.

[0127] It can be understood that the vector dimension of each feature vector of each node is 1xk, so the vector dimension of the word vector of each node is 3xk, and then the vector dimension of the logic sequence vector of each sample logic is 3xkxm, wherein m is the number of variables constituting the sample logic, that is, the vector length of the logic sequence vector. Assuming that the preset sliding window width is n, the vector dimension of each logic sequence sub-vector is 3xkxn. Referring to Figure 5 Taking the training process of the i-th logic sequence sub-vector as an example, the server inputs the first i logic sequence sub-vectors with a vector dimension of 3xkxn into the logic arrangement prediction model to be trained, obtains a target vector with a vector dimension of 3xk through the long short-term memory artificial neural network (the target vector corresponding to the i-th logic sequence sub-vector), then obtains a vector with a vector dimension of 3nxk through the attention mechanism network, and finally obtains a correlation degree vector with a vector dimension of cxl through the activation function (softmax function), wherein c is the number of components provided by the low-code platform. Each element in the correlation degree vector represents the correlation degree between the logic sequence sub-vector and each component provided by the low-code platform. The correlation degree is used to represent the possibility that the next node of the logic sequence sub-vector corresponds to the component provided by the low-code platform.

[0128] In this embodiment, the server trains the logic editing prediction model to be trained through the logical sequence sub-vector and the corresponding target component, can train the logic editing prediction model with prediction accuracy meeting the requirements, based on the model, can realize accurate prediction of the component to be added based on the overall arrangement of the current logic, so as to liberate the developer from the tedious selection of visual graphical components, so that the developer can concentrate better on the creative programming activities, thereby improving the efficiency of logic arrangement in the low-code platform.

[0129] In an exemplary embodiment, the attention mechanism network in the logic arrangement prediction model to be trained is obtained by: obtaining the context feature vector of each variable constituting each sample logic in the low-code platform; based on the context feature vector of each variable, the attention mechanism network in the logic arrangement prediction model to be trained is obtained.

[0130] The context feature vector of the variable is used to represent the distribution of the variable in the sample logic, such as the number of occurrences, the frequency of occurrence, etc.

[0131] Specifically, the server performs SBT (splay balanced tree) structured traversal on the syntax tree of each sample logic to obtain the context feature vector of each variable in the sample logic; then the server determines the weight in the attention mechanism network in the logic arrangement prediction model to be trained based on the context feature vector of each variable.

[0132] For example, the server first determines the variable category feature, variable type feature, variable number feature and variable distance feature of the variable on each node in the syntax tree according to the SBT (splay balanced tree) structured traversal result of the syntax tree; wherein the variable category feature is used to represent the category of the variable, and the category of the variable is divided into input variable, output variable and local variable; the variable type feature is used to represent the data type of the variable, such as integer data, floating point data, string, etc.; the variable number feature is used to represent the number of times the variable at the current position appears before the current position in the syntax tree; the variable distance feature is used to represent the distance between the variable at the current position and the last position where the variable appears in the syntax tree. Then, the server performs word vector mapping processing on the variable category feature, variable type feature, variable number feature and variable distance feature of the variable on each node respectively to obtain the context feature vector of the variable. For example, the variable category feature of the variable on the jth node is The variable type feature is The variable number feature is and variable distance feature is Therefore, the context feature vector of the variable on the jth node is Y j = {Y j1 , Y j2 , Y j3 , Y j4}. Then, the server determines the weight in the attention mechanism network in the logic arrangement prediction model to be trained according to formula 2:

[0133]

[0134] wherein, is the kth element of the lth feature vector of the jth node, w jlk is the kth element of the lth feature vector of the jth node, w j lk is the weight of the kth element of the lth feature vector of the jth node in the attention mechanism network; l = 1, 2, 3, 4, is the serial number of the feature vector (variable category feature, variable type feature, variable frequency feature, and variable distance feature).

[0135] In the embodiment, the server determines the context features of each variable in the sample logic by SBT structured traversal of the syntax tree of each sample logic, thereby determining the weight in the attention mechanism network in the logic arrangement prediction model to be trained, and further ensuring the prediction accuracy of the logic arrangement prediction model in the training process, and further improving the efficiency of logic arrangement in the low-code platform.

[0136] In an exemplary embodiment, the above step of obtaining the context feature vector of each variable constituting each sample logic in the low-code platform specifically includes the following contents: for each variable, determining the current position of the variable in the syntax tree of the corresponding sample logic; based on the current position, determining the variable frequency feature and the variable distance feature of the variable; based on the variable frequency feature and the variable distance feature of the variable, obtaining the context feature vector of the variable.

[0137] wherein, the variable frequency feature is used to represent the number of times the variable appears before the current position in the syntax tree; and the variable distance feature is used to represent the distance between the current position and the last position of the variable appearing in the syntax tree.

[0138] ​Specifically, the server determines, for each variable in the sample logic, a current position of the variable in a syntax tree of the corresponding sample logic, and then determines, based on the current position in the syntax tree, a number of times that the variable occurs before the current position as a variable number feature of the variable, and a distance between the current position and a last position at which the variable occurs as a variable distance feature of the variable. Finally, the server respectively performs word vector mapping processing on the variable category feature, the variable type feature, the variable number feature, and the variable distance feature of the variable to obtain a context feature vector of the variable.

[0139] In this embodiment, the server can determine the distribution of the variable on each node in the syntax tree through SBT structured traversal of the syntax tree, and further obtain the context feature vector of the variable in the sample logic to which the variable belongs, thereby providing a basis for determining the attention mechanism network in the logic arrangement prediction model to be trained, and further ensuring the prediction accuracy of the logic arrangement prediction model in the training process, and further improving the efficiency of logic arrangement in the low-code platform.

[0140] In an example embodiment, as shown in Figure 6 Another logic arrangement prediction model training method is provided, which is applied to a server as an example for illustration, and includes the following steps:

[0141] Step S601: For each sample logic in the low-code platform, a syntax tree of the sample logic is constructed.

[0142] Step S602: Based on the syntax tree, component type features, component identifier features, and component nesting features of each node in the syntax tree are determined.

[0143] Step S603: The node type of each node is determined according to the component nesting features.

[0144] Step S604: The component type features, component identifier features, and component nesting features of each node in each node are subjected to word vector mapping processing according to the node type, to obtain a logic sequence vector of the sample logic.

[0145] Step S605: The logic sequence vector is subjected to sliding window processing to obtain at least one logic sequence sub-vector of the sample logic.

[0146] Step S606: The component corresponding to the next vector element of the logic sequence sub-vector in the logic sequence vector is confirmed as a target component of the logic sequence sub-vector.

[0147] Step S607: The logic sequence sub-vector is subjected to feature extraction processing by a long short-term memory artificial neural network in the logic arrangement prediction model to be trained, to obtain a target vector corresponding to the logic sequence sub-vector.

[0148] Step S608, the target vector is classified and processed through the attention mechanism network in the logic editing prediction model to be trained, to obtain a prediction component corresponding to the logic sequence sub-vector.

[0149] Step S609, based on the difference information between the prediction component and the target component, the logic arrangement prediction model to be trained is trained to obtain a trained logic arrangement prediction model.

[0150] Before step S607, further comprising:

[0151] Step S610, for each variable in each sample logic in the low-code platform, the current position of the variable in the syntax tree of the corresponding sample logic is determined.

[0152] Step S611, based on the current position, the variable frequency feature and the variable distance feature of the variable are determined.

[0153] Step S612, based on the variable frequency feature and the variable distance feature of the variable, a context feature vector of the variable is obtained.

[0154] Step S613, based on the context feature vector of each variable, an attention mechanism network in the logic arrangement prediction model to be trained is obtained.

[0155] In the embodiment, first, the server divides the nodes into first nodes without nested sub-nodes and second sub-nodes with nested sub-nodes through the nesting relationship, so as to perform word mapping processing on the nodes according to the types of the nodes, to obtain a logic sequence vector that can accurately reflect the overall structure and internal nesting relationship of the logic, to provide a material basis for subsequent training of the logic arrangement prediction model, and to facilitate subsequent training of the logic arrangement prediction model; second, the server supervises and trains the logic editing prediction model to be trained through the logic sequence sub-vector and the corresponding target component, to train a logic editing prediction model with a prediction accuracy meeting the requirements, based on which accurate prediction of the component to be added can be realized based on the overall arrangement of the current logic; third, the context features of each variable in the sample logic are determined through the structured traversal of the syntax tree of each sample logic, to determine the weights in the attention mechanism network in the logic arrangement prediction model to be trained, and to ensure the prediction accuracy of the logic arrangement prediction model in the training process. The logic arrangement prediction model training method based on the above process can free the developers from the tedious selection of visual graphical components, so that the developers can better concentrate on creative programming activities, and thus improve the efficiency of logic arrangement in the low-code platform.

[0156] In an example embodiment, as Figure 7As shown, the present application also provides a logical arrangement method, and the present embodiment takes the method applied to a server as an example; it can be understood that the method can also be applied to a terminal, and can also be applied to a system including a server and a terminal, and is realized through the interaction between the server and the terminal. The server can be realized by an independent server or a server cluster composed of multiple servers; the terminal can be, but is not limited to, various personal computers, notebook computers, smart phones and tablet computers and the like. In the present embodiment, the method includes the following steps:

[0157] In step S702, a to-be-predicted node in the logical arrangement interface is identified, and a target logic to which the to-be-predicted node belongs is determined.

[0158] In step S704, based on the target logic, a logical sequence sub-vector corresponding to the to-be-predicted node is determined.

[0159] In step S706, the logical sequence sub-vector corresponding to the to-be-predicted node is input into the trained logical arrangement prediction model, to obtain at least one predicted component associated with the to-be-predicted node, and an association degree between each predicted component and the to-be-predicted node.

[0160] In step S708, at least one predicted component is displayed in the logical arrangement interface according to the association degree, and the target logic is arranged based on the at least one predicted component.

[0161] The trained logical arrangement prediction model is obtained according to the logical arrangement prediction model training method in any one of the above embodiments.

[0162] The association degree is used to represent the probability that the component to be inserted by the to-be-predicted node belongs to the predicted component.

[0163] Specifically, the server first identifies a node to which a developer is to insert a visual graphical component from a logical arrangement interface, and takes the node as a node to be predicted; then, the server determines a logic in which the node to be predicted is located as a target logic to which the node to be predicted belongs; then, the server determines a syntax tree of the target logic based on the target logic, and obtains a logical sequence vector of the target logic based on the syntax tree; then, the server obtains a preset number of vector elements before the node to be predicted as a logical sequence sub-vector corresponding to the node to be predicted; then, the server inputs the logical sequence sub-vector corresponding to the node to be predicted into the trained logical arrangement prediction model, obtains, through the trained logical arrangement prediction model, a possibility that the node to be predicted needs to insert a component as each component, that is, an association degree between the node to be predicted and each component, and then screens a component corresponding to the association degree satisfying a preset association degree threshold as a predicted component; finally, the server displays at least one predicted component in the logical arrangement interface in a descending order of the association degree, and the developer arranges the target logic based on the predicted component displayed.

[0164] It should be noted that the specific limitations of the above logical arrangement method can refer to the specific limitations of the logical arrangement prediction model training method, which will not be repeated here.

[0165] In the logical arrangement method provided in the above embodiments, the server obtains a logical sequence sub-vector corresponding to a node to be predicted based on a target logic to which the node to be predicted belongs, and then predicts, through a trained logical arrangement prediction model, a probability that the node to be predicted needs to insert a component as each component, so as to obtain a predicted component associated with the node to be predicted, and then intelligently recommends the logical arrangement of the developer; based on the above logical arrangement method, the developer can be freed from the tedious selection of visual graphical components, and the developer can better concentrate on creative programming activities, thereby improving the efficiency of logical arrangement in the low-code platform.

[0166] In an example embodiment, the step S704 of determining, based on the target logic, the logical sequence sub-vector corresponding to the node to be predicted specifically includes the following contents: constructing a syntax tree of the target logic based on the target logic; determining a logical sequence vector of the target logic according to component type features, component identifier features and component nesting features of each node in the syntax tree of the target logic; extracting, as a last element of the logical sequence sub-vector corresponding to the node to be predicted, a sub-vector with a preset length corresponding to the last element in the logical sequence vector of the target logic, as the logical sequence sub-vector corresponding to the node to be predicted.

[0167] Specifically, the server first constructs a syntax tree of the target logic according to the target logic; then, the server performs word vector mapping processing on the component type features, component identification features and component nesting features of each node in the syntax tree to obtain a logic sequence vector of the target logic; then, the server extracts a corresponding vector with a preset length as a logic sequence sub-vector corresponding to the to-be-predicted node from the logic sequence vector of the target logic, as the last element of the logic sequence sub-vector corresponding to the to-be-predicted node, where the vector element of the previous node of the to-be-predicted node in the logic sequence vector of the target logic.

[0168] For example, assuming that the logic sequence vector of the target logic is {Z1, Z2, Z3, Z4, Z5, Z6, Z7, Z8}, the to-be-predicted node is a node between X5 and X6, and the preset length of the logic sequence sub-vector is three vector elements, then the vector element of the previous node of the to-be-predicted node in the logic sequence vector of the target logic is X5, and the server can obtain the logic sequence sub-vector corresponding to the to-be-predicted node as {Z3, Z4, Z5}.

[0169] In this embodiment, the server can accurately extract the logic sequence sub-vector corresponding to the to-be-predicted node from the logic sequence vector of the target logic according to the vector element of the previous node of the to-be-predicted node in the logic sequence vector of the target logic and the preset length of the logic sequence sub-vector, thereby providing a prediction basis for predicting the predicted component corresponding to the to-be-predicted node, further improving the accuracy of component prediction, and further improving the efficiency of logic arrangement in the low-code platform.

[0170] In order to more clearly illustrate the logic arrangement prediction model training method provided in the embodiments of the present application, the logic arrangement prediction model training method will be specifically described below with one specific embodiment, but it should be understood that the embodiments of the present application are not limited thereto. In an example embodiment, as shown in Figure 8 The present application also provides a low-code logic arrangement intelligent assistance method based on a visual language, specifically including the following steps:

[0171] Step 1: feature extraction.

[0172] The server first constructs a syntax tree of the sample logic in the low-code platform, and converts the syntax tree into a vector expression using a word vector model to obtain a logic sequence vector of the sample logic. Then, the server performs SBT structured traversal based on the syntax tree to obtain a context feature vector of a variable represented by each node.

[0173] Step 2: model design.

[0174] The server constructs an attention mechanism network through the context feature vector of each variable in the sample logic, and adds the attention mechanism network to a long short-term memory artificial neural network model to obtain a logic arrangement prediction model to be trained.

[0175] Step 3: Model training.

[0176] The server first performs sliding window processing on the logic sequence vector of the sample logic to obtain a plurality of logic sequence sub-vectors of the same length, and confirms the component corresponding to the next vector element in the respective corresponding logic sequence vector as the target component of the logic sequence sub-vector; and trains the logic arrangement prediction model to be trained by taking the logic sequence sub-vector as input information and the target component as supervision information to obtain a trained logic arrangement prediction model.

[0177] Step 4: Intelligent recommendation.

[0178] Based on the feature extraction method of step 1, the logic sequence sub-vector corresponding to the node to be predicted in the logic arrangement interface is extracted, the logic sequence sub-vector corresponding to the node to be predicted is input into the trained logic arrangement prediction model, the predicted component to be inserted at the node to be predicted is obtained, and the predicted component is displayed in the logic arrangement interface, thereby realizing intelligent assistance based on low-code logic arrangement.

[0179] In this embodiment, the server can obtain the sequence features of the sample logic and the context features of each variable in the sample logic through feature extraction, thereby realizing training of the logic arrangement prediction model to be trained; and through the trained logic arrangement prediction model, the visual logic semantic features and the logic context information can be fully utilized when performing logic arrangement on the low-code platform, intelligent recommendation can be performed at the insertion point, and the development efficiency of the developer in logic arrangement can be improved.

[0180] It should be understood that although each step in the flowchart involved in each embodiment as described above is displayed in sequence according to the arrow, these steps are not necessarily executed in sequence according to the arrow. Unless otherwise specified herein, the execution of these steps is not strictly limited in sequence, and these steps can be executed in other sequences. Moreover, at least part of the steps in the flowchart involved in each embodiment as described above can include multiple steps or stages, which are not necessarily executed at the same time, but can be executed at different times, and the execution sequence of these steps or stages is not necessarily sequential, but can be executed in rotation or alternation with at least part of other steps or steps or stages in other steps.

[0181] Based on the same inventive concept, the embodiments of the present application also provide a logic arrangement prediction model training device for implementing the above-mentioned logic arrangement prediction model training method. The implementation scheme for solving problems provided by the device is similar to the implementation scheme described in the above method, so the specific limitations in one or more logic arrangement prediction model training device embodiments provided below can be referred to the limitations of the logic arrangement prediction model training method in the above, which will not be described here again.

[0182] In an exemplary embodiment, as shown in Figure 9 A logic arrangement prediction model training device is provided, comprising: a syntax construction module 902, a sequence determination module 904, a sliding window processing module 906, a component determination module 908, and a model training module 910, wherein:

[0183] The syntax construction module 902 is configured to construct a syntax tree of a sample logic for each sample logic in a low-code platform; each node in the syntax tree corresponds to each variable constituting the sample logic, and the variable is an instantiation object of a component.

[0184] The sequence determination module 904 is configured to determine a logic sequence vector of the sample logic based on the syntax tree; one vector element in the logic sequence vector corresponds to one variable constituting the sample logic.

[0185] The sliding window processing module 906 is configured to perform sliding window processing on the logic sequence vector to obtain at least one logic sequence sub-vector of the sample logic.

[0186] The component determination module 908 is configured to determine a component corresponding to a next vector element of the logic sequence sub-vector in the logic sequence vector as a target component of the logic sequence sub-vector.

[0187] The model training module 910 is configured to train a to-be-trained logic arrangement prediction model by taking the logic sequence sub-vector as input information and taking the target component of the logic sequence sub-vector as supervision information, to obtain a trained logic arrangement prediction model.

[0188] In an exemplary embodiment, the sequence determination module 904 is further configured to determine component type features, component identifier features, and component nesting features of each node in the syntax tree based on the syntax tree; the component nesting features are used to represent the nesting relationship between components; the node type of each node is determined according to the component nesting features; and the component type features, the component identifier features, and the component nesting features of each node in each node are processed by word vector mapping to obtain the logic sequence vector of the sample logic.

[0189] In an example embodiment, the sequence determining module 904 is further configured to, in a case where the node is a first node without nested child nodes, perform word vector mapping processing on the component type feature, the component identifier feature and the component nesting feature of the first node respectively to obtain a component type feature vector, a component identifier feature vector and a component nesting feature vector of the first node; in a case where the node is a second node with nested child nodes, perform word vector mapping processing on the component type feature and the component identifier feature of the second node respectively to obtain a component type feature vector and a component identifier feature vector of the second node, and perform word vector mapping processing on the component nesting feature of the second node based on the child nodes nested by the second node to obtain a component nesting feature vector of the second node.

[0190] In an example embodiment, the model training module 910 is further configured to perform feature extraction processing on the logic sequence sub-vector by a long short-term memory artificial neural network in the logic arrangement prediction model to be trained to obtain a target vector corresponding to the logic sequence sub-vector; perform classification processing on the target vector by an attention mechanism network in the logic editing prediction model to be trained to obtain a predicted component corresponding to the logic sequence sub-vector; and train the logic arrangement prediction model to be trained based on difference information between the predicted component and a target component to obtain a trained logic arrangement prediction model.

[0191] In an example embodiment, the logic arrangement prediction model training apparatus further comprises a network determining module configured to obtain a context feature vector of each variable constituting each sample logic in the low-code platform; and obtain an attention mechanism network in the logic arrangement prediction model to be trained based on the context feature vector of each variable.

[0192] In an example embodiment, the network determining module is further configured to, for each variable, determine a current position of the variable in a syntax tree of a corresponding sample logic; determine a variable frequency feature and a variable distance feature of the variable based on the current position; the variable frequency feature is used to represent a frequency of occurrence of the variable before the current position in the syntax tree; the variable distance feature is used to represent a distance between the current position and a last position of occurrence of the variable in the syntax tree; and obtain the context feature vector of the variable based on the variable frequency feature and the variable distance feature of the variable.

[0193] Based on the same inventive concept, the embodiments of the present application also provide a logic arrangement apparatus for implementing the above-mentioned logic arrangement method. The implementation scheme for solving the problem provided by the apparatus is similar to the implementation scheme described in the above method, and therefore the specific limitations in one or more logic arrangement apparatus embodiments provided below can refer to the limitations of the logic arrangement method described above, which will not be described here again.

[0194] In an example embodiment, asFigure 10 As shown in the figure, a logic arrangement device is provided, comprising a logic determination module 1002, a vector determination module 1004, a component prediction module 1006, and a logic arrangement module 1008, wherein:

[0195] The logic determination module 1002 is configured to identify a to-be-predicted node in a logic arrangement interface, and determine a target logic to which the to-be-predicted node belongs.

[0196] The vector determination module 1004 is configured to determine a logic sequence sub-vector corresponding to the to-be-predicted node based on the target logic.

[0197] The component prediction module 1006 is configured to input the logic sequence sub-vector corresponding to the to-be-predicted node into a trained logic arrangement prediction model, to obtain at least one predicted component associated with the to-be-predicted node and an association degree between each predicted component and the to-be-predicted node; the trained logic arrangement prediction model is the trained logic arrangement prediction model in the logic arrangement prediction model training method.

[0198] The logic arrangement module 1008 is configured to display the at least one predicted component in the logic arrangement interface according to the association degree, and arrange the target logic based on the at least one predicted component.

[0199] In an exemplary embodiment, the vector determination module 1004 is further configured to construct a syntax tree of the target logic based on the target logic, determine a logic sequence vector of the target logic according to component type features, component identifier features, and component nesting features of each node in the syntax tree of the target logic, and extract a sub-vector corresponding to a last element of the logic sequence sub-vector corresponding to the to-be-predicted node from the logic sequence vector of the target logic as the logic sequence sub-vector corresponding to the to-be-predicted node, with a vector element of a previous node of the to-be-predicted node in the logic sequence vector of the target logic as a last element of the logic sequence sub-vector corresponding to the to-be-predicted node.

[0200] The above-mentioned logic arrangement prediction model training device and logic arrangement device can be realized by software, hardware, and combinations thereof. The above-mentioned modules can be embedded in or independent of a processor in a computer device in hardware form, or can be stored in a memory in a computer device in software form, so as to be called and executed by a processor to perform operations corresponding to the above-mentioned modules.

[0201] In an exemplary embodiment, a computer device is provided, which can be a server, and an internal structure diagram of the computer device can be as shown in the figure. Figure 11As shown in the figure. The computer device includes a processor, a memory, an input / output interface (I / O for short) and a communication interface. Among them, the processor, the memory and the input / output interface are connected through the system bus, and the communication interface is connected to the system bus through the input / output interface. Among them, the processor of the computer device is used to provide computing and control capability. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system, a computer program and a database. The internal memory provides an environment for the operation of the operating system and the computer program in the non-volatile storage medium. The database of the computer device is used to store the related data of the sample logic provided by the low-code platform, such as the syntax tree of the sample logic, the logic sequence vector of the sample logic, and the context feature vector of each variable in the sample logic. The input / output interface of the computer device is used to exchange information between the processor and the external device. The communication interface of the computer device is used to communicate with the terminal outside through the network connection. The computer program is executed by the processor to implement a logic arrangement prediction model training method or a logic arrangement method.

[0202] Those skilled in the art can understand that, Figure 11 The structure shown in the figure is only a block diagram of part of the structure related to the scheme of the present application, and does not constitute a limitation on the computer device to which the scheme of the present application is applied. The specific computer device can include more or fewer components than those shown in the figure, or combine certain components, or have a different component arrangement.

[0203] In an exemplary embodiment, a computer device is also provided, including a memory and a processor, the memory storing a computer program, and the processor executing the computer program to implement the steps in each of the above method embodiments.

[0204] In an exemplary embodiment, a computer readable storage medium is provided, which stores a computer program, and the computer program is executed by a processor to implement the steps in each of the above method embodiments.

[0205] In an exemplary embodiment, a computer program product is provided, including a computer program, and the computer program is executed by a processor to implement the steps in each of the above method embodiments.

[0206] Those skilled in the art can understand that all or part of the processes in the above-mentioned embodiment methods can be completed by instructing the relevant hardware through a computer program. The computer program can be stored in a non-volatile computer readable storage medium, and when the computer program is executed, the processes of the above-mentioned embodiments of the methods can be included. Any reference to memory, database or other medium used in the embodiments provided in the present application can include at least one of non-volatile and volatile memory. Non-volatile memory can include read-only memory (Read-Only Memory, ROM), magnetic tape, floppy disk, flash memory, optical storage, high-density embedded non-volatile memory, resistive memory (ReRAM), magnetoresistive random access memory (Magnetoresistive Random Access Memory, MRAM), ferroelectric memory (Ferroelectric Random Access Memory, FRAM), phase change memory (Phase Change Memory, PCM), graphene memory, etc. Volatile memory can include random access memory (Random Access Memory, RAM) or external cache memory, etc. As an illustration but not limitation, RAM can be in various forms, such as static random access memory (Static Random Access Memory, SRAM) or dynamic random access memory (Dynamic Random Access Memory, DRAM), etc. The database involved in the embodiments provided in the present application can include at least one of a relational database and a non-relational database. The non-relational database can include a distributed database based on a block chain, etc., without being limited thereto. The processor involved in the embodiments provided in the present application can be a general-purpose processor, a central processing unit, a graphics processing unit, a digital signal processor, a programmable logic device, a data processing logic device based on quantum computing, etc., without being limited thereto.

[0207] Any combination of the technical features of the above embodiments can be made. In order to make the description simple, all possible combinations of the technical features in the above embodiments are not described, however, as long as the combination of the technical features does not exist contradictory, it should be considered as the scope of the present application.

[0208] The above embodiments only express several implementation manners of the present application, and the description is more specific and detailed, but it should not be understood as a limitation on the scope of the patent of the present application. It should be pointed out that for ordinary skilled in the art, without departing from the concept of the present application, a number of modifications and improvements can be made, which are within the scope of protection of the present application. Therefore, the protection scope of the present application should be subject to the appended claims.

Claims

1. A method for training a logical orchestration prediction model, characterized in that, The method comprises: For each sample logic in the low-code platform, a syntax tree of the sample logic is constructed; each node in the syntax tree corresponds to each variable that constitutes the sample logic, and the variable is an instantiation object of a component; Based on the syntax tree, a logic sequence vector of the sample logic is determined; one vector element in the logic sequence vector corresponds to one variable that constitutes the sample logic; The logic sequence vector is subjected to sliding window processing to obtain at least one logic sequence sub-vector of the sample logic; The component corresponding to the next vector element in the logic sequence vector is determined as the target component of the logic sequence sub-vector; The logic sequence sub-vector is taken as input information, and the target component of the logic sequence sub-vector is taken as supervision information, and a to-be-trained logic arrangement prediction model is trained to obtain a trained logic arrangement prediction model; The to-be-trained logic arrangement prediction model is a long short-term memory artificial neural network model with an attention mechanism network; The attention mechanism network in the to-be-trained logic arrangement prediction model is obtained by: obtaining a context feature vector of each variable that constitutes each sample logic in the low-code platform; and based on the context feature vector of each variable, the attention mechanism network in the to-be-trained logic arrangement prediction model is obtained; The context feature vector of each variable that constitutes each sample logic in the low-code platform is obtained by: for each variable, determining the current position of the variable in the syntax tree of the corresponding sample logic; based on the current position, determining the variable number feature and the variable distance feature of the variable; the variable number feature is used to represent the number of times the variable appears before the current position in the syntax tree; the variable distance feature is used to represent the distance between the current position and the last position where the variable appears in the syntax tree; based on the variable number feature and the variable distance feature of the variable, the context feature vector of the variable is obtained.

2. The method of claim 1, wherein, The logic sequence vector of the sample logic is determined based on the syntax tree, comprising: Based on the syntax tree, the component type feature, the component identification feature and the component nesting feature of each node in the syntax tree are determined; the component nesting feature is used to represent the nesting relationship between components; According to the component nesting feature, the node type of each node is determined; According to the node type, the component type feature, the component identification feature and the component nesting feature of each node in the syntax tree are subjected to word vector mapping processing to obtain the logic sequence vector of the sample logic.

3. The method of claim 2, wherein, The word vector mapping processing of the component type feature, the component identification feature and the component nesting feature of each node in the syntax tree according to the node type comprises: In a case where the node is a first node without nested child nodes, component type features, component identification features and component nesting features of the first node are respectively subjected to word vector mapping processing to obtain component type feature vectors, component identification feature vectors and component nesting feature vectors of the first node; In a case where the node is a second node with nested child nodes, component type features and component identification features of the second node are respectively subjected to word vector mapping processing to obtain component type feature vectors and component identification feature vectors of the second node, and component nesting features of the second node are subjected to word vector mapping processing based on the child nodes nested by the second node to obtain component nesting feature vectors of the second node.

4. The method of claim 1, wherein, The training of the to-be-trained logical arrangement prediction model is performed based on the difference information between the predicted component and the target component, and the trained logical arrangement prediction model is obtained. The method comprises: identifying a to-be-predicted node in a logical arrangement interface, determining a target logic to which the to-be-predicted node belongs; based on the target logic, determining a logical sequence sub-vector corresponding to the to-be-predicted node; 5. A method for logical orchestration, the method comprising: inputting the logical sequence sub-vector corresponding to the to-be-predicted node into the trained logical arrangement prediction model to obtain at least one predicted component associated with the to-be-predicted node and an association degree between each predicted component and the to-be-predicted node; the trained logical arrangement prediction model is trained according to the method of any one of claims 1 to 4; arranging the target logic based on the at least one predicted component by displaying the at least one predicted component in the logical arrangement interface according to the association degree. The method comprises: based on the target logic, constructing a syntax tree of the target logic; determining a logical sequence vector of the target logic according to component type features, component identification features and component nesting features of each node in the syntax tree of the target logic; 6. The method of claim 5, wherein, extracting a sub-vector with a preset length from the logical sequence vector of the target logic as the logical sequence sub-vector corresponding to the to-be-predicted node, with a vector element of a previous node of the to-be-predicted node in the logical sequence vector of the target logic as a last element of the logical sequence sub-vector corresponding to the to-be-predicted node. The device comprises: ​ ​ 7.A device for training a logical orchestration prediction model, characterized in that, ​ The syntax construction module is configured to construct a syntax tree of each sample logic in the low-code platform; each node in the syntax tree corresponds to a variable that constitutes the sample logic, and the variable is an instantiation object of a component; The sequence determination module is configured to determine a logic sequence vector of the sample logic based on the syntax tree; one vector element in the logic sequence vector corresponds to one variable that constitutes the sample logic; The sliding window processing module is configured to perform sliding window processing on the logic sequence vector to obtain at least one logic sequence sub-vector of the sample logic; The component determination module is configured to determine a target component of the logic sequence sub-vector as a component corresponding to a next vector element in the logic sequence vector; The model training module is configured to train a to-be-trained logic arrangement prediction model by taking the logic sequence sub-vector as input information and taking the target component of the logic sequence sub-vector as supervision information, to obtain a trained logic arrangement prediction model; The to-be-trained logic arrangement prediction model is a long short-term memory artificial neural network model with an attention mechanism network; The device further includes a network determination module configured to obtain a context feature vector of each variable that constitutes each sample logic in the low-code platform; and obtain an attention mechanism network in the to-be-trained logic arrangement prediction model based on the context feature vector of each variable. The network determination module is further configured to determine, for each variable, a current position of the variable in a syntax tree of a corresponding sample logic; determine a variable frequency feature and a variable distance feature of the variable based on the current position; the variable frequency feature is used to represent a frequency of occurrence of the variable before the current position in the syntax tree; the variable distance feature is used to represent a distance between the current position and a last position of occurrence of the variable in the syntax tree; and obtain the context feature vector of the variable based on the variable frequency feature and the variable distance feature of the variable.

8. A logical orchestration apparatus, characterized by, The device includes: The logic determination module is configured to identify a to-be-predicted node in a logic arrangement interface and determine a target logic to which the to-be-predicted node belongs; The vector determination module is configured to determine a logic sequence sub-vector corresponding to the to-be-predicted node based on the target logic; The component prediction module is configured to input the logic sequence sub-vector corresponding to the to-be-predicted node into the trained logic arrangement prediction model to obtain at least one predicted component associated with the to-be-predicted node and an association degree between each predicted component and the to-be-predicted node; and the trained logic arrangement prediction model is trained according to the method of any one of claims 1 to 4; The logic arrangement module is configured to display the at least one predicted component in the logic arrangement interface according to the association degree and arrange the target logic based on the at least one predicted component. 9.A computer device, comprising a memory and a processor, wherein the memory stores a computer program, and the computer device is configured to perform the method according to any one of claims 1-8 when the computer program is executed by the processor. The processor executes the computer program to implement the steps of the logic arrangement prediction model training method in any one of claims 1 to 4 or the steps of the logic arrangement method in any one of claims 5 to 6.

10. A computer-readable storage medium having stored thereon a computer program, characterized in that, The computer program is executed by a processor to implement the steps of the logical arrangement prediction model training method in any one of claims 1 to 4, or the steps of the logical arrangement method in any one of claims 5 to 6.

11. A computer program product comprising a computer program, characterized in that, The computer program is executed by a processor to implement the steps of the logical arrangement prediction model training method in any one of claims 1 to 4, or the steps of the logical arrangement method in any one of claims 5 to 6.

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