Display panel and display device

Abstract

Embodiments of the present application provide a display panel and a display device. The display panel comprises a pixel circuit and a light emitting element. The pixel circuit comprises a driving module, a light emitting control module and a compensation module. The driving module comprises a driving transistor. The light emitting control module comprises a first light emitting control module and a second light emitting control module. The first light emitting control module is connected between a first power signal line and the driving transistor. The second light emitting control module is connected between the driving transistor and the light emitting element. The compensation module is connected between a gate of the driving transistor and a second electrode of the driving transistor. The compensation module is turned on for a preset stage. In a light emitting stage, the light emitting control module is turned on. In a non-light emitting stage, at least the second light emitting control module is turned off. A length of time between when the second light emitting control module is turned off and when a first preset stage starts is L1. A length of time of the first preset stage is W1. L1>W1. Embodiments of the present application can improve flicker problems of the display panel.

Description

Technical Field

[0001] This application belongs to the field of display technology, and in particular relates to a display panel and a display device. Background Technology

[0002] With the continuous development of display technology, people have increasingly higher requirements for the performance of display panels.

[0003] However, the inventors of this application have discovered that when the display panel displays at a lower grayscale, the displayed image will exhibit varying degrees of flicker, which in turn affects the display effect of the display panel. Summary of the Invention

[0004] This application provides a display panel and a display device that can improve the flickering problem of the display panel.

[0005] In a first aspect, embodiments of this application provide a display panel, the display panel including: a pixel circuit and a light-emitting element; the pixel circuit includes a driving module, a light-emitting control module, and a compensation module; the driving module includes a driving transistor, the driving transistor including a gate, a first electrode, and a second electrode; the light-emitting control module includes a first light-emitting control module and a second light-emitting control module, the first light-emitting control module being connected between a first power signal line and the driving transistor, and the second light-emitting control module being connected between the driving transistor and the light-emitting element; the compensation module is connected between the gate and the second electrode of the driving transistor, and the compensation module is turned on for a preset period; the working process of the pixel circuit includes a non-light-emitting stage and a light-emitting stage; in the light-emitting stage, the first light-emitting control module and the second light-emitting control module are turned on; in the non-light-emitting stage, at least the second light-emitting control module is turned off; wherein, in the non-light-emitting stage, the time length between the second light-emitting control module being turned off and the start of the first preset stage is L1, and the time length of the first preset stage is W1; wherein, L1 > W1.

[0006] Secondly, embodiments of this application provide a display device, which includes a display panel as provided in the first aspect.

[0007] In the display panel and display device of this application embodiment, the compensation module is turned on for a preset period. During the non-light-emitting period, the time interval between the second light-emitting control module being turned off and the start of the first preset period is L1, and the time interval of the first preset period is W1, where L1 > W1. By ensuring L1 > W1, a longer time interval is maintained between the non-light-emitting period and the first preset period. This allows the potentials of the nodes between the second light-emitting control module and the driving transistor, and between the second light-emitting control module and the light-emitting element (i.e., the first electrode of the light-emitting element), to stabilize, ensuring that the potential of the first electrode of the light-emitting element is fully discharged to a lower potential. Since the potential of the first electrode of the light-emitting element has been fully discharged to a lower potential, even if the potential of the first electrode of the light-emitting element is pulled up again due to the coupling effect of parasitic capacitance, the pulled-up potential of the first electrode of the light-emitting element is still relatively small, and the light-emitting element is less likely to emit light again. This effectively improves the flicker phenomenon and enhances the display effect of the display panel. Attached Figure Description

[0008] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments of this application will be briefly introduced below. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0009] Figure 1 This is a schematic diagram of a pixel circuit.

[0010] Figure 2 This is a schematic diagram of the driving timing of a pixel circuit.

[0011] Figure 3 This is a schematic diagram of the structure of a display panel provided in an embodiment of this application;

[0012] Figure 4 A schematic diagram of a pixel circuit in a display panel provided in an embodiment of this application;

[0013] Figure 5 A schematic diagram of the driving timing of a pixel circuit in a display panel provided in an embodiment of this application;

[0014] Figure 6 Another driving timing diagram of the pixel circuit in the display panel provided in the embodiments of this application;

[0015] Figure 7 This is another driving timing diagram of the pixel circuit in the display panel provided in the embodiments of this application;

[0016] Figure 8 Another circuit diagram of the pixel circuit in the display panel provided in the embodiments of this application;

[0017] Figure 9 This is another driving timing diagram of the pixel circuit in the display panel provided in the embodiments of this application;

[0018] Figure 10 This is another driving timing diagram of the pixel circuit in the display panel provided in the embodiments of this application;

[0019] Figure 11 This is another driving timing diagram of the pixel circuit in the display panel provided in the embodiments of this application;

[0020] Figure 12 This is yet another circuit diagram of the pixel circuit in the display panel provided in an embodiment of this application;

[0021] Figure 13 This is another driving timing diagram of the pixel circuit in the display panel provided in the embodiments of this application;

[0022] Figure 14 This is another driving timing diagram of the pixel circuit in the display panel provided in the embodiments of this application;

[0023] Figure 15 This is another driving timing diagram of the pixel circuit in the display panel provided in the embodiments of this application;

[0024] Figure 16 This is another driving timing diagram of the pixel circuit in the display panel provided in the embodiments of this application;

[0025] Figure 17 This is another driving timing diagram of the pixel circuit in the display panel provided in the embodiments of this application;

[0026] Figure 18 This is another driving timing diagram of the pixel circuit in the display panel provided in the embodiments of this application;

[0027] Figure 19 This is another driving timing diagram of the pixel circuit in the display panel provided in the embodiments of this application;

[0028] Figure 20 A schematic diagram illustrating the operation of the display panel provided in this application embodiment;

[0029] Figure 21 This is a schematic diagram of the structure of a display panel provided in an embodiment of this application;

[0030] Figure 22 This is yet another circuit diagram of the pixel circuit in the display panel provided in an embodiment of this application;

[0031] Figure 23 for Figure 22 The diagram shows a driving timing sequence corresponding to a pixel circuit.

[0032] Figure 24 This is a schematic diagram of a display device provided in an embodiment of this application. Detailed Implementation

[0033] The features and exemplary embodiments of various aspects of this application will be described in detail below. To make the objectives, technical solutions, and advantages of this application clearer, the application will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are only intended to explain this application and not to limit it. For those skilled in the art, this application can be implemented without some of these specific details. The following description of the embodiments is merely to provide a better understanding of this application by illustrating examples.

[0034] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising..." does not exclude the presence of additional identical elements in the process, method, article, or apparatus that includes said element.

[0035] It should be understood that the term "and / or" used in this article is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, and B existing alone. Additionally, the character " / " in this article generally indicates that the preceding and following related objects have an "or" relationship.

[0036] It should be noted that the transistors in the embodiments of this application can be either N-type or P-type transistors. For N-type transistors, the on-state level is high and the off-state level is low. That is, when the gate of an N-type transistor is high, its first and second terminals are connected; when the gate of an N-type transistor is low, its first and second terminals are off. For P-type transistors, the on-state level is low and the off-state level is high. That is, when the control terminal of a P-type transistor is low, its first and second terminals are connected; when the control terminal of a P-type transistor is high, its first and second terminals are off. In specific implementations, the gate of each transistor is used as its control terminal. Furthermore, depending on the signal and type of the gate of each transistor, its first terminal can be used as the source and its second terminal as the drain, or vice versa. No distinction is made here. Additionally, the on-state and off-state levels in the embodiments of this invention are general terms. The on-state level refers to any level that enables the transistor to conduct, and the off-state level refers to any level that enables the transistor to turn off / become off.

[0037] In the embodiments of this application, the term "electrical connection" can refer to two components being directly electrically connected, or it can refer to two components being electrically connected via one or more other components.

[0038] In the embodiments of this application, the first node, the second node, the third node, and the fourth node are defined only for the convenience of describing the circuit structure, and the first node, the second node, the third node, and the fourth node are not actual circuit units.

[0039] Various modifications and variations can be made to this application without departing from its spirit or scope, which will be apparent to those skilled in the art. Therefore, this application is intended to cover modifications and variations falling within the scope of the corresponding claims (the claimed technical solutions) and their equivalents. It should be noted that the embodiments provided in this application can be combined with each other without contradiction.

[0040] Before describing the technical solutions provided in the embodiments of this application, in order to facilitate understanding of the embodiments of this application, this application first specifically explains the problems existing in the related technologies:

[0041] Figure 1 This is a circuit diagram of a pixel circuit. For example... Figure 1As shown, the pixel circuit may include a driving module 11', an emissive control module 12', and a compensation module 13'. The control terminal of the driving module 11' can be electrically connected to a first node N1', the first terminal of the driving module 11' can be electrically connected to a second node N2' (which can receive a first power supply voltage signal), and the second terminal of the driving module 11' can be electrically connected to a third node N3'. The control terminal of the emissive control module 12' can be electrically connected to an emissive control signal line EM', the first terminal of the emissive control module 12' is electrically connected to the third node N3', and the second terminal of the emissive control module 12' is electrically connected to the first electrode of the emissive element D'. The emissive control module 12' is used to control the emissive element D' to emit light. For example, when the emissive control module 12' is turned on, the output current provided by the pixel circuit is transmitted to the first electrode of the emissive element D', causing the emissive element D' to emit light. The control terminal of the compensation module 13' is electrically connected to a scan signal line Sn', the first terminal of the compensation module 13' is electrically connected to the first node N1', and the second terminal of the compensation module 13' is electrically connected to the third node N3'. The compensation module 13' is used to compensate the threshold voltage of the drive module 11'.

[0042] Figure 2 This is a schematic diagram of the driving timing of a pixel circuit. Combined with... Figure 1 and Figure 2 As shown, taking the example where the light-emitting control signal provided by the light-emitting control signal line EM' is at a low level and the scan signal provided by the scan signal line Sn' is at a high level, when the light-emitting control signal is at a high level (e.g., Figure 2 When the signal is at a low level (as shown), the driving current of the pixel circuit is transmitted to the fourth node N4', raising the potential of the fourth node N4', and the light-emitting element D' emits light. The inventors of this application have discovered that when the light-emitting control signal switches from the on level to the off level (as shown), the driving current of the pixel circuit is transmitted to the fourth node N4', raising the potential of the fourth node N4', and the light-emitting element D' emits light. Figure 2 After the high level shown, the discharge of the fourth node N4' takes a period of time. When the time interval 'a' between the end of the conduction level of the light-emitting control signal and the start of the conduction level of the scan signal is small, the fourth node N4' fails to discharge completely and remains at a high potential. When the scan signal switches from low to high, the potential of the fourth node N4' is pulled up again through the parasitic capacitance between the scan signal line Sn' and the fourth node N4' and / or the parasitic capacitance of the light-emitting control module 12'. Because the fourth node N4' fails to discharge completely, the light-emitting element D' is easily caused to emit light again after its potential is pulled up again, resulting in flickering. Moreover, this flickering phenomenon is particularly noticeable at lower refresh rates and lower gray levels.

[0043] In view of the inventors’ above-mentioned research findings, the present application provides a display panel and a display device that can solve the technical problem of flickering in display panels in related technologies.

[0044] The technical concept of this application embodiment lies in increasing the time interval between the non-light-emitting stage and the first preset stage, thereby stabilizing the potential of the node between the second light-emitting control module and the driving transistor, and the node between the second light-emitting control module and the light-emitting element (i.e., the first electrode of the light-emitting element), allowing the potential of the first electrode of the light-emitting element to fully discharge to a lower potential. Since the potential of the first electrode of the light-emitting element has been fully discharged to a lower potential, even if the potential of the first electrode of the light-emitting element is pulled up again under the coupling effect of parasitic capacitance, the pulled-up potential of the first electrode of the light-emitting element is still relatively small, and the light-emitting element is less likely to emit light again. This effectively improves the flickering phenomenon and enhances the display effect of the display panel.

[0045] The display panel provided in the embodiments of this application will be described first below.

[0046] Figure 3 This is a schematic diagram of a display panel provided in an embodiment of this application. Figure 3 As shown, the display panel 30 may include pixel circuitry 31 and light-emitting elements D. Exemplarily, the light-emitting element D includes, but is not limited to, organic light-emitting diodes (OLEDs), inorganic light-emitting diodes (LEDs), or quantum dot (QD) diodes. Inorganic light-emitting diodes may include, for example, mini light-emitting diodes (mini LEDs), micro light-emitting diodes (micro LEDs), or quantum dot light-emitting diodes (QLEDs), but this embodiment is not limited thereto.

[0047] Figure 4 This is a schematic diagram of a pixel circuit in a display panel provided in an embodiment of this application. Figure 4As shown, the pixel circuit 31 may include a driving module 311, a light-emitting control module 312, and a compensation module 313. The driving module 311 may include a driving transistor T1, which may include a gate g1, a first electrode a1, and a second electrode a2. The gate g1 of the driving transistor T1 may be electrically connected to a first node N1, the first electrode a1 of the driving transistor T1 may be electrically connected to a second node N2, and the second electrode a2 of the driving transistor T1 may be electrically connected to a third node N3. The light-emitting control module 312 may include a first light-emitting control module 312a and a second light-emitting control module 312b. The first light-emitting control module 312a may be connected between the first power signal line VDD and the driving transistor T1. For example, the control terminal of the first light-emitting control module 312a may be electrically connected to the first light-emitting control signal line EM1, the first terminal of the first light-emitting control module 312a may be electrically connected to the first power signal line VDD, and the second terminal of the first light-emitting control module 312a may be electrically connected to the first electrode a1 of the driving transistor T1. For example, the first power signal line VDD can be used to provide a first power signal with a positive voltage value.

[0048] The second light-emitting control module 312b can be connected between the driving transistor T1 and the light-emitting element D. For example, the control terminal of the second light-emitting control module 312b can be electrically connected to the second light-emitting control signal line EM2, the first terminal of the second light-emitting control module 312b can be electrically connected to the second electrode a2 of the driving transistor T1, and the second terminal of the second light-emitting control module 312b can be electrically connected to the first electrode of the light-emitting element D. The second electrode of the light-emitting element D can be electrically connected to the second power signal line VEE. The first electrode of the light-emitting element D can include the anode of the light-emitting element D, and the second electrode of the light-emitting element D can include the cathode of the light-emitting element D. Exemplarily, the second power signal line VEE can be used to provide a second power signal with a negative voltage value.

[0049] It should be noted that in some examples, the second light emission control signal line EM2 can reuse the first light emission control signal line EM1. In other examples, the second light emission control signal line EM2 may not reuse the first light emission control signal line EM1, and this application embodiment does not limit this.

[0050] The compensation module 313 can be connected between the gate g1 and the second terminal a2 of the driving transistor T1. For example, the control terminal of the compensation module 313 can be electrically connected to the first scan signal line Sn1, the first terminal of the compensation module 313 can be electrically connected to the gate g1 of the driving transistor T1, and the second terminal of the compensation module 313 can be electrically connected to the second terminal a2 of the driving transistor T1. The compensation module 313 can be used to compensate for the threshold voltage of the driving transistor T1.

[0051] Figure 5 This is a schematic diagram illustrating the driving timing of a pixel circuit in a display panel provided in an embodiment of this application. (In conjunction with...) Figure 4 and Figure 5 As shown, the compensation module 313 is activated for a preset period t1. During the preset period t1, the first scan signal provided by the first scan signal line Sn1 can be at a conduction level, and the compensation module 313 is activated in response to the conduction level provided by the first scan signal line Sn1. Figure 5 The example is illustrated with the first scan signal being at a high conduction level. That is, the compensation module 313 may include an N-type transistor. In some specific examples, the compensation module 313 may include a low-temperature polycrystalline oxide (LTPO) transistor, thereby reducing the leakage current of the gate g1 of the driving transistor T1 and improving the flicker problem of the display panel during low-frequency driving.

[0052] The operation of pixel circuit 31 can include a non-light-emitting stage nf and a light-emitting stage f.

[0053] During the light-emitting stage f, the first light-emitting control module 312a and the second light-emitting control module 312b are turned on. During the light-emitting stage f, the driving current of the pixel circuit 31 is transmitted to the first electrode of the light-emitting element D, and the light-emitting element D emits light.

[0054] During the non-light-emitting phase nf, at least the second light-emitting control module 312b is turned off. The first light-emitting control module 312a may also be turned off or not; this embodiment does not limit this. Since at least the second light-emitting control module 312b is turned off, the nf pixel circuit 31 does not provide driving current to the first electrode of the light-emitting element D during the non-light-emitting phase, and the light-emitting element D does not emit light.

[0055] During the non-light-emitting phase nf, the time length t2 between the second light-emitting control module 312b being turned off and the start of the first preset phase t1 is L1, and the time length of the first preset phase t1 is W1. Specifically, the first preset phase t1 can be understood as the first preset phase t1 in the next light-emitting cycle. That is, the time length L1 can be the length of the time period t2 between the second light-emitting control module 312b being turned off and the start of the first preset phase t1 in the next light-emitting cycle. Alternatively, it can be understood as the minimum time interval between the second light-emitting control module 312b being turned off and the preset phase t1 in the next light-emitting cycle.

[0056] In this embodiment, L1 > W1, ensuring that the time interval t2 between the non-light-emitting stage and the first preset stage has a relatively long duration. Therefore, after time interval t2, the node between the second light-emitting control module and the driving transistor (e.g., Figure 4 The third node N3 shown) and the node between the second light-emitting control module and the light-emitting element (as shown) Figure 4 The potential of the fourth node (N4) shown can be stabilized, allowing the potential of the fourth node N4 (i.e., the potential of the first electrode of the light-emitting element) to fully discharge to a lower potential. Thus, since the potential of the first electrode of the light-emitting element has been fully discharged to a lower potential, even if the potential of the first electrode of the light-emitting element is pulled up again due to the coupling effect of parasitic capacitance, the pulled-up potential of the first electrode of the light-emitting element is still relatively small, and the light-emitting element is less likely to emit light again. This effectively improves the flickering phenomenon and enhances the display effect of the display panel.

[0057] The inventors of this application further realized that at the end of the preset stage t1, if the first scan signal provided by the first scan signal line Sn1 switches from a high level to a low level (i.e., the potential jumps low), the parasitic capacitance between the first scan signal line Sn1 and the fourth node N4 and / or the parasitic capacitance of the light emission control module 12' may affect the potential of the fourth node N4.

[0058] If the time interval t3 between the end time of the preset stage t1 and the start time of the second light-emitting control module 312b is short, it may affect the potential of the fourth node N4 in the light-emitting stage f, which may in turn affect the brightness of the light-emitting element, such as causing the brightness of the light-emitting element to be low or fluctuate.

[0059] In view of this, this application considers increasing the time period t3 between the end time of the preset stage t1 and the start time of the second light-emitting control module 312b, thereby reducing the influence of the parasitic capacitance coupling effect on the potential of the fourth node N4 in the light-emitting stage f, so that the brightness of the light-emitting element can reach the expected brightness and improve the flicker problem.

[0060] Figure 6 This is another driving timing diagram of the pixel circuit in the display panel provided in an embodiment of this application. (In conjunction with...) Figure 4 and Figure 6 As shown, according to some embodiments of this application, optionally, in the non-light-emitting stage nf, the time length of the time period t3 between the end of the last preset stage t1 and the start of the second light-emitting control module 312b is Ln, and the time length of the last preset stage t1 is Wn. Figure 6Taking a non-light-emitting stage nf that includes a preset stage t1 as an example, in other embodiments, the non-light-emitting stage nf may also include multiple preset stages t1, and this application embodiment does not limit this. The time length Ln can be understood as the minimum time interval between the end time of the preset stage t1 and the turn-on time of the second light-emitting control module 312b. For example, when the non-light-emitting stage nf includes multiple preset stages t1, the time length Ln may be the time interval between the end time of the preset stage t1 closest to the turn-on time of the second light-emitting control module 312b and the turn-on time of the second light-emitting control module 312b.

[0061] Where Ln > Wn. This ensures that the time period t3 between the end of the last preset stage t1 and the activation of the second light-emitting control module 312b has a relatively long duration, reducing the impact of parasitic capacitance coupling on the potential of the fourth node N4 in the light-emitting stage f, so that the brightness of the light-emitting element can reach the expected brightness and improve the flicker problem.

[0062] According to some embodiments of this application, optionally, the non-light-emitting stage may include N preset stages, where N≥1 and N is an integer.

[0063] See also Figure 6 In some embodiments, for example, N=1, that is, the non-light-emitting stage nf may include a preset stage t1. Since there is only one preset stage t1, the first preset stage t1 and the last preset stage t1 are the same preset stage t1, so W1=Wn.

[0064] Figure 7 This is another driving timing diagram of the pixel circuit in the display panel provided in an embodiment of this application. For example... Figure 7 As shown, in some other examples, N can be greater than 1, meaning the non-luminescent stage nf can include multiple preset stages t1. When N > 1, the duration W1 of the first preset stage t1 can be equal to the duration Wn of the last preset stage t1. This helps improve the uniformity of the first scan signal and reduces its complexity. Of course, when N > 1, the duration W1 of the first preset stage t1 may not be equal to the duration Wn of the last preset stage t1. This increases the flexibility of the first scan signal adjustment to meet different application scenarios. Figure 7 For example, let's take W1 = Wn as an example.

[0065] Figure 8 This is another circuit diagram of the pixel circuit in the display panel provided in an embodiment of this application. For example... Figure 8As shown, according to some embodiments of this application, optionally, the pixel circuit 31 may further include a data writing module 314, which may be connected to the first terminal a1 of the driving transistor T1. For example, the control terminal of the data writing module 314 is electrically connected to the second scan signal line S2, the first terminal of the data writing module 314 is electrically connected to the data signal line data, and the second terminal of the data writing module 314 is electrically connected to the first terminal a1 of the driving transistor T1. The data writing module 314 can be turned on under the control of the second scan signal line S2 to provide a data signal to the driving transistor T1.

[0066] Figure 9 This is another driving timing diagram of the pixel circuit in the display panel provided in an embodiment of this application. For example... Figure 9 As shown, the operation of the pixel circuit can include a data writing stage t4. Figure 9 The example is illustrated using the second scan signal provided by the second scan signal line S2 as an example where the on-state level is low. Combined with... Figure 8 and Figure 9 As shown, during the data writing phase t4, the data writing module 314 and the compensation module 313 are turned on, and the data writing module 314 provides a data signal to the driving transistor T1. Specifically, during the data writing phase t4, the data writing module 314 responds to the conduction level provided by the second scan signal line S2 (e.g., ...). Figure 9 When the low level shown is turned on, the compensation module 313 responds to the turn-on level provided by the first scan signal line Sn1 (such as...). Figure 9 When the high level shown is turned on, the data signal of the data signal line data is written to the gate g1 of the driving transistor T1 in sequence through the data writing module 314, the driving transistor T1 and the compensation module 313.

[0067] Thus, during the data writing stage t4, the data writing module 314 and the compensation module 313 are turned on, which ensures that the data signal is successfully written to the gate g1 of the driving transistor T1, completing the data writing.

[0068] See also Figure 9 According to some embodiments of this application, optionally, N=1, that is, the non-light-emitting stage nf may include a preset stage t1. The time length of the data writing stage t4 is Wd. The preset stage t1 may cover the data writing stage t4, and W1=Wn>Wd. For example, in some examples, the start time of the preset stage t1 may be earlier than the start time of the data writing stage t4, and the end time of the preset stage t1 may be later than the end time of the data writing stage t4.

[0069] In other words, combining Figure 8 and Figure 9As shown, the compensation module 313 can be turned on a certain period of time before the data writing module 314 is turned on; and the compensation module 313 can be turned off a certain period of time before the data writing module 314 is turned off. In this way, on the one hand, since the preset stage t1 covers the data writing stage t4, sufficient time can be ensured to complete the writing of the data signal; on the other hand, turning on the compensation module 313 a certain period of time in advance and turning it off a certain period of time in advance can ensure that the compensation module 313 is in a stable on state when the data writing module 314 is writing the data signal, thereby ensuring the accuracy of the data signal writing and ensuring that the potential of the gate g1 of the driving transistor T1 reaches the expected potential.

[0070] Figure 10 This is another driving timing diagram of the pixel circuit in the display panel provided in an embodiment of this application. For example... Figure 10 As shown, with Figure 9 Unlike the illustrated embodiments, in other embodiments of this application, optionally, N > 1, meaning the non-light-emitting stage nf may include multiple preset stages t1. The i-th preset stage t1 covers the data writing stage t4, and Wi > Wd. Wd is the time length of the data writing stage t4, Wi is the time length of the i-th preset stage t1, and 1 ≤ i ≤ N. Figure 10 For example, the example is 1 < i < N. The values ​​of i and N can be flexibly adjusted according to the actual situation, and this application does not limit them.

[0071] For example, in some examples, the start time of the i-th preset stage t1 may be earlier than the start time of the data writing stage t4, and the end time of the i-th preset stage t1 may be later than the end time of the data writing stage t4.

[0072] In other words, combining Figure 8 and Figure 10 As shown, the compensation module 313 can be turned on a certain period of time before the data writing module 314 is turned on; and the compensation module 313 can be turned off a certain period of time before the data writing module 314 is turned off. In this way, on the one hand, since the i-th preset stage t1 covers the data writing stage t4, sufficient time can be ensured to complete the writing of the data signal; on the other hand, turning on the compensation module 313 a certain period of time in advance and turning off the compensation module 313 a certain period of time in advance can ensure that the compensation module 313 is in a stable on state when the data writing module 314 writes the data signal, thereby ensuring the accuracy of the data signal writing and making the potential of the gate g1 of the driving transistor T1 reach the expected potential.

[0073] Figure 11 This is another driving timing diagram of the pixel circuit in the display panel provided in an embodiment of this application. For example... Figure 11 As shown, with Figure 9 Unlike the illustrated embodiments, in some other embodiments of this application, optionally, N > 1, meaning the non-light-emitting stage nf may include multiple preset stages t1. The Nth preset stage t1 covers the data writing stage t4, and Wn > Wd. That is, in the non-light-emitting stage nf, the last preset stage t1 covers the data writing stage t4. The size of N can be flexibly adjusted according to actual conditions, and this application does not limit this.

[0074] For example, in some examples, the start time of the Nth preset stage t1 can be earlier than the start time of the data writing stage t4, and the end time of the Nth preset stage t1 can be later than the end time of the data writing stage t4. That is, combining... Figure 8 and Figure 11 As shown, the compensation module 313 can be turned on a certain period of time before the data writing module 314 is turned on; and the compensation module 313 can be turned off a certain period of time before the data writing module 314 is turned off.

[0075] In this way, on the one hand, since the Nth preset stage t1 covers the data writing stage t4, it can be guaranteed that there is enough time to complete the writing of the data signal; on the other hand, by turning on the compensation module 313 a certain period of time in advance and turning off the compensation module 313 a certain period of time after the data writing module 314 writes the data signal, it can be guaranteed that the compensation module 313 is in a stable on state, thereby ensuring the accuracy of the data signal writing and making the potential of the gate g1 of the driving transistor T1 reach the expected potential.

[0076] On the other hand, since the Nth preset stage t1 covers the data writing stage t4, the compensation module 313 will not be turned on again before the light emission stage f, which can ensure the stability of the potential of the gate g1 of the driving transistor T1, thereby ensuring that the brightness of the light emission element can reach the expected brightness.

[0077] See also Figure 11 According to some embodiments of this application, optionally, when the Nth preset stage t1 covers the data writing stage t4, Wn > Wj, 1 ≤ j ≤ N-1. That is, the time length Wn of the Nth preset stage t1 can be greater than the time length of any one or more preset stages t1 located before the Nth preset stage t1.

[0078] In this way, ensuring that the Nth preset stage t1 has a relatively long time length Wn allows it to fully cover the data writing stage t4, thus guaranteeing sufficient time to complete the data signal writing. On the other hand, by enabling the compensation module 313 a considerable period in advance and deactivating it a considerable period in advance, it is largely ensured that the compensation module 313 is stably enabled when the data writing module 314 writes the data signal, thereby ensuring the accuracy of the data signal writing and ensuring that the potential of the gate g1 of the driving transistor T1 reaches the expected potential.

[0079] Figure 12 This is yet another circuit diagram of the pixel circuit in the display panel provided in an embodiment of this application. For example... Figure 12 As shown, according to some embodiments of this application, the pixel circuit 31 may optionally include a bias adjustment module 315, which may be connected to the first pole a1 or the second pole a2 of the driving transistor T1. Figure 12 For example, the bias adjustment module 315 is connected to the first terminal a1 of the driving transistor T1. However, in other embodiments, the bias adjustment module 315 can also be connected to the second terminal a2 of the driving transistor T1, with the same or similar effect. This application does not limit this aspect. Figure 12 For example, in some examples, the control terminal of the bias adjustment module 315 can be electrically connected to the third scan signal line S3, the first terminal of the bias adjustment module 315 can be electrically connected to the bias adjustment signal line DVH, and the second terminal of the bias adjustment module 315 can be electrically connected to the first terminal a1 of the driving transistor T1. The bias adjustment module 315 can be turned on in response to the conduction level provided by the third scan signal line S3, transmitting the bias adjustment signal of the bias adjustment signal line DVH to the first terminal a1 of the driving transistor T1. Since the driving transistor T1 is turned on under the control of the first node N1, the bias adjustment signal can be transmitted through the driving transistor T1 to the second terminal a2 of the driving transistor T1, so that the potential of the second terminal a2 of the driving transistor T1 is higher than or equal to the potential of the gate g1 of the driving transistor T1, thereby reducing the degree of ion polarization inside the driving transistor T1, such as reducing the threshold voltage Vth of the driving transistor T1, and realizing the adjustment of the offset state of the threshold voltage Vth of the driving module.

[0080] Figure 13 This is another driving timing diagram of the pixel circuit in the display panel provided in the embodiments of this application. (Combined with...) Figure 12 and Figure 13 As shown, the operation of the pixel circuit may also include a bias adjustment stage p, which may include a first type of bias adjustment stage p1 and / or a second type of bias adjustment stage p2. Figure 13The example shown is that the bias adjustment stage p includes both the first type of bias adjustment stage p1 and the second type of bias adjustment stage p2. However, in other embodiments, the bias adjustment stage p may only include the first type of bias adjustment stage p1 or only include the second type of bias adjustment stage p2. This application does not limit this.

[0081] During the first type of bias adjustment phase p1, the compensation module 313 is activated. For example, in some specific examples, during the first type of bias adjustment phase p1, the compensation module 313 may respond to the on-level of the first scan signal line Sn1 (e.g., Figure 13 When the high level shown is turned on, the bias adjustment module 315 can respond to the on-state level provided by the third scan signal line S3 (such as...). Figure 13 When the low level shown is turned on, the bias adjustment signal of the bias adjustment signal line DVH is transmitted sequentially through the bias adjustment module 315, the driving transistor T1 and the compensation module 313 to the gate g1 of the driving transistor T1, so that the potential of the second pole a2 of the driving transistor T1 is equal to the potential of the gate g1 of the driving transistor T1, thereby adjusting the offset state of the threshold voltage of the driving transistor T1.

[0082] During the second type of bias adjustment phase p2, the compensation module 313 is turned off. For example, in some specific examples, during the second type of bias adjustment phase p2, the compensation module 313 may respond to the cutoff level of the first scan signal line Sn1 (e.g., Figure 13 When the low level shown is turned off, the bias adjustment module 315 can respond to the on level provided by the third scan signal line S3 (such as...). Figure 13 When the low level shown is turned on, the bias adjustment signal of the bias adjustment signal line DVH is transmitted to the second terminal a2 of the driving transistor T1 through the bias adjustment module 315 and the driving transistor T1, so that the potential of the second terminal a2 of the driving transistor T1 is higher than the potential of the gate g1 of the driving transistor T1, thereby adjusting the offset state of the threshold voltage of the driving transistor T1.

[0083] In this way, by adjusting the threshold voltage offset state of the driving transistor T1 through the bias adjustment module 315, it is beneficial to make the brightness of the first few frames after the screen switch reach the expected brightness, and further improve the flicker problem.

[0084] Figure 14 This is another driving timing diagram of the pixel circuit in the display panel provided in an embodiment of this application. For example... Figure 14 As shown, according to some embodiments of this application, optionally, the non-light-emitting stage nf may include at least one first-type bias adjustment stage p1 and a data writing stage t4. The duration of the first-type bias adjustment stage p1 is Ws, and the duration of the data writing stage t4 is Wd.

[0085] N > 1, meaning the non-light-emitting stage nf can include multiple preset stages t1. Among them, the x-th preset stage t1 can cover the first type of bias adjustment stage p1, and the y-th preset stage t1 can cover the data writing stage t4, 1 ≤ x ≤ N, 1 ≤ y ≤ N. Figure 14 Taking x≠y as an example, such as x=1, y=N, but in other embodiments, x can also be equal to y, that is, the first type of bias adjustment stage p1 and the data writing stage t4 can be covered by the same preset stage t1.

[0086] The time length of the x-th preset stage t1 is Wx, and the time length of the y-th preset stage t1 is Wy. Where Wx > Ws, Wy > Wd. That is, the time length of the x-th preset stage t1 is greater than the time length of the first type of bias adjustment stage p1, and the time length of the y-th preset stage t1 is greater than the time length of the data writing stage t4.

[0087] For example, in some specific embodiments, the start time of the xth preset stage t1 may be earlier than the start time of the first type of bias adjustment stage p1, and the end time of the xth preset stage t1 may be later than the end time of the first type of bias adjustment stage p1. The start time of the yth preset stage t1 may be earlier than the start time of the data writing stage t4, and the end time of the yth preset stage t1 may be later than the end time of the data writing stage t4.

[0088] Thus, on the one hand, since the x-th preset stage t1 covers the first type of bias adjustment stage p1, sufficient time can be ensured to complete the writing of the bias adjustment signal, thereby better achieving the adjustment of the threshold voltage offset state of the driving transistor T1; on the other hand, turning on the compensation module 313 a certain period of time in advance and turning off the compensation module 313 a certain period of time in a certain period of time can ensure that the compensation module 313 is in a stable on state when the data writing module 314 writes the bias adjustment signal, thereby ensuring the accuracy of the bias adjustment signal writing, such as making the potential of the second electrode a2 of the driving transistor T1 reach the expected potential.

[0089] Similarly, since the y-th preset stage t1 covers the data writing stage t4, it can be ensured that there is enough time to complete the writing of the data signal; on the other hand, turning on the compensation module 313 a certain period of time in advance and turning off the compensation module 313 a certain period of time in a certain period of time can ensure that the compensation module 313 is in a stable on state when the data writing module 314 writes the data signal, thereby ensuring the accuracy of the data signal writing and making the potential of the gate g1 of the driving transistor T1 reach the expected potential.

[0090] In some embodiments, the data writing stage t4 may be later than the first type of bias adjustment stage p1. This ensures that the potential of the gate g1 of the driving transistor T1 remains stable after the data signal is written and before the light emission stage f, thereby ensuring that the brightness of the light-emitting element reaches the expected brightness.

[0091] Of course, in other embodiments, at least one first type bias adjustment stage p1 may also be located after the data writing stage t4. For example, the voltage value of the bias adjustment signal written in the last first type bias adjustment stage p1 may be the same as the voltage value of the data signal written in the data writing stage t4, thereby ensuring that the potential of the gate g1 of the driving transistor T1 can reach the preset target potential, thereby ensuring that the brightness of the light-emitting element can reach the expected brightness.

[0092] Figure 15 This is another driving timing diagram of the pixel circuit in the display panel provided in an embodiment of this application. For example... Figure 15 As shown, with Figure 14 Unlike the illustrated embodiment, according to other embodiments of this application, optionally, the first type of bias adjustment stage p1 and the data writing stage t4 can be covered by the same preset stage t1.

[0093] Specifically, the non-light-emitting stage nf may include at least one first-type bias adjustment stage p1 and a data writing stage t4. The duration of the first-type bias adjustment stage p1 is Ws, and the duration of the data writing stage t4 is Wd.

[0094] When N=1, the non-light-emitting stage nf can include a preset stage t1. The preset stage t1 can cover the first type of bias adjustment stage p1 and the data writing stage t4. It should be noted that when N>1, the first type of bias adjustment stage p1 and the data writing stage t4 can be covered by any one of the N preset stages t1; this embodiment does not limit this.

[0095] Wherein, W1 = Wn > (Ws + Wd). That is, the time length W1 (or Wn) of the preset stage t1 is greater than the sum of the time length Ws of the first type of bias adjustment stage p1 and the time length Wd of the data writing stage t4.

[0096] Thus, since W1 = Wn > (Ws + Wd), there is enough time to complete the writing of the bias adjustment signal, which can better achieve the adjustment of the threshold voltage offset state of the driving transistor T1, and there is enough time to complete the writing of the data signal.

[0097] For example, in some specific embodiments, the first type of bias adjustment phase p1 may be located before the data writing phase t4, the start time of the preset phase t1 may be earlier than the start time of the first type of bias adjustment phase p1, the end time of the first type of bias adjustment phase p1 may be earlier than the start time of the data writing phase t4, and the end time of the preset phase t1 may be later than the end time of the data writing phase t4.

[0098] Combination Figure 12 and Figure 15 As shown, since there is at least a first-type bias adjustment stage p1 between the start time of the data writing stage t4 and the start time of the preset stage t1, the compensation module 313 will be turned on a relatively long time in advance. This ensures that when the data writing module 314 is turned on, the compensation module 313 is in a stable on state, thereby ensuring the accuracy of the data signal writing.

[0099] Through long-term research, the inventors of this application have discovered that when the time interval L1 between the second light-emitting control module being turned off and the start of the first preset stage t1 is greater than or equal to 20µs, after time interval t2, the node between the second light-emitting control module and the driving transistor (e.g., Figure 12 The third node N3 shown) and the node between the second light-emitting control module and the light-emitting element (as shown) Figure 12 The potential of the fourth node N4 shown has basically stabilized, and the potential of the fourth node N4 (i.e. the potential of the first electrode of the light-emitting element) has been basically fully discharged to a lower potential.

[0100] In view of this, in some embodiments, L1 ≥ 20 μs. For example, in some specific embodiments, L1 may be greater than or equal to 40 μs, 60 μs, 100 μs or 200 μs, etc., and the embodiments of this application do not limit this.

[0101] In this way, since the potential of the first electrode of the light-emitting element has been fully discharged to a lower potential, even if the potential of the first electrode of the light-emitting element is pulled up again under the coupling effect of parasitic capacitance, the potential of the first electrode of the light-emitting element after the pull-up is still small, and the light-emitting element is also more difficult to emit light again. This can effectively improve the flickering phenomenon and enhance the display effect of the display panel.

[0102] Through long-term research, the inventors of this application have discovered that when the time length Ln of the time period t3 between the end of the last preset stage t1 and the start of the second light-emitting control module is greater than or equal to 20us, after the time period t3, the charge generated by the coupling of parasitic capacitance has been basically released, and the effect on the potential of the fourth node N4 in the light-emitting stage f is very small.

[0103] In view of this, in some embodiments, Ln ≥ 20 μs. For example, in some specific embodiments, Ln can be greater than or equal to 40 μs, 60 μs, 100 μs, or 200 μs, etc., and the embodiments of this application do not limit this.

[0104] In this way, the effect of parasitic capacitance coupling on the potential of the fourth node N4 in the light-emitting stage f can be reduced to a large extent, so that the brightness of the light-emitting element can reach the expected brightness and improve the flicker problem.

[0105] In some embodiments, the display panel can support multiple display modes. For example, the brightness of the display panel can differ in different modes. And / or, the base frequency of the display panel can differ in different modes. The base frequency can be the number of on-state (e.g., low-level) light emission control signals within a preset duration (e.g., 1 second), i.e., the number of times light emission occurs within the preset duration. For example, when the base frequency is 60Hz, the number of on-state light emission control signals received by a pixel circuit within the preset duration is 60. When the base frequency is 120Hz, the number of on-state light emission control signals received by a pixel circuit within the preset duration is 120.

[0106] According to some embodiments of this application, optionally, the operation of the display panel may include a first mode and a second mode. Figure 16 This is another driving timing diagram of the pixel circuit in the display panel provided in an embodiment of this application. For example... Figure 16 As shown, in the first mode M1, the non-luminescent phase nf is the first non-luminescent phase nf1, and the duration of the first non-luminescent phase nf1 is S11. In the second mode M2, the non-luminescent phase nf is the second non-luminescent phase nf2, and the duration of the second non-luminescent phase nf2 is S22. S11 and S22 can be different.

[0107] For example, in some examples, the brightness of the display panel in the first mode M1 can be different from the brightness of the display panel in the second mode M2. For example, the brightness of the display panel in the first mode M1 can be less than the brightness of the display panel in the second mode M2. That is, the first mode M1 can be a low-brightness mode, and the second mode M2 ​​can be a high-brightness mode. Accordingly, S11 > S22. That is, when the display panel operates in a low-brightness mode, the duration of the first non-emitting phase nf1 can be longer, which can reduce the duty cycle of the light-emitting control signal, thereby making the brightness of the display panel lower. When the display panel operates in a high-brightness mode, the duration of the first non-emitting phase nf1 can be shorter, which can increase the duty cycle of the light-emitting control signal, thereby making the brightness of the display panel higher.

[0108] For example, in some examples, the base frequency of the display panel in the first mode M1 may be different from the base frequency of the display panel in the second mode M2. For example, the base frequency of the display panel in the first mode M1 may be lower than the base frequency of the display panel in the second mode M2. Accordingly, S11 > S22. Since the preset duration (e.g., 1 second) is constant, when the base frequency is low, the number of on-level and off-level light emission control signals is small, and therefore the pulse width of the on-level and off-level light emission control signals is long. Therefore, when the display panel operates in a low base frequency mode, the duration of the first non-light emission phase nf1 can be large, which can reduce the number of off-level light emission control signals, thereby making the base frequency of the display panel low. When the display panel operates in a high base frequency mode, the duration of the first non-light emission phase nf1 can be small, which can increase the number of off-level light emission control signals, thereby making the base frequency of the display panel high.

[0109] Combination Figure 12 and Figure 16 As shown, according to some embodiments of this application, optionally, in the first non-light-emitting stage nf1, the time period t2 between the second light-emitting control module 312b being turned off and the start of the first preset stage t1 is L11, and the time period t1 is W11. In the second non-light-emitting stage nf2, the time period t2 between the second light-emitting control module 312b being turned off and the start of the first preset stage t1 is L21, and the time period t1 is W21.

[0110] Wherein, L11 > L21. That is, when the brightness of the display panel in the first mode M1 is less than the brightness of the display panel in the second mode M2, and / or when the base frequency of the display panel in the first mode M1 is less than the base frequency of the display panel in the second mode M2, the time length L11 corresponding to the first mode M1 can be greater than the time length L21 corresponding to the second mode M2.

[0111] As mentioned earlier, flickering is more pronounced at lower gray levels and lower fundamental frequencies. Therefore, setting L11 > L21 can further increase the time length between the non-emitting phase and the first preset phase t2 under lower gray levels and / or lower fundamental frequencies. This ensures that, under lower gray levels and / or lower fundamental frequencies, after time period t2, the node between the second light-emitting control module and the driving transistor (e.g., ...) remains constant. Figure 12 The third node N3 shown) and the node between the second light-emitting control module and the light-emitting element (as shown) Figure 12The potential of the fourth node N4 shown tends to stabilize to a large extent, allowing the potential of the fourth node N4 (i.e., the potential of the first electrode of the light-emitting element) to fully discharge to a lower potential. This effectively improves flickering at lower grayscale levels and / or lower fundamental frequencies, enhancing the display panel's performance.

[0112] Combination Figure 12 and Figure 16 As shown, according to some embodiments of this application, optionally, L11 > W11 and L21 > W21. That is, in some examples, the duration of the first non-light-emitting stage nf1 can be made to meet the expected requirements by lengthening the time period t2 between the second light-emitting control module 312b being turned off and the start of the first preset stage t1.

[0113] This not only ensures that the duration of the first non-emissive phase nf1 meets the expected requirements, but also guarantees a longer time interval t2 between the non-emissive phase and the first preset phase under lower grayscale and / or lower fundamental frequency conditions, and also guarantees a longer time interval t2 between the non-emissive phase and the first preset phase under higher grayscale and / or higher fundamental frequency conditions. This significantly improves flickering at lower grayscale and / or lower fundamental frequency conditions, and also significantly enhances the display panel's display performance.

[0114] Figure 17 This is another driving timing diagram of the pixel circuit in the display panel provided in an embodiment of this application. For example... Figure 17 As shown, according to some embodiments of this application, optionally, L11 > W11 and L21 < W21. As mentioned above, when the display panel operates in a high-brightness mode or a high-fundamental-frequency mode, the duration of the first non-emitting phase nf1 is short, and the preset phase t1 needs to be guaranteed to have a certain duration. Therefore, in the second mode M2, L21 can be less than W21 so that the duration of the first non-emitting phase nf1 in the second mode M2 ​​meets the preset requirements, thereby ensuring that the display panel can operate in a high-brightness mode or a high-fundamental-frequency mode.

[0115] Furthermore, flickering is relatively less noticeable at higher grayscale levels and / or higher fundamental frequencies. Therefore, in some examples, L21 < W21 can be set so that the duration of the first non-emitting phase nf1 in the second mode M2 ​​meets the preset requirements, thereby ensuring that the display panel can operate in a higher brightness mode or a higher fundamental frequency mode.

[0116] Furthermore, by setting L11 > L21, the time length between the non-emitting stage and the first preset stage t2 under lower grayscale and / or lower fundamental frequency conditions can be further increased. Therefore, it can be guaranteed that under lower grayscale and / or lower fundamental frequency conditions, after time period t2, the node between the second light-emitting control module and the driving transistor (e.g., ...) remains constant. Figure 12 The third node N3 shown) and the node between the second light-emitting control module and the light-emitting element (as shown) Figure 12 The potential of the fourth node N4 shown tends to stabilize to a large extent, allowing the potential of the fourth node N4 (i.e., the potential of the first electrode of the light-emitting element) to fully discharge to a lower potential. This effectively improves flickering at lower grayscale levels and / or lower fundamental frequencies, enhancing the display panel's performance.

[0117] See also Figure 17 According to some embodiments of this application, optionally, (L11-W11) > (W21-L21). That is, it is ensured that in the first mode M1, the time period t2 between the second light-emitting control module being turned off and the start of the first preset stage t1 has a relatively long duration. Alternatively, it is ensured that in the second mode M2, W21-L21 is not too large, that is, L21 is not too small.

[0118] This can effectively improve flickering at lower gray levels and / or lower base frequencies, and also effectively improve flickering at higher gray levels and / or higher base frequencies, thereby significantly enhancing the display effect of the display panel.

[0119] Figure 18 This is another driving timing diagram of the pixel circuit in the display panel provided in the embodiments of this application. (Combined with...) Figure 12 and Figure 18 As shown, according to some embodiments of this application, optionally, in the first non-light-emitting stage nf1, the time period t3 between the end of the last preset stage t1 and the activation of the second light-emitting control module 312b is L1n, and the time period t1 is W1n. In the second non-light-emitting stage nf2, the time period t3 between the end of the last preset stage t1 and the activation of the second light-emitting control module 312b is L2n, and the time period t1 is W2n.

[0120] Wherein, L1n≥L2n. That is, when the brightness of the display panel in the first mode M1 is less than the brightness of the display panel in the second mode M2, and / or when the base frequency of the display panel in the first mode M1 is less than the base frequency of the display panel in the second mode M2, the time length L1n corresponding to the first mode M1 can be greater than or equal to the time length L2n corresponding to the second mode M2.

[0121] In other words, under the condition of lower grayscale and / or lower fundamental frequency, the time length of the period t3 between the end of the last preset stage t1 and the start of the second light emission control module 312b can be set to be relatively large.

[0122] Thus, under the conditions of lower grayscale and / or lower fundamental frequency, the time period t3 between the end of the last preset stage t1 and the activation of the second light-emitting control module 312b has a longer duration, which can reduce the influence of the parasitic capacitance coupling effect on the potential of the fourth node N4 in the light-emitting stage f, so that the brightness of the light-emitting element can reach the expected brightness and improve the flicker problem.

[0123] Combination Figure 12 and Figure 18 As shown, according to some embodiments of this application, optionally, L1n > W1n and L2n > W2n. That is, in some examples, the time length of the first non-light-emitting stage nf1 can be made to meet the expected requirements by lengthening the time period t3 between the end of the last preset stage t1 and the start of the second light-emitting control module 312b.

[0124] This approach not only ensures that the duration of the first non-emitting phase nf1 meets the expected requirements, but also minimizes the impact of parasitic capacitance coupling on the potential of the fourth node N4 in the emitting phase f at lower gray levels and / or lower fundamental frequencies. Furthermore, it minimizes the impact of parasitic capacitance coupling on the potential of the fourth node N4 in the emitting phase f at higher gray levels and / or higher fundamental frequencies. This significantly improves the brightness of the light-emitting element, allowing it to reach the expected brightness and reducing flicker.

[0125] Figure 19 This is another driving timing diagram of the pixel circuit in the display panel provided in an embodiment of this application. For example... Figure 19 As shown, according to some embodiments of this application, optionally, L1n > W1n and L2n < W2n. As mentioned above, when the display panel operates in a high-brightness mode or a high-fundamental-frequency mode, the duration of the first non-emissive phase nf1 is short, and the preset phase t1 needs to be guaranteed to have a certain duration. Therefore, in the second mode M2, L2n can be less than W2n, so that the duration of the first non-emissive phase nf1 in the second mode M2 ​​meets the preset requirements, thereby ensuring that the display panel can operate in a high-brightness mode or a high-fundamental-frequency mode.

[0126] Furthermore, flickering is relatively less noticeable at higher grayscale levels and / or higher fundamental frequencies. Therefore, in some examples, setting L2n < W2n can ensure that the duration of the first non-emitting phase nf1 in the second mode M2 ​​meets the preset requirements, thereby guaranteeing that the display panel can operate in a higher brightness mode or a higher fundamental frequency mode.

[0127] Furthermore, by setting L1n > W1n, it can be ensured that the time period t3 between the end of the last preset stage t1 and the start of the second light-emitting control module 312b has a longer duration under the conditions of lower gray levels and / or lower fundamental frequencies. This reduces the influence of parasitic capacitance coupling on the potential of the fourth node N4 in the light-emitting stage f, enabling the brightness of the light-emitting element to reach the expected brightness and improving the flicker problem.

[0128] See also Figure 19 According to some embodiments of this application, optionally, (L1n-W1n) > (W2n-L2n). That is, it is ensured that in the first mode M1, the time period t3 between the end of the last preset stage t1 and the activation of the second light-emitting control module has a relatively long duration. Alternatively, it is ensured that in the second mode M2, W2n-L2n is not too large, that is, L2n is not too small.

[0129] This approach ensures that the coupling effect of parasitic capacitance on the potential of the fourth node N4 in the light-emitting stage f is reduced at lower gray levels and / or lower fundamental frequencies, and also ensures that the coupling effect of parasitic capacitance on the potential of the fourth node N4 in the light-emitting stage f is reduced at higher gray levels and / or higher fundamental frequencies. This allows the brightness of the light-emitting element to largely reach the expected brightness and significantly improves the flicker problem.

[0130] Figure 20 This is a schematic diagram illustrating the operation of a display panel provided in an embodiment of this application. Figure 20 As shown, according to some embodiments of this application, optionally, the operation process of the display panel may include a first time period T1 and a second time period T2, wherein the first time period T1 and the second time period T2 are different time periods.

[0131] Combination Figure 4 and Figure 20As shown, in the first time period T1, the pixel circuit 31 can operate in the first mode M1. In the second time period T2, the pixel circuit 31 can operate in the second mode M2. In some examples, the brightness of the display panel in the first mode M1 may be different from the brightness of the display panel in the second mode M2. And / or, the base frequency of the display panel in the first mode M1 may be different from the base frequency of the display panel in the second mode M2. For example, the brightness of the display panel in the first mode M1 may be less than the brightness of the display panel in the second mode M2. For example, the base frequency of the display panel in the first mode M1 may be less than the base frequency of the display panel in the second mode M2.

[0132] In this way, the pixel circuit can work in different modes at different times to meet different application scenarios.

[0133] Figure 21 This is a schematic diagram of a display panel provided in an embodiment of this application. Figure 21 As shown, according to some embodiments of this application, optionally, the display panel 30 may include a first pixel circuit 31a and a second pixel circuit 31b. The first pixel circuit 31a and the second pixel circuit 31b are pixel circuits 31 at different locations.

[0134] Combination Figure 16 and Figure 21 As shown, during at least a portion of the time period during the operation of the display panel, the first pixel circuit 31a can operate in the first mode M1, and the second pixel circuit 31b can operate in the second mode M2.

[0135] That is, during the same time period, the first pixel circuit 31a can work in the first mode M1 and the second pixel circuit 31b can work in the second mode M2, so that different areas in the display panel can be displayed in different modes to meet user needs.

[0136] For example, in some examples, the display panel 30 may include a first display area A1 and a second display area A2. Both the first display area A1 and the second display area A2 can be used to display an image. The first pixel circuit 31a may be located in the first display area A1, and the second pixel circuit 31b may be located in the second display area A2.

[0137] During the same time period, the first display area A1 can, for example, display in a first mode with lower brightness, and the second display area A2 can, for example, display in a second mode with higher brightness. For example, in some specific application embodiments, the first display area A1 can be used to display an always-on display containing information such as a clock, and the second display area A2 can be used to display complex scenes in games or video scenarios.

[0138] Thus, the first display area A1 of the display panel displays according to the first mode, and the second display area A2 of the display panel displays according to the second mode. That is, different areas of the display panel are displayed according to different modes, which can realize the simultaneous display of multiple screens and meet user needs.

[0139] According to some embodiments of this application, optionally, the data refresh frequency of the first pixel circuit 31a can be Fs1, and the data refresh frequency of the second pixel circuit 31b can be Fs2. Wherein, Fs1 ≠ Fs2. The data refresh frequency is different from the base frequency; it can be the number of times a data signal is written within a preset duration (e.g., 1 second). For example, when the data refresh frequency is 1Hz, only one data signal can be written within the preset duration. When the data refresh frequency is 60Hz, 60 data signals can be written within the preset duration. Therefore, the data refresh frequency can also be understood as the screen refresh frequency.

[0140] Since the first pixel circuit 31a operates in the first mode M1 and the second pixel circuit 31b operates in the second mode M2, the data refresh frequency of the first pixel circuit 31a and the data refresh frequency of the second pixel circuit 31b can be different, thereby meeting the display requirements of different modes and improving the display quality of the first mode M1 and the second mode M2.

[0141] For example, in some specific embodiments, Fs1 < Fs2. As mentioned earlier, the brightness corresponding to the first mode M1 is lower, and the brightness corresponding to the second mode M2 ​​is higher. For example, the first display area A1 is used to display an always-on display containing information such as a clock, and the second display area A2 is used to display complex scenes in games or videos. Therefore, in the first mode M1, a lower data refresh rate can be used to reduce the power consumption of the display panel. In the second mode M2, a higher data refresh rate can be used to improve the smoothness of the image and enhance the user experience.

[0142] In some other specific embodiments, Fs1 may optionally be greater than Fs2. That is, a higher data refresh rate can be used in the first mode M1, and a lower data refresh rate can be used in the second mode M2. This application does not limit this aspect.

[0143] To facilitate understanding of the embodiments of this application, the display panel provided in the embodiments of this application will be illustrated below with reference to the 8T1C pixel circuit.

[0144] Figure 22 This is another circuit diagram of the pixel circuit in the display panel provided in the embodiments of this application. Figure 23 for Figure 22 The diagram shows a driving timing sequence corresponding to a pixel circuit. (Combined with...) Figure 22 and Figure 23 As shown, the pixel circuit 31 includes a driving module 311, an emissive control module 312, a compensation module 313, a data writing module 314, a bias adjustment module 315, a first reset module 316, a second reset module 317, and a storage module 318. The emissive control module 312 may include a first emissive control module 312a and a second emissive control module 312b.

[0145] The driving module 311 may include a driving transistor T1; the first light-emitting control module 312a may include a second transistor T2; the second light-emitting control module 312b may include a third transistor T3; the compensation module 313 may include a fourth transistor T4; the data writing module 314 may include a fifth transistor T5; the bias adjustment module 315 may include a sixth transistor T6; the first reset module 316 may include a seventh transistor T7; the second reset module 317 may include an eighth transistor T8; and the storage module 318 may include a storage capacitor Cst. The connection methods of each transistor and the storage capacitor Cst are as follows: Figure 22 As shown, it will not be elaborated further here.

[0146] In some embodiments, the first light emission control signal line EM1 and the second light emission control signal line EM2 can be reused and uniformly represented by the light emission control signal line EM.

[0147] In some embodiments, the fourth transistor T4 and the seventh transistor T7 can be N-type transistors, and the other transistors can be P-type transistors.

[0148] Figure 23 The example is illustrated using the non-luminescent stage nf, which includes two preset stages t1. Combined with... Figure 22 and Figure 23 As shown, the non-light-emitting stage nf may also include a reset stage t0. In the reset stage t0, the first reset module 316 is turned on under the control of the fourth scan signal line Sn4, and transmits the first reset signal of the first reset signal line Vref1 to the first node N1 to reset the first node N1.

[0149] In the first type of bias adjustment stage p1, the compensation module 313 can be turned on in response to the on-level of the first scan signal line Sn1, and the bias adjustment module 315 can be turned on in response to the on-level provided by the third scan signal line S3. The bias adjustment signal of the bias adjustment signal line DVH is transmitted to the gate g1 of the driving transistor T1 in sequence through the bias adjustment module 315, the driving transistor T1 and the compensation module 313, so that the potential of the second terminal a2 of the driving transistor T1 is equal to the potential of the gate g1 of the driving transistor T1, thereby adjusting the offset state of the threshold voltage of the driving transistor T1.

[0150] During the data writing phase t4, the data writing module 314 is turned on in response to the conduction level provided by the second scan signal line S2, and the compensation module 313 is turned on in response to the conduction level provided by the first scan signal line Sn1. The data signal of the data signal line data is sequentially written to the first node N1 through the data writing module 314, the driving transistor T1, and the compensation module 313. The second reset module 317 is turned on under the control of the second scan signal line S2, and transmits the second reset signal of the second reset signal line Vref2 to the first electrode of the light-emitting element D to reset the first electrode of the light-emitting element D.

[0151] In the second type of bias adjustment stage p2, the compensation module 313 can be turned off in response to the cutoff level of the first scan signal line Sn1, and the bias adjustment module 315 can be turned on in response to the on-level provided by the third scan signal line S3. The bias adjustment signal of the bias adjustment signal line DVH is transmitted to the second terminal a2 of the driving transistor T1 through the bias adjustment module 315 and the driving transistor T1, thereby making the potential of the second terminal a2 of the driving transistor T1 higher than the potential of the gate g1 of the driving transistor T1, thereby adjusting the offset state of the threshold voltage of the driving transistor T1.

[0152] During the light-emitting stage f, the first light-emitting control module 312a and the second light-emitting control module 312b are turned on under the control of the light-emitting control signal line EM. The driving current provided by the pixel circuit 31 is transmitted to the first pole of the light-emitting element D, and the light-emitting element D emits light.

[0153] In this embodiment, the duration L1 of time period t2 is greater than W1, ensuring a relatively long duration of time period t2 between the non-light-emitting stage and the first preset stage. Therefore, after time period t2, the potentials of the third node N3 and the fourth node N4 can stabilize, allowing the potential of the first electrode of the light-emitting element to fully discharge to a lower potential. Since the potential of the first electrode of the light-emitting element has already fully discharged to a lower potential, even if the potential of the first electrode of the light-emitting element is pulled up again due to the coupling effect of parasitic capacitance, the pulled-up potential of the first electrode of the light-emitting element is still relatively small, and the light-emitting element is less likely to emit light again. This effectively improves the flickering phenomenon and enhances the display effect of the display panel.

[0154] In some embodiments, the duration Ln of time period t3 is greater than Wn. This ensures that the time period t3 between the end of the last preset stage t1 and the activation of the second light-emitting control module 312b has a longer duration, reducing the impact of parasitic capacitance coupling on the potential of the fourth node N4 in the light-emitting stage f, so that the brightness of the light-emitting element can reach the expected brightness and improve the flicker problem.

[0155] Based on the display panel provided in the above embodiments, this application also provides a display device, including the display panel provided in this application. Please refer to... Figure 24 , Figure 24 This is a schematic diagram of a display device provided in an embodiment of this application. Figure 24 The provided display device 1000 includes the display panel 30 provided in any of the above embodiments of this application. Figure 24 The embodiments use a mobile phone as an example to describe the display device 1000. It is understood that the display device provided in the embodiments of this application can be other display devices with display functions, such as wearable products, computers, televisions, and in-vehicle display devices. This application does not impose specific limitations on these. The display device provided in the embodiments of this application has the beneficial effects of the display panel 30 provided in the embodiments of this application. For details, please refer to the specific descriptions of the display panel 30 in the above embodiments. These descriptions will not be repeated here.

[0156] It should be understood that the specific circuit structures and display panel timings provided in the accompanying drawings of the embodiments of this application are merely examples and are not intended to limit this application. Furthermore, the above embodiments provided in this application can be combined with each other unless there is contradiction.

[0157] It should be clarified that the various embodiments in this specification are described in a progressive manner. Similar or identical parts between embodiments can be referred to interchangeably. Each embodiment focuses on describing the differences from other embodiments. According to the embodiments described above, these embodiments do not exhaustively describe all details, nor do they limit this application to only the specific embodiments described. Obviously, many modifications and variations can be made based on the above description. This specification selects and specifically describes these embodiments to better explain the principles and practical applications of this application, thereby enabling those skilled in the art to make good use of this application and modifications based on it. This application is limited only by the claims and their full scope and equivalents.

[0158] Those skilled in the art will understand that the above embodiments are exemplary and not restrictive. Different technical features appearing in different embodiments can be combined to achieve beneficial effects. Based on a study of the drawings, specification, and claims, those skilled in the art should be able to understand and implement other variations of the disclosed embodiments. In the claims, the term "comprising" does not exclude other structures; the quantity refers to "one" but does not exclude multiple; the terms "first" and "second" are used to identify names and not to indicate any particular order. Any reference numerals in the claims should not be construed as limiting the scope of protection. The appearance of certain technical features in different dependent claims does not mean that these technical features cannot be combined to achieve beneficial effects.

Claims

1. A display panel, characterized in that, include: Pixel circuits and light-emitting elements; The pixel circuit includes a driving module, a light emission control module, and a compensation module; The driving module includes a driving transistor, and the driving transistor includes a gate, a first electrode, and a second electrode. The light-emitting control module includes a first light-emitting control module and a second light-emitting control module. The first light-emitting control module is connected between the first power signal line and the driving transistor, and the second light-emitting control module is connected between the driving transistor and the light-emitting element. The compensation module is connected between the gate and the second electrode of the driving transistor, and the compensation module is turned on for a preset period. The operation of the pixel circuit includes a non-light-emitting stage and a light-emitting stage; During the light-emitting phase, the first light-emitting control module and the second light-emitting control module are activated; During the non-light-emitting phase, at least the second light-emitting control module is turned off; wherein, During the non-light-emitting phase, the time length between the second light-emitting control module being turned off and the start of the first preset phase is L1, and the time length of the first preset phase is W1; wherein, L1 > W1; The operation of the display panel includes a first mode and a second mode; in the first mode, the non-light-emitting stage is a first non-light-emitting stage; in the second mode, the non-light-emitting stage is a second non-light-emitting stage. In the first non-light-emitting phase, the time length between the second light-emitting control module being turned off and the start of the first preset phase is L11; in the second non-light-emitting phase, the time length between the second light-emitting control module being turned off and the start of the first preset phase is L21; wherein, L11 > L21; And / or, in the first non-light-emitting stage, the time length between the end of the last preset stage and the activation of the second light-emitting control module is L1n; in the second non-light-emitting stage, the time length between the end of the last preset stage and the activation of the second light-emitting control module is L2n; wherein, L1n≥L2n.

2. The display panel according to claim 1, characterized in that, In the non-light-emitting phase, the time length between the end of the last preset phase and the activation of the second light-emitting control module is Ln, and the time length of the last preset phase is Wn; wherein... Ln>Wn.

3. The display panel according to claim 2, characterized in that, The non-luminescent stage includes N preset stages, where N≥1; When N=1, W1=Wn; or, When N > 1, W1 = Wn, or W1 ≠ Wn.

4. The display panel according to claim 3, characterized in that, The pixel circuit includes a data writing module, which is connected to the first electrode of the driving transistor; The operation of the pixel circuit includes a data writing phase; During the data writing phase, the data writing module and the compensation module are activated, and the data writing module provides data signals to the driving transistor.

5. The display panel according to claim 4, characterized in that, The duration of the data writing phase is Wd; N=1, the preset stage covers the data writing stage, and W1=Wn>Wd.

6. The display panel according to claim 4, characterized in that, The duration of the data writing phase is Wd; N > 1, the i-th preset stage covers the data writing stage, and Wi > Wd, where Wi is the time length of the i-th preset stage, 1 ≤ i ≤ N.

7. The display panel according to claim 6, characterized in that, N > 1, the Nth preset stage covers the data writing stage, and Wn > Wd.

8. The display panel according to claim 7, characterized in that, Wn>Wj, 1≤j≤N-1.

9. The display panel according to claim 4, characterized in that, The pixel circuit includes a bias adjustment module, which is connected to the first and second terminals of the driving transistor. The operation of the pixel circuit includes a bias adjustment stage, which includes a first type of bias adjustment stage and / or a second type of bias adjustment stage. During the first type of bias adjustment phase, the compensation module is activated; During the second type of bias adjustment phase, the compensation module is turned off.

10. The display panel according to claim 9, characterized in that, The non-light-emitting phase includes at least one of the first type of bias adjustment phases, the duration of the first type of bias adjustment phase is Ws, and the duration of the data writing phase is Wd. N > 1, the x-th preset stage covers the first type of bias adjustment stage, the y-th preset stage covers the data writing stage, 1 ≤ x ≤ N, 1 ≤ y ≤ N; where... Wx > Ws, Wy > Wd.

11. The display panel according to claim 10, characterized in that, The non-light-emitting phase includes at least one of the first type of bias adjustment phases, the duration of the first type of bias adjustment phase is Ws, and the duration of the data writing phase is Wd. N=1, the preset stage covers the first type of bias adjustment stage and the data writing stage; W1 = Wn > (Ws + Wd).

12. The display panel according to claim 1, characterized in that, L1≥20us.

13. The display panel according to claim 2, characterized in that, Ln≥20us.

14. The display panel according to claim 1, characterized in that, The duration of the first non-luminescent phase is S11; The duration of the second non-luminescent phase is S22; wherein, S11>S22.

15. The display panel according to claim 1, characterized in that, In the first non-luminescent phase, the duration of the first preset phase is W11; in the second non-luminescent phase, the duration of the first preset phase is W21. L11 > W11, and L21 < W21.

16. The display panel according to claim 15, characterized in that, (L11-W11)>(W21-L21).

17. The display panel according to claim 1, characterized in that, In the first non-luminescent phase, the duration of the first preset phase is W11; in the second non-luminescent phase, the duration of the first preset phase is W21. L11 > W11, and L21 > W21.

18. The display panel according to claim 1, characterized in that, In the first non-luminescent stage, the duration of the last preset stage is W1n; in the second non-luminescent stage, the duration of the last preset stage is W2n. L1n>W1n, and L2n<W2n.

19. The display panel according to claim 18, characterized in that, (L1n-W1n)>(W2n-L2n).

20. The display panel according to claim 1, characterized in that, In the first non-luminescent stage, the duration of the last preset stage is W1n; in the second non-luminescent stage, the duration of the last preset stage is W2n. L1n>W1n, and L2n>W2n.

21. The display panel according to claim 1, characterized in that, The operation of the display panel includes a first time period and a second time period, which are different time periods. During the first time period, the pixel circuit operates in the first mode; During the second time period, the pixel circuit operates in the second mode.

22. The display panel according to claim 1, characterized in that, The display panel includes a first pixel circuit and a second pixel circuit; During at least a portion of the time period during the operation of the display panel, the first pixel circuit operates in the first mode, and the second pixel circuit operates in the second mode.

23. The display panel according to claim 22, characterized in that, The data refresh frequency of the first pixel circuit is Fs1, and the data refresh frequency of the second pixel circuit is Fs2; wherein, Fs1≠Fs2.

24. The display panel according to claim 23, characterized in that, Fs1 < Fs2.

25. The display panel according to claim 23, characterized in that, Fs1 > Fs2.

26. The display panel according to claim 22, characterized in that, The display panel includes a first display area and a second display area; The first pixel circuit is located in the first display area, and the second pixel circuit is located in the second display area.

27. A display device, characterized in that, Includes the display panel as described in any one of claims 1-26.

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