A multi-die storage and computing architecture FPGA with high memory bandwidth

Abstract

The present application discloses a multi-die storage and computing architecture FPGA with high storage bandwidth, and relates to the field of FPGA technology. The multi-die storage and computing architecture FPGA encapsulates an FPGA die and a storage die together, and a storage and computing unit is formed inside the FPGA die. Each storage and computing unit performs calculations based on instructions and data of a local storage unit. The data read and write ports of the local storage unit in each storage and computing unit are connected to a silicon connection layer, and are connected to the data read and write ports of the storage die via cross-die connections in the silicon connection layer to form a storage and computing read and write channel. The storage die reads and writes data to the connected local storage unit through the storage and computing read and write channel, and a larger data bandwidth can be achieved, so that the waiting time for data can be reduced when multi-core parallel storage and computing operations are realized through multiple storage and computing units, and the storage and computing performance is excellent, the data processing efficiency is high, and the computing speed is fast.

Description

Technical Field

[0001] The present application relates to the field of FPGA technology, and in particular to a multi-die storage and computing architecture FPGA with high storage bandwidth. Background Art

[0002] With the development of high-tech technologies such as the Internet of Things, cloud computing, and artificial intelligence, various data-intensive applications based on hardware platforms have also grown dramatically. FPGA (Field Programmable Gate Array) is a commonly used hardware platform due to its advantages of parallelism and reconfigurability.

[0003] The existing FPGA, like most traditional hardware platforms, adopts the von Neumann architecture. The FPGA contains a large number of resource modules such as CLB, DSP and BRAM. These resource modules are connected by highly configurable interconnects to form computing units and storage units in the FPGA. BRAM is an important on-chip storage unit. On-chip data is mainly stored in BRAM, and on-chip data must be transferred to the computing unit during calculation.

[0004] Therefore, existing FPGAs, like other hardware platforms that use the von Neumann architecture, need to repeatedly transfer large amounts of data between storage units and computing units when performing various computing tasks. Frequent and large-scale data movement not only consumes a large amount of wiring resources and interconnection resources, but also causes huge delays and energy losses, thereby limiting the data processing efficiency of FPGAs. Summary of the invention

[0005] In response to the above problems and technical requirements, the applicant has proposed a multi-die storage and computing architecture FPGA with high storage bandwidth. The technical solution of this application is as follows:

[0006] A multi-die storage and computing architecture FPGA with high storage bandwidth, the multi-die storage and computing architecture FPGA comprising a substrate, a silicon connection layer stacked on the substrate, an FPGA die and a storage die stacked on the silicon connection layer, wherein the silicon connection layer covers all the FPGA die and the storage die;

[0007] The FPGA die includes a number of resource modules arranged in a predetermined structure and interconnection resources arranged around the resource modules. The resource modules located in the same sub-area are connected through the interconnection resources inside the FPGA to realize a storage and computing unit. The local storage unit in each storage and computing unit is used to store the instructions and data of the storage and computing unit.

[0008] The data read and write ports of the local storage units in each storage and computing unit in the FPGA die are connected to the silicon connection layer, and are connected to the data read and write ports of the storage die via cross-die connections in the silicon connection layer to form a storage and computing read and write channel. The storage die reads and writes data to the connected local storage unit through the storage and computing read and write channel, and each storage and computing unit performs calculations based on the instructions and data of the local storage unit.

[0009] Its further technical solution is that the data read and write ports of the local storage units in different storage and computing units are connected to the data read and write ports of the storage chip via different cross-die connections to form multiple storage and computing read and write channels, and the storage chip reads and writes the local storage units in multiple storage and computing units in parallel through different storage and computing read and write channels.

[0010] Its further technical solution is that the multi-die storage and computing architecture FPGA also includes a DMA controller corresponding to each storage and computing read and write channel. The DMA controller is connected to the read and write control port of the storage die and the read and write control port of the corresponding local storage unit. The DMA controller is used to control the reading and writing of data between the storage die and the corresponding local storage unit.

[0011] Its further technical solution is that the DMA controller is arranged in the silicon connection layer and is respectively connected to the read-write control lead-out terminal of the storage die and the read-write control lead-out terminal of the FPGA die through the connections in the silicon connection layer. The read-write control port of the storage die is connected to the read-write control lead-out terminal, and the read-write control port of the local storage unit in the FPGA die is connected to the read-write control lead-out terminal.

[0012] Its further technical solution is that the first circuit structure of the DMA controller is arranged in the silicon connection layer, and the second circuit structure is arranged in the FPGA die, the second circuit structure is connected to the read-write control port of the local storage unit in the FPGA die, the first circuit structure is connected to the read-write control lead-out terminal of the storage die through the connection in the silicon connection layer, and the read-write control port of the storage die is connected to the read-write control lead-out terminal; the first circuit structure is connected to the circuit connection lead-out terminal of the FPGA die, and the circuit connection lead-out terminal of the FPGA die is connected to the second circuit structure in the FPGA die to form a DMA controller.

[0013] A further technical solution is that for the local storage unit in each storage and computing unit in each FPGA die:

[0014] The data write port of the local storage unit is connected to the first connection point lead-out end of the FPGA die, the first connection point lead-out end of the FPGA die is connected to the second connection point lead-out end of the storage die via the cross-die connection line in the silicon connection layer, and the second connection point lead-out end of the storage die is connected to the data read port of the storage die;

[0015] and / or;

[0016] The read port of the local storage unit is connected to the third connection point lead-out terminal of the FPGA die, the third connection point lead-out terminal of the FPGA die is connected to the fourth connection point lead-out terminal of the storage die via the cross-die connection within the silicon connection layer, and the fourth connection point lead-out terminal of the storage die is connected to the write port of the storage die.

[0017] A further technical solution is that the data write port of the local storage unit is connected to the first connection point lead-out terminal of the FPGA die and the interconnection resource inside the FPGA respectively through a first multiplexer;

[0018] And / or, the data read port of the local storage unit is connected to the third connection point lead-out terminal 6 of the FPGA die and the interconnection resources inside the FPGA respectively through the second multiplexer.

[0019] Its further technical solution is that the multi-die storage and computing architecture FPGA includes multiple FPGA dies, each FPGA die has multiple storage and computing units, and the data read and write ports of the local storage units in the storage and computing units in each FPGA die are connected to the data read and write ports of the storage die via cross-die connections in the silicon connection layer.

[0020] Its further technical solution is that the multi-die storage and computing architecture FPGA includes multiple storage dies, and the data read and write port of each storage die is connected to the data read and write port of the local storage unit of one or more storage and computing units. The multiple local storage units connected to the data read and write port of the same storage die belong to the same FPGA die or to multiple different FPGA dies.

[0021] A further technical solution is that the storage die in the multi-die storage and computing architecture FPGA includes DRAM and / or HBM.

[0022] The beneficial technical effects of this application are:

[0023] The present application discloses a multi-die storage and computing architecture FPGA with high storage bandwidth. The multi-die storage and computing architecture FPGA packages the FPGA die and the storage die together. The storage and computing unit is formed inside the FPGA die. The storage die can be connected to the storage and computing unit via a silicon connection layer to read and write data, thereby achieving a larger data bandwidth. When multi-core parallel storage and computing operations are implemented through multiple storage and computing units, the waiting time for data can be reduced, the storage and computing performance can be improved, and the multi-die storage and computing architecture FPGA has higher data processing efficiency and computing speed.

[0024] The FPGA die does not need to occupy pins when connected to the storage die, which reduces the occupancy of pin resources. Moreover, since the number of connection point leads of the FPGA die is much larger than the number of pins, the number of FPGA die that read and write storage units in parallel can be increased, further increasing the bandwidth.

[0025] The multi-die storage and computing architecture FPGA can also have a built-in DMA controller to control the data reading and writing process between the storage die and the storage and computing unit. The DMA controller can be deployed in the silicon connection layer, reducing the occupation of the internal resources of the FPGA die, so that the resources in the FPGA die can realize a larger number of storage and computing units. Moreover, the DMA controller is easier to manufacture when it is deployed in the silicon connection layer, which also reduces the difficulty of implementation. In addition, the DMA controller can be partially deployed in the FPGA die and partially deployed on the silicon connection layer for joint implementation.

[0026] The resource modules in the same sub-area of ​​the multi-die storage and computing architecture FPGA are connected through interconnection resources to realize a storage and computing unit. The processor and local storage unit of each storage and computing unit are in the same sub-area. When executing, the processor only needs to read and write the instructions and data in the adjacent local storage unit, which reduces the wiring resources and interconnection resources consumed by the data transmission between the processor and the local storage unit, reduces the data transmission delay and energy loss, and improves the data processing efficiency of the multi-die storage and computing architecture FPGA. In addition, the multi-die storage and computing architecture FPGA can realize multi-core parallel storage and computing operations through multiple storage and computing units. The processors of each storage and computing unit will not cause conflicts with each other. Each storage and computing unit can perform operations at full speed, which is not affected by the storage bandwidth, and can further improve the overall data processing efficiency and operation speed of the multi-die storage and computing architecture FPGA. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 It is a schematic diagram of the stacked structure of a multi-die storage and computing architecture FPGA according to an embodiment of the present application.

[0028] Figure 2 It is a schematic diagram of the arrangement of resource modules inside an FPGA die and a schematic diagram of the storage and computing unit formed in an embodiment of the present application.

[0029] Figure 3 This is a connection diagram between an FPGA die, a silicon connection layer, and a storage die in one embodiment of the present application.

[0030] Figure 4 This is another connection diagram between the FPGA die, the silicon connection layer and the storage die in one embodiment of the present application. DETAILED DESCRIPTION

[0031] The specific implementation of the present application is further described below in conjunction with the accompanying drawings.

[0032] This application discloses a multi-die storage and computing architecture FPGA with high storage bandwidth, please refer to Figure 1 The multi-die storage-computing architecture FPGA includes a substrate 1, a silicon connection layer 2 stacked on the substrate 1, an FPGA die and a storage die stacked on the silicon connection layer 2, and the silicon connection layer covers all the FPGA die and the storage die. Figure 1 Taking only one FPGA die as an example, in one embodiment, the storage die in the multi-die storage and computing architecture FPGA includes DRAM and / or HBM.

[0033] The FPGA bare chip in this application is the same as a conventional FPGA, and includes several resource modules arranged in a predetermined structure and interconnection resources arranged around the resource modules. The predetermined structure can be arranged according to actual conditions. For example, taking the currently mainstream Column-Based structure as an example, the resource modules are arranged in a row and column structure to form a two-dimensional array architecture. The same type of resource modules are arranged in each column, and interconnection resources are arranged around each resource module. The types of resource modules contained in the FPGA include configurable logic modules CLB, configurable storage modules BRAM, and configurable multiplication and addition modules DSP. The configurable logic module CLB contains units such as lookup tables and registers, which can be configured to implement various logical functions. The configurable multiplication and addition module DSP contains arithmetic units that can perform multiple operations such as multiplication, addition, and multi-bit logic gates. The configurable storage module BRAM contains block storage units that can implement single-port and dual-port storage and FIFO storage of various widths and depths. Please refer to Figure 2 The schematic diagram of the resource module inside the FPGA die shown is a schematic diagram of the resource module inside the FPGA die. This part of the structure follows the structure inside the existing FPGA die and will not be elaborated in this application.

[0034] All resource modules arranged in a predetermined structure in the FPGA die of the present application are divided into several sub-areas, each of which contains a certain amount of resource modules. Figure 2In the example shown, the resource modules inside the FPGA die are divided into 8 sub-areas, each sub-area contains the same number and type of resource modules, and each area framed by a dotted box represents a sub-area obtained by the division. The resource modules located in the same sub-area are connected through the interconnection resources inside the FPGA die to implement a storage and computing unit, and the resource modules in multiple different sub-areas correspondingly implement multiple storage and computing units. The present application does not limit the number and type of resource modules contained in each sub-area, but the number and type of resource modules contained in each sub-area must be sufficient to implement the processor and local storage unit in a storage and computing unit. The processor in a storage and computing unit is mainly implemented based on DSP, and the storage unit in a storage and computing unit is mainly implemented based on BRAM. In addition, a certain number of CLBs are also required. Figure 2 The resource modules in each sub-area shown in the figure implement a storage and computing unit. Figure 2 Also shown is a schematic structural diagram of eight storage and computing units formed by resource modules in eight sub-areas inside the FPGA die, which are respectively denoted as storage and computing unit 1 to storage and computing unit 8.

[0035] Each storage and computing unit includes its own processor and local storage unit. The processor in each storage and computing unit is connected to the local storage unit in the storage and computing unit via interconnection resources. The local storage unit in each storage and computing unit is used to store the instructions and data of the storage and computing unit, and the processor in each storage and computing unit is used to operate according to the instructions and data stored in the connected local storage unit.

[0036] In one embodiment, the instruction sets used by the two storage and computing units implemented by the resource modules in any two sub-areas are the same or different, and the bit widths of the two storage and computing units using the same instruction set are the same or different. In the present application, the storage and computing units formed inside the FPGA die can form various typical general-purpose 8-bit processors including RISC, 8051 and 6802.

[0037] In one embodiment, the number and type of resource modules contained in any two sub-areas obtained by division are the same, or in another embodiment, the number and type of resource modules contained in any two sub-areas obtained by division are at least one different, that is, the multiple sub-areas obtained by division may be completely the same or not necessarily the same. In addition, each resource module in the FPGA die belongs to a sub-area, all resource modules in the FPGA die are divided into corresponding sub-areas, or some resource modules in the FPGA die are divided into corresponding sub-areas, that is, the FPGA die may be divided into sub-areas globally or locally.

[0038] The data read and write port of the local storage unit in each storage and computing unit in the FPGA die is connected to the silicon connection layer. Specifically, in addition to resource modules such as CLB, BRAM and DSP, the FPGA die also includes a silicon stack connection module, each of which also has an interconnection resource module distributed around the silicon stack connection module, and each of which includes a number of silicon stack connection points. The data read and write port of the local storage unit in the storage and computing unit is connected to the silicon stack connection point, and the silicon stack connection point is connected to the corresponding connection point lead-out end on the surface of the FPGA die through the connection line in the redistribution layer. Micro-convex balls are grown on the FPGA die, and the connection point lead-out end is connected to the silicon connection layer 2 through the micro-convex balls, thereby achieving the effect of connecting the data read and write port of the local storage unit to the silicon connection layer.

[0039] After the data read and write port of the local storage unit in each storage and computing unit is connected to the silicon connection layer, it is connected to the data read and write port of the storage die via the cross-die connection 3 in the silicon connection layer 2, forming a storage and computing read and write channel from the data read and write port of the local storage unit to the data read and write port of the storage die. Similarly, inside the storage die, the cross-die in the silicon connection layer is connected to the connection point lead-out end of the storage die, and the connection point lead-out end is connected to the data read and write port of the storage array via the silicon stack connection point inside the storage die. Thus, the storage die can read and write data to the connected local storage unit through the formed storage and computing read and write channel. Therefore, the storage and computing unit does not need to occupy the pins of the FPGA die, but exchanges data with the storage die through the silicon stack connection point and the silicon connection layer, reducing the occupation of the pin, which is a precious on-chip resource.

[0040] The data read and write ports of the local storage unit in each storage and computing unit include a data read port RD and a data write port WD. Similarly, the data read and write ports of the storage chip also include a data read port RD and a data write port WD. The data read port RD of the local storage unit is connected to the data write port WD of the storage chip via a storage and computing read and write channel, so that the storage chip can write data to the local storage unit, and / or the data write port WD of the local storage unit is connected to the data read port RD of the storage chip via a storage and computing read and write channel, so that the storage chip can read data from the local storage unit.

[0041] For any storage and computing unit, the local storage unit in the storage and computing unit can be connected to the storage die through both the data read port RD and the data write port WD, and the storage die reads and writes data to the local storage unit completely. However, the local storage unit in the storage and computing unit can also be connected to the storage die only through the data read port RD or only through the data write port WD, and the other data read and write port can be connected to the outside through the pin of the multi-die storage and computing architecture FPGA, so as to achieve the effect that the storage die writes data to the local storage unit, and the data is read out to the outside of the multi-die storage and computing architecture FPGA, or the outside of the multi-die storage and computing architecture FPGA writes data to the local storage unit, and the data is read out to the storage die. However, the transmission delay between the local storage unit and the off-chip of the multi-die storage and computing architecture FPGA is greater than the transmission delay between the local storage unit and the storage die. These two implementation methods may be difficult to operate continuously due to the mismatch between the off-chip read and write speed and the storage die read and write speed, affecting the data processing speed. In some special cases, such as when the amount of data written is significantly different from the amount of data read, this transmission method can be used. For example, when the amount of data read is large and the amount of data written is small, data can be written to the local storage unit from the outside of the multi-die storage and computing architecture FPGA, and the data can be read to the storage die, which can basically not affect the processing performance. However, in most common cases, the data read port RD and the data write port WD of the local storage unit in the storage and computing unit are connected to the storage die to realize the reading and writing between the storage die.

[0042] Then, for any local storage unit in a storage and computing unit, the data write port WD of the local storage unit is connected to the first connection point lead-out terminal 4 of the FPGA die, the first connection point lead-out terminal 4 of the FPGA die is connected to the second connection point lead-out terminal 5 of the storage die via the cross-die connection 3 in the silicon connection layer, and the second connection point lead-out terminal 5 of the storage die is connected to the data read port RD of the storage die, then the data write port WD of the local storage unit and the data read port RD of the storage die form a storage and computing read and write channel. And / or, the data read port RD of the local storage unit is connected to the third connection point lead-out terminal 6 of the FPGA die, the third connection point lead-out terminal 6 of the FPGA die is connected to the fourth connection point lead-out terminal 7 of the storage die via the cross-die connection 3 in the silicon connection layer, and the fourth connection point lead-out terminal 7 of the storage die is connected to the data write port WD of the storage die, as shown in FIG. Figure 1 shown.

[0043] In actual applications, the FPGA die includes a large number of storage and computing units, and the data read and write ports of the local storage units in different storage and computing units in the FPGA die are connected to the data read and write ports of the storage die via different cross-die connections to form multiple storage and computing read and write channels, and the connection method between each local storage unit and the storage die is similar. The storage die reads and writes the local storage units in multiple storage and computing units in parallel through different storage and computing read and write channels. Whether it is the FPGA die or the entire multi-die storage and computing architecture FPGA, the number of pins is very limited, generally less than 2,000, so the pins are important on-chip resources. Therefore, due to the number of pins, the number of local storage units that can be connected to the outside of the FPGA die and the outside of the multi-die storage and computing architecture FPGA through pins is limited. The number of silicon stack connection points in the FPGA die is relatively large, generally reaching 20,000 to 50,000. Therefore, when the method of the present application is used to connect the local storage unit in the storage and computing unit to the storage die through the silicon stack connection point via the silicon connection layer, compared to the method of reading and writing through pins, the number of storage and computing units that the storage die can simultaneously connect and read and write can be greatly increased, thereby greatly improving the read and write bandwidth, reducing the waiting time for reading and writing the computing units in the FPGA die, and improving the storage and computing performance of the multi-die storage and computing architecture FPGA.

[0044] The multiple storage and computing units formed inside the multi-die storage and computing architecture FPGA of this architecture of the present application all support independent storage and computing operations in the form of soft cores. The FPGA can realize a multi-core storage and computing operation through the multiple storage and computing units formed inside. Taking the data reading and writing of the local storage unit as an example, the method for realizing a multi-core storage and computing operation includes: first, after writing data from the outside of the multi-die storage and computing architecture FPGA, the storage chip writes the parameters of each storage and computing unit into the local storage unit of the corresponding storage and computing unit in the FPGA die through each storage and computing read and write channel, and the parameters written to the local storage unit of each storage and computing unit include the instructions and / or data of the storage and computing unit, that is, only instructions or data can be written to the storage and computing unit, or instructions and data can be written at the same time. Start each storage and computing unit to operate in parallel at the same time, and the processor in each storage and computing unit performs operations according to the instructions and data in the local storage unit of the storage and computing unit, and stores the operation results in the local storage unit of the storage and computing unit. Then, the operation results in the local storage unit of each storage and computing unit can be read out to the storage die via the storage and computing read and write channel. According to actual needs, the data of the storage die can also be read to the outside of the multi-die storage and computing architecture FPGA.

[0045] On this basis, according to actual needs, FPGA can realize multiple storage and calculation operations in sequence through the storage and calculation units implemented internally until all operations are completed. And when FPGA realizes any storage and calculation operation, the corresponding parameters are written from the storage die to the local storage units of all storage and calculation units, or to the local storage units of some storage and calculation units. Similarly, the parameters here include the instructions and / or data of the storage and calculation units. All storage and calculation units or some storage and calculation units are started to calculate in parallel at the same time. Then the calculation results in the local storage units of all storage and calculation units or the calculation results in the local storage units of some storage and calculation units are read out to the storage die. That is, when multiple storage and calculation operations are realized, each storage and calculation operation can use all the storage and calculation units formed inside the FPGA, or only use some storage and calculation units and skip other storage and calculation units. When using some storage and calculation units, the same or different storage and calculation units can also be used multiple times. In addition, each storage and calculation operation can adjust the parameters written to each storage and calculation unit. Each storage and calculation operation can read the calculation results of all or some storage and calculation units. That is, the processes of executing multiple storage and computing operations are basically similar, but each storage and computing operation can flexibly adjust the data reading and writing of each storage and computing unit, without the need to perform the same data reading and writing operations on the local storage units in all storage and computing units every time.

[0046] In order to improve the read and write efficiency between the storage and computing unit and the storage die, in one embodiment, the multi-die storage and computing architecture FPGA also includes a DMA controller corresponding to each storage and computing read and write channel, and the DMA controller is connected to the read and write control port of the storage die and the read and write control port of the corresponding local storage unit. The read and write control port of the local storage unit includes a read control port REN and a write control port WEN, and the read and write control port of the storage die also includes a read control port REN and a write control port WEN. Then, the type of the read and write control port of the local storage unit connected to the DMA controller matches the type of the data read and write port of the local storage unit connected to the corresponding storage and computing read and write channel, and the type of the read and write control port of the storage die connected to the DMA controller matches the type of the data read and write port of the storage die connected to the corresponding storage and computing read and write channel. That is, when a storage and computing read and write channel is connected to the data read port RD of the local storage unit, the DMA controller corresponding to the storage and computing read and write channel is connected to the read control port REN of the local storage unit, and when a storage and computing read and write channel is connected to the data write port WD of the local storage unit, the DMA controller corresponding to the storage and computing read and write channel is connected to the write control port WEN of the local storage unit. Similarly, when a storage and computing read / write channel is connected to the data read port RD of the storage die, the DMA controller corresponding to the storage and computing read / write channel is connected to the read control port REN of the storage die; when a storage and computing read / write channel is connected to the data write port WD of the storage die, the DMA controller corresponding to the storage and computing read / write channel is connected to the write control port WEN of the storage die. Figure 3A DMA controller corresponding to a storage-computing read-write channel connected between a data write port WD of a local storage unit and a data read port RD of a storage die is shown, and the DMA controller is connected to a write control port WEN of the local storage unit and a read control port REN of the storage die.

[0047] The DMA controller is used to control the reading and writing of data between the storage die and the corresponding local storage unit. It can efficiently provide the required read and write control signals to the storage die and the local storage unit of the storage and computing unit to control the data reading and writing process of the two.

[0048] Considering that implementing the DMA controller entirely in the FPGA die will occupy too many resources in the FPGA die, in one embodiment, the DMA controller is arranged in the silicon connection layer 2, and is respectively connected to the read-write control lead-out terminal of the storage die and the read-write control lead-out terminal of the FPGA die through the connection lines in the silicon connection layer 2, the read-write control port of the storage die is connected to the read-write control lead-out terminal, and the read-write control port of the local storage unit in the FPGA die is connected to the read-write control lead-out terminal. Correspondingly, the read-write control lead-out terminal of the FPGA die includes a read control lead-out terminal 8 and a write control lead-out terminal 9, and the DMA controller is respectively connected to the read control lead-out terminal 8 and the write control lead-out terminal 9 of the FPGA die through the connection lines in the silicon connection layer 2, the read control lead-out terminal 8 of the FPGA die is connected to the read control port REN of the FPGA die, and the write control lead-out terminal 9 of the storage die is connected to the write control port WEN of the FPGA die. Similarly, the read and write control pins of the storage die include a read control pin 10 and a write control pin 11. The DMA controller is connected to the read control pin 10 and the write control pin 11 of the storage die through the wiring in the silicon connection layer 2. The read control pin 10 of the storage die is connected to the read control port REN of the storage die, and the read control pin 11 of the storage die is connected to the write control port WEN of the storage die. Figure 3 As shown. Since the silicon connection layer is easy to manufacture, placing the DMA controller in the silicon connection layer 2 can reduce the demand for resources in the FPGA die. At the same time, the resources in the FPGA die are not occupied by the DMA controller, so the number of storage and computing units in the FPGA die can be maximized as much as possible.

[0049] In another embodiment, the DMA controller is arranged in the silicon connection layer and the FPGA die at the same time, that is, the first circuit structure of the DMA controller is arranged in the silicon connection layer 1, and the second circuit structure is arranged in the FPGA die, the second circuit structure is connected to the read-write control port of the local storage unit in the FPGA die, the first circuit structure is connected to the read-write control lead-out terminal of the storage die through the connection in the silicon connection layer, and the read-write control port of the storage die is connected to the read-write control lead-out terminal, specifically Figure 3The first circuit structure is connected to the circuit connection lead-out terminal 12 of the FPGA die, and the circuit connection lead-out terminal 12 of the FPGA die is connected to the second circuit structure in the FPGA die to form a DMA controller. Figure 4 shown.

[0050] In another embodiment, for a local storage unit in any storage and computing unit, the data write port WD of the local storage unit is connected to the first connection point lead-out terminal 4 of the FPGA die and the interconnection resource INT inside the FPGA through the first multiplexer MUX1; and / or, the data read port RD of the local storage unit is connected to the third connection point lead-out terminal 6 of the FPGA die and the interconnection resource INT inside the FPGA through the second multiplexer MUX2. This allows the local storage unit to not only read and write data with the storage die, but also to achieve connection with other resource modules through the interconnection resource INT.

[0051] Similarly, for a local storage unit in any storage and computing unit, the write control port WEN of the local storage unit is connected to the write control lead-out terminal 9 of the FPGA die and the interconnection resource INT inside the FPGA through the third multiplexer MUX3; and / or, the read control port REN of the local storage unit is connected to the read control lead-out terminal 8 of the FPGA die and the interconnection resource INT inside the FPGA through the fourth multiplexer MUX4. The local storage unit can not only read and write data with the storage die, but also be connected to other resource modules through the interconnection resource INT.

[0052] In another embodiment, the multi-die storage and computing architecture FPGA includes multiple FPGA dies, and one or more of the FPGA dies have storage and computing units formed in accordance with the above structure, and each FPGA die has multiple storage and computing units formed in it, and the data read and write ports of the local storage units in the storage and computing units in each FPGA die are connected to the data read and write ports of the storage die via cross-die connections in the silicon connection layer. The implementation methods of each FPGA die are similar to those described above, and this embodiment will not be repeated, so the multi-die storage and computing architecture FPGA can achieve higher concurrent storage and computing operations through the storage and computing units in multiple FPGA dies.

[0053] Since the processor and local storage unit of each storage and computing unit are in the same sub-area, the processor only needs to read and write instructions and data in the adjacent local storage unit during execution, thus reducing the wiring resources and interconnection resources consumed by data transmission between the processor and the local storage unit, reducing data transmission delay and energy loss, and improving the data processing efficiency of the multi-die storage and computing architecture FPGA. In addition, in a multi-core scenario, if multiple computing cores read and write the same main memory at the same time, the read and write bandwidth of the main memory will form a bottleneck, restricting the data processing efficiency. This problem will be particularly obvious in high-performance computing. For multi-die storage and computing architecture FPGAs that support artificial intelligence or machine learning applications, multi-die storage and computing architecture FPGAs generally have a large number of relatively simple computing cores inside, and the number of computing cores will exceed 100, which requires a greater read and write bandwidth for the main memory, and the problem is more prominent. The multi-die storage and computing architecture FPGA of the present application is also a multi-core scenario, and due to the architectural improvement, it can support more storage and computing units in parallel. Since the processors in each storage and computing unit read and write local storage units respectively, instead of all processors uniformly reading and writing the same memory, the processors of each storage and computing unit will not cause conflicts with each other, and each storage and computing unit can perform operations at full speed, which is not affected by the storage bandwidth, which is conducive to improving the overall data processing efficiency and computing speed. This makes the multi-die storage and computing architecture FPGA of the present application applicable to scenarios containing a large number of storage and computing units, and even if the number of storage and computing units exceeds 100, it can have a higher computing rate, so as to better support artificial intelligence and machine learning scenarios.

[0054] The above is only a preferred embodiment of the present application, and the present application is not limited to the above embodiments. It is understood that other improvements and changes directly derived or associated by those skilled in the art without departing from the spirit and concept of the present application should be considered to be included in the protection scope of the present application.

Claims

1. A multi-die storage and computing architecture FPGA with high storage bandwidth, characterized in that: The multi-die storage-computing architecture FPGA includes a substrate, a silicon connection layer stacked on the substrate, an FPGA die and a storage die stacked on the silicon connection layer, and the silicon connection layer covers all the FPGA die and the storage die; The FPGA die includes a plurality of resource modules arranged in a predetermined structure and interconnection resources arranged around the resource modules. The resource modules located in the same sub-area are connected through the interconnection resources inside the FPGA die to realize a storage and computing unit. Each storage and computing unit includes a respective processor and a local storage unit. The processor in each storage and computing unit is connected to the local storage unit in the storage and computing unit via the interconnection resources. The local storage unit in each storage and computing unit is used to store instructions and data of the storage and computing unit. The data read / write port of the local storage unit in each storage and computing unit in the FPGA die is connected to the silicon connection layer, and is connected to the data read / write port of the storage die via the cross-die connection in the silicon connection layer to form a storage and computing read / write channel. The storage die reads and writes data to the connected local storage unit through the storage and computing read / write channel, and each storage and computing unit performs calculations based on the instructions and data of the local storage unit; the data read / write ports of the local storage units in different storage and computing units are connected to the data read / write port of the storage die via different cross-die connections to form multiple storage and computing read / write channels, and the storage die reads and writes the local storage units in multiple storage and computing units in parallel through different storage and computing read / write channels; The multi-die storage and computing architecture FPGA realizes a multi-core storage and computing operation through multiple storage and computing units formed inside, including: writing data from the outside of the multi-die storage and computing architecture FPGA to the storage die, and the storage die writes the parameters of each storage and computing unit into the local storage unit of the corresponding storage and computing unit in the FPGA die through each storage and computing read and write channel, and the parameters written to the local storage unit of each storage and computing unit include the instructions and / or data of the storage and computing unit; starting each storage and computing unit to perform parallel operations at the same time, and the processor in each storage and computing unit performs operations according to the instructions and data in the local storage unit of the storage and computing unit, and stores the operation results in the local storage unit of the storage and computing unit; The calculation results in the local storage units of each storage and calculation unit are read out to the storage die through the storage and calculation read and write channel.

2. The multi-die storage and computing architecture FPGA according to claim 1, characterized in that: The multi-die storage and computing architecture FPGA also includes a DMA controller corresponding to each of the storage and computing read and write channels, the DMA controller is connected to the read and write control port of the storage die and the read and write control port of the corresponding local storage unit, and the DMA controller is used to control the reading and writing of data between the storage die and the corresponding local storage unit.

3. The multi-die storage and computing architecture FPGA according to claim 2, characterized in that: The DMA controller is arranged in the silicon connection layer and is respectively connected to the read-write control lead-out terminal of the storage die and the read-write control lead-out terminal of the FPGA die through the connections in the silicon connection layer. The read-write control port of the storage die is connected to the read-write control lead-out terminal, and the read-write control port of the local storage unit in the FPGA die is connected to the read-write control lead-out terminal.

4. The multi-die storage and computing architecture FPGA according to claim 2, characterized in that: The first circuit structure of the DMA controller is arranged in the silicon connection layer, and the second circuit structure is arranged in the FPGA die. The second circuit structure is connected to the read and write control port of the local storage unit in the FPGA die. The first circuit structure is connected to the read and write control lead-out terminal of the storage die through the connection in the silicon connection layer, and the read and write control port of the storage die is connected to the read and write control lead-out terminal; the first circuit structure is connected to the circuit connection lead-out terminal of the FPGA die, and the circuit connection lead-out terminal of the FPGA die is connected to the second circuit structure in the FPGA die to form the DMA controller.

5. The multi-die storage and computing architecture FPGA according to claim 1, characterized in that: For each local storage unit in each storage and computing unit in each of the FPGA die: The data write port of the local storage unit is connected to the first connection point lead-out terminal of the FPGA die, the first connection point lead-out terminal of the FPGA die is connected to the second connection point lead-out terminal of the storage die via the cross-die connection line in the silicon connection layer, and the second connection point lead-out terminal of the storage die is connected to the data read port of the storage die; and / or; The read port of the local storage unit is connected to the third connection point lead-out terminal of the FPGA die, the third connection point lead-out terminal of the FPGA die is connected to the fourth connection point lead-out terminal of the storage die via the cross-die connection within the silicon connection layer, and the fourth connection point lead-out terminal of the storage die is connected to the write port of the storage die.

6. The multi-die storage and computing architecture FPGA according to claim 5, characterized in that: The data write port of the local storage unit is connected to the first connection point lead-out end of the FPGA die and the interconnection resources inside the FPGA die respectively through a first multiplexer; And / or, the data read port of the local storage unit is connected to the third connection point lead-out terminal of the FPGA die and the interconnection resources inside the FPGA die respectively through a second multiplexer.

7. The multi-die storage and computing architecture FPGA according to claim 1, characterized in that: The multi-die storage and computing architecture FPGA includes multiple FPGA dies, each of which has multiple storage and computing units formed therein, and the data read and write ports of the local storage units in the storage and computing units in each of the FPGA dies are respectively connected to the data read and write ports of the storage die via cross-die connections in the silicon connection layer.

8. The multi-die storage and computing architecture FPGA according to claim 7, characterized in that: The multi-die storage and computing architecture FPGA includes multiple storage dies, and the data read and write port of each storage die is connected to the data read and write port of the local storage unit of one or more storage and computing units. The multiple local storage units connected to the data read and write port of the same storage die belong to the same FPGA die or to multiple different FPGA dies.

9. The multi-die storage and computing architecture FPGA according to claim 8, characterized in that: The storage die within the multi-die storage-computing architecture FPGA includes DRAM and / or HBM.

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