Interconnection structure and interconnection method between wafer and substrate

Abstract

The invention relates to an interconnection structure and method between a wafer and a substrate; the method comprises the following steps: preparing a metal nano-sintered body with metal probes; opening a dipping groove corresponding to each metal probe on the upper end surface of a second silicon plate; pouring nano-metal slurry into each dipping groove, moving the metal nano-sintered body above the second silicon plate, and making the bottom of each metal probe extend into the corresponding dipping groove; arranging welding pieces corresponding to each metal probe on the substrate, moving the metal nano-sintered body dipped with nano-metal slurry above the substrate, making each metal probe contact with the corresponding welding piece, and obtaining a wafer and substrate interconnection structure through a sintering process; the interconnection method can solve the technical problem that the existing chip and wafer interconnection method has no heat dissipation channel and cannot meet the use of high-power devices in high temperature and high current density scenarios.

Description

Technical Field

[0001] The present invention relates to the technical field of chip packaging, and in particular to an interconnection structure and an interconnection method between a wafer and a substrate. Background Art

[0002] In electronic devices, the interconnection between the chip and the substrate not only fixes the chip and provides mechanical protection, but also provides electrical connection and heat dissipation channels for the chip. High-power devices need to work in harsh environments such as higher temperatures and greater current densities, so higher requirements are placed on high-power devices.

[0003] The traditional chip-wafer interconnection method uses conductive glue and solder paste, which has no heat dissipation channel and cannot meet the requirements of high-power devices under high temperature and high current density scenarios.

[0004] Therefore, in view of the above problems, the present invention urgently needs to provide an interconnection structure and an interconnection method between a wafer and a substrate. Summary of the invention

[0005] The object of the present invention is to provide an interconnection structure and an interconnection method between a wafer and a substrate. The interconnection method between the wafer and the substrate is proposed to solve the technical problem that the existing chip-wafer interconnection method uses conductive glue and solder paste for connection, has no heat dissipation channel, and cannot meet the use requirements of high-power devices in high temperature and high current density scenarios.

[0006] The present invention provides a method for interconnecting a wafer and a substrate, comprising the following steps:

[0007] Prepare a metal nano sintered body with metal probes, the metal nano sintered body with metal probes comprising a wafer, a plurality of metal probes are arranged at intervals on the lower end surface of the wafer;

[0008] The second silicon plate has an end surface on which dipping grooves corresponding to the metal probe pillars are formed;

[0009] Filling each dipping groove with nano-metal slurry, moving the metal nano-sintered body to the top of the second silicon plate, and allowing the bottom of each metal probe to extend into the corresponding dipping groove;

[0010] Solder pads corresponding to each metal probe are arranged on the substrate, and the metal nano sintered body dipped in nano metal slurry is moved above the substrate so that each metal probe contacts the corresponding solder pad. Through the sintering process, the wafer and substrate interconnection structure is obtained.

[0011] Preferably, the thickness of the welding sheet is 0.1-10 mm.

[0012] Preferably, the area of ​​the welding piece is larger than the area of ​​the metal probe column.

[0013] Preferably, the nano metal paste is a paste containing metal nanoparticles.

[0014] Preferably, the metal nanoparticles are at least one of copper, gold, palladium, silver, aluminum, silver-palladium alloy, gold-palladium alloy, copper-silver alloy, copper-indium alloy, copper-silver-nickel alloy, copper-silver-tin alloy, copper-silver-titanium alloy or copper-aluminum alloy, silver-coated copper, tin-coated copper, organic-coated copper or organic-coated silver particles.

[0015] Preferably, the steps of preparing the metal nano-sintered body having the metal probe pillar include:

[0016] Prepare first insulating layers on the upper and lower surfaces of the first silicon plate respectively;

[0017] Using an etching process, one of the first insulating layers is etched to form a plurality of etching holes arranged at intervals on the insulating layer, and an etching solution is injected into the etching holes to form etching grooves on the first silicon plate;

[0018] forming a second insulating layer on the inner wall of the etched hole, the bottom and the side wall of the etched groove by a thermal oxidation process;

[0019] preparing a sacrificial layer on the first insulating layer and the second insulating layer;

[0020] The sacrificial layer is spin-coated with nano-metal slurry, and the nano-metal slurry is filled with the etched grooves and etched holes. The sintering process is adopted to form metal probes in the etched grooves and etched holes, and a wafer is formed on the sacrificial layer. The sacrificial layer is cleaned, and the metal probes and the wafer are separated to obtain a metal nano-sintered body with metal probes.

[0021] Preferably, at least one of polyvinyl pyrrolidone, sodium polystyrene sulfonate or ethyl cellulose.

[0022] Preferably, the sintering process is pressure sintering or pressureless sintering.

[0023] Preferably, the thickness of the first insulating layer is 0.3-0.6 μm; the thickness of the second insulating layer is 0.3-0.6 μm; the depth of the etched groove is 0.1-1000 μm; and the thickness of the wafer is 0.1-50 μm.

[0024] The present invention also provides a wafer-substrate interconnection structure obtained based on the wafer-substrate interconnection method as described in any one of the above.

[0025] The interconnection structure and method between a wafer and a substrate provided by the present invention have the following improvements compared with the prior art:

[0026] 1. The present invention uses a combination of wet etching technology and metal nanoparticles to produce high-density copper columns and pads on the surfaces of the wafer and substrate respectively, where the positions of the two correspond one to one, and then connects the substrate and the wafer by pressure or pressureless sintering, thereby realizing wafer-substrate interconnection with high precision, high pin density, high reliability, and good electrical and thermal conductivity.

[0027] 2. The metal probe column of the present invention provides a heat dissipation channel, which can meet the use requirements of high-power devices in scenarios of high temperature and high current density.

[0028] 3. The present invention adopts a sintering process to form a dense column structure on the wafer, thereby realizing the connection between the power device and the chip. The obtained metal probe column has no voids, high density, high mechanical strength, and good electrical conductivity and thermal conductivity.

[0029] 4. The sacrificial layer of the present invention adopts the organic substance PssNa polystyrene sulfonate which is easily soluble in water, which greatly simplifies the demoulding process. The demoulding agent only needs water and does not produce other waste liquids. It is highly efficient and can be demoulded by putting it in water.

[0030] 5. The present invention can adopt pressure sintering, and pressure assistance can shorten the process time, increase the density, and improve the mechanical strength, electrical conductivity, and thermal conductivity of the metal column. At the same time, the sintering process is simple and the cost is low. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] In order to more clearly illustrate the specific implementation methods of the present invention or the technical solutions in the prior art, the drawings required for use in the specific implementation methods or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some implementation methods of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0032] Figure 1 This is a schematic structural diagram of a metal nano-sintered body with a metal probe obtained in step S1 in a specific embodiment;

[0033] Figure 2 A schematic diagram of the step-by-step preparation of the metal nano-sintered body with the metal probe in step S1 (step S11);

[0034] Figure 3 A schematic diagram of the step-by-step preparation of the metal nano-sintered body with the metal probe in step S1 (step S12);

[0035] Figure 4 A schematic diagram of the step-by-step preparation of the metal nano-sintered body with the metal probe in step S1 (step S13);

[0036] Figure 5 A schematic diagram of the step-by-step preparation of the metal nano-sintered body with the metal probe in step S1 (step S14);

[0037] Figure 6 This is a structural diagram of step S2 in a specific embodiment;

[0038] Figure 7 This is a structural diagram of step S3 in a specific embodiment;

[0039] Figure 8 It is a schematic structural diagram of the wafer and substrate interconnection structure obtained in step S4 in a specific embodiment.

[0040] Description of reference numerals:

[0041] 1. Silicon plate; 2. First insulating layer; 3. Etched hole; 4. Etched groove; 5. Second insulating layer; 6. Sacrificial layer; 7. Metal probe; 8. Wafer; 9. Second silicon plate; 10. Dipping groove; 11. Substrate; 12. Solder pad. DETAILED DESCRIPTION

[0042] The technical solution of the present invention will be described clearly and completely below in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0043] In the description of the present invention, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc., indicating the orientation or positional relationship, are based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as limiting the present invention. In addition, the terms "first", "second", and "third" are used for descriptive purposes only, and cannot be understood as indicating or implying relative importance.

[0044] In the description of the present invention, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, or it can be the internal communication of two components. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0045] like Figure 1 , Figure 6, Figure 7 , Figure 8 As shown, this embodiment provides a method for interconnecting a wafer and a substrate, comprising the following steps:

[0046] S1) preparing a metal nano-sintered body with metal probes, wherein the metal nano-sintered body with metal probes comprises a wafer 8, and a plurality of metal probes are arranged at intervals on the lower end surface of the wafer 8);

[0047] S2) a dipping groove 10 corresponding to each metal probe column 7 is provided on the upper end surface of the second silicon plate 9;

[0048] S3) pouring nano-metal slurry into each dipping groove 10, moving the metal nano-sintered body to the top of the second silicon plate 9, and making the bottom of each metal probe 7 extend into the corresponding dipping groove 10;

[0049] S4) Arrange welding pieces 12 corresponding to each metal probe 7 on the substrate 11, move the metal nano sintered body dipped in nano metal slurry to the top of the substrate 11, so that each metal probe 7 contacts the corresponding welding piece 12, and obtain the wafer and substrate interconnection structure through the sintering process.

[0050] The present invention uses a wet etching technology combined with metal nanoparticles to produce high-density copper columns and pads on the surfaces of the wafer and substrate respectively, wherein the positions of the two correspond one to one, and then connects the substrate and the wafer by pressure or pressureless sintering, thereby realizing wafer-substrate interconnection with high precision, high pin density, high reliability, and good electrical and thermal conductivity.

[0051] The metal probe column of the present invention provides a heat dissipation channel, which can meet the use requirements of high-power devices in scenarios of high temperature and high current density.

[0052] In some embodiments, the solder tab 12 has a thickness of 0.1-10 mm.

[0053] In some embodiments, the area of ​​the welding piece 12 is larger than the area of ​​the metal probe to ensure the stability of welding.

[0054] In some embodiments, the nanometal slurry is a slurry containing metal nanoparticles; the metal nanoparticles are at least one of copper, gold, palladium, silver, aluminum, silver-palladium alloy, gold-palladium alloy, copper-silver alloy, copper-indium alloy, copper-silver-nickel alloy, copper-silver-tin alloy, copper-silver-titanium alloy or copper-aluminum alloy, silver-coated copper, tin-coated copper, organic-coated copper or organic-coated silver particles.

[0055] In this embodiment, Figure 1 , Figure 2 , Figure 3 , Figure 4 , Figure 5As shown, the steps for preparing the metal nano-sintered body with the metal probe include:

[0056] S11) preparing a first insulating layer 2 on the upper end surface and the lower end surface of the first silicon plate 1 respectively;

[0057] S12) using an etching process to etch one of the first insulating layers 2, so that a plurality of etching holes 3 arranged at intervals are formed on the insulating layer 2, and an etching solution is injected into the etching holes 3, so that etching grooves 4 are formed on the first silicon plate 1;

[0058] S13) forming a second insulating layer 5 on the inner wall of the etching hole 3, the bottom and sidewall of the etching groove 4 by a thermal oxidation process;

[0059] S14) preparing a sacrificial layer 6 on the first insulating layer 2 and the second insulating layer 5; spin coating the sacrificial layer 6 with nano-metal slurry, and allowing the nano-metal slurry to fill the etched grooves 4 and the etched holes, and sintering the etched grooves 4 and the etched holes using a sintering process, so that the etched grooves 4 and the etched holes form metal probes 7, and a wafer 8 is formed on the sacrificial layer 6;

[0060] S15) cleaning the sacrificial layer, separating the metal probe 7 and the wafer 8, and obtaining a metal nano-sintered body with the metal probe.

[0061] Specifically, at least one of polyvinyl pyrrolidone, sodium polystyrene sulfonate or ethyl cellulose; the sintering process is pressure sintering or pressureless sintering; when the sintering process is pressure sintering, the pressure of pressure sintering is 20-30mPa, which can shorten the process time, increase the density, and improve the mechanical strength, electrical conductivity and thermal conductivity of the metal column.

[0062] The thickness of the first insulating layer 2 of the present invention is 0.3-0.6 μm; the thickness of the first insulating layer 2 can be adjusted according to the specific process, and the thickness of the first insulating layer 2 is preferably 0.5 μm;

[0063] The thickness of the second insulating layer 5 of the present invention is 0.3-0.6 μm, which can be adjusted according to the specific process. The thickness of the first insulating layer 2 is preferably 0.5 μm.

[0064] The depth of the etching groove 4 of the present invention is 0.1-1000 μm, which is selected according to the specific process.

[0065] The thickness of the wafer 8 of the present invention is 0.1-50 μm, which is selected according to the specific process.

[0066] The transverse cross section of the etching groove 4 of the present invention is circular, square or any other shape. Circular, square or any other shape as required can be selected, and the preferred shape is circular.

[0067] Specifically, the preparation process of the wafer-substrate interconnection structure obtained by the wafer-substrate interconnection method includes the following steps:

[0068] 101) preparing a first insulating layer 2 on the upper end surface and the lower end surface of the silicon plate 1 respectively, wherein the first insulating layer 2 is made of silicon dioxide;

[0069] 102) using photoresist as a mask, forming a mask layer on the first insulating layer 2, forming an opening in the silicon dioxide layer on the silicon wafer by etching, the size of the opening depends on the pillar planting requirements, using a strong base to etch the exposed part, so that etching holes 3 are formed on the first insulating layer, injecting a strong base into each etching hole 3, and continuing to etch the silicon plate, so that etching grooves 4 are formed on the silicon plate;

[0070] 103) forming a second insulating layer 5 on the inner wall of the etching hole 3, the bottom and the side wall of the etching groove 4 by a thermal oxidation process; the material of the second insulating layer 5 is silicon dioxide;

[0071] 104) preparing a sacrificial layer 6 on the first insulating layer 2 and the second insulating layer 5, comprising at least one of polyvinyl pyrrolidone, sodium polystyrene sulfonate or ethyl cellulose;

[0072] 105) Spin-coating nano-metal slurry on the sacrificial layer 6, and allowing the nano-metal slurry to fill the etched grooves 4 and the etched holes, and sintering is performed using a sintering process, so that the etched grooves 4 and the etched holes form metal probes 7, and a wafer 8 is formed on the sacrificial layer 6;

[0073] 106) soaking in deionized water to separate the metal probe 7 and the wafer 8, and obtaining a metal nano sintered body with a metal probe; the metal nano sintered body with a metal probe comprises a wafer 8, and a plurality of metal probes are arranged at intervals on the lower end surface of the wafer 8;

[0074] 107) A dipping groove 10 corresponding to each metal probe column 7 is provided on the upper end surface of the second silicon plate 9;

[0075] 108) Pour nano-metal slurry into each dipping groove 10, move the metal nano-sintered body to above the second silicon plate 9, and make the bottom of each metal probe 7 extend into the corresponding dipping groove 10;

[0076] 109) Welding pads 12 corresponding to each metal probe 7 are arranged on the substrate 11, and the metal nano-sintered body dipped in nano-metal slurry is moved to the top of the substrate 11, so that each metal probe 7 contacts the corresponding welding pad 12, and the wafer and substrate interconnection structure is obtained through the sintering process.

[0077] The thickness of the first insulating layer 2 of the present invention is 0.3-0.6 μm; the thickness of the first insulating layer 2 can be adjusted according to the specific process, and the thickness of the first insulating layer 2 is preferably 0.5 μm;

[0078] The thickness of the second insulating layer 5 of the present invention is 0.3-0.6 μm, which can be adjusted according to the specific process. The thickness of the first insulating layer 2 is preferably 0.5 μm.

[0079] The depth of the etching groove 4 of the present invention is 0.1-1000 μm, which is selected according to the specific process.

[0080] The thickness of the wafer 8 of the present invention is 0.1-50 μm, which is selected according to the specific process.

[0081] The transverse cross section of the etching groove 4 of the present invention is circular, square or any other shape. Circular, square or any other shape as required can be selected, and the preferred shape is circular.

[0082] The sintering process is pressureless sintering or pressure sintering.

[0083] When pressure sintering is selected, the pressure of pressure sintering is 20-30mPa, which can shorten the process time, increase the density, and improve the mechanical strength, electrical conductivity, and thermal conductivity of the metal column.

[0084] Nanometal slurry is a slurry containing metal nanoparticles; the metal nanoparticles are at least one of copper, gold, palladium, silver, aluminum, silver-palladium alloy, gold-palladium alloy, copper-silver alloy, copper-indium alloy, copper-silver-nickel alloy, copper-silver-tin alloy, copper-silver-titanium alloy or copper-aluminum alloy, silver-coated copper, tin-coated copper, organic-coated copper or organic-coated silver particles.

[0085] The strong alkaline solution is NaOH or KOH, with a concentration of 30-40wt%; the etching time is 40-70min;

[0086] The spin coating speed is 1000-5000rpm, and the spin coating time is 30-60s;

[0087] The sacrificial layer can also be cleaned by soaking in deionized water and using ultrasound to improve work efficiency.

[0088] The present invention adopts a sintering process to form a dense column structure on a wafer, thereby realizing the connection between a power device and a chip. The obtained metal probe column has no voids, high density, high mechanical strength, and good electrical conductivity and thermal conductivity.

[0089] The sacrificial layer of the present invention adopts the organic substance PssNa polystyrene sulfonate which is easily soluble in water, which greatly simplifies the demoulding process. The demoulding agent only needs water and does not generate other waste liquids. It is highly efficient and can be demoulded by putting it in water.

[0090] The present invention can adopt pressure sintering, and pressure-assisted sintering can shorten the process time, increase the density, and improve the mechanical strength, electrical conductivity, and thermal conductivity of the metal column. At the same time, the sintering process is simple and the cost is low.

[0091] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A method for interconnecting a wafer and a substrate, characterized in that: The steps include: A metal nano-sintered body with a metal probe column is prepared, wherein the metal nano-sintered body with a metal probe column comprises a wafer (8), and a plurality of metal probe columns (7) are arranged at intervals on the lower end surface of the wafer (8); A dipping groove (10) corresponding to each metal probe column (7) is provided on the upper end surface of the second silicon plate (9); Filling each dipping groove (10) with nano-metal slurry, moving the metal nano-sintered body to above the second silicon plate (9), and allowing the bottom of each metal probe column (7) to extend into the corresponding dipping groove (10); Soldering pieces (12) corresponding to each metal probe column (7) are arranged on a substrate (11), and a metal nano-sintered body dipped in nano-metal slurry is moved above the substrate (11) so that each metal probe column (7) contacts the corresponding soldering piece (12). A wafer and substrate interconnection structure is obtained through a sintering process.

2. The method for interconnecting a wafer and a substrate according to claim 1, wherein: The thickness of the welding sheet (12) is 0.1-10 mm.

3. The method for interconnecting a wafer and a substrate according to claim 1, wherein: The area of ​​the welding piece (12) is larger than the area of ​​the metal probe column.

4. The method for interconnecting a wafer and a substrate according to claim 1, wherein: Nanometal slurry is a slurry containing metal nanoparticles.

5. The method for interconnecting a wafer and a substrate according to claim 4, characterized in that: The metal nanoparticles are at least one of copper, gold, palladium, silver, aluminum, silver-palladium alloy, gold-palladium alloy, copper-silver alloy, copper-indium alloy, copper-silver-nickel alloy, copper-silver-tin alloy, copper-silver-titanium alloy or copper-aluminum alloy, silver-coated copper, tin-coated copper, organic-coated copper or organic-coated silver particles.

6. The method for interconnecting a wafer and a substrate according to claim 1, wherein: The steps of preparing the metal nano-sintered body with the metal probe include: Preparing a first insulating layer (2) on the upper end surface and the lower end surface of the first silicon plate (1) respectively; Using an etching process, one of the first insulating layers (2) is etched to form a plurality of etching holes (3) arranged at intervals on the insulating layer (2); and an etching liquid is injected into the etching holes (3) to form etching grooves (4) on the first silicon plate (1); Forming a second insulating layer (5) on the inner wall of the etching hole (3) and the bottom and side wall of the etching groove (4) through a thermal oxidation process; Preparing a sacrificial layer (6) on the first insulating layer (2) and the second insulating layer (5); Spin-coating a nano-metal slurry on the sacrificial layer (6) and allowing the nano-metal slurry to fill the etched groove (4) and the etched hole, performing sintering using a sintering process, the etched groove (4) and the etched hole forming a metal probe column (7), and forming a wafer (8) on the sacrificial layer (6); The sacrificial layer is cleaned, the metal probe column (7) and the wafer (8) are separated, and a metal nano sintered body with the metal probe column is obtained.

7. The method for interconnecting a wafer and a substrate according to claim 6, wherein: The sacrificial layer is made of at least one of polyvinyl pyrrolidone, sodium polystyrene sulfonate or ethyl cellulose.

8. The method for interconnecting a wafer and a substrate according to claim 6, wherein: The sintering process is pressure sintering or pressureless sintering.

9. The method for interconnecting a wafer and a substrate according to claim 6, wherein: The thickness of the first insulating layer (2) is 0.3-0.6 μm; the thickness of the second insulating layer (5) is 0.3-0.6 μm; The depth of the etched groove (4) is 0.1-1000 μm; The thickness of the wafer (8) is 0.1-50 μm.

10. A wafer-to-substrate interconnection structure obtained based on the wafer-to-substrate interconnection method according to any one of claims 1 to 9.

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