Timing Deskew in Time-Interleaved Data Converters for Carrier Aggregation

Abstract

An apparatus includes an analog-to-digital converter configured to receive one or more first frames of a first component carrier signal having a first uplink-downlink subframe type and one or more additional frames of at least one additional component carrier signal, the one or more additional frames including one or more second frames of a second component carrier signal, the at least one additional component carrier signal including the second component carrier signal. The apparatus may further include control logic configured to activate timing skew calibration for at least one of the first or second component carrier signal based at least in part on an operating mode of the second component carrier signal and respective symbols of the first and second component carrier signals.

Description

[0001] Copyright Notice

[0002] A portion of the disclosure of this patent document contains material which is subject to copyright protection. The copyright owner has no objection to the facsimile reproduction by anyone of the patent document or the patent disclosure, as it appears in the Patent and Trademark Office patent file or records, but otherwise reserves all copyright rights whatsoever. Technical Field

[0003] The present disclosure generally relates to methods, systems, and apparatus for timing skew calibration in time-interleaved data converters. Background Art

[0004] Time-interleaved data converters, such as analog-to-digital converters (ADCs) and digital-to-analog converters (DACs), are widely used in various systems. Time-interleaved ADCs (TI-ADCs) comprise a large number of individual unit ADCs, requiring a multi-level sampling stage to capture and demultiplex the broadband input signal for digitization by the unit ADCs. Given the large number of unit ADCs and the high clock speed within a TI-ADC, the alignment of the high-speed sample clock between different levels directly impacts system performance, such as the quality of signal conversion from the analog-to-digital domain. This becomes particularly problematic in the context of carrier aggregation (CA).

[0005] Therefore, a method, system, and apparatus for timing skew calibration of TI-ADC in carrier aggregation are provided. Summary of the Invention BRIEF DESCRIPTION OF THE DRAWINGS

[0006] A further understanding of the nature and advantages of certain embodiments may be realized by reference to the remainder of the specification and the accompanying drawings, in which like reference numerals are used to refer to like components. In some instances, a sub-label is associated with a reference numeral to designate one of multiple similar components. When reference is made to a reference numeral without specifying the existing sub-label, it is intended to refer to all such multiple similar components.

[0007] Figure 1 is a schematic block diagram of a system for timing skew calibration control in a TI-ADC according to various embodiments;

[0008] Figure 2 is a schematic block diagram of a fourth generation long term evolution (4G-LTE) time division duplex (TDD) radio frame according to various embodiments;

[0009] Figure 3 is a schematic block diagram of a fifth generation new radio (5G-NR) TDD radio frame according to various embodiments;

[0010] Figure 4 is a schematic diagram illustrating an example of a frame control scheme for a TDD-TDD component carrier according to various embodiments;

[0011] Figure 5 is a timing diagram illustrating a timing skew calibration control scheme for an FDD-TDD component carrier according to various embodiments;

[0012] Figure 6 is a timing diagram illustrating a timing skew calibration control scheme for a TDD-TDD component carrier according to various embodiments; and

[0013] Figure 7 is a flow chart of a method for controlling timing deskew in a TI-ADC in CA, according to various embodiments. DETAILED DESCRIPTION

[0014] Various embodiments provide tools and techniques for timing deskew in TI-ADCs in CA.

[0015] In some embodiments, a method for timing skew calibration control in a TI-ADC in carrier aggregation is provided. The method may include: receiving one or more first frames of a first component carrier signal having a first uplink-downlink subframe pattern; receiving one or more additional frames of at least one additional component carrier signal, the one or more additional frames including one or more second frames of a second component carrier signal, the at least one additional component carrier signal including the second component carrier signal; and activating timing skew calibration of at least one of the first or second component carrier signals based at least in part on an operating mode of the second component carrier signal and respective symbols of the first and second component carrier signals.

[0016] In some embodiments, an apparatus for controlling timing skew calibration in a TI-ADC in carrier aggregation is provided. The apparatus may include an analog-to-digital converter configured to receive one or more first frames of a first component carrier signal having a first uplink-downlink subframe pattern, and one or more additional frames of at least one additional component carrier signal, the one or more additional frames including one or more second frames of a second component carrier signal, the at least one additional component carrier signal including the second component carrier signal. The apparatus may further include control logic configured to activate timing skew calibration for at least one of the first or second component carrier signal based at least in part on an operating mode of the second component carrier signal and respective symbols of the first and second component carrier signals.

[0017] In another embodiment, an apparatus for controlling timing skew calibration in a TI-ADC in carrier aggregation may include a non-transitory computer-readable medium in communication with a processor, the non-transitory computer-readable medium having encoded thereon a set of instructions executable by the processor to perform various functions. The set of instructions may include instructions executable by the processor to: receive one or more first frames of a first component carrier signal having a first uplink-downlink subframe pattern; receive one or more additional frames of at least one additional component carrier signal, the one or more additional frames including one or more second frames of a second component carrier signal, the at least one additional component carrier signal including the second component carrier signal; and activate timing skew calibration of at least one of the first or second component carrier signals based at least in part on an operating mode of the second component carrier signal and respective symbols of the first and second component carrier signals.

[0018] In the following description, for purposes of explanation, numerous details are set forth to provide a thorough understanding of the described embodiments. However, it will be understood by those skilled in the art that other embodiments may be practiced without some of these details. In other examples, structures and devices are shown in block diagram form without complete details for the sake of clarity. Several embodiments are described herein, and although various features are attributed to different embodiments, it will be understood that features described with respect to one embodiment may also be incorporated with respect to other embodiments. However, by the same reference, any single feature or features of any described embodiment should not be considered essential to every embodiment of the present invention, as other embodiments of the present invention may omit such features.

[0019] Similarly, when an element is referred to herein as being "connected" or "coupled" to another element, it is understood that the element may be directly connected to the other element or have intervening elements between the elements. In contrast, when an element is referred to as being "directly connected to another element" or "directly coupled to another element," it is understood that no intervening elements are present in the "direct" connection between the elements. However, the presence of a direct connection does not preclude other connections in which intervening elements may be present.

[0020] In addition, for ease of description, the methods and processes described herein may be described in a particular order. However, it should be understood that unless the context indicates otherwise, intervening processes may occur before and / or after any portion of the described process, and that various procedures may be reordered, added, and / or omitted according to various embodiments.

[0021] Unless otherwise indicated, all numbers used herein to express quantities, dimensions, and the like should be understood as being modified in all instances by the term "about". In this application, unless expressly stated otherwise, the use of the singular includes the plural, and the use of the terms "and" and "or" means "and / or" unless otherwise indicated. Furthermore, the use of the term "including" and other forms such as "includes" and "included" should be considered non-exclusive. Furthermore, unless expressly stated otherwise, terms such as "element" or "component" encompass both elements and components comprising one unit and elements and components comprising more than one unit.

[0022] Conventional methods for skew calibration are not applicable to instances where two carriers are aggregated and present at the input of the TI-ADC array. Specifically, in the case of two component carrier (CC) CA, calibration using conventional techniques cannot be achieved. As used herein, a component carrier may refer to a carrier signal (e.g., a frequency block) that will (or is being) aggregated with another carrier signal in CA. The embodiments described below improve the performance of the TI-ADC system by providing an effective solution to perform skew calibration in a two-CC case (focusing on specific frequency division duplex (FDD) and time division duplex (TDD) (e.g., FDD-TDD) and TDD-TDD combinations) by utilizing TDD timing control and carrier detection.

[0023] Figure 1 1 is a schematic block diagram of a system for timing skew calibration control in a TI-ADC according to various embodiments. System 100 includes a clock divider 105, skew calibration control logic 110, skew calibration circuit 115, one or more ADC slices 120a to 120n, and a retimer circuit 125. It should be noted that the various components of system 100 are Figure 1 1 is schematically shown in FIG, and modifications to the various components and other arrangements of system 100 may be possible according to various embodiments.

[0024] In various embodiments, a clock input to the system is coupled to a clock divider 105, which can divide the clock into one or more input clock signals for each of the one or more ADC slices 120a to 120n. The clock divider 105 is coupled to a skew calibration circuit 115, which is further coupled to the skew calibration control logic 110. The skew calibration circuit 115 can be configured to calibrate the timing skew of the input clock signal according to the skew calibration control logic 110. Specifically, timing skew (also often referred to as "clock skew") can refer to the difference in the expected relative phase of the clock signal from the input clock signal at each of the corresponding ADC slices 120a to 120n and / or the corresponding sub-ADCs (e.g., the difference in the relative phase of the input clock signal). Therefore, the skew calibration circuit 115 can calibrate the timing skew of the corresponding clock signal provided to each of the one or more ADC slices 120a to 120n to correct for these differences in phase. One or more ADC slices 120a to 120n may further receive as input a corresponding "slice" of an analog input signal that has been partitioned into n slices, and convert the corresponding slice of the analog input signal into a corresponding slice of a digital output signal. Thus, an ADC slice may refer to a group of corresponding sub-ADCs that process a corresponding slice of the input signal. The output of each of the one or more ADC slices 120a to 120n may be further coupled to a retimer circuit 125, which may adjust the timing of the output of the corresponding ADC slice (e.g., a slice of a digital signal) to form a digital output signal and provide the digital output signal to a downstream processor (e.g., a digital signal processor (DSP)).

[0025] In various embodiments, one or more ADC slices 120a through 120n are part of a TI-ADC, each of which further includes one or more corresponding sub-ADCs. The first ADC slice 120a may receive a first clock signal from a clock divider 105, which includes a first-level clock signal for a track-and-hold (T&H) circuit (e.g., a multi-level T&H circuit). In some embodiments, the first-level clock signal may be generated by a clock generator, such as a first clock generator. The T&H circuit, also known as a "sample-and-hold" circuit, is an input sampling circuit for each of the one or more ADC slices 120a through 120n.

[0026] In various examples, a system clock, such as an I / IB / Q / QB clock from a receiver phase-locked loop (PLL), may be divided by a clock divider 105. The clock divider 105 is configured to divide the input clock into n divided clocks corresponding to each of n channels (e.g., a corresponding ADC slice in one or more ADC slices 120a to 120n), where n is an integer. The divided clock signals are then provided to a skew calibration circuit 115, which may be configured to remove sampling time mismatches at the T&H. The skew calibration circuit 115 may calibrate the divided clock signals according to the skew calibration control logic 110. In some examples, clock skew may be adjusted by adjusting the number of clock inverters that are turned on. Thus, in various examples, a first-level clock signal (e.g., a skew-calibrated divided clock signal) is generated and provided to the corresponding ADC slices 120a to 120n.

[0027] In various embodiments, the skew calibration control logic 110 may include hardware, software, or a combination of hardware and software. The skew calibration control logic 110 may be configured to control skew calibration of a divided clock signal based at least in part on TDD radio frames of one or more TDD CCs in a two-CC CA system. Specifically, in various instances, the skew calibration control logic 110 may be configured to control skew calibration activation in two two-CC cases: FDD-TDD and TDD-TDD. As used herein, FDD-TDD may refer to a two-CC case in which a 4G-LTE CC is in FDD operation and a 5G-NR CC is in TDD operation. Similarly, TDD-TDD may refer to a two-CC case in which both a 4G-LTE CC and a 5G-NR CC are in TDD operation. In current 5G-NR deployments in the 3.5 GHz mid-band, all network timing synchronization can typically be achieved by using the same TDD frame structure configuration and absolute timing reference. When the 3.5 GHz band TDD is aggregated with the 2 GHz and 2.5 GHz bands that can operate in FDD or TDD, multi-band operation, such as CA with two CCs, becomes mandatory. As will be described in more detail below, the proposed method and associated control scheme of the skew calibration control logic 110 provides an effective solution to mitigate the special case of timing skew mismatch in skew timing calibration.

[0028] In various examples, in TDD operation, 4G-LTE utilizes frames with a total duration of 10 milliseconds (ms). Each frame may include 10 subframes, each subframe having a duration of 1 ms. Each LTE TDD frame may be frequency-divided into a 6×10 matrix of subframes for a total of 60 subframes (or 120 resource blocks (RBs), two RBs per subframe). Each RB includes one slot and 12 subcarriers, where each slot is half a subframe. Each slot includes 7 symbols. Each RB may further include multiple resource elements (REs), where each resource element is a combination of a subcarrier and a symbol. Thus, in the above example, each RB includes 84 REs.

[0029] 4G-LTE utilizes a fixed TDD UL-DL pattern for each frame. In each frame, the pattern is referred to as TDD configuration numbers 0, 1, 2, 3, 4, 5, and 6. In various embodiments, the skew calibration control logic 110 may be configured to use or cause to be used an uplink (UL)-downlink (DL) pattern with a periodicity of 5 ms for downlink (DL) to DL-UL transitions. In various examples, the DL-UL pattern may refer to a pattern of subframe types for a frame (or multiple frames). In some examples, this may correspond to TDD configuration numbers 0, 1, 2, and 6 for DL-UL transitions. For DL-UL switching, a guard period (GP) may be utilized between DL-UL transitions. In some examples, a GP may refer to a period during which no data is exchanged on the corresponding channel (e.g., CC). GP is implemented during special subframes (interchangeably referred to as "GP" subframes or "S" subframes). In one example, a GP subframe includes 7 DL symbols (labeled "D"), followed by two GP symbols (labeled "G"), and 5 UL symbols (labeled "U").

[0030] As used herein, UL (uplink) may refer to upstream communication. Using the example of a base station, UL may refer to data received by the base station from a user equipment (UE), which may include end-user devices such as mobile phones and computers. DL (downlink) may refer to downstream communication. Continuing with the example of a base station, DL may refer to data to be transmitted to the UE. Thus, when a frame, subframe, time slot, or symbol is a DL frame, subframe, time slot, or symbol, the corresponding time corresponding to the frame, subframe, time slot, or symbol is used (or indicated to be used) for DL ​​communication. Similarly, when a frame, subframe, time slot, or symbol is a UL frame, subframe, time slot, or symbol, the corresponding time is used (or indicated to be used) for UL communication. As used herein, a symbol may refer to the state (e.g., UL, DL, GP) of a channel (e.g., CC) during a corresponding unit time interval (e.g., the smallest time unit within which the channel state can be set for a given CC).

[0031] In 5G-NR, in various instances, a unified frame of 10ms duration is used for both FDD and TDD operations, each with 10 subframes of 1ms duration. In each subframe, 1, 2, 4, 8, or 16 slots may be used per subcarrier spacing. Each slot may include 14 symbols of three types: D (for downlink), U (for uplink), and F (for flexible). In FDD operation, a subframe is assigned to the DL band when all D is used, or to the UL band when all U is used. In TDD operation, 56 different UL-DL types are supported. A "D" subframe is used to refer to a subframe with all D symbols, and "U" is used to designate a subframe with all U symbols.

[0032] In various embodiments, the skew calibration control logic 110 may be configured to use or cause to be used one of two UL-DL patterns out of 56 different UL-DL patterns. For example, the timing skew calibration control logic 110 may be configured to use or cause to be used one of the following two UL-DL patterns for a given TDD frame: "DDDSU DDDSU" or "DDDDDDDSUU." Thus, in various examples, a special sub-frame "S" is used to designate a sub-frame having mixed D, G (e.g., guard period), and U symbols. In various embodiments, an S sub-frame may include 14 symbols having a 10:2:2 ratio of D, G, and U symbols (e.g., "DDDDDDDDDDGGUU").

[0033] Considering this basic structure, according to the embodiments set out above, examples of 4G-LTE TDD frames and 5G-NR TDD frames are referred to below. Figure 2 and 3 describe.

[0034] Figure 2 2 is a schematic block diagram of a 4G-LTE TDD radio frame 200 according to various embodiments. The 4G-LTE TDD radio frame 200 includes a first radio frame 205, a second radio frame 210, a third radio frame 215, and a fourth radio frame 220. The first radio frame 205 includes 10 subframes: a first subframe 205a to a tenth subframe 205j. Similarly, the second radio frame 210 includes 10 subframes: a first subframe 210a to a tenth subframe 210j. Each of the third and fourth radio frames 215, 220 may include 10 subframes, starting from the respective first subframe 215a, 220a to the tenth subframe 215j, 220j. It should be noted that the arrangement of the 4G-LTE TDD radio frame 200 is Figure 22 and modifications to the arrangement of frames 205 , 210 , 215 , 220 , sub-frames 205 a to 205 j , 210 a to 210 j , 215 a to 215 j , 220 a to 220 j and symbols may be possible and according to various embodiments.

[0035] In various embodiments, the first radio frame 205 includes first through tenth subframes 205a through 205j with an UL-DL pattern of "D, GP, U, D, D, D, D, D, D," starting with the first subframe 205a being a "D" subframe, the second subframe 205b being a "GP" subframe, the third subframe 205c being a "U" subframe, and all subsequent subframes 205d through 205j of the first frame 205 being "D" subframes. As previously described, a "D" subframe may indicate a subframe containing all D symbols. A "GP" subframe may indicate a special subframe containing a mix of D, G, and U symbols. In various embodiments, a GP subframe may include 14 symbols in the following order: "DDDDDDDGGUUUUU." The second frame 210 includes subframes 210a through 210j with an UL-DL pattern of "D, GP, U, D, D, GP, U, D, D." The third frame 215 includes sub-frames 215a to 215j that follow the UL-DL pattern “D, GP, U, U, D, D, GP, U, U, D”, and the fourth frame 220 includes sub-frames 220a to 220j that follow the UL-DL pattern “D, GP, U, U, U, D, GP, U, U, U”.

[0036] The preferred DL / UL ratio for 4G-LTE is 20 / 13 and is widely adopted by 4G-LTE mobile network operators (MNOs). For mid-band TDD operation, the global trend is toward the adoption of SFNs (Single Frequency Networks), where all network timing is synchronized to a unified TDD frame and timing control to minimize TDD interference. In various embodiments, TDD frame control may be employed, where at least two of every four frames for 4G-LTE TDD are selected to follow a UL-DL pattern with a 5ms periodicity according to configuration numbers 0, 1, 2, or 6. The first frame 205 may therefore follow a UL-DL pattern with a 10ms periodicity according to TDD configuration number 5. The second frame 210 may follow a UL-DL pattern according to TDD configuration 2, the third frame 215 may follow a UL-DL pattern according to TDD configuration 1, and the fourth frame 220 may follow a UL-DL pattern according to TDD configuration 0. Thus, a 20 / 13 DL / UL ratio can be implemented using four 10ms frames, or 40 subframes. It should be understood that in other embodiments, other cyclic permutations that accomplish the same purpose may be utilized, wherein at least two frames that follow one of configuration numbers 0, 1, 2, and 6 are selected.

[0037] Figure 33 is a schematic block diagram of a fifth generation new radio (5G-NR) TDD radio frame 300 according to various embodiments. The 5G-NR TDD radio frame 300 includes a first radio frame 305, which includes a first subframe 305a to a tenth subframe 305j. The fourth subframe 305d and the ninth subframe 305i are special subframes designated by the letter "S". Each subframe may include 14 symbols. The symbols of the fourth subframe 305d are shown, starting from the first symbol 310a to the fourteenth symbol 310n. It should be noted that the arrangement of the 5G-NR TDD radio frame 300 is as follows: Figure 3 3 and 4. Modifications to the arrangement of the frame 305, sub-frames 305a to 305j and symbols 310a to 310n are schematically shown in FIG. 3 and may be possible and according to various embodiments.

[0038] In various embodiments, the first rate frame 305 includes first through tenth subframes 305a through 305j having an UL-DL pattern of "D, D, D, S, U, D, D, D, S, U," starting with the first subframe 305a being a "D" subframe, the second subframe 305b being a "D" subframe, the third subframe 305c being a "D" subframe, the fourth subframe 305d being an "S" subframe, the fifth subframe 305e being a "U" subframe, and all subsequent subframes 305f through 305j repeating the pattern "D, D, D, S, U." As previously described, a "D" subframe may indicate a subframe containing all D symbols. An "S" subframe may indicate a special subframe containing a mix of D, G, and U symbols. In various embodiments, an S subframe may include 14 symbols in the following order of D:G:U symbols following a 10:2:2 ratio: "DDDDDDDDDDGGUU."

[0039] In various embodiments, a TDD frame DDDSU is employed for most 5G NR bands, and in particular, for bands n77 and n78 spanning frequencies from 3.4 GHz to 3.8 GHz. This corresponds to a DL / UL symbol ratio of =4×(52:16)=204:64, where the two guard period symbols "G" have a duration of 2 symbols. It will be appreciated that in other embodiments, another UL-DL pattern may be used. Specifically, an alternative UL-DL pattern of "D, D, D, D, D, D, D, S, U, U" of the subframe may be utilized, as will be described below with respect to the following Figure 4 Describe in more detail.

[0040] Figure 4 FIG2 is a diagram illustrating an example of a frame control scheme 400 for a TDD-TDD CC carrier aggregation case according to various embodiments. Specifically, CA combining a 4G-LTE CC and a 5G-NR CC, both operating in TDD, is depicted. Figure 4A specific 5G-NR CC numerology chosen for explanation purposes is depicted (e.g., 15 kHz subcarrier spacing corresponding to numerology 0), but it should be understood that in other embodiments, different 5G numerologies may be utilized by the 5G-NR CC, resulting in different Figure 4 As previously described, in other embodiments, each subframe may include 1, 2, 4, 8, or 16 time slots depending on the subcarrier spacing.

[0041] Thus, frame control scheme 400 presents a simplified case where the slots of a 5G-NR TDD frame have the same duration as a 4G-LTE subframe (e.g., 1 ms), and techniques for performing timing skew calibration to operate during periods where only one TDD or FDD component carrier is present while the other TDD component carrier is in downlink transmission. Specifically, in frame control scheme 400, a subcarrier spacing of 15 kHz is used for both 4G-LTE CCs and 5G-NR CCs. A 1 ms 4G-LTE subframe corresponds to one 5G-NR slot. Frame control scheme 400 shows both 4G-LTE and 5G-NR CCs aligned in the uplink over a duration of 40 ms (a period of 4 frames).

[0042] In other examples employing other 5G numerologies, with corresponding subcarrier spacings of 30kHz, 60kHz, and 120kHz, a 1ms 5G subframe may include 2, 4, and 8 slots, respectively, each having corresponding durations of 0.5ms, 0.25ms, and 0.125ms. Thus, a 1ms 5G-NR subframe may include 2, 4, or 8 slots, with each slot further comprising 14 symbols. Thus, in some examples, TDD DL / UL patterns are scheduled at the subframe level for 4G-LTE and at the slot level for 5G-NR, and the relative timing relationships may differ from those depicted in frame control scheme 400. However, the same principles of timing skew correction remain applicable at the symbol level to a finer granularity, specifically, within the "S" slot. Therefore, it should be understood that embodiments should not be limited to any single 5G-NR numerology or frame structure, and that other 5G-NR numerologies may be utilized in other embodiments.

[0043] Thus, in various embodiments, the frame control scheme 400 includes a first scheme 405, a second scheme 410, a third scheme 415, and a fourth scheme 420, which differ depending on the 5G-NR TDD frame utilized (e.g., a repeating "DDSSU" pattern or a "DDDDDDDSUU" pattern). Using the n77 3.5 GHz band as an example, for most 5G-NR bands, and in particular for the n77 and n78 bands, the TDD frame DDDSU (12:2:2) is deployed.

[0044] In various embodiments, the 4G-LTE band (lower) may use “DGPUDD DGPUDD DGPUUD DGPUUD DGPUUU DGPUUUDGPUDD DDDDD” for a DL / UL ratio of 20 / 13 in four possible arrangements as shown in the first to fourth schemes 405 to 420. The 5G-NR band may correspondingly use “DDDSU DDDSU DDDSU DDDSUDDDSU DDDSU DDDSU DDDSU” or “DDDDD DDSUU DDDDD DDSUU DDDDD DDSUU DDDDD DDSUU DDDDD DDSUU” for a DL / UL ratio of 80 / 30. As shown below, in various embodiments, for single carrier skew calibration, the period corresponding to the shaded time slot (in this example, which corresponds to the entire sub-frame) indicates the period that can be used solely for skew calibration of the 5G-NR carrier, while the period corresponding to the shaded time slot (which corresponds to the sub-frame) can be used solely for skew calibration of the 4G-LTE carrier.

[0045] Therefore, in various embodiments, in a first scenario 405, a 4G-LTE CC may utilize a UL-DL pattern of "DGPUDD DGPUDDDGPUUD DGPUUD DGPUUU DGPUUU DGPUDD DDDDD." In a second scenario 410, a 4G-LTE CC may utilize a UL-DL pattern of "DGPUUU DGPUUU DGPUDD DDDDD DGPUDD DGPUUD DGPUUD." In a third scenario 415, a 4G-LTE CC may utilize a UL-DL pattern of "DGPUUD DGPUUD DGPUUU DGPUUU DGPUDD DDDDD DGPUDDDGPUDD." In a fourth scenario 420, a 4G-LTE CC may utilize a UL-DL pattern of "DGPUDD DDDDD DGPUDD DGPUUD DGPUUD DGPUUU DGPUUU." In each of the first to fourth schemes, the 5G-NR CC may utilize the “DDDDD DDSUU DDDDD DDSUU DDDDD DDSUU DDDDD DDSUU” UL-DL pattern for a DL / UL ratio of 80 / 30.

[0046] Thus, in various embodiments, a CC may be aligned during an uplink subframe, slot, and / or symbol, while all other CCs are aligned during a downlink (or special / guard period) subframe, slot, and / or symbol. This is discussed below with respect to Figure 5 and 6The timing diagram is described in more detail. In addition, although the above example and the timing diagram below may refer to a two-CC example, it should be understood that in other embodiments, there may be more than two CCs. Specifically, in the case where two or more component carriers are presented to the timing skew calibration subsystem (e.g., timing skew control logic and timing skew calibration circuit) at the same time, there may be a possible risk of inter-carrier interference, thereby degrading performance. Therefore, timing skew calibration is selectively performed for periods in which only one component carrier is present. Therefore, in the case where the TDD CCs in both 4G-LTE and / or 5G NR systems are simultaneously received by the uplink receiver using the TI-ADC, a period of only one uplink CC is presented to the timing skew calibration subsystem of the uplink receiver for calibration, wherein multiple FDD and / or TDD CCs may be present during the operation of the uplink receiver in CA mode.

[0047] Figure 5 5 is a timing diagram 500 illustrating a timing skew calibration control scheme for FDD-TDD component carriers according to various embodiments. Specifically, timing diagram 500 illustrates a timing diagram for the skew calibration control scheme for various embodiments, where a 4G-LTE carrier (e.g., CC) may operate in FDD while a 5G-NR carrier operates in TDD.

[0048] A first timing diagram 505 illustrates the TDD subframe state of a second carrier (e.g., a 5G-NR carrier), while the frequency band associated with the first carrier (e.g., a 4G-LTE carrier) is the UL band. A second timing diagram 510 illustrates the TDD on / off signal (of the second carrier) over time. Specifically, when TDD is "on" for the second carrier (e.g., TDD is in the downlink or S / GP subframe or one of the downlink symbols of the S / GP subframe), timing skew calibration for the first carrier operating in FDD occurs only in the shaded area. Thus, calibration can occur on the FDD UL signal of the first carrier when TDD is on, and is in a calibration standby state when TDD is off (e.g., in the uplink subframe and / or uplink symbols of a special frame).

[0049] Figure 6 6 is a timing diagram illustrating a timing skew calibration control scheme for TDD-TDD component carriers according to various embodiments. Specifically, timing diagram 600 illustrates a timing diagram for the skew calibration control scheme for various embodiments, where a 4G-LTE carrier and a 5G-NR carrier operate in TDD.

[0050] A first timing diagram 605 illustrates TDD subframes for a lower-band carrier 1 (e.g., 4G-LTE) and a higher-band carrier 2 (e.g., a 5G-NR carrier). In various embodiments, the higher-band includes a TDD DL subframe (e.g., all D subframes in which all symbols in a subframe are downlink D symbols), followed by a special subframe or "S" subframe that includes D, G, and U symbols at a 10:2:2 symbol ratio, followed by a TDD UL subframe (e.g., all U subframes in which all symbols in a subframe are uplink U symbols). For lower-band carrier 2, the TDD DL subframe is followed by a guard period (e.g., GP) subframe that may, for example, include D, G, and U symbols at a 7:2:5 symbol ratio, followed by a TDD UL subframe.

[0051] In various embodiments, although both higher-band carrier 2 and lower-band carrier 1 exhibit 10 ms frames with a UL-UL periodicity of 5 ms, the TDD timing may be offset such that carrier 1 TDD timing is turned on (e.g., in the DL state) to coincide with the U symbol of the S subframe of carrier 2. In this way, calibration control may be staggered between the two carriers, as set forth in the second timing diagram 610 (e.g., calibration control signal timing diagram) as provided by, for example, using unified TDD frames and synchronized timing control in an SFN.

[0052] The second timing diagram depicts the TDD on / off signal for the second carrier (Carrier 2) at the top, followed by the first carrier (Carrier 1), followed by the calibration control timing for Carrier 1, followed by the calibration control timing for Carrier 2. As shown and as previously described with respect to Figure 4 In this example, calibration for carrier 1 can occur when TDD is in the off state for carrier 1 (e.g., TDD UL) and in the on state for carrier 2 (e.g., TDD DL). In some examples, calibration can be turned on during the GP subframe of carrier 1. This can include during the U symbol of the GP subframe. In another example, calibration can be turned on during the G symbol of the GP subframe. Similarly, calibration can be turned off when TDD is turned on for carrier 1 (e.g., TDD DL subframe). In some examples, this can occur during the S subframe of carrier 2. In another example, this can coincide with the start of the U symbol of the S subframe of carrier 2, while in other examples, it can occur during the G symbol.

[0053] Similarly, for carrier 2, calibration can be turned on when carrier 2 is in the TDD UL state (or subframe). In some examples, this can occur during the S subframe, for example, during the first U symbol of the S subframe or during the G symbol of the S subframe. Similarly, this can coincide with the TDD off state of carrier 1, where carrier 1 transitions from UL to DL operation. In this way, skew calibration for a carrier can only be activated when TDD is off on a carrier while it is on for other carriers aggregated with it. When both CCs are on, calibration remains standby for both carriers, and situations where both CCs are off can be avoided through TDD frame control via radio resource control (RRC) at the base station and / or skew calibration control logic implemented at the base station. In some examples, the base station comprises one or more of a gNodeB and / or an eNodeB.

[0054] It should be understood that in various embodiments, timing deskew may be implemented with any suitable timing deskew technique, including techniques known to those skilled in the art and later developed, and that the embodiments described herein are not limited to any single timing deskew technique.

[0055] Figure 7 is a flow chart of a method 700 for controlling timing skew calibration in a TI-ADC in CA according to various embodiments. The method 700 may begin at block 705 by receiving a first CC TDD frame utilizing a first UL-DL pattern. In various embodiments, the first CC may be a 5G-NR carrier (described previously with respect to FIG. Figure 5 and 6 (referred to as carrier 2). In some examples, the first CC may have a first UL-DL pattern of a subframe. As previously described, the UL-DL pattern may include one of "DDDSU DDDSU" or "DDDDD DDSUU" for a given TDD frame, where the UL-DL pattern may repeat.

[0056] Method 700 may continue at block 710 by receiving a second CC. In some examples, the second CC may be a 4G-LTE carrier (described previously with respect to Figure 5 and 6, referred to as carrier 1). In some instances, the second CC may be in FDD or TDD. In some instances, when in TDD, the second CC may have a DL-UL pattern exhibiting a DL / UL ratio of 20 / 13. As previously described, in some embodiments, the 4G-LTE band (lower) may use "DGPUDD DGPUDD DGPUUD DGPUUD DGPUUU DGPUUU DGPUDD DDDDD" in 4 possible arrangements of corresponding groups of DL-UL patterns (e.g., Group 1: DGPUDDDGPUDD; Group 2: DGPUUD DGPUUD; Group 3: DGPUUU DGPUUU; and Group 4: DGPUDD DDDDD). Figure 6 In display.

[0057] Method 700 continues at block 715 by determining the operating mode of the second CC. As used herein, operating mode may refer to TDD or FDD. Thus, at block 715, in various instances, a determination is made as to whether the second CC is in TDD or FDD mode (or operation). If it is determined that the second CC is in TDD operation, then at block 720, method 700 continues by determining whether the first CC is in a TDD-off state. As previously described, in various embodiments, the TDD-off state may correspond to an uplink subframe, or in some instances, to an uplink symbol in a special subframe, as previously described. A CC is considered to be in an "on" state when a frame is in one of a downlink or special / GP subframe or a downlink symbol of a special / GP subframe.

[0058] If it is determined that the first CC is in the TDD OFF state, method 700 may continue at block 725 by determining whether the second CC is in the TDD ON state. If the second CC is in the TDD ON state, method 700 may continue at block 730 by calibrating the timing skew of the first CC. Thus, in various embodiments, in the TDD-TDD2-CC case, the timing skew calibration control logic may be configured to activate timing skew calibration of the first CC when the frame is an uplink "U" symbol (e.g., OFF) and the second CC is a downlink symbol "D."

[0059] If it is determined at block 720 that the first CC is in the TDD-on state, method 700 may continue at block 735 by determining whether the second CC is in the TDD-off state. If it is determined that the second CC is in the TDD-off state, method 700 may continue at block 740 by calibrating the timing skew of the second CC. As described above, in various embodiments, in the TDD-TDD2-CC case, the timing skew calibration control logic may activate timing skew calibration of the second CC during a U symbol of the second CC that occurs concurrently with a D symbol of the first CC.

[0060] Similarly, in further embodiments, if it is determined at block 715 that the second CC is in FDD operation, the method 700 may further include determining whether the first CC is in the TDD-on state at block 745. If it is determined that the first CC is in the TDD-on state, the method 700 may continue by calibrating the timing skew of the second CC at block 745. As previously described, in various embodiments, in the FDD-TDD case, the timing skew calibration logic may activate timing skew calibration of the second CC (in FDD).

[0061] The techniques and processes described above with respect to various embodiments may be performed by the system 100 and / or subsystems and components thereof, such as those described above with respect to Figure 1 The skew calibration control logic 110 described herein may be implemented as described herein and may execute methods provided by various other embodiments as described herein.

[0062] Although some features and aspects have been described with respect to embodiments, those skilled in the art will recognize that numerous modifications are possible. For example, the methods and processes described herein may be implemented using hardware components, custom integrated circuits (ICs), programmable logic, and / or any combination thereof. Furthermore, although, for ease of description, the various methods and processes described herein may be described with respect to specific structural and / or functional components, the methods provided by the various embodiments are not limited to any specific structural and / or functional architecture, but may be implemented with any suitable hardware configuration. Similarly, although some functionality is attributed to one or more system components, unless the context indicates otherwise, this functionality may be distributed among various other system components according to several embodiments.

[0063] In addition, although the procedures of the methods and processes described herein are described in a particular order for ease of description, unless the context indicates otherwise, the various procedures may be reordered, added, and / or omitted according to various embodiments. In addition, the procedures described with respect to one method or process may be incorporated into other methods or processes described; similarly, system components described according to a particular structural architecture and / or with respect to one system may be organized in alternative structural architectures and / or incorporated into other systems described. Therefore, although those embodiments are described with or without some features for ease of description and to illustrate aspects of various embodiments, unless the context indicates otherwise, the various components and / or features described herein with respect to a particular embodiment may be replaced, added, and / or subtracted from other embodiments described. Therefore, although several embodiments are described above, it should be understood that the present invention is intended to cover all modifications and equivalents within the scope of the appended claims.

Claims

1. A method for signal processing, comprising: receiving, using an analog-to-digital converter, one or more first frames of a first component carrier signal having a first uplink-downlink sub-frame pattern; receiving, using the analog-to-digital converter, one or more additional frames of at least one additional component carrier signal, the one or more additional frames comprising one or more second frames of a second component carrier signal, the at least one additional component carrier signal comprising the second component carrier signal; and activating, using control logic, timing skew calibration of the first component carrier signal or the second component carrier signal based at least in part on an operating mode of the first component carrier signal and the second component carrier signal and respective symbols of the first component carrier signal and the second component carrier signal; The first uplink-downlink sub-frame pattern follows a repeating sequence of sub-frame types.

2. The method according to claim 1, further comprising: In response to the operating mode of the second component carrier signal being time division duplex: Timing deskew calibration of the first component carrier signal is activated during an uplink symbol of the first component carrier signal occurring concurrently with a downlink symbol of the second component carrier.

3. The method according to claim 1, further comprising: In response to the operating mode of the second component carrier signal being time division duplex: Timing deskew calibration of the second component carrier signal is activated during an uplink symbol of the second component carrier signal occurring concurrently with a downlink symbol of the first component carrier.

4. The method according to claim 1, further comprising: In response to the operating mode of the second component carrier signal being frequency division duplex: Timing deskew of the second component carrier signal is activated during downlink symbols of the first component carrier.

5. The method of claim 1 , wherein the first uplink-downlink subframe pattern is a repeating pattern of subframe types D, S, and U, wherein subframe type D includes all downlink symbols, subframe type S includes a mix of downlink, guard period, and uplink symbols, and subframe type U includes all uplink symbols, wherein a first repeating sequence of subframe types follows the order: D, D, D, S, U.

6. The method of claim 5, wherein the sub-frame type S comprises a symbol in a symbol sequence of 10 downlink symbols, followed by two guard period symbols, followed by two uplink symbols.

7. The method of claim 5, wherein the second repeating sequence of sub-frame types follows the following order: D, D, D, D, D, D, S, U, U.

8. The method of claim 7, wherein the first component carrier signal is a fifth generation new radio signal and the second component carrier signal is a fourth generation long term evolution signal.

9. A device for signal processing, comprising: An analog-to-digital converter configured to: receiving one or more first frames of a first component carrier signal having a first uplink-downlink subframe type, and receiving one or more additional frames of at least one additional component carrier signal, the one or more additional frames comprising one or more second frames of a second component carrier signal, the at least one additional component carrier signal comprising the second component carrier signal; control logic configured to activate timing skew calibration of the first component carrier signal or the second component carrier signal based at least in part on an operating mode of the first component carrier signal and the second component carrier signal and respective symbols of the first component carrier signal and the second component carrier signal; The first uplink-downlink sub-frame pattern is a repetitive pattern of sub-frame types D, S, and U.

10. The apparatus of claim 9, wherein in response to the operating mode of the second component carrier signal being time division duplex, the control logic is further configured to activate timing deskew of the first component carrier signal during an uplink symbol of the first component carrier signal that occurs concurrently with a downlink symbol of the second component carrier.

11. The apparatus of claim 9 , wherein in response to the operating mode of the second component carrier signal being time division duplex, the control logic is further configured to activate timing skew calibration of the second component carrier signal during an uplink symbol of the second component carrier signal that occurs concurrently with a downlink symbol of the first component carrier.

12. The apparatus of claim 9, wherein in response to the operating mode of the second component carrier signal being frequency division duplex, the control logic is further configured to activate timing deskew of the second component carrier signal during downlink symbols of the first component carrier.

13. The apparatus of claim 9 , wherein the sub-frame type D includes all downlink symbols, the sub-frame type S includes a mix of downlink, guard period, and uplink symbols, and the sub-frame type U includes all uplink symbols, wherein the first uplink-downlink sub-frame pattern follows a repeating sequence of sub-frame types, wherein a first repeating sequence of sub-frame types follows the following order: D, D, D, S, U.

14. The apparatus of claim 13, wherein the sub-frame type S comprises a symbol in a symbol sequence of 10 downlink symbols, followed by two guard period symbols, followed by two uplink symbols.

15. A non-transitory computer-readable medium for signal processing in communication with a processor, the non-transitory computer-readable medium having encoded thereon a set of instructions executable by the processor to: receiving one or more first frames of a first component carrier signal having a first uplink-downlink sub-frame type; receiving one or more additional frames of at least one additional component carrier signal, the one or more additional frames comprising one or more second frames of a second component carrier signal, the at least one additional component carrier signal comprising the second component carrier signal; and activating timing skew calibration of the first component carrier signal or the second component carrier signal based at least in part on an operating mode of the first component carrier signal and the second component carrier signal and respective symbols of the first component carrier signal and the second component carrier signal; The first uplink-downlink subframe type is a repeating pattern of subframe types D, S, and U, wherein subframe type D includes all downlink symbols, subframe type S includes a mix of downlink, guard period, and uplink symbols, and subframe type U includes all uplink symbols.

16. The non-transitory computer-readable medium of claim 15, wherein the set of instructions is further executable by the processor to: In response to the operating mode of the second component carrier signal being time division duplex: Timing deskew calibration of the first component carrier signal is activated during an uplink symbol of the first component carrier signal occurring concurrently with a downlink symbol of the second component carrier.

17. The non-transitory computer-readable medium of claim 15, wherein the set of instructions is further executable by the processor to: In response to the operating mode of the second component carrier signal being time division duplex: Timing deskew calibration of the second component carrier signal is activated during an uplink symbol of the second component carrier signal occurring concurrently with a downlink symbol of the first component carrier.

18. The non-transitory computer-readable medium of claim 15, wherein the set of instructions is further executable by the processor to: In response to the operating mode of the second component carrier signal being frequency division duplex: Timing deskew of the second component carrier signal is activated during downlink symbols of the first component carrier.

19. The non-transitory computer-readable medium of claim 15 , wherein the first uplink-downlink subframe pattern follows a repeating sequence of subframe types, wherein a first repeating sequence of subframe types follows the following order: D, D, D, S, U, wherein the subframe type S comprises a symbol in a symbol sequence of 10 downlink symbols, followed by two guard period symbols, followed by two uplink symbols.

20. The non-transitory computer-readable medium of claim 15 , wherein the second component carrier signal has a second uplink-downlink subframe pattern of subframe types D, GP, and U, wherein subframe type D includes all downlink symbols, subframe type GP includes a mix of downlink, guard period, and uplink symbols, and subframe type U includes all uplink symbols, wherein the second uplink-downlink subframe pattern includes four respective groups of a sequence of subframe types, wherein the four corresponding groups include: a first group following the order: D, GP, U, D, D, D, GP, U, D, D; a second group following the order: D, GP, U, U, D, D, GP, U, U, D; a third group following the order: D, GP, U, U, U, DG, P, U, U, U; and a fourth group following the order: D, GP, U, D, D, D, D, D, D, D, and The second uplink-downlink sub-frame pattern is an arrangement of the four corresponding groups of sub-frame type sequences.

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