Display panel and display device

Abstract

The application discloses a display panel and a display device, and relates to the technical field of display, and is used for improving the packaging performance of the display panel. The display panel has a display area and a peripheral area surrounding the display area. The display panel comprises a substrate, a first metal layer, a planarization layer and a barrier structure. The first metal layer is arranged on the substrate, and the first metal layer comprises a signal line pattern located in the peripheral area. The planarization layer is arranged on the side of the first metal layer away from the substrate, and the planarization layer is provided with an opening in the peripheral area. The barrier structure is located in the peripheral area and surrounds the display area. At least part of the barrier structure is located in the opening. The signal line pattern is provided with at least one through hole, the orthographic projection of the at least one through hole on the substrate is located in the orthographic projection of the opening on the substrate, and the orthographic projection of the barrier structure on the substrate is located on the side close to the display area and / or the side away from the display area. The display panel provided by the application is used for displaying images.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of display, and in particular, to a display panel and a display device. BACKGROUND

[0002] With the development of display technology, the organic light-emitting diode (OLED) display panel has been widely used due to its self-luminous, wide viewing angle, high contrast, fast response, low power consumption, ultra-thin and other characteristics.

[0003] The OLED display panel adopts organic materials. However, the organic materials will undergo irreversible photo-oxidation reaction in the presence of water vapor and oxygen. In addition, water and oxygen also have strong corrosion effect on electrode materials such as aluminum, magnesium or silver, and the blocking effect of the display panel on water and oxygen will directly affect the reliability and service life of the display panel. How to improve the packaging effect of the display panel is a problem that needs to be solved urgently for the OLED display panel.

[0004] DISCLOSURE

[0005] Embodiments of the present disclosure provide a display panel and a display device, which can improve the packaging performance of the display panel and reduce the risk of packaging failure of the display device.

[0006] In one aspect, a display panel is provided. The display panel has a display area and a peripheral area surrounding the display area. The display panel includes a substrate, a first metal layer, a planarization layer, and a barrier structure. The first metal layer is disposed on the substrate, and the first metal layer includes a signal line pattern in the peripheral area. The planarization layer is disposed on a side of the first metal layer away from the substrate, and the planarization layer is provided with an opening in the peripheral area. The barrier structure is located in the peripheral area and surrounds the display area. At least part of the barrier structure is located in the opening. The signal line pattern is provided with at least one through hole, and a projection of the at least one through hole on the substrate is located in a projection of the opening on the substrate, and a projection of the barrier structure on the substrate is close to one side of the display area and / or away from the other side of the display area.

[0007] The display panel provided by the embodiments of the present disclosure, the first metal layer includes a via located in the peripheral area, and the via is located in the opening of the planarization layer, so that the via can increase the side wall area of the first metal layer. In this way, in the subsequent process of forming the planarization layer (forming the opening), the amount of developing solution in contact with the unit area of the side wall of the first metal layer can be reduced, the effect of sharing the developing solution and reducing the developing solution load effect is achieved, and then the erosion effect of the developing solution on the first metal layer is reduced, the risk of forming an undercut in the side wall of the first metal layer is reduced, and the depth of the undercut is reduced. In this way, the packaging performance of the display panel is improved.

[0008] In some embodiments, the signal line pattern is provided with a plurality of vias, the plurality of vias are arranged into at least one row, and the plurality of vias in one row are distributed at intervals along the extension direction of the barrier structure located in the opening.

[0009] In some embodiments, at least one row of vias is arranged on the side of the barrier structure close to the display area; and / or, at least one row of vias is arranged on the side of the barrier structure away from the display area.

[0010] In some embodiments, the plurality of vias are arranged into multiple rows, and any two adjacent rows of vias are distributed at intervals in a direction perpendicular to the arrangement direction of one row of vias.

[0011] In some embodiments, the opening includes opposite first and second boundaries, the first boundary is located on the side of the barrier structure close to the display area, and the second boundary is located on the side of the barrier structure away from the display area. At least one via is arranged between the barrier structure and the first boundary. At least one via is arranged between the barrier structure and the second boundary.

[0012] In some embodiments, the distance between the barrier structure and the first boundary is less than the distance between the barrier structure and the second boundary.

[0013] In some embodiments, the opening includes a first boundary located on the side of the barrier structure close to the display area. At least one via is arranged between the barrier structure and the first boundary, and the distance between at least one via and the barrier structure is 11 μm

[0014] ~ 40 μm.

[0015] In some embodiments, the opening includes a second boundary located on the side of the barrier structure away from the display area. At least one via is arranged between the barrier structure and the second boundary, and the distance between at least one via and the barrier structure is 11 μm

[0016] ~75 μm.

[0017] In some embodiments, the opening comprises a first boundary and a second boundary, the first boundary is located at a side of the barrier structure close to the display area, and the second boundary is located at a side of the barrier structure away from the display area. At least one of the through holes is provided between the barrier structure and the first boundary, and the minimum distance from the through hole to the first boundary is substantially equal to the minimum distance from the through hole to the barrier structure; and / or, at least one of the through holes is provided between the barrier structure and the second boundary, and the minimum distance from the through hole to the second boundary is substantially equal to the minimum distance from the through hole to the barrier structure.

[0018] In some embodiments, the shape of the orthographic projection of the through hole on the substrate is circular or rectangular.

[0019] In some embodiments, the area of the sidewall of one of the through holes is 40 μm 2 ~100 μm 2 .

[0020] In some embodiments, the sidewall of at least one of the through holes comprises a groove, the bottom wall of the groove is substantially arc-shaped, and the maximum distance from the lowest point of the bottom wall to the sidewall of the through hole is negatively correlated with the number of the through holes.

[0021] In some embodiments, the opening comprises a first boundary and a second boundary, the first boundary is located at a side of the barrier structure close to the display area, and the second boundary is located at a side of the barrier structure away from the display area. The first through hole is provided between the barrier structure and the first boundary, and the second through hole is provided between the barrier structure and the second boundary. The number of the first through holes is less than the number of the second through holes, and the average depth of the groove of the sidewall of the first through hole is less than the average depth of the groove of the sidewall of the second through hole; or, the number of the second through holes is less than the number of the first through holes, and the average depth of the groove of the sidewall of the second through hole is less than the average depth of the groove of the sidewall of the first through hole; or, the number of the first through holes is equal to the number of the second through holes, and the average depth of the groove of the sidewall of the first through hole is substantially equal to the average depth of the groove of the sidewall of the second through hole.

[0022] In some embodiments, the sidewall of at least one of the through holes comprises a groove; the more the number of the through holes, the smaller the average depth of each through hole or the average depth of the groove.

[0023] In some embodiments, the first metal layer includes at least one voltage signal line, and a portion of the at least one voltage signal line is disposed in the peripheral region and located in the at least one opening, and the via is disposed in the portion of the at least one signal line located in the peripheral region and in the at least one opening.

[0024] In some embodiments, the peripheral region includes a fan-out region located at one side of the display region, and a bonding region located at a side of the fan-out region away from the display region. The at least one voltage signal line includes a first voltage signal line and a second voltage signal line. The first voltage signal line includes a plurality of first sub-lines disposed in the display region, a first bus located in the fan-out region, and a first connecting line extending from the fan-out region to the bonding region; each of the plurality of first sub-lines is electrically connected to the first bus at a side close to the fan-out region, and the first bus is electrically connected to the first connecting line. The second voltage signal line includes a second sub-line disposed in the peripheral region and at least partially surrounding the display region, a second bus located in the fan-out region, and a second connecting line extending from the fan-out region to the bonding region; both ends of the second sub-line extend to the fan-out region and are electrically connected to the second bus, and the second bus is electrically connected to the first connecting line. Wherein, the first bus and the second bus extend along a first direction, and the first direction is an extension direction of a side of the display region where the fan-out region is located; the signal line pattern includes the first bus and the second bus, and the at least one via is disposed on the first bus and / or the second bus.

[0025] In some embodiments, a plurality of vias are disposed on the first bus, and the plurality of vias are arranged in a row along the first direction.

[0026] In some embodiments, the second voltage signal line includes two second buses located at two sides of the fan-out region respectively; each second bus is electrically connected to end portions of the second sub-lines extending to the same side of the fan-out region. A plurality of vias are disposed on at least one second bus, and the plurality of vias are arranged in a row along the first direction.

[0027] In some embodiments, the first metal layer includes a metal titanium layer, a metal aluminum layer, and a metal titanium layer stacked.

[0028] In some embodiments, the barrier structure includes a first barrier and a second barrier spaced apart, and the first barrier is closer to the display region than the second barrier. The at least one via is disposed on a side of the first barrier close to the display region, and / or the at least one via is disposed on a side of the second barrier away from the display region.

[0029] In some embodiments, the first barrier wall and the second barrier wall each comprise a spacer, and the spacer is located on the planarization layer.

[0030] In another aspect, a display device is provided. The display device comprises the display panel according to any one of the above embodiments.

[0031] It can be understood that the display device provided by the above embodiments of the present disclosure can achieve the beneficial effects as described above for the display panel, which will not be repeated here. BRIEF DESCRIPTION OF DRAWINGS

[0032] In order to more clearly illustrate the technical solutions in the present disclosure, the drawings needed to be used in some embodiments of the present disclosure will be briefly introduced as follows. Obviously, the drawings in the following description are only some drawings of the embodiments of the present disclosure, and other drawings can also be obtained by those skilled in the art according to these drawings. In addition, the drawings in the following description can be regarded as schematic diagrams, and are not limited to the actual size, actual process, actual timing of signals, etc. of the products involved in the embodiments of the present disclosure.

[0033] Figure 1 A structural diagram of the display panel according to some embodiments;

[0034] Figure 2A A structural diagram of the display panel according to some embodiments; Figure 1 A structural diagram of the display panel according to some embodiments;

[0035] Figure 2B A structural diagram of the display panel according to some embodiments; Figure 1 A structural diagram of the display panel according to some embodiments;

[0036] Figure 3A A structural diagram of the first metal layer according to some embodiments;

[0037] Figure 3B A structural diagram of the first metal layer according to some embodiments;

[0038] Figure 4 An equivalent circuit diagram of the pixel driving circuit according to some embodiments;

[0039] Figure 5A A planar structural diagram of the touch function layer according to some embodiments;

[0040] Figure 5B A cross-sectional view along the cross-sectional line D-D; Figure 5A

[0041] A structural diagram along the cross-sectional line C-C; Figure 6 Figure 3B

[0042] ​​Figure 7 A structure diagram of a signal line pattern sidewall groove in the related art;

[0043] Figure 8 A structure diagram of an array substrate according to some embodiments;

[0044] Figure 9A A structure diagram of Figure 8 A partial enlarged view of E;

[0045] Figure 9B A cross-sectional view along Figure 9A A cross-sectional view along section line F-F;

[0046] Figure 10A A structure diagram of Figure 8 Another partial enlarged view of E;

[0047] Figure 10B A cross-sectional view along Figure 10A A cross-sectional view along section line G-G;

[0048] Figure 11A A structure diagram of Figure 8 Still another partial enlarged view of E;

[0049] Figure 11B A cross-sectional view along Figure 11A A cross-sectional view along section line H-H;

[0050] Figure 11C A structure diagram of Figure 11B A partial enlarged view of I;

[0051] Figure 12 A schematic diagram of via hole setting positions according to some embodiments;

[0052] Figure 13 A structure diagram of a via hole sidewall groove according to some embodiments;

[0053] Figure 14 A structure diagram of Figure 1 A structure diagram along section line B-B;

[0054] Figure 15A A structure diagram of Figure 8 Still another partial enlarged view of E;

[0055] Figure 15B A structure diagram of Figure 8 Still another partial enlarged view of E;

[0056] Figure 15C A structure diagram of Figure 8 Still another partial enlarged view of E;

[0057] Figure 16A Another structure diagram of an array substrate according to some embodiments;

[0058] Figure 16B For Figure 16A A partial enlarged view of M in the middle;

[0059] Figure 17A For another structure diagram of an array substrate according to some embodiments;

[0060] Figure 17B For Figure 17A A partial enlarged view of N in the middle;

[0061] Figure 18 For a manufacturing step diagram of a display panel according to some embodiments. DETAILED DESCRIPTION

[0062] The technical solutions in the embodiments of the present disclosure will be clearly and completely described below with reference to the drawings. Obviously, the described embodiments are only some of the embodiments of the present disclosure, but not all the embodiments. Based on the embodiments provided by the present disclosure, all other embodiments obtained by those of ordinary skill in the art are within the scope of protection of the present disclosure.

[0063] Unless otherwise required by context, the term "comprise" and other forms of the term "comprise", such as "comprises" and "comprising", are to be construed as open, inclusive, meaning that "comprising" means "including, but not limited to". In the description of the specification, the terms "one embodiment", "some embodiments", "exemplary embodiments", "example", or "some examples" are intended to mean that the particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the present disclosure. The illustrative representations of the above terms do not necessarily refer to the same embodiment or example. In addition, the specific features, structures, materials, or characteristics described can be included in any appropriate manner in any one or more embodiments or examples.

[0064] Hereinafter, the terms "first", "second" are only used for description purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined with "first", "second" can explicitly or implicitly include one or more of the features. In the description of the embodiments of the present disclosure, unless otherwise specified, the meaning of "a plurality of" is two or more.

[0065] "A and / or B" includes the following three combinations: A only, B only, and a combination of A and B.

[0066] The use of "adapted to" or "configured to" herein means an open and inclusive language that does not exclude devices that are adapted to or configured to perform additional tasks or steps.

[0067] As used herein, "about," "approximately," or "around" includes the recited value and the average value within an acceptable range of deviation from the particular value, as determined by one of ordinary skill in the art considering the measurement at issue and the error in measurement associated with the particular quantity being measured (i.e., the limitations of the measurement system).

[0068] Exemplary embodiments are described herein with reference to cross-sectional and / or plan view illustrations that are idealized examples. In the drawings, the thickness of layers and regions are exaggerated for clarity. Accordingly, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and / or tolerances, are to be expected. Thus, the exemplary embodiments should not be construed as limited to the particular shapes of regions as illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, an etched region illustrated as a rectangle will typically have rounded or curved features. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of the exemplary embodiments.

[0069] Some embodiments of the present disclosure provide a display device 1000, referring to Figure 1 The display device 1000 can be a television, a notebook computer, a tablet computer, a mobile phone, a personal digital assistant (PDA), a navigation device, a wearable device, an augmented reality (AR) device, a virtual reality (VR) device, or any product or component having a display function.

[0070] The display device includes a display panel 100. The display panel 100 has a display area 101 and a peripheral area 102 surrounding the display area 101. The peripheral area 102 includes a fan-out area 1021 located at one side of the display area 101 and a binding area 1022, and the binding area 1022 is located at a side of the fan-out area 1021 away from the display area 101.

[0071] It should be understood that in some embodiments, the peripheral area 102 can also be located at one or more sides of the display area 101, and embodiments of the present disclosure do not make specific limitations thereon.

[0072] The display region 101 includes a plurality of sub-pixels, each of which includes a pixel driving circuit 110 on the substrate 11 and a light-emitting device 20 electrically connected to the pixel driving circuit 110. The peripheral region 102 includes a plurality of signal lines and an IC (Integrated Circuit) chip and the like, wherein the IC chip is arranged in a bonding region 1022 in the peripheral region 102.

[0073] Referring to Figure 2A and Figure 2B , the display panel 100 includes an array substrate 10, a light-emitting device 20 and an encapsulation layer 30 arranged in layers. The array substrate 10 includes a substrate 11.

[0074] Referring to Figure 2A , the array substrate 10 further includes a semiconductor layer 12, a first gate dielectric layer 13, a first gate electrode layer 14, a second gate dielectric layer 15, a second gate electrode layer 16, an interlayer dielectric layer 171, a first source-drain metal layer 181, a passivation layer 172, a first planarization layer 191, a second source-drain metal layer 182 and a second planarization layer 192 arranged in sequence on the substrate 11.

[0075] Alternatively, referring to Figure 2B , the array substrate 10 further includes a semiconductor layer 12, a first gate dielectric layer 13, a first gate electrode layer 14, a second gate dielectric layer 15, a second gate electrode layer 16, an interlayer dielectric layer 171, a third source-drain metal layer 183, a passivation layer 172 and a third planarization layer 193 arranged in sequence on the substrate 11.

[0076] In an embodiment of the present disclosure, the first metal layer 18 includes a source-drain metal layer farthest from the substrate 11, i.e., the second source-drain metal layer 182 in Figure 2A , or Figure 2B the third source-drain metal layer 183 in .

[0077] In another embodiment of the present disclosure, the first metal layer 18 includes at least one of the plurality of metal layers on the substrate 11. For example, the first metal layer 18 includes one or more of the first gate electrode layer 14, the second gate electrode layer 16, the first source-drain metal layer 181 and the second source-drain metal layer 182 in Figure 2A .

[0078] In an embodiment of the present disclosure, the planarization layer 19 includes a planarization layer farthest from the substrate 11 (a planarization layer on the side of the first metal layer 18 away from the substrate 11), i.e., the second planarization layer 192 in Figure 2A , or Figure 2B the third planarization layer 193 in .

[0079] In another embodiment of the present disclosure, the planarization layer 19 includes at least one of the plurality of planarization layers on the substrate 11, i.e.,Figure 2A The first planarization layer 191 and / or the second planarization layer 192 in the middle; or Figure 2B The third planarization layer 193 in the middle.

[0080] In the embodiments of this disclosure, with Figure 2A Taking the display panel 100 shown as an example, the content of the application is described exemplarily.

[0081] The pixel driving circuit 110 includes multiple thin-film transistors (TFTs) and at least one capacitor Cst (only one TFT and one capacitor Cst are shown exemplary in the figure). For example, the pixel driving circuit 110 can be a "7T1C" circuit, a "7T2C" circuit, or a "3T1C" circuit, etc. The embodiments of this disclosure do not specifically limit the structure of the pixel driving circuit 110. "T" refers to a thin-film transistor, and the number before "T" indicates the number of thin-film transistors; "C" refers to a capacitor Cst, and the number before "C" indicates the number of capacitors Cst.

[0082] For example, see Figure 4 The pixel driving circuit 110 can be a "7T1C" circuit. Thus, the pixel driving circuit 110 includes a first initialization transistor T1, a second initialization transistor T2, a driving transistor T3, a data writing transistor T4, a compensation transistor T5, a first light-emitting control transistor T6, a second light-emitting control transistor T7, and a capacitor Cst.

[0083] Specifically, the first initialization transistor T1 is configured to provide an initialization signal to the control electrode of the driving transistor T3 under the control of the first scan line GL1. The second initialization transistor T2 is configured to provide an initialization signal to the anode of the light-emitting device 20 under the control of the first scan line GL1. Figure 4 An initialization signal is provided to the upper end of the light-emitting device 20. Data writing transistor T4 and compensation transistor T5 are configured to provide data signals to the control electrode of driving transistor T3 under the control of the second scan line GL2. Driving transistor T3 is configured to control the current through the light-emitting device 20 under the control of the data signal, thereby adjusting the brightness of the light-emitting device. First light-emitting control transistor T6 and second light-emitting control transistor T7 are configured to control whether the light-emitting device 20 emits light under the control of the enable signal line EM.

[0084] The TFT may include a semiconductor pattern 121 located in the semiconductor layer 12, a gate 141 located in the first gate layer 14, and a source 18' and a drain 18" located in the first source-drain metal layer 181. The capacitor Cst may include a first electrode 142 located in the first gate layer 14 and a second electrode 161 located in the second gate layer 16.

[0085] Referring to Figure 3A , Figure 3A is a partial structural view of the first metal layer 18. The first metal layer 18 includes a signal line pattern 184 located in the peripheral area 102. Referring to Figure 6 , Figure 6 is a cross-sectional structural view of the first metal layer 18; the first metal layer 18 includes a metal titanium layer 18a, a metal aluminum layer 18b and a metal titanium layer 18c arranged in sequence, i.e., the first metal layer 18 is a titanium-aluminum-titanium laminated structure. The metal aluminum layer 18b is beneficial to improve the electrical conductivity of the first metal layer 18 and reduce the impedance of the first metal layer 18, and the metal titanium layer 18c can protect the metal aluminum layer 18b and reduce the risk of oxidation or corrosion of the metal aluminum layer 18b. The thickness of the metal titanium layer 18a and the metal titanium layer 18c can be equal or unequal.

[0086] Referring to Figure 2A and Figure 8 , the planarization layer 19 (the second planarization layer 192) is located on the side of the first metal layer 18 (the second source-drain metal layer 182) away from the substrate 11, and the planarization layer 19 is provided with an opening 194 in the peripheral area 102. The planarization layer 19 includes an organic material, and the organic material has certain water absorption characteristics. The opening 194 can avoid external water vapor from invading the display area 101 of the display panel 100 along the planarization layer 19.

[0087] Exemplarily, the planarization layer 19 forms the opening 194 in the peripheral area 102, and the opening 194 can be annular and arranged around the display area 101. In this way, the opening 194 can maximize the path of water vapor invading the display area 101 of the display panel 100 along the organic layer (the planarization layer 19).

[0088] Exemplarily, the planarization layer 19 forms the opening 194 in the peripheral area 102, and the opening 194 can also be discontinuous, i.e., the opening 194 is discontinuous around the display area 101. For example, the planarization layer 19 includes a plurality of openings 194, the plurality of openings 194 are arranged around the display area 101, and there is a spacing between any two adjacent openings 194.

[0089] Exemplarily, the opening 194 at the corner of the peripheral area 102 can be an arc structure or a right angle structure.

[0090] Exemplarily, the width (the size along the plane parallel to the plane where the display panel 100 is located and perpendicular to the extension direction of the opening 194) of the opening 194 at each position can be the same or different.

[0091] Embodiments of the present disclosure do not specifically limit the structure (position, shape and size, etc.) of the opening 194.

[0092] Referring to Figure 2AThe light emitting device 20 includes, in a direction perpendicular to the substrate 11 and away from the substrate 11, an anode layer 21, a pixel defining layer 22, a light emitting layer 23, a spacer layer 24, and a cathode layer 25, which are sequentially disposed on the planarization layer 19.

[0093] The anode layer 21 includes a plurality of mutually separated anodes 211. Figure 2A The pixel defining layer 22 has a plurality of first openings 221, each of which exposes at least a partial area of one of the anodes 211.

[0094] The light emitting layer 23 includes a plurality of light emitting patterns 231, each of which is at least partially located within one of the first openings 221. The light emitting layer 23 can include one or more of an election transporting layer (ETL), an election injection layer (EIL), a hole transporting layer (HTL), and a hole injection layer (HIL).

[0095] The spacer layer 24 includes a plurality of spacers 241 for supporting a mask plate in an evaporation process. The cathode layer 25 can be a full layer structure. The material of the cathode layer 25 can be a transparent conductive material, such as Indium Tin Oxides (ITO). One light emitting device 20 includes one of the anodes 211, the light emitting pattern 231 located on the anode 211, and a portion of the cathode layer 25 in contact with the light emitting pattern 231.

[0096] An encapsulation layer 30 is disposed on a side of the cathode layer 25 away from the substrate 11. The encapsulation layer 30 is configured to isolate the light emitting device 20 from water and oxygen. Exemplarily, the encapsulation layer 30 can include a first inorganic layer 31, an organic encapsulation layer 32, and a second inorganic layer 33, which are sequentially stacked. The first inorganic layer 31 and the second inorganic layer 33 are configured to block water and oxygen from the outside, and the organic encapsulation layer 32 is configured to release stress and planarize within the film layer.

[0097] In some embodiments, the display panel 100 can further include a touch function layer 60 disposed on the encapsulation layer 30, that is, the display panel 100 adopts a Flexible Multiple Layer on Cell (FMLOC) process.

[0098] Referring to Figure 5A and Figure 5B , Figure 5A is a planar structure of the touch function layer 60,Figure 5B A cross-sectional structure of the touch function layer 60. The touch function layer 60 can include, in sequence along a direction perpendicular to and away from the display panel 100 (a third direction Z), an isolation layer 61, a first electrode layer 62, a second insulating layer 43, a second electrode layer 44, and an insulating cover layer 45.

[0099] The material of the isolation layer 61 can be silicon nitride (SiNx). The second insulating layer 43 is used to block the first electrode layer 62 and the second electrode layer 44 to prevent electrical contact between them at positions other than the intended positions. The material of the second insulating layer 43 can also be silicon nitride (SiNx) for example. The insulating cover layer 45 is used to protect the second electrode layer 44. The material of the insulating cover layer 45 can include polyimide (PI) for example.

[0100] The first electrode layer 62 includes a plurality of bridge lines 421. The first electrode layer 62 is generally made of metal titanium, metal aluminum, and metal titanium that are sequentially stacked, or indium tin oxide (ITO), silver, and indium tin oxide that are stacked, i.e., the bridge lines 421 adopt a titanium-aluminum-titanium (Ti-Al-Ti) stacked structure, or an ITO-silver-ITO stacked structure.

[0101] The second electrode layer 44 includes a plurality of touch electrodes 441 and a plurality of touch wires 442. Two adjacent touch electrodes 441 in the second direction X (horizontal direction) are directly electrically connected, and two adjacent touch electrodes 441 in the third direction Y (vertical direction) are electrically connected through a bridge line 421 in the first electrode layer 62. The material of the second electrode layer 44 can be the same as that of the first electrode layer 62. Figure 5A Figure 5A

[0102] It can be understood that the positions of the first electrode layer 62 and the second electrode layer 44 can also be interchanged, i.e., the first electrode layer 62 can include a plurality of touch electrodes 441 and a plurality of touch wires 442, and the second electrode layer 44 includes a plurality of bridge lines.

[0103] In the related art, the process of forming the planarization layer 19 (annular opening 194) includes a developing process. During the developing process, part of the developing solution will be in contact with the sidewall of the first metal layer 18 located in the opening 194, and will chemically react with the metal aluminum layer 18b in the first metal layer 18 (2Al+2OH - +2H2O=2AlO2-+3H2↑), thereby forming an undercut 185 on the sidewall of the first metal layer 18 (as shown in FIG. 2B). Figure 7 ​​In the subsequent process of forming the anode layer 21, the etching liquid further etches the aluminum layer in the first metal layer 18, and deepens the depth H of the groove 185. In the subsequent process of forming the encapsulation layer 30 (the first inorganic layer 31 and the second inorganic layer 33) by chemical vapor deposition (CVD), part of the material of the encapsulation layer 30 is embedded into the groove 185, which causes micro-cracks in the encapsulation layer 30 near the groove 185, affects the encapsulation effect of the display panel 100, increases the risk of water vapor entering the display area 101, and easily causes the failure of the light-emitting material, forming a dark spot (the dark spot is referred to as "BDSX defect"). Figure 3A As shown in FIGS. 1B and 1C, in the peripheral area 102, the region D between the first voltage signal line L1 and the second voltage signal line L2 along the first direction X becomes a GDSX region.

[0104] To solve the above problems, some embodiments of the present disclosure provide a display panel 100. Referring to FIGS. 1A to 1C, Figure 8 Figure 9A and Figure 9B The display panel 100 further includes a barrier structure 40, the barrier structure 40 is located in the peripheral area 102, and at least part of the barrier structure 40 is located in the opening 194. The normal projection of the barrier structure 40 in the opening 194 on the substrate 11 partially overlaps the normal projection of the signal line pattern 184 on the substrate 11, that is, at least part of the signal line pattern 184 is located below the barrier structure 40 in the opening 194.

[0105] At least one through hole 50 is provided in the signal line pattern 184. The normal projection of the at least one through hole 50 on the substrate 11 is located in the normal projection of the opening 194 on the substrate 11, and is located on the side of the normal projection of the barrier structure 40 on the substrate 11 close to the display area 101 and / or on the side far away from the display area 101.

[0106] That is, the part of the signal line pattern 184 located in the opening 194 is provided with the through hole 50, and the through hole 50 is located on the side of the barrier structure 40 close to the display area 101 (as shown in FIGS. 1B and 1C), or the through hole 50 is located on the side of the barrier structure 40 far away from the display area 101 (as shown in FIGS. 1B and 1C), or the through hole 50 includes the part located on the side of the barrier structure 40 close to the display area 101 and the part located on the side of the barrier structure 40 far away from the display area 101 (as shown in FIGS. 1B and 1C). Figure 9A Figure 9B Figure 10A Figure 10B Figure 11A Figure 11B

[0107] ​​​​​​​Some embodiments of the present disclosure provide a display panel 100, the first metal layer 18 includes a via 50 located in the peripheral region 102, and the via 50 is located in the opening 194 of the planarization layer 19, so that the via 50 can increase the sidewall area of the first metal layer 18. In the subsequent process of forming the planarization layer 19 (forming the opening 194), the amount of developing solution in contact with the unit area (sidewall) of the first metal layer 18 can be reduced, achieving the effect of sharing the developing solution and reducing the developing solution load effect, thereby reducing the erosion of the developing solution to the first metal layer 18, reducing the risk of forming an undercut 185 (Undercut) on the sidewall of the first metal layer 18, and reducing the depth of the undercut 185 (as shown in Figure 13 Thus, it is beneficial to reduce the risk of the encapsulation layer 30 embedding in the above-mentioned undercut 185, and reduce the amount of material of the encapsulation layer 30 embedded in the undercut 185, reduce the risk of micro-cracks of the encapsulation layer 30 at the undercut 185, reduce the risk of water vapor invading the display area 101 along the above-mentioned micro-cracks, and thus improve the encapsulation performance of the display panel 100.

[0108] Referring to Figure 12 and Table 1 below:

[0109] Table 1: Depth of undercut when the via is arranged at different positions

[0110]

[0111] In Table 1, A01 and A02 refer to two comparative tests performed at the same position. “—” means: the number 0. The unit of each value is i.e. 10 x -10 meters. “Inner side” refers to the side close to the display area 101, and “outer side” refers to the side away from the display area 101.

[0112] Figure 12 In Table 1, numbers 1-6 correspond to the positions of the vias 50 arranged in “Split1-Split6”. Taking Split1 as an example, Split1 refers to arranging the via 50 in the retaining wall structure 40 (the center position of the second retaining wall 42), that is Figure 12 In Table 1, the depth of the undercut 185 at each position of the signal line pattern 184.

[0113] It should be understood that, in Table 1, at Split 1, the via hole 50 is covered by the planarization layer 19 in the barrier structure 40, and during the etching process of forming the opening 194, the developing solution cannot contact the sidewall of the via hole 50, so it can be used as a control group. That is, the depth of the groove 185 (SD Undercut) at different positions of the first metal layer 18 when the via hole 50 is not arranged. It can be seen that, when the via hole 50 is not arranged or arranged below the barrier structure 40 (the orthogonal projection of the barrier structure 40 on the substrate 11 overlaps the orthogonal projection of the via hole 50 on the substrate 11), the average depth of the groove 185 at different positions of the first metal layer 18 is 0.927 mm. That is, 0.927 mm.

[0114] It can be seen from Split 2 to Split 4 that when the via hole 50 is arranged on the side of the barrier structure 40 away from the display area 101, the average depth of the groove 185 at different positions of the first metal layer 18 is 0.560 mm, 0.434 mm and 0.359 mm respectively, which are all less than 0.927 mm. That is, when the via hole 50 is arranged on the side of the barrier structure 40 away from the display area 101, the average depth of the groove 185 at different positions of the signal line pattern 184 can be significantly reduced.

[0115] It can be seen from Split 5 and Split 6 that when the via hole 50 is arranged on the side of the barrier structure 40 close to the display area 101, the average depth of the groove 185 at different positions of the first metal layer 18 is 0.467 mm and 0.392 mm respectively, which are all less than 0.927 mm. That is, when the via hole 50 is arranged on the side of the barrier structure 40 close to the display area 101, the average depth of the groove 185 at different positions of the first metal layer 18 can be significantly reduced.

[0116] It can be seen from the above that arranging the via hole 50 on the signal line pattern 184 (the orthogonal projection of the via hole 50 on the substrate 11 is located within the orthogonal projection of the opening 194 on the substrate 11, and is located on the side of the orthogonal projection of the barrier structure 40 on the substrate 11 close to the display area 101 and / or away from the display area 101) can reduce the average depth of the groove 185 at different positions of the signal line pattern 184, thereby reducing the amount of material of the packaging layer 30 embedded in the groove 185, reducing the risk of micro-cracks of the packaging layer 30 at the groove 185, reducing the risk of water vapor invading the display area 101 along the above-mentioned micro-cracks, and thereby improving the packaging performance of the display panel 100.

[0117] It should be understood that, referring to Table 1 and Figure 13In the process of forming the pixel definition layer 22 (PDL layer), part of the PI will remain in the groove 185. The PI filled in the groove 185 can reduce the depth of the groove 185. That is, the final depth of the groove 185 is the depth of the etched metal aluminum layer (SD Undercut) minus the depth of the remaining PI in the groove 185.

[0118] In some embodiments, referring to Figure 9A and Figure 10A , the dam structure 40 includes a first dam 41 (Dam1) and a second dam 42 (Dam2) arranged at intervals. The first dam 41 is closer to the display area 101 than the second dam 42. The at least one through hole 50 is arranged on the side of the first dam 41 close to the display area 101 (as shown in Figure 9A ), or on the side of the second dam 42 away from the display area 101 (as shown in Figure 10A ). The dam structure 40 can improve the packaging performance of the display panel 100 and reduce the risk of water vapor entering the display area 101.

[0119] The at least one through hole 50 arranged on the side of the dam structure 40 close to the display area 101 means that the at least one through hole 50 is arranged on the side of the first dam 41 close to the display area 101. The at least one through hole 50 arranged on the side of the dam structure 40 away from the display area 101 means that the at least one through hole 50 is arranged on the side of the second dam 42 away from the display area 101. That is, the at least one through hole 50 is arranged on the side of the first dam 41 close to the display area 101, and / or arranged on the side of the second dam 42 away from the display area 101.

[0120] In some embodiments, referring to Figure 14 , the dam structure 40 (the first dam 41 and / or the second dam 42) includes one or more of a first pad 401, a second pad 402, and a third pad (not shown in the figure) arranged in layers. The first pad 401 is the same as and arranged in the same layer as the planarization layer 19; the second pad 402 is the same as and arranged in the same layer as the pixel definition layer 22; and the third pad can be the same as and arranged in the same layer as the spacer layer 24. In the case where the display panel 100 includes a first planarization layer 191, the dam structure 40 can further include a fourth pad 404, which is the same as and arranged in the same layer as the first planarization layer 191. For example, referring to Figure 14 , the first dam 41 and the second dam 42 each include the first pad 401, the second pad 402, and the third pad. The second dam 42 includes the fourth pad 404.

[0121] It can be understood that, in the case where the barrier structure 40 includes the first pad 401 which is made of the same material as the planarization layer 19 and is arranged in the same layer, the first pad 401 divides the opening 194 to form a plurality of sub-openings 194A. For example, referring to Figure 9B In the case where both the first barrier 41 and the second barrier 42 include the first pad 401, the first pad 401 divides the opening 194 to form three sub-openings 194A. The three sub-openings 194A are respectively one sub-opening 194A between the first boundary 1941 and the first barrier 41, one sub-opening 194A between the first barrier 41 and the second barrier 42, and one sub-opening 194A between the second barrier 42 and the second boundary 1942. In this way, the “orthographic projection of the via 50 on the substrate 11 is located in the orthographic projection of the opening 194 on the substrate 11” means that the orthographic projection of the via 50 on the substrate 11 is located in the orthographic projection of the sub-opening 194A on the substrate 11; that is, the via 50 is arranged in the region of the first metal layer 18 which is located in the opening 194 and is not covered by the planarization layer 19.

[0122] In some embodiments, the first metal layer 18 includes at least one voltage signal line, and a portion of the at least one voltage signal line is arranged in the peripheral region 102 and is located in the at least one opening 194. The via 50 is arranged in the portion (hereinafter referred to as the first portion) of the at least one signal line which is located in the peripheral region 102 and is located in the at least one opening 194. In this way, the etching liquid and the developing liquid can be prevented from eroding the sidewall of the first portion of the signal line, and the depth of the groove 185 formed by the sidewall of the signal line can be reduced.

[0123] For example, the at least one voltage signal line L includes a first voltage signal line (such as a VDD voltage signal line) and a second voltage signal line (such as a VSS voltage signal line). For example, the first voltage signal line L1 is configured to provide a VDD voltage signal to the pixel driving circuit, and the second voltage signal line L2 is configured to provide a VSS voltage signal to the light emitting device.

[0124] For example, referring to Figure 3B , Figure 3B For example, referring to

[0125] For example, referring to Figure 3A and Figure 3BThe first voltage signal line L1 can include a plurality of first sub-lines L11, a first bus L12 and a first connecting line L13 located on the first metal layer 18. The plurality of first sub-lines L11 are located in the display area 101 and are arranged side by side along the first direction X, each first sub-line L11 extending along the second direction Y. The first bus L12 is located in the fan-out area 1021 and extends along the first direction X. Each first sub-line L11 is electrically connected to the first bus L12 at an end close to the fan-out area 1021. The first connecting line L13 is electrically connected to the first bus L12 and extends from the fan-out area 1021 to the binding area 1022.

[0126] The first direction X is the extension direction of the boundary between the display area 101 and the fan-out area 1021, i.e. the horizontal direction in Figure 3B The second direction Y is perpendicular to the first direction X, i.e. the vertical direction in Figure 3B .

[0127] For example, referring to Figure 3A and Figure 3B , the second voltage signal line L2 can include a second sub-line L21, a second bus L22 and a second connecting line L23 located on the first metal layer 18. The second sub-line L21 is located in the peripheral area 102 except the binding area 1022 and at least partially surrounds the display area 101. The two ends of the second sub-line L21 extend to the fan-out area 1021. The second bus L22 is located in the fan-out area 1021 and is electrically connected to the ends of the second sub-line L21 extending to the fan-out area 1021. The second connecting line L23 is electrically connected to the second bus L22 and extends from the fan-out area 1021 to the binding area 1022.

[0128] The first bus L12 and the second bus L22 extend along the first direction X.

[0129] The second voltage signal line L2 includes two second buses L22, which are located on the two sides of the fan-out area 1021 along the first direction X; each second bus L22 is electrically connected to the end of the second sub-line L21 extending to the same side of the fan-out area 1021.

[0130] For example, referring to Figure 3A , the width of the end portions of the first bus L12 is smaller than the width of the middle portion, so that a stepped shape is formed at the end portions of the first bus L12. The second bus L22 is arranged at the step, and along the first direction X, the end of the second bus L22 close to the step is arranged opposite to the portion of the first bus L12. The area between the second bus L22 and the first bus L12 is referred to as a GDSX area.

[0131] For example, referring to Figure 8 and Figure 9AThe normal projection of the opening 194 on the substrate 11 overlaps with the part of the normal projection of the first bus line L12 and the second bus line L22 on the substrate 11. The signal line pattern 184 can include the part of the first voltage signal line L1 and the second voltage signal line L2 located in the fan-out region 1021. For example, the signal line pattern 184 includes the first bus line L12 and the second bus line L22.

[0132] In some embodiments, referring to Figure 9A , Figure 10A and Figure 11A , a plurality of through holes 50 is disposed on the signal line pattern 184. The plurality of through holes 50 is arranged in at least one row, and the plurality of through holes 50 in one row is distributed along the extension direction (i.e., the first direction X) of the sidewall structure 40 located in the opening 194. The plurality of through holes 50 can further increase the sidewall area of the signal line pattern 184 (the part not covered by the planarization layer 19), increase the effect of the through holes 50 sharing the developing liquid load effect, and reduce the risk and depth of the groove 185 generated on the signal line pattern 184. The plurality of through holes 50 is distributed along the first direction X, which is beneficial to simplify the pattern of the signal line pattern 184 and reduce the processing difficulty of the plurality of through holes 50.

[0133] In some embodiments, at least one row of through holes is disposed on the side of the sidewall structure 40 close to the display region 101. For example, one row of through holes 50 (as shown in Figure 9A ) or two rows of through holes 50 (as shown in Figure 15A ) can be disposed.

[0134] In some embodiments, at least one row of through holes 50 is disposed on the side of the sidewall structure 40 away from the display region 101. For example, one row of through holes 50 (as shown in Figure 10A ) or two rows of through holes 50 (as shown in Figure 15B ) can be disposed.

[0135] In some embodiments, at least one row of through holes is disposed on the side of the sidewall structure 40 close to the display region 101, and at least one row of through holes 50 is disposed on the side of the sidewall structure 40 away from the display region 101. The number of rows of through holes 50 and the number of through holes 50 in each row on both sides of the sidewall structure 40 can be equal or unequal. For example, one row of through holes 50 can be disposed on the side of the sidewall structure 40 close to the display region 101, and two rows of through holes 50 can be disposed on the side of the sidewall structure 40 away from the display region 101 (as shown in Figure 15C ). Alternatively, one row of through holes 50 can be disposed on both sides of the sidewall structure 40 (as shown in Figure 11A ).

[0136] In some embodiments, referring to Figure 15CThe plurality of through holes 50 are arranged in multiple rows. Any two adjacent rows of through holes 50 are spaced apart in a direction (second direction Y) perpendicular to the arrangement direction (first direction X) of one row of through holes 50. By arranging the plurality of through holes 50, the number of through holes 50 can be increased, and thus the effect of the through holes 50 sharing the load of the developing solution can be increased, and the risk and depth of the groove 185 on the signal line pattern 184 can be reduced. The plurality of through holes 50 can be located on the same side of the barrier structure 40, or on different sides of the barrier structure 40.

[0137] For example, the plurality of through holes 50 are located on the same side of the barrier structure 40, such as the plurality of through holes 50 are located on the side of the barrier structure 40 away from the display area 101 (as shown in FIG. 8A), or on the side of the barrier structure 40 close to the display area 101 (as shown in FIG. 8B). Figure 15B Figure 15A For example, the plurality of through holes 50 are located on the same side of the barrier structure 40, such as the plurality of through holes 50 are located on the side of the barrier structure 40 away from the display area 101 (as shown in FIG. 8A), or on the side of the barrier structure 40 close to the display area 101 (as shown in FIG. 8B).

[0138] For example, the plurality of through holes 50 are located on the same side of the barrier structure 40, such as the plurality of through holes 50 are located on the side of the barrier structure 40 away from the display area 101 (as shown in FIG. 8A), or on the side of the barrier structure 40 close to the display area 101 (as shown in FIG. 8B). Figure 11A Figure 15C For example, the plurality of through holes 50 are located on the same side of the barrier structure 40, such as the plurality of through holes 50 are located on the side of the barrier structure 40 away from the display area 101 (as shown in FIG. 8A), or on the side of the barrier structure 40 close to the display area 101 (as shown in FIG. 8B).

[0139] In some embodiments, referring to FIG. 9, which is a cross-sectional view of one through hole 50. The sidewall 51 of the at least one through hole 50 includes a groove 185, and the bottom wall 1851 of the groove 185 is substantially arc-shaped. The end of the bottom wall 1851 close to the substrate 11 (the lower end in FIG. 9) is closer to the center line L0 of the through hole 50 than the end of the bottom wall 1851 away from the substrate 11 (the upper end in FIG. 9). Figure 11C Figure 11C In some embodiments, referring to FIG. 9, which is a cross-sectional view of one through hole 50. The sidewall 51 of the at least one through hole 50 includes a groove 185, and the bottom wall 1851 of the groove 185 is substantially arc-shaped. The end of the bottom wall 1851 close to the substrate 11 (the lower end in FIG. 9) is closer to the center line L0 of the through hole 50 than the end of the bottom wall 1851 away from the substrate 11 (the upper end in FIG. 9). Figure 11C Figure 11C The maximum distance H2 between the lowest point of the bottom wall 1851 (usually the end of the bottom wall 1851 away from the substrate 11) and the sidewall 51 of the through hole 50 (the sidewall of the metal titanium layer 18a) is negatively correlated with the number of through holes 50. That is, the more the number of through holes 50, the better the effect of the through holes 50 sharing the load of the developing solution and etching solution, and the smaller the erosion of the sidewall of the through hole 50 by the developing solution and etching solution, so that the distance between the maximum distance H2 and the sidewall 51 of the through hole 50 is smaller. Conversely, the fewer the number of through holes 50, the greater the distance between the maximum distance H2 and the sidewall 51 of the through hole 50.

[0140] The maximum distance H2 between the lowest point of the bottom wall 1851 (usually the end of the bottom wall 1851 away from the substrate 11) and the sidewall 51 of the through hole 50 (the sidewall of the metal titanium layer 18a) is negatively correlated with the number of through holes 50. That is, the more the number of through holes 50, the better the effect of the through holes 50 sharing the load of the developing solution and etching solution, and the smaller the erosion of the sidewall of the through hole 50 by the developing solution and etching solution, so that the distance between the maximum distance H2 and the sidewall 51 of the through hole 50 is smaller. Conversely, the fewer the number of through holes 50, the greater the distance between the maximum distance H2 and the sidewall 51 of the through hole 50.

[0141] ​​​​In some embodiments, the sidewall 51 of at least one of the through holes 50 comprises a recess 185. The more the number of the through holes 50, the smaller the average depth of each of the through holes 50 or the average depth of the recess 185 is. That is, the more the number of the through holes 50, the better the effect of the through holes 50 to share the developing solution and etching solution, the smaller the erosion of the sidewall of the through holes 50 to the developing solution and etching solution, and the smaller the average depth of the through holes 50 or the average depth of the recess 185 is.

[0142] Exemplarily, as shown in Figure 15C , the opening 194 comprises opposite first and second boundaries 1941 and 1942, the first boundary 1941 is located on the side of the barrier structure 40 close to the display area AA, and the second boundary 1942 is located on the side of the barrier structure 40 away from the display area AA. The first through hole 501 is arranged between the barrier structure 40 and the first boundary 1941, and the second through hole 502 is arranged between the barrier structure 40 and the second boundary 1942.

[0143] For example, the number of the first through holes 501 is less than the number of the second through holes 502, and the average depth (depth H) of the recess 185 of the sidewall 51 of the first through hole 501 is less than the average depth of the recess 185 of the sidewall 51 of the second through hole 502.

[0144] It can be understood that the number of the first through holes 501 is less than the number of the second through holes 502 is that the number of the first through holes 501 per unit area is less than the number of the second through holes 502 per unit area. Therefore, it can also be understood that the distribution density of the first through holes 501 is less than the distribution density of the second through holes 502.

[0145] The bottom wall 1851 of the recess 185 can not be flat or smooth, therefore, the average depth H of the recess 185 can be understood as the average value of the maximum depth H2 and the minimum depth H1 of the recess 185. For example, referring to Figure 11C , the average depth H of the recess 185 can be the average value of the maximum depth H2 and the minimum depth H1 of the recess 185.

[0146] For example, the number of the second through holes 502 is less than the number of the first through holes 501, and the average depth of the recess 185 of the sidewall 51 of the second through hole 502 is less than the average depth of the recess 185 of the sidewall 51 of the first through hole 501.

[0147] For example, the number of the first through holes 501 is equal to the number of the second through holes 502, and the average depth of the recess 185 of the sidewall 51 of the first through hole 501 is substantially equal to the average depth of the recess 185 of the sidewall 51 of the second through hole 502.

[0148] In some embodiments, referring to Figure 9AThe opening 194 includes a first boundary 1941 opposite a second boundary 1942, the first boundary 1941 is located on the side of the barrier structure 40 close to the display area 101, and the second boundary 1942 is located on the side of the barrier structure 40 away from the display area 101.

[0149] The distance between the barrier structure 40 (the first barrier 41) and the first boundary 1941 is a third distance D3, the distance between the barrier structure 40 (the second barrier 42) and the second boundary 1942 is a fourth distance D4, the third distance D3 is less than the fourth distance D4, so as to improve the packaging performance of the display panel 100.

[0150] Exemplarily, the distance D3 between the barrier structure 40 and the first boundary 1941 can be 50-60 μm, for example, the distance D3 is 50 μm, 55 μm or 60 μm, etc. The distance D4 between the barrier structure 40 and the second boundary 1942 can be 85-110 μm, for example, the distance D4 is 85 μm, 95 μm or 110 μm, etc.

[0151] At least one through hole 50 is arranged between the barrier structure 40 and the first boundary 1941, and the minimum distance between the at least one through hole 50 and the barrier structure 40 is a first distance D1. At least one through hole 50 is arranged between the barrier structure 40 and the second boundary 1942, and the minimum distance between the at least one through hole 50 and the barrier structure 40 is a second distance D2. Adapted to the third distance D3 being less than the fourth distance D4, the first distance D1 is less than the second distance D2, so as to optimize the spatial arrangement of the plurality of through holes 50.

[0152] In some embodiments, the minimum distance D1 between the at least one through hole 50 and the barrier structure 40 arranged between the barrier structure 40 and the first boundary 1941 is 11-40 μm, at which time the through hole 50 can better share the effect of the developer load. Exemplarily, the minimum distance D1 between the at least one through hole 50 arranged between the barrier structure 40 and the first boundary 1941 and the barrier structure 40 is 11 μm, 16 μm, 21 μm, 36 μm or 40 μm, etc., which will not be listed one by one here.

[0153] In a specific example, it is verified through multiple tests that when the minimum distance D1 between the at least one through hole 50 arranged between the barrier structure 40 (the first barrier 41) and the first boundary 1941 and the barrier structure 40 is 16 μm, the effect of reducing the depth of the groove 185 is optimal, and the depth of the groove 185 finally formed is about 0.35 μm.

[0154] For example, referring to Split 5 in Table 1 above, when the first distance D1 is 16 μm, the average depth of the recess 185 formed is about 0.467 μm - 0.120 μm = 0.347 μm. For Split 6, when the first distance D1 between the via 50 and the barrier structure 40 is 36 μm, the average depth of the recess 185 formed is about 0.392 μm - 0.000 μm = 0.392 μm.

[0155] In some embodiments, at least one via 50 is provided between the barrier structure 40 (the second barrier 42) and the second boundary 1942, and the minimum distance between the via 50 and the barrier structure 40 is a second distance D2, which is in the range of 11 μm to 75 μm. In this case, the via 50 can better share the effect of the developer load. For example, the second distance D2 between the via 50 and the barrier structure 40 provided between the barrier structure 40 and the second boundary 1942 is 11 μm, 16 μm, 36 μm, 51 μm, 56 μm, or 61 μm, and the like, which will not be listed one by one here.

[0156] In a specific example, it has been verified through multiple tests that when the second distance D2 between the via 50 and the barrier structure 40 provided between the barrier structure 40 and the second boundary 1942 is 56 μm, the effect of reducing the depth of the recess 185 is optimal, and the depth of the recess 185 finally formed is about 0.35 μm.

[0157] For example, referring to Split 3 in Table 1 above, when the second distance D2 between the via 50 and the barrier structure 40 is 36 μm, the average depth of the recess 185 formed is about 0.434 μm - 0.000 μm = 0.434 μm. Referring to Split 4 in Table 1 above, when the second distance D2 between the via 50 and the barrier structure 40 is 56 μm, the depth of the recess 185 formed is about 0.359 μm - 0.000 μm = 0.359 μm.

[0158] In some embodiments, at least one via 50 is provided between the barrier structure 40 and the first boundary 1941, and the minimum distance between the via 50 and the first boundary 1941 is substantially equal to the distance between the via 50 and the barrier structure 40 (the first distance D1). And / or, at least one via 50 is provided between the barrier structure 40 and the second boundary 1942, and the distance between the via 50 and the second boundary 1942 is substantially equal to the distance between the via 50 and the barrier structure 40 (the second distance). That is, the distance between the via 50 and the barrier structure 40 is substantially equal to the distance between the via 50 and the boundary of the opening 194, and the via 50 is substantially located in the middle region between the barrier structure 40 and the boundary of the opening 194 in the second direction Y.

[0159] Exemplarily, the third interval D3 between the barrier structure 40 and the first boundary 1941 can be 52 μm, and at least one via hole 50 is arranged between the barrier structure 40 and the first boundary 1941, the first interval D1 between the via hole 50 and the barrier structure 40 is 16 μm, the size of the via hole 50 along the second direction Y can be 20 μm, and the interval between the via hole 50 and the first boundary 1941 is 16 μm.

[0160] Exemplarily, the fourth interval D4 between the barrier structure 40 and the second boundary 1942 can be 110 μm, and at least one via hole 50 is arranged between the barrier structure 40 and the second boundary 1942, the second interval D2 between the via hole 50 and the barrier structure 40 is 56 μm, the size of the via hole 50 along the second direction Y can be 15 μm, and the interval between the via hole 50 and the second boundary 1942 is 39 μm.

[0161] In some embodiments, referring to Figure 15A and Figure 15C , the shape of the orthographic projection of the via hole 50 on the substrate 11 can be circular or rectangular (oblong or square), which is beneficial to simplify the pattern of the via hole 50 and reduce the difficulty of manufacturing the via hole 50. When the signal line pattern 184 is provided with a plurality of via holes 50, the shapes of the orthographic projections of the plurality of via holes 50 on the substrate 11 can be the same or different, and the embodiments of the present disclosure do not make specific limitations thereon.

[0162] Exemplarily, when the shape of the orthographic projection of the via hole 50 on the substrate 11 is circular, the diameter of the circle can be 3 μm to 25 μm.

[0163] Exemplarily, when the shape of the orthographic projection of the via hole 50 on the substrate 11 is rectangular, the maximum side length of the via hole 50 can be 3 μm to 25 μm.

[0164] In some embodiments, the area of the sidewall of each via hole 50 is 40 μm 2 to 100 μm 2 . If the sidewall area of the via hole 50 is too small (for example, less than 40 μm 2 ), the via hole 50 is too small, which can be not conducive to the patterning manufacturing of the via hole 50 and can be not conducive to improving the effect of the via hole 50 sharing the load of the developing solution. If the sidewall area of the via hole 50 is too large (for example, greater than 100 μm 2 ), the via hole 50 is too large, which can affect the impedance of the signal line pattern 184 and reduce the structural strength of the signal line pattern 184.

[0165] Exemplarily, the thickness of the first metal layer 18 is generally 0.7 μm to 1.0 μm in the direction perpendicular to the display panel 100. For example, the thickness of the first metal layer 18 can be 0.7 μm, 0.8 μm, and 1.0 μm.

[0166] For example, when the shape of the orthogonal projection of the through hole 50 on the substrate 11 is circular, the diameter of the circle can be 20 μm or 25 μm, etc. When the shape of the orthogonal projection of the through hole 50 on the substrate 11 is rectangular, the length (dimension along the first direction X) of the rectangle can be 20 μm, and the width (dimension along the second direction Y) can be 15 μm. The shape and size of the through hole 50 can be selected according to actual needs, which are not listed one by one here.

[0167] When a plurality of through holes 50 are provided on the signal line pattern 184, the interval D5 between two adjacent through holes 50 can be 1 μm to 20 μm. For example, the interval between two adjacent through holes 50 in a row of through holes 50 can be 1 μm, 10 μm or 20 μm, etc. Or the interval D5 between two adjacent rows of through holes 50 can be 1 μm, 10 μm or 20 μm, etc.

[0168] In some embodiments, the orthogonal projection of the opening 194 on the substrate 11 partially overlaps with the orthogonal projection of the first bus L12 and the second bus L22 on the substrate 11, i.e., at least part of the first bus L12 and the second bus L22 is located in the opening 194. In this way, the through hole 50 can be provided on the first bus L12 and / or the second bus L22.

[0169] For example, at least one through hole 50 can be provided on the first bus L12 (as shown in Figure 16A and Figure 16B ). Or at least one through hole 50 can be provided on the second bus L22 (as shown in Figure 17A and Figure 17B ). Or at least one through hole 50 can be provided on the first bus L12, and at least one through hole 50 can be provided on the second bus L22 (as shown in Figure 8 and Figure 9A ).

[0170] In some embodiments, the display panel 100 is a flexible display panel, and the binding area 1022 at least partially bends the back side of the display area 101. During the bending process of the binding area 1022, the stress on both sides of the binding area 1022 along the first direction X is greater than the stress on the middle part.

[0171] In this way, referring to Figure 16A and Figure 16B , a plurality of through holes 50 can be provided on the first bus L12, and the plurality of through holes 50 are arranged in a row along the first direction X; that is, only the through holes 50 are provided on the first bus L12. In this way, the risk of fracture or deformation of the second bus L22 can be reduced.

[0172] In some embodiments, the display panel 100 can be a rigid display panel, and the binding area 1022 is uniformly stressed in the first direction X.

[0173] In this way, referring to Figure 16A and Figure 16B , a plurality of through holes 50 can be provided on at least one second bus L22, and the plurality of through holes 50 are arranged in a row along the first direction X. Exemplarily, a plurality of through holes 50 are provided on both of the second buses L22, so that the number of through holes 50 can be increased, thereby increasing the effect of through holes 50 sharing the load effect of the developing solution and reducing the risk and depth of the groove 185 generated on the signal line pattern 184.

[0174] Alternatively, referring to Figure 8 and Figure 9A , a plurality of through holes 50 can be provided on the first bus L12, and the plurality of through holes 50 are arranged in a row along the first direction X. And at the same time, a plurality of through holes 50 are provided on at least one second bus L22, and the plurality of through holes 50 are arranged in a row along the first direction X.

[0175] In some embodiments, some embodiments of the present disclosure also provide a preparation method of the display panel 100. Wherein, taking the display panel 100 shown in Figure 2A as an example, the display panel 100 includes a first planarization layer 191 and a second planarization layer 192 (19). Referring to Figure 18 , the preparation method includes S100-S400.

[0176] S100, forming a first planarization layer 191.

[0177] The first planarization layer 191 includes a second opening 1911. In the case where the barrier wall structure 40 includes a fourth pad 404 located in the first planarization layer 191, the fourth pad 404 divides the second opening 1911 into two second sub-openings 1911A.

[0178] S200, forming a first metal layer 18 on the side of the first planarization layer 191 away from the substrate 11.

[0179] The first metal layer 18 includes at least one through hole 50 Figure 18 (exemplified by a plurality of through holes 50 in the figure), and the orthographic projection of the through hole 50 on the first planarization layer 191 is located in the second opening 1911.

[0180] S300, forming a second planarization layer 192 on the side of the first metal layer 18 away from the first planarization layer 191.

[0181] The second planarization layer 192 includes an opening 194. In the case where the first barrier wall 41 and the second barrier wall 42 each include a first pad 401 of the same material as the second planarization layer 192 and disposed in the same layer, the first pad 401 separates the opening 194 to form a plurality of sub-openings 194A. At least one of the sub-openings 194A exposes at least one of the through holes 50. That is, a normal projection of the sub-openings 194A in a plane in which the first planarization layer 191 is located covers a normal projection of at least one of the through holes 50 in the plane in which the first planarization layer 191 is located.

[0182] S400, forming a pixel definition layer 22 on a side of the second planarization layer 192 away from the first metal layer 18.

[0183] The pixel definition layer 22 includes a third opening 222. In the case where the first barrier wall 41 and the second barrier wall 42 each include a second pad 402 of the same material as the pixel definition layer 22 and disposed in the same layer, the second pad 402 separates the third opening 222 to form a plurality of third sub-openings 222A.

[0184] The above merely provides a specific implementation of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any person skilled in the art who thinks of changes or replacements within the technical scope disclosed by the present disclosure should be covered within the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be subject to the protection scope of the claims.

Claims

1. A display panel, characterized by, The display panel comprises: a display area and a peripheral area surrounding the display area; the display panel comprises: a substrate; a first metal layer disposed on the substrate; the first metal layer comprises a signal line pattern in the peripheral area; a planarization layer disposed on a side of the first metal layer away from the substrate; the planarization layer comprises at least one opening in the peripheral area; a barrier structure in the peripheral area and surrounding the display area; at least part of the barrier structure is in the at least one opening; the barrier structure comprises a first barrier and a second barrier arranged at intervals, and the first barrier is closer to the display area than the second barrier; 2. The display panel of claim 1, wherein, wherein the opening comprises opposite first and second boundaries; the first boundary is on a side of the barrier structure closer to the display area, and the second boundary is on a side of the barrier structure away from the display area; the signal line pattern comprises at least one via hole; a projection of the at least one via hole on the substrate is within a projection of the opening on the substrate; at least one of the via holes is arranged between the barrier structure and the first boundary, and at least one of the via holes is arranged between the barrier structure and the second boundary.

3. The display panel of claim 2, wherein, The signal line pattern comprises a plurality of via holes arranged in at least one row; the plurality of via holes in a row are arranged at intervals along an extension direction of the barrier structure in the opening. The side of the barrier structure closer to the display area is provided with at least one row of via holes; and / or, 4. The display panel of claim 2, wherein, the side of the barrier structure away from the display area is provided with at least one row of via holes. The plurality of via holes are arranged in multiple rows; any two adjacent rows of via holes are arranged at intervals in a direction perpendicular to the arrangement direction of a row of via holes.

5. The display panel of claim 1, wherein:

6. The display panel of any one of claims 1-5, wherein, a distance between the barrier structure and the first boundary is less than a distance between the barrier structure and the second boundary. The opening comprises a first boundary on a side of the barrier structure closer to the display area; 7. The display panel according to any one of claims 1 to 5, characterized in that, at least one of the via holes is arranged between the barrier structure and the first boundary, and a distance between at least one of the via holes and the barrier structure is 11 μm to 40 μm. The opening comprises a second boundary on a side of the barrier structure away from the display area; 8. The display panel of any one of claims 1-5, wherein, at least one of the via holes is arranged between the barrier structure and the second boundary, and a distance between at least one of the via holes and the barrier structure is 11 μm to 75 μm. The opening comprises a first boundary on a side of the barrier structure closer to the display area and a second boundary on a side of the barrier structure away from the display area; at least one of the via holes is arranged between the barrier structure and the first boundary, and a minimum distance of the via hole to the first boundary is equal to a minimum distance of the via hole to the barrier structure; and / or, at least one of the via holes is arranged between the barrier structure and the second boundary, and a minimum distance of the via hole to the second boundary is equal to a minimum distance of the via hole to the barrier structure.

9. The display panel of any one of claims 1-5, wherein, A shape of a normal projection of the through hole on the substrate comprises a circle or a rectangle.

10. The display panel of any one of claims 1-5, wherein, The area of the side wall of at least one of the through holes is 40 μm 2 ~ 100 μm 2 .

11. The display panel of claim 10, wherein, A side wall of at least one of the through holes comprises a groove, a bottom wall of the groove is arc-shaped, and a maximum distance from a lowest point of the bottom wall to the side wall of the through hole is negatively correlated with a number of the through holes.

12. The display panel of claim 11, wherein, The opening comprises opposite first and second boundaries, the first boundary is located on a side of the barrier structure close to the display area, and the second boundary is located on a side of the barrier structure away from the display area. A first through hole is arranged between the barrier structure and the first boundary, and a second through hole is arranged between the barrier structure and the second boundary. A number of the first through holes is less than a number of the second through holes, and an average depth of the groove of the side wall of the first through hole is less than an average depth of the groove of the side wall of the second through hole; or a number of the second through holes is less than a number of the first through holes, and an average depth of the groove of the side wall of the second through hole is less than an average depth of the groove of the side wall of the first through hole; or a number of the first through holes is equal to a number of the second through holes, and an average depth of the groove of the side wall of the first through hole is equal to an average depth of the groove of the side wall of the second through hole.

13. The display panel of any one of claims 1-5, wherein, A side wall of at least one of the through holes comprises a groove; the more the number of the through holes, the smaller the average depth of the through holes or the average depth of the groove.

14. The display panel of claim 1, wherein, The first metal layer comprises at least one voltage signal line, a part of the at least one voltage signal line is arranged in the peripheral area and located in the at least one opening, and the through hole is arranged in the at least one voltage signal line and located in the peripheral area and in the at least one opening.

15. The display panel of claim 14, wherein, The peripheral area comprises a fan-out area located on a side of the display area and a binding area located on a side of the fan-out area away from the display area. The at least one voltage signal line comprises: a first voltage signal line comprising a plurality of first sub-lines arranged in the display area, a first bus located in the fan-out area, and a first connection line extended from the fan-out area to the binding area; one end of each of the plurality of first sub-lines close to the fan-out area is electrically connected to the first bus, and the first bus is electrically connected to the first connection line; a second voltage signal line comprising a second sub-line arranged in the peripheral area and at least partially surrounding the display area, a second bus located in the fan-out area, and a second connection line extended from the fan-out area to the binding area; both ends of the second sub-line are extended to the fan-out area and electrically connected to the second bus, and the second bus is electrically connected to the first connection line; wherein the first bus and the second bus extend along a first direction, the first direction is an extension direction of a side of the display area where the fan-out area is located; the signal line pattern comprises the first bus and the second bus, and the at least one through hole is arranged on the first bus and / or the second bus.

16. The display panel of claim 15, wherein, A plurality of through holes are arranged on the first bus and arranged in a row along the first direction.

17. The display panel of claim 15 or 16, wherein, The second voltage signal line includes two second buses respectively located on two sides of the fan-out area; each second bus is electrically connected with end portions of second sub-lines extending to the same side of the fan-out area; At least one second bus is provided with a plurality of through holes, and the plurality of through holes are arranged in a row along the first direction.

18. The display panel of claim 1, wherein, The first metal layer includes a metal titanium layer, a metal aluminum layer, and a metal titanium layer which are stacked. 19.The display panel of claim 1, wherein, The at least one through hole is arranged on a side of the first barrier wall close to the display area, and / or the at least one through hole is arranged on a side of the second barrier wall away from the display area.

20. The display panel of claim 19, wherein, The first barrier wall and the second barrier wall each include a pad, and the pad is located on the planarization layer.

21. A display device comprising: A display panel as claimed in any one of claims 1 to 20.

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