Display device and driving method thereof

Abstract

The application discloses a display device and a driving method thereof. The display device comprises a plurality of pixel circuits arranged in an array, a first scanning circuit, a plurality of first scanning lines and a first voltage line. The first scanning circuit is electrically connected with the pixel circuits of a corresponding row through a corresponding first scanning line. The first voltage line is electrically connected with the pixel circuits. The pixel circuits are configured to write the voltage on the first voltage line into the pixel circuits in response to a pulse signal of a first scanning signal on the first scanning line. Different voltages are output to the first voltage line in a first period and a second period within at least one picture refresh period. The present application can improve the display unevenness caused by the difference in the in-plane load in different periods, and is beneficial to improve the display effect.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of display, in particular to a display device and a driving method thereof. BACKGROUND

[0002] With the development of display technology, people have higher and higher requirements on the display quality of display panels.

[0003] At present, the existing display panel has the phenomenon of uneven display brightness, which presents the visual effect of uneven display and seriously reduces the display quality. SUMMARY

[0004] The present application provides a display device and a driving method thereof to improve the phenomenon of uneven display in the display process and improve the display quality.

[0005] According to an aspect of the present application, a display device is provided, comprising:

[0006] a plurality of pixel circuits arranged in an array;

[0007] a first scanning circuit and a plurality of first scanning lines, the first scanning circuit being electrically connected to the pixel circuits of a corresponding row through a corresponding first scanning line;

[0008] a first voltage line, electrically connected to the pixel circuits, the pixel circuits being configured to write a voltage on the first voltage line into the pixel circuits in response to a pulse signal of a first scanning signal on the first scanning line;

[0009] different voltages are output to the first voltage line in a first time period and a second time period within at least one picture refresh period.

[0010] Optionally, a picture refresh period includes an effective phase and a blank phase, the first time period is located in the effective phase, and the second time period is located in the blank phase.

[0011] Optionally, the display device further comprises a voltage adjustment module electrically connected to the first voltage line, the voltage adjustment module being configured to output different voltages to the first voltage line in the first time period and the second time period within at least one picture refresh period.

[0012] Optionally, the voltage adjustment module is configured to output a constant voltage to the first voltage line in the effective phase.

[0013] The voltage adjustment module is configured to output a constant voltage to the first voltage line in the blank phase, or output a voltage that changes in a stepwise manner with time to the first voltage line in the blank phase.

[0014] Optionally, a picture refresh period includes a write frame, the effective phase is in the write frame, and at least part of the blank phase is in the write frame.

[0015] Optionally, the one frame refresh period further comprises a holding frame, and the holding frame is located in the blank stage.

[0016] Optionally, at least part of time in the first time period, the pulse signals output to the N first scan lines overlap with each other, and at least part of time in the second time period, the pulse signals output to the M first scan lines overlap with each other, N and M are unequal positive integers.

[0017] Optionally, N is greater than M, and an absolute value of the voltage output to the first voltage line in the first time period is greater than an absolute value of the voltage output to the first voltage line in the second time period.

[0018] Optionally, in the one frame refresh period, the first scan signal on the same first scan line comprises a plurality of pulse signals.

[0019] Optionally, the display device further comprises a plurality of data lines and a plurality of second scan lines, the data line is electrically connected with the pixel circuit of the corresponding column; the second scan line is electrically connected with the pixel circuit of the corresponding row; the pixel circuit is used for writing the data voltage on the data line into the pixel circuit in response to the second scan signal on the second scan line in the data writing stage;

[0020] In the one frame refresh period, the first scan signal on the same first scan line comprises a plurality of first pulse signals after the data writing stage of the pixel circuit electrically connected with the same first scan line;

[0021] In at least part of time in the first time period, the first pulse signals output to the N first scan lines overlap with each other, and in at least part of time in the second time period, the first pulse signals output to the M first scan lines overlap with each other.

[0022] The first time period is before the second time period;

[0023] Optionally, in the one frame refresh period, a width of the first first pulse signal of the first scan signal on the same first scan line is less than or equal to a width of the remaining first pulse signals; the width of the first first pulse signal is less than a width of at least one of the remaining first pulse signals.

[0024] Optionally, the first scan circuit comprises a plurality of cascaded shift registers, the first time period is before the last stage shift register of the first scan circuit outputs the first first pulse signal to the corresponding electrically connected first scan line; and the second time period is after the last stage shift register of the first scan circuit outputs the first first pulse signal to the corresponding electrically connected first scan line.

[0025] Optionally, in the one frame refresh period, the first scan signal on the same first scan line comprises a second pulse signal before the data writing stage of the pixel circuit electrically connected with the same first scan line.

[0026] Optionally, the voltage output to the first voltage line in the first time period is a first sub-voltage, and the voltage output to the first voltage line in the second time period is a second sub-voltage,

[0027] The display device further includes a voltage adjustment module configured to determine a current compensation amount according to a current refresh frequency and / or a current display brightness value of the display device and a corresponding relationship between the refresh frequency and / or the display brightness value and the compensation amount, and determine the second sub-voltage according to the current compensation amount and the first sub-voltage.

[0028] Optionally, the second sub-voltage is equal to a sum of the first sub-voltage and the current compensation amount.

[0029] Optionally, an absolute value of the first sub-voltage is greater than an absolute value of the second sub-voltage.

[0030] The first sub-voltage and the second sub-voltage are negative voltages.

[0031] Optionally, the voltage output to the first voltage line in the second time period is the second sub-voltage, and the second sub-voltage includes a plurality of pulse signals with different amplitudes.

[0032] Optionally, if the current refresh frequency is a first preset refresh frequency, the second sub-voltage has a pulse number P; if the current refresh frequency is a second preset refresh frequency, the second sub-voltage has a pulse number Q; the first preset refresh frequency is greater than the second preset refresh frequency, P < Q, and P and Q are both integers greater than or equal to 1.

[0033] Optionally, the first voltage line is a first initialization signal line, the pixel circuit includes a driving module, a light-emitting module, and a first initialization module, the driving module is connected between the first power supply line and a first end of the light-emitting module, the first scan circuit is electrically connected to a control end of the first initialization module in the pixel circuit in the corresponding row through the corresponding first scan line, the first initialization module is connected between the first end of the light-emitting module and the first initialization signal line, and the first initialization module is configured to transmit a first initialization voltage on the first initialization signal line to the first end of the light-emitting module in response to a pulse signal of a first scan signal on the first scan line.

[0034] Optionally, the pixel circuit further includes a second initialization module, and the display device further includes a second initialization signal line, the second initialization module is connected between the second initialization signal line and the first end or the second end of the driving module, a control end of the second initialization module is electrically connected to the first scan line, and the second initialization module is configured to transmit a second initialization voltage on the second initialization signal line to the first end or the second end of the driving module in response to a pulse signal of the first scan signal on the first scan line.

[0035] Optionally, the pixel circuit further comprises a first light-emitting control module and a second light-emitting control module.

[0036] The display device further comprises a plurality of light-emitting control signal lines, the light-emitting control signal lines being connected to the control end of the first light-emitting control module and the control end of the second light-emitting control module in the pixel circuit of the corresponding row respectively, the first light-emitting control module being connected between the first power supply line and the first end of the driving module, and the second light-emitting control module being connected between the second end of the driving module and the first end of the light-emitting module.

[0037] Optionally, the pixel circuit further comprises a data writing module, a compensation module, a third initialization module and a storage module.

[0038] The display device further comprises:

[0039] a plurality of second scan lines, the second scan lines being connected to the control end of the data writing module in the pixel circuit of the corresponding row;

[0040] a data line, the data writing module being connected between the data line and the first end of the driving module, and the data writing module being configured to transmit a data voltage to the driving module in response to a second scan signal on the second scan line;

[0041] a plurality of third scan lines, the third scan lines being connected to the control end of the compensation module in the pixel circuit of the corresponding row, the compensation module being connected between the second end of the driving module and the control end, and the compensation module being configured to perform threshold compensation on the driving module in response to a third scan signal on the third scan line;

[0042] a plurality of fourth scan lines, the fourth scan lines being connected to the control end of the third initialization module in the pixel circuit of the corresponding row;

[0043] a third initialization signal line, the third initialization module being connected between the third initialization signal line and the second end of the driving module, and the third initialization module being configured to transmit a third initialization voltage on the third initialization signal line to the control end of the driving module through the compensation module in response to a fourth scan signal on the fourth scan line;

[0044] the storage module being connected between the first power supply line and the control end of the driving module.

[0045] According to another aspect of the present application, a driving method of a display device is provided, the display device comprising: a plurality of pixel circuits arranged in an array; a first scan circuit and a plurality of first scan lines, the first scan circuit being electrically connected to the pixel circuit of the corresponding row through the corresponding first scan line; a first voltage line, the pixel circuit being electrically connected to the first voltage line;

[0046] The driving method of the display device comprises:

[0047] In the first time period, a voltage is output to the first voltage line, and the pixel circuit of the corresponding row writes the voltage on the first voltage line into the pixel circuit in response to a pulse signal of the first scan signal on the first scan line;

[0048] In the second time period, a voltage different from that in the first time period is output to the first voltage line, and the pixel circuit of the corresponding row writes the voltage on the first voltage line into the pixel circuit in response to a pulse signal of the first scan signal on the first scan line.

[0049] Optionally, at least during part of the first time period, the pulse signals output to the N first scan lines overlap with each other;

[0050] At least during part of the second time period, the pulse signals output to the M first scan lines overlap with each other, and N and M are unequal positive integers.

[0051] The technical scheme provided by the embodiment of the present application outputs different voltages to the first voltage line in the first time period and the second time period in at least one picture refresh period, and the pixel circuit writes the voltage on the first voltage line into the pixel circuit in response to a pulse signal of the first scan signal on the first scan line. Since the voltage written by the first voltage line into the pixel circuit is different in the first time period and the second time period, the display unevenness caused by the difference in the in-plane load in different time periods can be improved, and the display effect is improved.

[0052] It should be understood that the content described in this part is not intended to identify the key or important features of the embodiments of the present application, nor is it used to limit the scope of the present application. Other features of the present application will become apparent from the following description. BRIEF DESCRIPTION OF DRAWINGS

[0053] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following will briefly introduce the drawings needed in the embodiment description. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can also be obtained by those skilled in the art without creative labor.

[0054] Figure 1 A partial structure diagram of a pixel circuit in the related art;

[0055] Figure 2 A schematic diagram of a display result of a display panel in the related art at a certain time;

[0056] Figure 3 A schematic diagram of a display result of the display panel shown in another time; Figure 2

[0057] Figure 4 ​A structural schematic diagram of a display device provided by an embodiment of the present application;

[0058] Figure 5 A driving timing waveform schematic diagram of a pixel circuit provided by an embodiment of the present application;

[0059] Figure 6 A voltage waveform schematic diagram transmitted on a first voltage line provided by an embodiment of the present application;

[0060] Figure 7 A structural schematic diagram of a pixel circuit provided by an embodiment of the present application;

[0061] Figure 8 A structural schematic diagram of another pixel circuit provided by an embodiment of the present application;

[0062] Figure 9 A structural schematic diagram of another pixel circuit provided by an embodiment of the present application;

[0063] Figure 10 A driving timing schematic diagram of a pixel circuit provided by an embodiment of the present application;

[0064] Figure 11 A voltage change schematic diagram of a first initialization signal line provided by an embodiment of the present application;

[0065] Figure 12 A driving timing schematic diagram of another pixel circuit provided by an embodiment of the present application;

[0066] Figure 13 A display result schematic diagram of a display panel in a first time period provided by an embodiment of the present application;

[0067] Figure 14 A display result schematic diagram of a display panel in a second time period provided by an embodiment of the present application;

[0068] Figure 15 A driving timing schematic diagram of another pixel circuit provided by an embodiment of the present application;

[0069] Figure 16 A flow chart of a driving method of a display device provided by an embodiment of the present application. DETAILED DESCRIPTION

[0070] In the following, the technical solutions in the embodiments of the present application will be described clearly and completely with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments of the present application. Based on the embodiments in the present application, all the other embodiments obtained by a person of ordinary skill in the art without creative work should belong to the protection scope of the present application.

[0071] It should be noted that the terms "first", "second" and the like in the description and claims of the present application and the above drawings are used to distinguish similar objects, and do not necessarily indicate a specific order or sequence. It should be understood that the data thus used can be interchanged under appropriate circumstances, so that the embodiments of the application described herein can be implemented in an order other than that illustrated or described herein. In addition, the terms "comprise" and "have" and any variations thereof are intended to cover non-exclusive inclusion, for example, a process, method, system, product or device comprising a series of steps or units does not necessarily limit to those steps or units clearly listed, but can include other steps or units not clearly listed or inherent to these processes, methods, products or devices.

[0072] The display panel in the related art has the phenomenon of displaying a split screen, which reduces the display quality. The inventor has found that the reasons for the above problems are as follows:

[0073] The corresponding refresh frequency of the display panel is different in different working modes. At present, the low refresh frequency is realized by frame skipping on the basis of the high refresh frequency, and a display period includes a write frame and a hold frame. By inserting a hold frame after the write frame and adjusting the time length of the hold frame, the refresh frequency can be changed. The display panel usually includes a pixel circuit for driving a light emitting device to emit light. In low-frequency display, the first electrode or the second electrode of the driving transistor in the pixel circuit is in a bias state for a long time, which causes the characteristics of the driving transistor to deviate, so that the display brightness of the driving transistor in the hold frame and the write frame is different, thereby causing the flicker phenomenon. In the related art, in order to solve the above problem, the first electrode or the second electrode of the driving transistor is usually voltage biased to improve the threshold characteristics of the driving transistor.

[0074] Figure 1 It is a partial structure diagram of a pixel circuit in the related art, referring to Figure 1The pixel circuit comprises a first transistor M1, a second transistor M2, a third transistor M3, a seventh transistor M7 and an eighth transistor M8, wherein the third transistor M3 is a driving transistor. In an initialization stage, the first transistor M1 is turned on in response to a scanning signal SP, and transmits an initialization voltage Vref to the first electrode of the light-emitting diode D1, so as to initialize the anode of the light-emitting diode D1; meanwhile, the second transistor M2 is turned on in response to the scanning signal SP, and transmits a bias voltage Vcom to the first electrode of the third transistor M3, so as to reset the voltage of the first electrode of the third transistor M3, so as to change the bias state of the third transistor M3, thereby improving the threshold characteristic of the third transistor M3, so as to reduce the luminance difference between a holding frame and a writing frame, and improve the uniformity of display luminance.

[0075] In actual application, the scanning signal SP controls the anode initialization of the light-emitting diode D1 and the voltage bias of the third transistor M3 at the same time, and the scanning signal SP is a high-frequency signal, and the scanning signal SP comprises a plurality of pulse signals. When the scanning signal SP scans the blank stage between adjacent frames (taking one frame as one display period as an example), there is a luminance difference between different display areas of the display panel, and the phenomenon of "split screen" occurs. For the convenience of understanding, specific examples are taken for description. Figure 2 FIG. 1 shows a schematic diagram of the display result of a display panel in the related art at a certain moment, Figure 3 FIG. 2 shows a schematic diagram of the display result of the display panel shown in FIG. 1 at another moment, and Figure 2 FIG. 3 shows a schematic diagram of the display result of the display panel shown in FIG. 1 at another moment, and Figures 1-3 The display area A in the display panel is provided with a plurality of pixel circuits, and the scanning signal SP comprises a plurality of pulses in one display period. In the active level of the scanning signal SP, the first transistor M1 and the second transistor M2 are turned on in response to the pulse signals of the scanning signal, so as to initialize the first electrode of the light-emitting diode D1 and the first electrode of the third transistor M3. Taking the scanning signal SP comprising three pulses as an example, the pulse width is associated with the scanning time of the pixel row. Here, the pulse width of the scanning signal SP can correspond to the scanning time of a plurality of rows (for example, 20 rows of pixel circuits). After the pixel circuit is stable, in the same stage of one display period, the pixel circuits in three areas in the display area A initialize the first electrode of the light-emitting diode D1 and the first electrode of the third transistor M3, that is, 20 rows of pixel circuits in the first area 11, 20 rows of pixel circuits in the second area 12 and 20 rows of pixel circuits in the third area 13 initialize the corresponding light-emitting diodes D1 in response to the three pulses of the scanning signal SP. At this time, the load in the display area A is the load corresponding to 60 rows of pixel circuits.

[0076] As shown in FIG. 3, Figure 3As shown, with the passage of time, one pulse timing of the scanning signal SP enters the blank phase, which can correspond to the Blank region B, which does not exist on the display panel, but only exists in the time dimension. That is, when one pulse timing of the scanning signal SP enters the blank phase, only the fourth region 21 and the fifth region 22 in the display area A are scanned, and the load in the display area A is the load corresponding to 40 rows of pixel circuits. Thus, in a certain phase of a display period, the pixel circuits in two regions of the display panel are initialized, and in other phases, the pixel circuits in three regions are initialized, which leads to different numbers of pixel rows in different display phases, different loads in the plane, and different degrees of initialization of the first electrode of the light-emitting diode D1 in the fourth region 21 and the fifth region 22. The difference in the voltage difference between the first electrode and the second electrode of the light-emitting diode D1 in the fourth region 21 and the fifth region 22 and the voltage difference of the light-emitting diode D1 in other regions, resulting in a difference in display brightness between the fourth region 21 and the fifth region 22 and other regions, thereby dividing the display area A into three parts at the fourth region 21 and the fifth region 22, and visually presenting a three-split screen effect.

[0077] To solve the above problems, an embodiment of the present application provides a display device. Figure 4 A structural schematic diagram of a display device provided by an embodiment of the present application, which can be a mobile phone, a computer, a tablet computer, or an electronic device, or a display panel. Referring to Figure 4 The display device comprises:

[0078] a plurality of pixel circuits PX arranged in an array;

[0079] a first scanning circuit 200 and a plurality of first scanning lines G1, the first scanning circuit 200 being electrically connected to the corresponding row of pixel circuits PX through the corresponding first scanning line G1. For example, the first first scanning line G1(1) is connected to the first row of pixel circuits PX, the second first scanning line G1(2) is connected to the second row of pixel circuits PX, and the nth first scanning line G1(n) is connected to the nth row of pixel circuits PX. The first scanning circuit 200 is used to transmit a first scanning signal to the first scanning line G1.

[0080] The first voltage line V1 is electrically connected with the pixel circuit PX, and the pixel circuit PX is configured to write the voltage on the first voltage line V1 into the pixel circuit PX in response to a pulse signal of the first scanning signal on the first scanning line G1. The number of the first voltage line V1 is at least one, and the extension direction of the first voltage line V1 can be the same as the extension direction of the first scanning line G1 or can intersect with the extension direction of the first scanning line G1. Here, the first voltage line V1 can be a power line or an initialization signal line. Optionally, the first voltage line V1 can be multiple, and the multiple first voltage lines V1 are electrically connected with each other and are electrically connected with the same voltage adjustment module. That is, the first voltage lines V1 (1) to V1 (n) are electrically connected with each other and transmit the same voltage. Different voltages are output to the first voltage line V1 in the first period and the second period in at least one picture refresh cycle.

[0081] The first period and the second period are two different time periods in one picture refresh cycle. In at least part of the first period, the pulse signals output to the N first scanning lines overlap with each other, and in at least part of the second period, the pulse signals output to the M first scanning lines overlap with each other. The first scanning circuit 200 is configured to output pulse signals to the N first scanning lines G1 simultaneously in the first period, and the second scanning circuit 200 is further configured to output pulse signals to the M first scanning lines G1 simultaneously in the second period. N and M are unequal positive integers. Therefore, the load in the display device is different in the first period and the second period. Optionally, the display device further comprises a voltage adjustment module 300 electrically connected with the first voltage line V1, and the voltage adjustment module 300 is configured to output different voltages to the first voltage line V1 in the first period and the second period in at least one picture refresh cycle. In this embodiment, when the in-plane load changes, the voltage output to the first voltage line V1 is adjusted to match the in-plane load (where the load of the first scanning circuit 200 is different in the first period and the second period, and the load of the first voltage line V1 is different in the first period and the second period), thereby improving display unevenness or other display defects. Optionally, N is greater than M, and the absolute value of the voltage output to the first voltage line V1 in the first period is greater than the absolute value of the voltage output to the first voltage line V1 in the second period.

[0082] The technical scheme provided by the embodiment of the application outputs different voltages to the first voltage line in the first period and the second period in at least one picture refresh cycle, and the pixel circuit writes the voltage on the first voltage line into the pixel circuit in response to the pulse signal of the first scanning signal on the first scanning line. Since the voltage written into the pixel circuit by the first voltage line is different in the first period and the second period, the display unevenness and other bad phenomena caused by the difference in in-plane load in different periods can be improved, and the display effect is improved.

[0083] The core idea of the present application is described above, and the present application will be described in detail below with reference to specific embodiments.

[0084] Figure 5 A driving timing waveform diagram is provided for the embodiment of the present application, as shown in Figure 5 In the embodiment, one frame refresh period F includes an active phase active and a blank phase blank. The frame refresh period F can be defined by a vertical synchronization signal V-sync, and the time between the falling edge of a V-sync pulse and the falling edge of the next V-sync pulse is the time of one frame refresh period F. The active phase active and the blank phase blank can be defined by an external interface signal TE of the display panel, where the TE signal is a non-display trigger signal, the high level of the TE signal corresponds to the blank phase blank, and the low level corresponds to the active phase active. In the active phase active, the pixel circuit PX can complete initialization, data writing, light emitting, and other operations. Between the time when the last row of pixel circuits of the display area A write the data of the previous frame and the time when the first row of pixel circuits write the data of the next frame, there is a vertical blanking time interval, also referred to as the blank phase blank.

[0085] Figure 6 A waveform diagram of the voltage transmitted on the first voltage line is provided for the embodiment of the present application, as shown in Figure 5 and Figure 6 In the first time period F1 in one frame refresh period F, the first voltage line V1 is configured to transmit a first sub-voltage VA1, and in the second time period F2, the first voltage line V1 is configured to transmit a second sub-voltage VA2 different from the first sub-voltage VA1. The first time period F1 is located in the active phase active, and the second time period F2 is located in the blank phase blank.

[0086] Continuing to refer to Figure 4 The display device further includes a plurality of data lines DL, and the data lines DL are used to transmit data voltages Vdata to realize different gray scale displays of the display device. The data lines DL extend along the Y direction, and the first scan lines G1 extend along the X direction, and the X direction intersects the Y direction. The data lines DL are electrically connected to the pixel circuits of the corresponding columns. The X direction can be the row direction. The Y direction can be the column direction.

[0087] Optionally, the display device further includes a plurality of second scan lines, and the second scan lines are electrically connected to the pixel circuits of the corresponding rows. The pixel circuit is configured to write the data voltage on the data line into the pixel circuit in response to a second scan signal S2 on the second scan line in a data writing phase. Figure 7 A structure diagram of a pixel circuit is provided for the embodiment of the present application, as shown in Figure 7On the basis of each of the above technical solutions, the pixel circuit PX comprises a driving module 110, a light-emitting module 140, and a first initialization module 130, the driving module 110 is connected between the first power supply line L1 and the first end of the light-emitting module 140; the first scan circuit 200 is electrically connected to the control end of the first initialization module 130 in the pixel circuit PX of the corresponding row via the corresponding first scan line G1; the first initialization module 130 is connected between the first end of the light-emitting module 140 and the first initialization signal line, and the first initialization module 130 is configured to transmit the first initialization voltage Vref1 on the first initialization signal line to the first end of the light-emitting module 140 in response to a pulse signal of the first scan signal S1 on the first scan line G1.

[0088] Optionally, the display device further comprises a plurality of light-emitting control signal lines, and the pixel circuit PX further comprises a first light-emitting control module 181 and / or a second light-emitting control module 182; the light-emitting control signal lines are respectively connected to the control end of the first light-emitting control module 181 and the control end of the second light-emitting control module 182 in the pixel circuit PX of the corresponding row, the first light-emitting control module 181 is connected between the first power supply line L1 and the first end S of the driving module 110, and the second light-emitting control module 182 is connected between the second end D of the driving module 110 and the first end of the light-emitting module 140.

[0089] Optionally, the pixel circuit PX further comprises a data writing module 150 and a compensation module 160.

[0090] The display device further comprises a plurality of second scan lines, the second scan lines are connected to the control end of the data writing module 150 in the pixel circuit PX of the corresponding row; the data writing module 150 is connected between the data line DL and the first end S of the driving module 110, and the data writing module 150 is configured to transmit the data voltage data to the driving module 110 in response to the second scan signal S2 on the second scan line.

[0091] The display device further comprises a plurality of third scan lines, the third scan lines are connected to the control end of the compensation module 160 in the pixel circuit PX of the corresponding row, the compensation module 160 is connected between the second end D of the driving module 110 and the control end G, and the compensation module 160 is configured to perform threshold compensation on the driving module 110 in response to the third scan signal S3 on the third scan line.

[0092] Optionally, the pixel circuit PX further comprises a storage module 170, and the storage module 170 is connected between the first power supply line L1 and the control end G of the driving module 110.

[0093] In the embodiment, the first voltage line V1 can be a first initialization signal line, and a voltage transmitted on the first voltage line V1 is a first initialization voltage Vref1, which can be a negative voltage and is used to reset the first end of the light emitting module 140.

[0094] Specifically, the first power line L1 is used to transmit a first power voltage VDD, and the second power line L2 is used to transmit a second power voltage VSS, the first power voltage VDD can be greater than the second power voltage VSS, and when the connection path between the first power line L1 and the second power line L2 is turned on, the driving module 110 drives the light emitting module 140 to emit light. The working process of the pixel circuit at least includes a first initialization stage, a data writing stage and a light emitting stage. In the first initialization stage, the first initialization module 130 turns on in response to the first scan signal S1, and transmits the first initialization voltage Vref1 to the first end of the light emitting module 140 to initialize the potential of the first end of the light emitting module 140. In the data writing stage, the data writing module 150 turns on in response to the second scan signal S2, transmits the data voltage Vdata on the data line DL to the first end S of the driving module 110, and writes the data voltage Vdata to the control end G of the driving module 110 through the compensation module 160. In the light emitting stage, the connection path between the first power line L1 and the second power line L2 is controlled to be turned on by the first light emitting control module 181 and the second light emitting control module 182, so that the driving module 110 can drive the light emitting module 120 to emit light.

[0095] Optionally, in a frame refresh period F, the first scan signal on the same first scan line G1 includes a plurality of pulse signals, and the first initialization module 130 is connected to the first scan circuit 200, and the first initialization module 130 is connected to the first scan circuit 200. Figure 2 and Figure 3 Taking an example of three pulse signals in the same first scan signal, in the first time period, each row of pixel circuits in the first region 11, the second region 12 and the third region 13 in the display area A correspond to the pulse signals of the first scan signal, and the first scan circuit 200 simultaneously outputs the pulse signals to the N first scan lines G1 corresponding to the three regions, and the pixel circuits PX of the corresponding rows respond to the pulse signals of the first scan signal to transmit the first sub-voltage VA1 on the first voltage line V1 to the corresponding pixel circuits PX. Here, Figure 2 and Figure 3Each pulse signal in the first scanning signal can correspond to multiple first scanning lines G1, that is, multiple rows of pixel circuits PX can be scanned simultaneously. At least part of the time in the first time period, for example, the first time and the second time, the first scanning circuit 200 simultaneously outputs pulse signals to N first scanning lines G1; since it is scanned row by row, for example, from top to bottom, the N first scanning lines G1 corresponding to the first time and the second time are not completely the same, for example, partially different, or completely different. For example, the first scanning line is 100, the N first scanning lines G1 corresponding to the first time are serial numbers 1 to 10 (corresponding to the third pulse signal output by each first scanning line), 41 to 50 (corresponding to the second pulse signal output by each first scanning line), and 81 to 90 (corresponding to the first pulse signal output by each first scanning line), and the N first scanning lines G1 corresponding to the second time are serial numbers 2 to 11 (corresponding to the third pulse signal output by each first scanning line), 42 to 51 (corresponding to the second pulse signal output by each first scanning line), and 82 to 91 (corresponding to the first pulse signal output by each first scanning line). The duration of each pulse signal is greater than the interval between the start times of the pulse signals of two adjacent first scanning lines (equivalent to the shift time interval of the pulse signals output by two adjacent shift registers in the first scanning circuit). In the second time period, at least one of the three pulse signals of the first scanning signal of the pixel circuits in the partial region enters the blank phase blank, at this time, only the pixel circuits in the fourth region 21 and the fifth region 22 in the display area A correspond to the pulse signals of the first scanning signal, and the first scanning circuit 200 simultaneously outputs pulse signals to M first scanning lines G1 in these two regions. That is, N can be greater than M. At least part of the time in the second time period, for example, the third time and the fourth time, the first scanning circuit 200 simultaneously outputs pulse signals to M first scanning lines G1; since it is scanned row by row, for example, from top to bottom, the M first scanning lines G1 corresponding to the third time and the fourth time are not completely the same, for example, partially different, or completely different. For example, the first scanning line is 100, the M first scanning lines G1 corresponding to the third time are serial numbers 31 to 40 (corresponding to the third pulse signal output by each first scanning line), 71 to 80 (corresponding to the second pulse signal output by each first scanning line), and the M first scanning lines G1 corresponding to the second time are serial numbers 32 to 41 (corresponding to the third pulse signal output by each first scanning line), 72 to 81 (corresponding to the second pulse signal output by each first scanning line). Since the in-plane load has changed, the voltage adjustment module 300 adjusts the first sub-voltage VA1 transmitted on the first voltage line V1 to the second sub-voltage VA2, and the pixel circuits PX corresponding to the row respectively respond to the pulse signals of the first scanning signal to transmit the second sub-voltage VA2 on the first voltage line V1 to the corresponding pixel circuits PX, so as to eliminate the screen splitting phenomenon caused by the difference in in-plane load in different time periods in a frame refresh period F.

[0096] The second sub-voltage VA2 can be adjusted according to the first sub-voltage VA1. Specifically, the voltage adjustment module 300 can determine a current compensation amount according to a current refresh frequency and / or a current display brightness value of the display device, and a corresponding relationship between the refresh frequency and / or the display brightness value and the compensation amount, and determine the second sub-voltage VA2 according to the current compensation amount and the first sub-voltage VA1. For example, when the first sub-voltage VA1 is -1.5V at a refresh frequency of 120Hz, and when the pulse signal of the first scanning signal S1 scans to the blank phase, the current compensation amount at the current refresh frequency is determined to be 0.5V according to the corresponding relationship between the refresh frequency and / or the display brightness value and the compensation amount, and then the second sub-voltage VA2 is determined to be -1.45V according to the current compensation amount and the first sub-voltage VA1, that is, the second sub-voltage VA2 is equal to the sum of the first sub-voltage VA1 and the current compensation amount.

[0097] In other embodiments, the compensation amount can also be represented by a compensation coefficient, in which case the second sub-voltage VA2 can also be equal to the product of the first sub-voltage VA1 and the current compensation amount.

[0098] It should be noted that, in the first time period, the first initialization voltage transmitted on the first initialization signal line is the first sub-voltage VA1, and in the second time period, the first initialization voltage transmitted on the first initialization signal line is the second sub-voltage VA2. Since the load is reduced in the second time period, the second sub-voltage VA2 is increased, and both the first sub-voltage VA1 and the second sub-voltage VA2 are negative voltages, so that the absolute value of the first sub-voltage VA1 is greater than the absolute value of the second sub-voltage VA2.

[0099] In actual application, the corresponding relationship between the refresh frequency and / or the display brightness value and the compensation amount can be stored in the driving chip in the form of a three-dimensional table, and when the display device displays, the driving chip can automatically detect the current refresh frequency and / or the display brightness value, and control the voltage adjustment module 300 to dynamically adjust the voltage value of the first initialization voltage Vref1 according to the corresponding relationship, so as to improve the display split screen phenomenon. The display brightness value (DBV) can also be referred to as the display brightness level. Mobile phones, computers and other display devices usually include a brightness adjustment button, and the user can change the input display brightness level through the brightness adjustment button. The brightness corresponding to the same gray scale is different at different DBV. For example, the greater the DBV, the greater the brightness corresponding to the maximum gray scale.

[0100] Figure 8 Another structure schematic diagram of a pixel circuit provided by an embodiment of the present application is shown in FIG. 4, Figure 9 Another structure schematic diagram of a pixel circuit provided by an embodiment of the present application is shown in FIG. 4, Figure 8 and Figure 9On the basis of the above technical solution, the pixel circuit PX further comprises a second initialization module 120, and the display device further comprises a second initialization signal line, the second initialization module 120 is connected between the second initialization signal line and the first end S or the second end D of the driving module 110, the control end of the second initialization module 120 is electrically connected with the first scan line, and the second initialization module 120 is configured to transmit the second initialization voltage Vref2 on the second initialization signal line to the first end S or the second end D of the driving module 110 in response to a pulse signal of the first scan signal S1 on the first scan line. In the second initialization stage, the second initialization module 120 is turned on in response to the first scan signal S1 to reset the first end S or the second end D of the driving module 110.

[0101] Optionally, the pixel circuit PX further comprises a third initialization module 190, and the display device further comprises a plurality of fourth scan lines, the fourth scan lines being connected with the control end of the third initialization module 190 in the pixel circuit PX of the corresponding row.

[0102] Optionally, the display device further comprises a third initialization signal line, the third initialization module 190 is connected between the third initialization signal line and the second end D of the driving module 110, and the third initialization module 190 is configured to transmit the third initialization voltage Vref3 on the third initialization signal line to the control end G of the driving module 110 through the compensation module 160 in response to the fourth scan signal S4 on the fourth scan line. Optionally, the third initialization module 190 can also be directly electrically connected with the control end G of the driving module 110, and the third initialization module 190 is connected between the third initialization signal line and one end of the control end G of the driving module 110 connected with the compensation module 160. The third initialization module 190 is configured to directly transmit the third initialization voltage Vref3 on the third initialization signal line to the control end G of the driving module 110 in response to the fourth scan signal S4 on the fourth scan line. In the third initialization stage, the third initialization module 190 is turned on in response to the fourth scan signal S4 to reset the control end G of the driving module 110.

[0103] Specifically, the first initialization module 130 comprises a first transistor M1, the gate of the first transistor M1 is connected with the first scan line G1, the first pole of the first transistor M1 is connected with the first initialization signal line, the second pole of the first transistor M1 is connected with the first end of the light-emitting module 140, and the first transistor M1 is configured to transmit the first initialization voltage Vref1 on the first initialization signal line to the first end of the light-emitting module 140 in the first initialization stage.

[0104] Optionally, the second initialization module 120 comprises a second transistor M2, the gate of the second transistor M2 is connected with the first scan line, the first pole of the second transistor M2 is connected with the second initialization signal line, and the second pole of the second transistor M2 is connected with the first end S (as shown in Figure 8 ) or the second end D (as shown in Figure 9 ) of the driving module 110, and the second transistor M2 is used for transmitting the second initialization voltage Vref2 on the second initialization signal line to the first end S or the second end D of the driving module 110 in the second initialization stage.

[0105] Optionally, the driving module 110 comprises a third transistor M3 (i.e. a driving transistor), the data writing module 150 comprises a fourth transistor M4, the compensation module 160 comprises a fifth transistor M5, the third initialization module 190 comprises a sixth transistor M6, the first light emitting control module 181 comprises a seventh transistor M7, the second light emitting control module 182 comprises an eighth transistor M8, the light emitting module 140 comprises a light emitting diode D1, and the storage module 170 comprises a capacitor C. The gate of the fourth transistor M4 is connected with the second scan line, the first pole of the fourth transistor M4 is connected with the data line, and the second pole of the fourth transistor M4 is connected with the first pole of the third transistor M3. The gate of the fifth transistor M5 is connected with the third scan line, the first pole of the fifth transistor M5 is connected with the second pole of the third transistor M3, and the second pole of the fifth transistor M5 is connected with the gate of the third transistor M3. The gate of the sixth transistor M6 is connected with the fourth scan line, the first pole of the sixth transistor M6 is connected with the second initialization signal line, and the second pole of the sixth transistor M6 is connected with the first pole of the fifth transistor M5. The gate of the seventh transistor M7 and the gate of the eighth transistor M8 are both connected with the light emitting control signal line, the first pole of the seventh transistor M7 is connected with the first power line L1, the second pole of the seventh transistor M7 is connected with the first pole of the third transistor M3, the first pole of the eighth transistor M8 is connected with the second pole of the third transistor M3, the second pole of the eighth transistor M8 is connected with the first pole of the light emitting diode D1, and the second pole of the light emitting diode D1 is connected with the second power line L2. The first pole of the capacitor C is connected with the first power line L1, and the second pole of the capacitor C is connected with the gate of the third transistor M3. Here, the first pole of the light emitting diode D1 can be an anode, and the second pole can be a cathode. The fifth transistor M5 and the sixth transistor M6 can be N-type transistors, or can be P-type transistors, and the rest of the transistors are P-type transistors. Figure 8 and Figure 9 Only the case that the fifth transistor M5 and the sixth transistor M6 are N-type transistors is shown. For example, the fifth transistor M5 and the sixth transistor M6 can both be metal oxide transistors. The advantage of this arrangement is that the leakage problem of the gate of the third transistor M3 can be reduced, which is conducive to maintaining the stability of the gate voltage of the third transistor M3.

[0106] Figure 10 A driving timing diagram of a pixel circuit provided by an embodiment of the present application can be applied to the pixel circuit shown in FIG. 1. Figure 8 and Figure 9 The pixel circuit provided by the embodiment of the present application includes a first initialization module 130, a second initialization module 120, a data writing module 150, a third initialization module 190, a first light emitting control module 181 and a second light emitting control module 182. Figures 8-10 In combination with the pixel circuit shown in FIG. 1, the working process of the pixel circuit provided by the embodiment of the present application includes t1-t8 stages.

[0107] In the t1 stage (corresponding to the third initialization stage), the first scan signal S1 is at an off level, for example, a high level, the second scan signal S2 is at an off level, for example, a high level, the third scan signal S3 is at an on level, for example, a high level, the fourth scan signal S4 is at an on level, for example, a high level, and the light emitting control signal EM is at an off level, for example, a high level. Therefore, the compensation module 160 and the third initialization module 190 are turned on, for example, the fifth transistor M5 and the sixth transistor M6 are turned on, the third initialization voltage Vref3 on the third initialization signal line is transmitted to the gate of the third transistor M3 through the sixth transistor M6 and the fifth transistor M5, and the gate voltage of the third transistor M3 is initialized. The third initialization voltage Vref3 is also transmitted to the second electrode D and the first electrode S of the third transistor M3 through the sixth transistor M6, and the second electrode D and the first electrode S of the third transistor M3 are initialized. The first initialization module 130, the second initialization module 120, the data writing module 150, the first light emitting control module 181 and the second light emitting control module 182 are turned off.

[0108] In the t2 stage (corresponding to the data writing stage), the first scan signal S1 is at an off level, for example, a high level, the second scan signal S2 is at an on level, for example, a low level, the third scan signal S3 is at an on level, for example, a high level, the fourth scan signal S4 is at an off level, for example, a low level, and the light emitting control signal EM is at an off level, for example, a high level. Therefore, the data writing module 150 and the compensation module 160 are turned on, for example, the fourth transistor M4 and the fifth transistor M5 are turned on, the data voltage Vdata is written to the gate of the third transistor M3 through the fourth transistor M4, the third transistor M3 and the fifth transistor M5, the gate voltage of the third transistor M3 is associated with the data voltage Vdata and the threshold voltage of the third transistor M3, and the threshold compensation of the third transistor M3 is realized. The capacitor C stores the gate voltage of the third transistor M3. The first initialization module 130, the second initialization module 120, the third initialization module 190, the first light emitting control module 181 and the second light emitting control module 182 are turned off.

[0109] In the t3 stage (corresponding to the first initialization stage and the second initialization stage), the first scan signal S1 is at an on level, e.g., a low level, the second scan signal S2 is at an off level, e.g., a high level, the third scan signal S3 is at an off level, e.g., a low level, the fourth scan signal S4 is at an off level, e.g., a low level, and the light emitting control signal EM is at an off level, e.g., a high level. Thus, the first initialization module 130 and the second initialization module 120 are turned on, e.g., the first transistor M1 and the second transistor M2 are turned on, the first initialization voltage Vref1 on the first initialization signal line is transmitted to the first electrode of the light emitting diode D1 through the first transistor M1, and the first electrode of the light emitting diode D1 is initialized. Meanwhile, the second initialization voltage Vref2 on the second initialization signal line is transmitted to the first electrode of the third transistor M3 through the second transistor M2, the voltage of the first electrode of the third transistor M3 is reset, the bias state of the third transistor M3 is changed, the threshold characteristics of the third transistor M3 can be kept stable at different gray scales, and the uniformity of the driving current generated by the third transistor M3 is improved. The data writing module 150, the compensation module 160, the third initialization module 190, the first light emitting control module 181 and the second light emitting control module 182 are turned off.

[0110] In the t4 stage (corresponding to the light emitting stage), the first scan signal S1 is at an off level, e.g., a high level, the second scan signal S2 is at an off level, e.g., a high level, the third scan signal S3 is at an off level, e.g., a low level, the fourth scan signal S4 is at an off level, e.g., a low level, and the light emitting control signal EM is at an on level, e.g., a low level. Thus, the first light emitting control module 181 and the second light emitting control module 182 are turned on, e.g., the seventh transistor M7 and the eighth transistor M8 are turned on, the connection path between the first power supply line L1 and the second power supply line L2 is turned on, the third transistor M3 generates a driving current to drive the light emitting diode D1 to emit light. The data writing module 150, the compensation module 160, the first initialization module 130, the second initialization module 120 and the third initialization module 190 are turned off.

[0111] The working states of the elements in the t5 stage and the t7 stage are the same as those in the t3 stage.

[0112] The working states of the elements in the t6 stage and the t8 stage are the same as those in the t4 stage.

[0113] It should be noted that, Figure 10 The driving timing shown is the driving timing in one frame refresh period F. In one frame refresh period F, each row of pixel circuits successively performs the third initialization stage and the data writing stage. As for the first scan signal S1, there are three pulse signals in one frame refresh period F. In the first time period, the in-plane (e.g., the row direction) of the pixel circuit is scanned, and the second time period and the third time period are the data writing stages of the pixel circuit. Figure 2The display area A) shown has three regions of pixel circuits in a scanning refresh state; as the scanning time continues, the first scanning signal pulse signal corresponding to the third region 13 is gradually shifted down, and the first scanning line G1 in the in-plane simultaneous driving is reduced, and the in-plane load is reduced accordingly, and the voltage adjustment module 300 adjusts the first sub-voltage VA1 on the first initialization signal line to the second sub-voltage VA2 according to the current refresh frequency and / or the current display brightness value, to reduce the initialization degree of the anode of the light-emitting diode D1 in the second period, and improve the uniformity of the display.

[0114] Figure 11 A voltage change diagram of a first initialization signal line provided by an embodiment of the present application is shown. For example, the refresh frequency is 120Hz, scheme 1 is the voltage change of the first initialization signal line in the related art, and the constant voltage source module outputs the same direct current potential to the first initialization signal line in the first period and the second period. For example, the constant voltage source module outputs the same direct current potential to the first initialization signal line in the active phase active and the blank phase blank. In the active phase active, the first initialization voltage Vref1 transmitted on the first initialization signal line is -1.5V. When the pulse signal of the first scanning signal S1 corresponding to the pixel circuit PX in the partial region is scanned to the blank phase blank, the first initialization voltage Vref1 transmitted on the first initialization signal line jumps to -1.55V due to the reduced load, the influence of the load and the line voltage drop, etc., and the first initialization voltage Vref1 is pulled low, so that the initialization degree of the anode of the light-emitting diode D1 is more sufficient.

[0115] Scheme 2 is the voltage change of the initialization signal line provided by the present embodiment. When the pulse signal of the first scanning signal S1 enters the blank phase blank, that is, in the second period, the first initialization voltage Vref1 is adjusted from -1.5V to -1.45V (that is, from the first sub-voltage VA1 to the second sub-voltage VA2) by the voltage adjustment module 300, so as to reduce the initialization degree of the anode of the light-emitting diode D1. The second sub-voltage VA2 is a constant value.

[0116] Alternatively, the voltage adjustment module 300 is configured to output a constant voltage to the first voltage line V1 in the active phase; the voltage adjustment module 300 is configured to output a constant voltage to the first voltage line V1 in the blank phase; or output a voltage that changes in a stepwise manner with time to the first voltage line V1 in the blank phase.

[0117] Of course, in another alternative provided by the embodiment, the second sub-voltage VA2 can also be a voltage that changes in steps over time, for example, as shown in Scheme 3. The second sub-voltage VA2 includes a plurality of pulse signals with different amplitudes, and the second sub-voltage VA2 is adjusted in a PWM voltage regulation manner, which is advantageous to improve the voltage accuracy of the second sub-voltage VA2 and facilitate the improvement of the display effect.

[0118] In a picture refresh period, the number of pulses of the second sub-voltage VA2 is related to the current refresh frequency. If the current refresh frequency is a first preset refresh frequency, the number of pulses of the second sub-voltage in a picture refresh period is P; if the current refresh frequency is a second preset refresh frequency, the number of pulses of the second sub-voltage in a picture refresh period is Q; the first preset refresh frequency is greater than the second preset refresh frequency, and P < Q, P and Q are both integers greater than or equal to 1.

[0119] Continuing to refer to Figure 11 , the Xth frame and the X+1th frame are two picture refresh periods, and the refresh frequency of the X+1th frame is less than that of the Xth frame. Since the refresh frequency of the X+1th frame is smaller, the duration of the blank phase blank corresponding to the X+1th frame is longer, and more pulse signals can be set to further improve the voltage accuracy. Alternatively, when the current refresh frequency is 120 Hz, the number of pulses of the second sub-voltage can be K, for example, 2, as shown in the Xth frame of Figure 11 ; when the current refresh frequency is 90 Hz, the number of pulses of the second sub-voltage can be 2K, for example, 4, as shown in the X+1th frame of Figure 11 ; when the current refresh frequency is 60 Hz, the number of pulses of the second sub-voltage can be 3K, for example, 6, and so on. K can be a positive integer.

[0120] Figure 12 is a driving timing diagram of another pixel circuit provided by the embodiment, referring to Figure 12 , alternatively, in a picture refresh period, the first scan signal S1 on the same first scan line includes a plurality of first pulse signals P1 after the data writing phase of the pixel circuit electrically connected to the same first scan line.

[0121] Alternatively, at least part of the time in the first period, there are first pulse signals P1 output to N first scan lines that overlap with each other, and at least part of the time in the second period, there are first pulse signals P1 output to M first scan lines that overlap with each other. It can be equivalent to the first scan circuit for simultaneously outputting the first pulse signals P1 to the N first scan lines in the first period and simultaneously outputting the first pulse signals P1 to the M first scan lines in the second period.

[0122] Alternatively, the first period is before the second period.

[0123] Figure 13 A schematic diagram of a display panel provided by an embodiment of the present application for displaying results in a first time period, Figure 14 A schematic diagram of a display panel provided by an embodiment of the present application for displaying results in a second time period, in combination with Figures 12-14 Optionally, in a picture refresh period, the width D1 of the first first pulse signal P1 of the first scan signal S1 on the same first scan line is less than or equal to the width D2 of the remaining first pulse signals P1. The width of the first first pulse signal P1 is less than the width of at least one of the remaining first pulse signals P1. The greater the width of the first pulse signal P1, the greater the number of rows of pixel circuits that the first pulse signal P1 corresponds to turn on, which is equivalent to the size of the first region 11, the second region 12, and the third region 13 in the column direction Y being greater. Such an arrangement can reduce the difference in the load of the first voltage line V1 in the first time period and the second time period (if the first pulse signal P1 is 3, and the widths of the first pulse signals P1 are equal, then the difference in the load of the first voltage line V1 in the first time period and the second time period is 1 / 3 of the load of the first voltage line V1 in the first time period, and if the width D1 of the first first pulse signal P1 is less than or equal to the width D2 of the remaining first pulse signals P1, and the widths D2 of the remaining first pulse signals P1 are equal, then the difference in the load of the first voltage line V1 in the first time period and the second time period is less than 1 / 3 of the load of the first voltage line V1 in the first time period), which is beneficial for improving the split-screen phenomenon, and / or better controlling the reset time of the anode of the light-emitting diode D1, and better matching the actual length of the blank phase.

[0124] Optionally, in a picture refresh period, the first pulse signal P1 on the same first scan line can be located in a write frame. In a picture refresh period, the first pulse signal P1 in the write frame can be multiple, for example, 2, 3, etc. For example, in a picture refresh period, the first pulse signal P1 on the same first scan line can be 2, so the present application can improve the two-split screen problem. For example, in a picture refresh period, the first pulse signal P1 on the same first scan line can be 3, so the present application can improve the three-split screen problem.

[0125] Continuing to refer to Figure 12Optionally, the first scan signal S1 on the same first scan line further comprises a second pulse signal P2 at a t0 stage (equivalent to an initialization stage) before a data writing stage (t2 stage) of the pixel circuit electrically connected to the same first scan line in a frame refresh period. The second pulse signal P2 can be used to reset the anode of the light emitting diode D1, and / or reset the gate of the driving transistor, and prepare for the reset of the source or drain. At the t0 stage, the first initialization module 130, the second initialization module 120, and the compensation module 160 are turned on to reset the control end G of the driving module 110 and the first end of the light emitting module 140, and reset the first end S or the second end D of the driving module 110. The data writing module 150, the third initialization module 190, the first light emitting control module 181, and the second light emitting control module 182 are turned off.

[0126] In combination Figure 5 Optionally, the first scan circuit 200 comprises a plurality of cascaded shift registers. In a low level of the TE signal, the shift registers of the first scan circuit 200 output the pulse signals of the first scan signal S1 in stages. The first time period is before the last shift register of the first scan circuit 200 outputs the first first pulse signal P1 to the corresponding first scan line G1; and the second time period is after the last shift register of the first scan circuit 200 outputs the first first pulse signal P1 to the corresponding first scan line G1.

[0127] Optionally, the time interval between the two adjacent first pulse signals P1 on the same first scan line is less than the time interval between the first first pulse signal P1 output by the first shift register and the first first pulse signal P1 output by the last shift register in the first scan circuit 200. The width of the first pulse signal P1 can be greater than the shift time interval between the first pulse signals P1 output by the two adjacent shift registers. Therefore, the greater the width of the first pulse signal P1, the more the shift registers in the first scan circuit 200 output the first first pulse signal P1 at the same time, and the more the rows of pixel circuits corresponding to the first first pulse signal P1. Similarly, it can be known that the rows of pixel circuits corresponding to other first pulse signals P1.

[0128] In the embodiment, the switching of the refresh frequency is generally based on the base frequency, and the one-frame refresh period of the base frequency includes a write frame, the active phase is located in the write frame, and at least part of the blank phase is located in the write frame. For example, when the refresh frequency is 120Hz, only the write frame is included, and no holding frame is included. The one-frame refresh period of the reduced refresh frequency (for example, less than 120Hz) includes a write frame and a holding frame, the active phase is located in the write frame, part of the blank phase is located in the write frame, and the holding frame is located in the blank phase. No data writing operation can be performed in the holding frame, that is, no data writing phase. Figure 15 FIG. 2 shows a driving timing diagram of another pixel circuit according to an embodiment of the present application. Figure 15 In the holding frame, the first scan signal S1 still outputs a pulse signal to reset the anode of the light-emitting diode D1.

[0129] In the embodiment, the frequencies of the second scan signal S2, the third scan signal S3, and the fourth scan signal S4 are equal to the refresh frequency, and the frequency of the first scan signal S1 is greater than the refresh frequency. For example, when the refresh frequency is 120Hz, the frequency of the first scan signal S1 can be 360Hz. By setting the frequency of the first scan signal S1 to be greater than the refresh frequency, the first electrode (anode) of the light-emitting diode D1 can be initialized in both the write frame and the holding frame, so as to improve the display effect.

[0130] Optionally, the embodiment of the present application further provides a driving method of a display device, which can be used to drive the display device provided in any of the above embodiments. Figure 16 FIG. 4 shows a flowchart of a driving method of a display device according to an embodiment of the present application. Figure 16 The driving method comprises the following steps.

[0131] In the first time period, a voltage is output to the first voltage line, and the pixel circuit of the corresponding row writes the voltage on the first voltage line into the pixel circuit in response to the pulse signal of the first scan signal on the first scan line.

[0132] In the second time period, a voltage different from that in the first time period is output to the first voltage line, and the pixel circuit of the corresponding row writes the voltage on the first voltage line into the pixel circuit in response to the pulse signal of the first scan signal on the first scan line.

[0133] The technical scheme provided by the embodiment of the present application outputs different voltages to the first voltage line in the first time period and the second time period within at least one picture refresh period, and the pixel circuit writes the voltage on the first voltage line into the pixel circuit in response to the pulse signal of the first scanning signal on the first scanning line. Since the voltage written by the first voltage line into the pixel circuit is different in the first time period and the second time period, the display unevenness caused by the difference in the in-plane load in different time periods can be improved, and the display effect is improved.

[0134] Optionally, the first voltage line is a first initialization signal line, used to provide a first initialization voltage to the light-emitting module, and the first time period is located in an effective stage of a picture refresh period, and the second time period is located in a blank stage.

[0135] The step S110 specifically comprises:

[0136] In the first time period, the voltage adjustment module outputs a first sub-voltage to the first voltage line, and the pixel circuit of the corresponding row writes the voltage on the first voltage line into the pixel circuit in response to the pulse signal of the first scanning signal on the first scanning line.

[0137] The step S120 specifically comprises:

[0138] In the second time period, the voltage adjustment module determines a current compensation amount according to the current refresh frequency and / or the current display brightness value of the display device and the corresponding relationship between the refresh frequency and / or the display brightness value and the compensation amount, and determines a second sub-voltage according to the current compensation amount and the first sub-voltage; outputs the second sub-voltage to the first voltage line, and controls the pixel circuit of the corresponding row to write the voltage on the first voltage line into the pixel circuit in response to the pulse signal of the first scanning signal on the first scanning line.

[0139] The driving method provided by the embodiment of the present application can be applied to the display device provided by any of the above embodiments, and therefore, the driving method also has the beneficial effects described in any of the above embodiments.

[0140] Optionally, at some time or all time in the first time period, there are pulse signals output to the N first scanning lines that overlap with each other. Optionally, in the first time period, the first scanning circuit simultaneously outputs pulse signals to the N first scanning lines.

[0141] Optionally, at some time or all time in the second time period, there are pulse signals output to the M first scanning lines that overlap with each other, and N and M are different positive integers. Optionally, in the second time period, the first scanning circuit simultaneously outputs pulse signals to the M first scanning lines, and N and M are different positive integers.

[0142] It should be understood that the various forms of flow shown above can be used to reorder, add, or remove steps. For example, the steps recited in the present application can be performed in parallel, in series, or in a different order, as long as the desired results of the technical solutions of the present application can be achieved, which are not limited herein.

[0143] The above detailed description does not constitute a limitation on the protection scope of the present application. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent replacements, and improvements made within the spirit and principles of the present application shall be included in the protection scope of the present application.

Claims

1. A display device, characterized in that, include: Multiple pixel circuits arranged in an array; A first scanning circuit and multiple first scanning lines, wherein the first scanning circuit is electrically connected to the pixel circuit of the corresponding row via the corresponding first scanning line; The first voltage line is electrically connected to the pixel circuit, and the pixel circuit is used to write the voltage on the first voltage line into the pixel circuit in response to the pulse signal of the first scan signal on the first scan line. Different voltages are output to the first voltage line during the first and second time periods within at least one screen refresh cycle; At least a portion of the time during the first time period, there are pulse signals output to N first scan lines that overlap with each other, and at least a portion of the time during the second time period, there are pulse signals output to M first scan lines that overlap with each other, where N and M are unequal positive integers.

2. The display device according to claim 1, characterized in that, A screen refresh cycle includes an active phase and a passive phase. The first time period is located within the effective phase, and the second time period is located within the blank phase.

3. The display device according to claim 2, characterized in that, The display device further includes a voltage adjustment module electrically connected to the first voltage line. The voltage adjustment module is used to output different voltages to the first voltage line during a first time period and a second time period within at least one screen refresh cycle.

4. The display device according to claim 3, characterized in that, The voltage adjustment module is used to output a constant voltage to the first voltage line during the effective phase; The voltage adjustment module is used to output a constant voltage to the first voltage line during the blanking phase; or, during the blanking phase, to output a voltage that varies in a stepwise manner with time to the first voltage line.

5. The display device according to claim 2, characterized in that, A screen refresh cycle includes a write frame, the active phase is within the write frame, and at least a portion of the blank phase is located within the write frame.

6. The display device according to claim 5, characterized in that, A screen refresh cycle also includes a hold frame, which is located within the blank phase.

7. The display device according to claim 1, characterized in that, N is greater than M, and the absolute value of the voltage output to the first voltage line in the first time period is greater than the absolute value of the voltage output to the first voltage line in the second time period.

8. The display device according to claim 1, characterized in that, Within a screen refresh cycle, the first scan signal on the same first scan line includes multiple pulse signals.

9. The display device according to claim 1, 7, or 8, characterized in that, The display device further includes multiple data lines and multiple second scan lines. The data lines are electrically connected to the pixel circuits of corresponding columns; the second scan lines are electrically connected to the pixel circuits of corresponding rows; the pixel circuits are used to write data voltages on the data lines into the pixel circuits in response to a second scan signal on the second scan line during the data writing phase. Within a screen refresh cycle, the first scan signal on the same first scan line includes a plurality of first pulse signals following the data writing phase of the pixel circuit electrically connected to the same first scan line. At least a portion of the first time period, the first pulse signals output to N first scan lines overlap with each other; at least a portion of the second time period, the first pulse signals output to M first scan lines overlap with each other. The first time period precedes the second time period.

10. The display device according to claim 9, characterized in that, Within a screen refresh cycle, the width of the first pulse signal of the first scan signal on the same first scan line is less than or equal to the width of the remaining first pulse signals; The width of the first pulse signal is less than the width of at least one of the remaining first pulse signals.

11. The display device according to claim 9, characterized in that, Within a screen refresh cycle, the first scan signal on the same first scan line also includes a second pulse signal prior to the data writing phase of the pixel circuit electrically connected to the same first scan line.

12. The display device according to claim 9, characterized in that, The first scanning circuit includes multiple cascaded shift registers. The first time period is before the last stage shift register of the first scanning circuit outputs the first first pulse signal to the first scan line corresponding to the electrical connection. The second time period is after the last stage shift register of the first scanning circuit outputs the first first pulse signal to the first scan line corresponding to the electrical connection.

13. The display device according to claim 1, characterized in that, The voltage output to the first voltage line during the first time period is the first sub-voltage, and the voltage output to the first voltage line during the second time period is the second sub-voltage. The display device further includes a voltage adjustment module, which is used to determine a current compensation amount based on the current refresh rate and / or current display brightness value of the display device, and the correspondence between the refresh rate and / or display brightness value and the compensation amount; and to determine a second sub-voltage based on the current compensation amount and the first sub-voltage.

14. The display device according to claim 13, characterized in that, The second sub-voltage is equal to the sum of the first sub-voltage and the current compensation amount.

15. The display device according to claim 13, characterized in that, The absolute value of the first sub-voltage is greater than the absolute value of the second sub-voltage.

16. The display device according to claim 15, characterized in that, The first sub-voltage and the second sub-voltage are negative.

17. The display device according to claim 1, characterized in that, The voltage output to the first voltage line during the second time period is the second sub-voltage, which includes multiple pulse signals with different amplitudes.

18. The display device according to claim 17, characterized in that, If the current refresh frequency is the first preset refresh frequency, the number of pulses of the second sub-voltage is P; If the current refresh frequency is the second preset refresh frequency, the number of pulses of the second sub-voltage is Q; Wherein, the first preset refresh frequency is greater than the second preset refresh frequency, P < Q, and P and Q are both integers greater than or equal to 1.

19. The display device according to claim 1, characterized in that, The first voltage line is the first initialization signal line. The pixel circuit includes a driving module, a light-emitting module, and a first initialization module. The driving module is connected between a first power line and a first end of the light-emitting module. The first scanning circuit is electrically connected to the control terminal of the first initialization module in the pixel circuit of the corresponding row via the corresponding first scanning line. The first initialization module is connected between the first end of the light-emitting module and the first initialization signal line. The first initialization module is used to transmit a first initialization voltage on the first initialization signal line to the first end of the light-emitting module in response to a pulse signal of a first scanning signal on the first scanning line.

20. The display device according to claim 19, characterized in that, The pixel circuit also includes a second initialization module; The display device further includes: a second initialization signal line, a second initialization module connected between the second initialization signal line and a first or second end of the driving module, a control terminal of the second initialization module electrically connected to the first scan line, and the second initialization module being used to transmit a second initialization voltage on the second initialization signal line to the first or second end of the driving module in response to a pulse signal of a first scan signal on the first scan line.

21. The display device according to claim 19, characterized in that, The pixel circuit also includes a first light-emitting control module and a second light-emitting control module. The display device further includes: multiple light-emitting control signal lines, which are respectively connected to the control terminals of the first light-emitting control module and the second light-emitting control module in the pixel circuit of the corresponding row. The first light-emitting control module is connected between the first power line and the first end of the driving module, and the second light-emitting control module is connected between the second end of the driving module and the first end of the light-emitting module.

22. The display device according to claim 19, characterized in that, The pixel circuit also includes a data writing module, a compensation module, a third initialization module, and a storage module; The display device further includes: Multiple second scan lines, each second scan line being connected to the control terminal of the data writing module in the pixel circuit of the corresponding row; A data line, wherein the data writing module is connected between the data line and the first end of the driving module, and the data writing module is used to transmit data voltage to the driving module in response to the second scan signal on the second scan line; Multiple third scan lines are provided, and the third scan lines are connected to the control terminal of the compensation module in the pixel circuit of the corresponding row. The compensation module is connected between the second terminal of the driving module and the control terminal. The compensation module is used to perform threshold compensation on the driving module in response to the third scan signal on the third scan line. Multiple fourth scan lines, wherein the fourth scan lines are connected to the control terminal of the third initialization module in the pixel circuit of the corresponding row; The third initialization signal line is connected between the third initialization signal line and the second terminal of the driving module. The third initialization module is used to respond to the fourth scan signal on the fourth scan line and transmit the third initialization voltage on the third initialization signal line to the control terminal of the driving module through the compensation module. The storage module is connected between the first power line and the control terminal of the drive module.

23. A driving method for a display device, characterized in that, The display device includes: Multiple pixel circuits arranged in an array; A first scanning circuit and multiple first scanning lines, wherein the first scanning circuit is electrically connected to the pixel circuit of the corresponding row via the corresponding first scanning line; The first voltage line is electrically connected to the pixel circuit. The driving method for the display device includes: During the first time period, a voltage is output to the first voltage line, and the pixel circuit of the corresponding row responds to the pulse signal of the first scan signal on the first scan line and writes the voltage on the first voltage line into the pixel circuit. In the second time period, a voltage different from that in the first time period is output to the first voltage line. The pixel circuit of the corresponding row responds to the pulse signal of the first scan signal on the first scan line and writes the voltage on the first voltage line into the pixel circuit. At least a portion of the first time period, there are pulse signals output to the N first scan lines that overlap with each other; At least a portion of the second time period, there are pulse signals output to M of the first scan lines that overlap with each other, where N and M are unequal positive integers.

24. The driving method for the display device according to claim 23, characterized in that, N is greater than M, and the absolute value of the voltage output to the first voltage line in the first time period is greater than the absolute value of the voltage output to the first voltage line in the second time period.

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