Memory device

Abstract

A memory device in which characteristics of a memory cell are improved is provided. The memory device of the first embodiment includes: a first conductive layer and a second conductive layer arranged apart from each other along a first direction intersecting a substrate; a first semiconductor film arranged apart from the first conductive layer along a second direction intersecting the first direction; a second semiconductor film arranged apart from the second conductive layer along the second direction; a first resistance variable film provided on an opposite side of the first conductive layer with respect to the first semiconductor film; a second resistance variable film provided on an opposite side of the second conductive layer with respect to the second semiconductor film; and a first conductive film having a first end connected to the first semiconductor film and the first resistance variable film and a second end connected to the second semiconductor film and the second resistance variable film.

Description

[0001] Reference to relevant applications

[0002] This application enjoys priority based on Japanese Patent Application No. 2022-044021 (filed on March 18, 2022). This application incorporates the entire contents of the basic application by reference to that basic application. Technical Field

[0003] The implementation involves memory devices. Background Technology

[0004] As a memory device capable of storing data non-volatilely, resistive variable memory (VRAM) is known. To achieve high integration and large capacity for memory devices like VRAM, three-dimensional memory structures are being researched. Summary of the Invention

[0005] The problem to be solved by the present invention is to provide a memory device that improves the characteristics of a memory cell. A memory device according to an embodiment includes a first conductive layer, a second conductive layer, a first semiconductor film, a second semiconductor film, a first resistance-changing film, a second resistance-changing film, and a first conductive film. The first conductive layer and the second conductive layer are arranged separately from each other along a first direction intersecting a substrate. The first semiconductor film and the first conductive layer are arranged separately from each other along a second direction intersecting the first direction. The second semiconductor film and the second conductive layer are arranged separately from each other along the second direction. The first resistance-changing film is disposed on the opposite side of the first conductive layer relative to the first semiconductor film. The second resistance-changing film is disposed on the opposite side of the second conductive layer relative to the second semiconductor film. The first conductive film has a first end in contact with the first semiconductor film and the first resistance-changing film, and a second end in contact with the second semiconductor film and the second resistance-changing film. Attached Figure Description

[0006] Figure 1 This is a block diagram illustrating an example of the configuration of a memory system including memory devices in an embodiment.

[0007] Figure 2 This is a circuit diagram illustrating an example of the configuration of a memory cell array of a memory device according to an embodiment.

[0008] Figure 3 This is a top view showing an example of the planar layout of a memory cell array of a memory device according to an embodiment.

[0009] Figure 4 This is an example of a cross-sectional structure of a memory cell array of a memory device according to an embodiment, along... Figure 3A cross-sectional view of line IV-IV.

[0010] Figure 5 This is an example of a cross-sectional structure of a memory cell in a memory device according to an embodiment, along... Figure 4 A cross-sectional view of the V-V line.

[0011] Figure 6 This is an example of a cross-sectional structure of a memory cell in a memory device according to an embodiment, along... Figure 4 A cross-sectional view of the VI-VI line.

[0012] Figure 7 This is an example of a cross-sectional structure of the selection transistor of a memory device illustrating an implementation method, along... Figure 4 A cross-sectional view of line VII-VII.

[0013] Figure 8 This is a timing diagram illustrating an example of a write operation in a memory device according to an implementation method.

[0014] Figure 9 This is a timing diagram illustrating an example of a read operation in a memory device according to an implementation method.

[0015] Figure 10 This is a cross-sectional view showing an example of the cross-sectional structure of a memory device during the manufacturing process of an embodiment.

[0016] Figure 11 This is a cross-sectional view showing an example of the cross-sectional structure of a memory device during the manufacturing process of an embodiment.

[0017] Figure 12 This is a cross-sectional view showing an example of the cross-sectional structure of a memory device during the manufacturing process of an embodiment.

[0018] Figure 13 This is a cross-sectional view showing an example of the cross-sectional structure of a memory device during the manufacturing process of an embodiment.

[0019] Figure 14 This is a cross-sectional view showing an example of the cross-sectional structure of a memory device during the manufacturing process of an embodiment.

[0020] Figure 15 This is a cross-sectional view showing an example of the cross-sectional structure of a memory device during the manufacturing process of an embodiment.

[0021] Figure 16 This is a cross-sectional view showing an example of the cross-sectional structure of a memory device during the manufacturing process of an embodiment.

[0022] Figure 17This is a cross-sectional view showing an example of the cross-sectional structure of a memory device during the manufacturing process of an embodiment.

[0023] Figure 18 This is a cross-sectional view showing an example of the cross-sectional structure of a memory device during the manufacturing process of an embodiment.

[0024] Figure 19 This is a cross-sectional view showing an example of the cross-sectional structure of a memory device during the manufacturing process of an embodiment.

[0025] Figure 20 This is a cross-sectional view showing an example of the cross-sectional structure of a memory device during the manufacturing process of an embodiment.

[0026] Figure 21 This is a cross-sectional view showing an example of the cross-sectional structure of a memory device during the manufacturing process of an embodiment.

[0027] Figure 22 This is a cross-sectional view showing an example of the cross-sectional structure of a memory device during the manufacturing process of an embodiment.

[0028] Figure 23 This is a cross-sectional view showing an example of the cross-sectional structure of a memory device during the manufacturing process of an embodiment.

[0029] Figure 24 This is a cross-sectional view showing an example of the cross-sectional structure of a memory device during the manufacturing process of an embodiment.

[0030] Figure 25 This is a cross-sectional view showing an example of the cross-sectional structure of a memory device during the manufacturing process of an embodiment. Detailed Implementation

[0031] The embodiments will now be described with reference to the accompanying drawings. The dimensions and scale of the drawings are not necessarily the same as those in reality.

[0032] Furthermore, in the following description, the same reference numerals are used to denote constituent elements that have substantially the same function and structure. Where elements with the same structure are specifically distinguished from each other, different text or numbers may be appended to the end of the same reference numerals.

[0033] 1. Implementation Method

[0034] 1.1 Composition

[0035] 1.1.1 Memory System

[0036] Figure 1This is a block diagram illustrating an example configuration of a memory system including a memory device according to an embodiment. Memory system 1 is a storage device configured as an external host device (not shown). Memory system 1 is, for example, an SD card. TM A memory card, or SSD (solid state drive). Memory system 1 includes a memory controller 2 and memory devices 3.

[0037] The memory controller 2 is constructed, for example, by an integrated circuit such as a system-on-a-chip (SoC). The memory controller 2 controls the memory device 3 based on requests from the host device. Specifically, for example, the memory controller 2 writes data requested to be written by the host device to the memory device 3. Furthermore, the memory controller 2 reads data requested to be read by the host device from the memory device 3 and sends it back to the host device.

[0038] Memory device 3 is a non-volatile memory. Memory device 3 is, for example, PCRAM (Phase Change Random Access Memory). Memory device 3 stores data non-volatilely.

[0039] The communication between the memory controller 2 and the memory device 3 is based on, for example, an SDR (single data rate) interface, a toggle DDR (double data rate) interface, or ONFI (Open NAND flash interface).

[0040] 1.1.2 Memory Devices

[0041] Continue, refer to Figure 1 The block diagram shown illustrates the internal structure of the memory device in the embodiment. The memory device 3 includes, for example, a memory cell array 10, an instruction register 11, an address register 12, a sequencer 13, a driver module 14, a line decoder module 15, and a sensor amplifier module 16.

[0042] The memory cell array 10 contains (n+1) blocks BLK0 to BLKn (n is an integer greater than or equal to 1). The memory cell array 10 may also contain only one block BLK. A block BLK is a collection of multiple memory cells. Memory cells store data non-volatilely. Furthermore, the memory cell array 10 includes multiple bit lines and multiple word lines. Each memory cell is associated with, for example, one bit line and one word line. A detailed description of the configuration of the memory cell array 10 will follow.

[0043] Instruction register 11 stores instructions (CMD) received by memory device 3 from memory controller 2. Instructions (CMD) may include commands that cause sequencer 13 to perform read, write, or erase operations.

[0044] Address register 12 stores address information ADD received by memory device 3 from memory controller 2. Address information ADD includes, for example, block address BAd, page address PAd, and column address CAd. For example, block address BAd, page address PAd, and column address CAd are used for selecting the block BLK, word line, and bit line, respectively.

[0045] The sequencer 13 controls the overall operation of the memory device 3. For example, based on the instruction CMD held in the instruction register 11, the sequencer 13 controls the driver module 14, the line decoder module 15, and the sensor amplifier module 16 to perform read and write operations.

[0046] The driver module 14 generates the voltage used in read and write operations, etc. Furthermore, the driver module 14 applies the generated voltage to the signal line corresponding to the selected word line, for example, based on the page address PAd stored in the address register 12.

[0047] The row decoder module 15 selects a block BLK within the corresponding memory cell array 10 based on the block address BAd stored in the address register 12. Furthermore, the row decoder module 15, for example, transmits the voltage applied to the signal line corresponding to the selected word line to the selected word line within the selected block BLK.

[0048] During the write operation, the sensor amplifier module 16 applies a desired voltage to each bit line based on the write data DAT received from the memory controller 2. Furthermore, during the read operation, the sensor amplifier module 16 determines the data stored in the memory cell based on the voltage of the bit line and transmits the determination result as read data DAT to the memory controller 2.

[0049] 1.1.3 Circuit Configuration of Memory Cell Array

[0050] Figure 2 This is a circuit diagram illustrating an example of the circuit configuration of a memory cell array included in a memory device according to an embodiment. Figure 2 The image shows one of the multiple block BLKs contained in the memory cell array 10. For example... Figure 2 As shown, block BLK contains, for example, four string units SU0 to SU3.

[0051] Each string unit SU contains multiple memory strings MS associated with bit lines BL0 to BLm (integers above m1). The number of bit lines BL can also be one. Each memory string MS, for example, contains memory cells MC0 to MC7 and a selection transistor STD. In each memory string MS, the selection transistor STD and the memory cells MC0 to MC7 are connected in series.

[0052] Specifically, the first terminal of the selector transistor STD is connected to the corresponding bit line BL. The second terminal of the selector transistor STD is connected to the first terminal of memory cell MC7. The second terminal of memory cell MC7 is connected to the first terminal of memory cell MC6. Similarly, for integers i between 1 and 6, the second terminal of memory cell MCI is connected to the first terminal of memory cell MC(i-1). The second terminal of memory cell MC0 is connected to the source line SL.

[0053] Each memory cell MC includes a switching element SW and a resistance changing element RC. The switching element SW and resistance changing element RC in the same memory cell MC are connected in parallel with respect to adjacent memory cells MC. That is, the first terminal of the switching element SW and the first terminal of the resistance changing element RC of memory cell MC7 are shared and connected to the second terminal of the selection transistor STD. The second terminal of the switching element SW and the second terminal of the resistance changing element RC of memory cell MC7 are shared and connected to the first terminal of the switching element SW and the first terminal of the resistance changing element RC of memory cell MC6, respectively. Similarly, for any integer i between 1 and 6, the second terminal of the switching element SW and the second terminal of the resistance changing element RC of memory cell MCI are shared and connected to the first terminal of the switching element SW and the first terminal of the resistance changing element RC of memory cell MC(i-1), respectively. The second terminal of the switching element SW and the second terminal of the resistance changing element RC of memory cell MC0 are shared and connected to the source line SL.

[0054] The resistance-changing element RC in this embodiment is a component that can reversibly transition between a low-resistance state and a high-resistance state through a change in its crystallization state. The resistance value of the resistance-changing element RC in its low-resistance state is, for example, more than 10 times (one bit) higher than the channel resistance value of the switching element SW in its on state. Therefore, in a memory cell MC, when the switching element SW in the memory cell MC is in the on state, almost no current flows through the resistance-changing element RC in the memory cell MC. On the other hand, the resistance value of the resistance-changing element RC in its high-resistance state is, for example, more than 10 times (one bit) lower than the channel resistance value of the switching element SW in its off state. Therefore, in a memory cell MC, when the switching element SW in the memory cell MC is in the off state, a meaningful current flows through the resistance-changing element RC in the memory cell MC. Hereinafter, the change in the crystallization state of the resistance-changing element RC is referred to as a "phase transition." The states where the resistance-changing element RC is in a low-resistance state and a high-resistance state are referred to as the "set state" and "reset state," respectively.

[0055] Within the same block BLK, the control terminals of the switching elements SW of memory cell MC0 to MC7 are connected to word lines WL0 to WL7, respectively. The control terminals of the selection transistors STD within serial cells SU0 to SU3 are connected to the selection gate lines SGD0 to SGD3, respectively.

[0056] Bit lines BL0 to BLm are each assigned a different column address. Each bit line BL is shared by a memory string MS that is assigned the same column address across multiple blocks BLK. Word lines WL0 to WL7 are configured for each block BLK. Source lines SL are shared, for example, across multiple blocks BLK.

[0057] A collection of multiple memory cells MC connected to a common word line WL within a single serial cell SU is called a single cell CU. For example, the storage capacity of a single cell CU containing memory cells MC that each store 1 bit of data is defined as "1 page of data". A single cell CU may have a storage capacity of more than 2 pages of data, depending on the number of bits of data stored in the memory cells MC.

[0058] Furthermore, the circuit configuration of the memory cell array 10 provided in the memory device 3 of the embodiment is not limited to the configuration described above. For example, the number of string cells SU included in each BLK can be designed to be any number. The number of memory cells MC and selection transistors STD included in each memory string MS can each be designed to be any number.

[0059] 1.1.4 Layout of Memory Cell Array

[0060] Next, an example of the layout of the memory cell array of the memory device according to the embodiment will be described.

[0061] Furthermore, in the accompanying drawings referred to below, the X direction corresponds to the extension direction of the word line WL. The Y direction corresponds to the extension direction of the bit line BL. The Z direction corresponds to the vertical direction relative to the surface of the semiconductor substrate used in the memory device 3. In the top view, shaded lines have been appropriately added for easier viewing of the drawings. The shaded lines added in the top view are not necessarily related to the raw materials or characteristics of the constituent elements to which the shaded lines are added. In the cross-sectional views, schematic diagrams of the components have been appropriately omitted for easier viewing of the drawings.

[0062] Figure 3 This is a top view showing an example of the planar layout of a memory cell array of a memory device according to an embodiment. Figure 3 The image shows a region containing a block BLK (i.e., string units SU0 to SU3). For example... Figure 3 As shown, the memory cell array 10 includes a stacked wiring structure LS, multiple memory pillars MP, multiple components SLT, multiple components SHE, multiple contacts CV, and multiple bit lines BL.

[0063] A stacked routing structure (LS) is a configuration in which multiple routing lines are separated and stacked along the Z-axis. The multiple routing lines within an LS include word lines WL0 to WL7 and a select gate line SGD. The LS is divided into multiple sections arranged along the Y-axis. Each section of the LS corresponds to a block BLK.

[0064] Multiple component SLTs each have a plate-like structure parallel to the XZ plane. The multiple component SLTs are arranged along the Y direction. Each component SLT extends along the X direction in the boundary region between adjacent blocks BLK. That is, each component SLT divides adjacent stacked wiring structures LS via itself.

[0065] Each component SLT includes a contact LI and a spacer SP. The contact LI is a conductive film extending in the XZ plane. The spacer SP is an insulating film disposed on the side of the contact LI. In other words, the contact LI is surrounded by the spacer SP when viewed from above.

[0066] Multiple SHE components each have a plate-like structure parallel to the XZ plane. These multiple SHE components are arranged along the Y direction. Figure 3 In this example, three components SHE are positioned between adjacent components SLT. Each component SHE extends along the X direction. Each component SHE, through which it divides the select gate line SGD in the adjacent stacked wiring configuration LS.

[0067] Multiple memory columns (MPs) function, for example, as a memory string (MS). The multiple memory columns (MPs) are arranged in an interleaved pattern of, for example, 19 columns in the region between two adjacent components (SLTs). Furthermore, for example, counting from the top of the paper, the memory column (MP) in the 5th column, the memory column (MP) in the 10th column, and the memory column (MP) in the 15th column each overlap with a component (SHE).

[0068] Multiple bit lines BL extend along the Y direction and are arranged along the X direction. Each bit line BL is configured to overlap with at least one memory column MP for each string cell SU. Figure 3 In the example, a memory cylinder MP is shown, which is configured to overlap with two bit lines BL. The memory cylinder MP and one of the multiple bit lines BL overlapping the memory cylinder MP are electrically connected via a contact CV.

[0069] The contact CV between the memory cylinder MP and the bit line BL that contact the component SHE is omitted. In other words, the contact CV between the memory cylinder MP and the bit line BL that are connected to two different select gate lines SGD is omitted.

[0070] Furthermore, the number and configuration of memory cylinders (MP) and components (SHE) between adjacent SLTs are not limited to the use of Figure 3 The configuration described can be modified as appropriate. The number of bit lines BL overlapping with each memory cylinder MP can be designed to be arbitrary.

[0071] 1.1.5 Cross-sectional structure of memory cell array

[0072] Figure 4 As an example of the cross-sectional construction of the memory cell array of the memory device of the embodiment, along... Figure 3 A cross-sectional view of line IV-IV. (See attached image.) Figure 4 As shown, the memory cell array 10 further includes a semiconductor substrate 20, conductive layers 21-24, and insulating layers 30-34. The insulating layers 30-34 include, for example, silicon oxide.

[0073] The semiconductor substrate 20 is, for example, a P-type semiconductor. An insulating layer 30 is provided on the upper surface of the semiconductor substrate 20. Circuitry (not shown) is provided on the semiconductor substrate 20 and the insulating layer 30. The circuitry provided on the semiconductor substrate 20 and the insulating layer 30 corresponds to the line decoder module 15, the sensor amplifier module 16, etc.

[0074] A conductive layer 21 is provided on the upper surface of the insulating layer 30. The conductive layer 21 is, for example, a plate-shaped conductor extending along the XY plane. The conductive layer 21 is used as the source line SL. The conductive layer 21 contains, for example, phosphorus-doped silicon. An insulating layer 31 is provided on the upper surface of the conductive layer 21.

[0075] On the upper surface of the insulating layer 31, conductive layers 22 and insulating layers 32 are alternately stacked. The conductive layer 22 is, for example, a plate-shaped conductor extending along the XY plane. The stacked conductive layers 22 are used as word lines WL0 to WL7 sequentially from the semiconductor substrate 20 side. The conductive layer 22 contains, for example, tungsten.

[0076] A conductive layer 23 is provided on the upper surface of the uppermost insulating layer 32. The conductive layer 23 is, for example, a plate-shaped conductor extending along the XY plane. The conductive layer 23 is used as the select gate line (SGD). The conductive layer 23 contains, for example, tungsten. An insulating layer 33 is provided on the upper surface of the conductive layer 23.

[0077] A conductive layer 24 is provided on the upper surface of the insulating layer 33. The conductive layer 24 is, for example, a linear conductor extending along the Y direction. The conductive layer 24 is used as a bit line BL. That is, in the area not shown, multiple conductive layers 24 are arranged along the X direction. The conductive layer 24 contains, for example, copper. An insulating layer 34 is provided on the upper surface of the conductive layer 24.

[0078] Multiple memory pillars (MPs) are arranged to penetrate insulating layers 31 and 32, and conductive layers 22 and 23. Each memory pillar (MP) extends along the Z-direction. The bottom of each memory pillar (MP) reaches conductive layer 21. The portion where a memory pillar (MP) intersects with a conductive layer 22 functions as a memory cell (MC). The portion where a memory pillar (MP) intersects with a conductive layer 23 functions as a select transistor (STD).

[0079] Each memory column MP includes, for example, a core film 40, a conductive film 41, a resistance-changing film 42, an insulating film 43, a semiconductor film 44, an insulating film 45, and a core film 46.

[0080] The core film 40 extends along the Z direction. The upper end of the core film 40 is located between the uppermost conductive layer 22 and conductive layer 23. The lower end of the core film 40 is located between the lowermost conductive layer 22 and conductive layer 21. The core film 40 may contain, for example, silicon nitride.

[0081] A core film 46 is disposed on the upper surface of the core film 40. The upper end of the core film 46 is located above the conductive layer 23. The core film 46 may contain, for example, silicon oxide.

[0082] The resistance-changing film 42 covers the portion of the core film 40 that intersects with the conductive layer 22. The resistance-changing film 42 is divided into multiple portions, each intersecting with a conductive layer 22. The upper surface of the portion of the resistance-changing film 42 located at the intersection with a conductive layer 22 is positioned below the upper surface of that conductive layer 22. The lower surface of the portion of the resistance-changing film 42 located at the intersection with a conductive layer 22 is positioned above the lower surface of that conductive layer 22. The resistance-changing film 42 is an alloy-type phase change material containing at least two elements selected from germanium (Ge), antimony (Sb), and tellurium (Te) as its main components. Furthermore, in addition to the aforementioned main components, the resistance-changing film 42 may also contain less than 10% of indium (In) or similar additive elements. The portion of the resistance-changing film 42 located at the intersection with a conductive layer 22 functions as a resistance-changing element RC for a memory cell MC located at the intersection with that conductive layer 22.

[0083] An insulating film 43 covers the sides of the resistance-changing film 42. The insulating film 43 is divided into multiple portions, each disposed at a location intersecting a conductive layer 22. The upper surface of the portion of the insulating film 43 disposed at a location intersecting a conductive layer 22 is located below the upper surface of that conductive layer 22. The lower surface of the portion of the insulating film 43 disposed at a location intersecting a conductive layer 22 is located above the lower surface of that conductive layer 22. The insulating film 43 comprises silicon oxide.

[0084] Semiconductor film 44, for example, comprises polycrystalline silicon. Semiconductor film 44 covers the sides of insulating film 43 and the sides of core film 46 at the portions intersecting with conductive layer 23. Semiconductor film 44 is separated into portions respectively disposed at the positions intersecting with a conductive layer 22 and at the positions intersecting with conductive layer 23.

[0085] The upper surface of the portion of the semiconductor film 44 located at the intersection with a conductive layer 22 is positioned below the upper surface of the conductive layer 22. The lower surface of the portion of the semiconductor film 44 located at the intersection with the conductive layer 22 is positioned above the lower surface of the conductive layer 22. The portion of the semiconductor film 44 located at the intersection with the conductive layer 22 functions as a channel for the switching element SW of the memory cell MC located at the intersection with the conductive layer 22.

[0086] The upper surface of the portion of the semiconductor film 44 located at the intersection with the conductor layer 23 is positioned below the upper surface of the conductor layer 23. The lower surface of the portion of the semiconductor film 44 located at the intersection with the conductor layer 23 is positioned above the lower surface of the conductor layer 23. The portion of the semiconductor film 44 located at the intersection with a conductor layer 23 functions as a channel for the selection transistor STD.

[0087] The conductive film 41 covers the portion of the side of the core film 46 not covered by the semiconductor film 44, the portion of the side of the core film 40 not covered by the resistance-changing film 42, and the metal film on the lower surface of the core film 40. The conductive film 41 may contain, for example, nickel silicide (NiSi) or nickel disilicide (NiSi2). The conductive film 41 is divided into a portion below the bottom conductive layer 22, a portion between two adjacent conductive layers 22, a portion between the top conductive layer 22 and the conductive layer 23, and a portion above the conductive layer 23.

[0088] The lower end of the portion of the conductive film 41 that is below the lowest conductive layer 22 is connected to the conductive layer 21. The upper end of the portion of the conductive film 41 that is below the lowest conductive layer 22 is connected to the lower ends of both the portion of the resistance-changing film 42 located at the intersection with the lowest conductive layer 22 and the portion of the semiconductor film 44. Thus, the upper end of the portion of the conductive film 41 that is below the lowest conductive layer 22 is Schottky-bonded to the lower end of the portion of the semiconductor film 44 located at the intersection with the lowest conductive layer 22.

[0089] The lower end of the portion between two adjacent conductive layers 22 in the conductive film 41 is connected to the upper end of both the portion of the resistance-changing film 42 located at the intersection with the lower conductive layer 22 and the portion of the semiconductor film 44. Thus, the lower end of the portion between two adjacent conductive layers 22 in the conductive film 41 is Schottky-bonded to the upper end of the portion of the semiconductor film 44 located at the intersection with the lower conductive layer 22. The upper end of the portion between two adjacent conductive layers 22 in the conductive film 41 is connected to the lower end of both the portion of the resistance-changing film 42 located at the intersection with the upper conductive layer 22. Thus, the upper end of the portion between two adjacent conductive layers 22 in the conductive film 41 is Schottky-bonded to the lower end of the portion of the semiconductor film 44 located at the intersection with the upper conductive layer 22.

[0090] The lower end of the portion between the uppermost conductive layer 22 and conductive layer 23 in the conductive film 41 is connected to the upper ends of both the portion of the resistance-changing film 42 located at the intersection with the uppermost conductive layer 22 and the portion of the semiconductor film 44. Thus, the lower end of the portion between the uppermost conductive layer 22 and conductive layer 23 in the conductive film 41 is Schottky-bonded to the upper end of the portion of the semiconductor film 44 located at the intersection with the uppermost conductive layer 22. The upper end of the portion between the uppermost conductive layer 22 and conductive layer 23 in the conductive film 41 is connected to the lower end of the portion of the semiconductor film 44 located at the intersection with the conductive layer 23. Thus, the upper end of the portion between the uppermost conductive layer 22 and conductive layer 23 in the conductive film 41 is Schottky-bonded to the lower end of the portion of the semiconductor film 44 located at the intersection with the conductive layer 23.

[0091] The lower end of the portion above the conductive layer 23 in the conductive film 41 is connected to the upper end of the portion of the semiconductor film 44 located at the position where it intersects with the conductive layer 23.

[0092] An insulating film 45 covers the semiconductor film 44 and the conductive film 41. The insulating film 45 is configured as a continuous film relative to a memory column MP. That is, the insulating film 45 has portions located between the semiconductor films 44 corresponding to the conductive layers 22 and 23, respectively. The insulating film 45 may contain, for example, silicon oxide, silicon oxynitride, or metal oxide. The insulating film 45 functions as the gate insulating film of the switching elements SW of each memory cell MC0 to MC7 and the selection transistor STD.

[0093] With the above configuration, the conductor layers 22 and 23, the conductor film 41, the semiconductor film 44, and the insulating film 45 enable the switching element SW and the selection transistor STD of the memory cells MC0 to MC7 to function as Schottky barrier transistors.

[0094] At the upper end of the portion of the conductive film 41 above the conductive layer 23, there is a columnar contact CV. The two contacts CV shown in the figure correspond to one of the two memory pillars MP in the cross-sectional area divided by components SLT and SHE, respectively. In addition, one of the three memory pillars MP shown in the figure that is not connected to a contact CV is connected to the corresponding contact CV in an area not shown.

[0095] On the upper surface of the contact CV, a conductive layer 24, i.e., a bit line BL, is provided. The conductive layer 24 is connected to a contact CV in the space divided by the components SLT and SHE. That is, the conductive layer 24 is electrically connected to the memory pillar MP located between adjacent components SLT and SHE, and to the memory pillar MP located between two adjacent components SHE.

[0096] Component SLT, for example, has a portion disposed along the XZ plane. Component SLT divides conductive layers 22 and 23. The upper end of component SLT is located above conductive layer 23. A portion of the upper end of contact LI within component SLT is in contact with insulating layer 33. The lower end of contact LI is in contact with conductive layer 21. Spacer SP is disposed between contact LI and conductive layers 22 and 23. That is, contact LI is separated from and insulated from conductive layers 22 and 23 by spacer SP. Contact LI can be used as part of source line SL.

[0097] Component SHE, for example, has a portion disposed along the XZ plane. Component SHE divides conductive layer 23. The upper end of component SHE is connected to insulating layer 33. The lower end of component SHE is connected to the uppermost insulating layer 32.

[0098] Next, use and refer to Figure 5 , Figure 6 as well as Figure 7 The cross-sectional structure of the memory cylinder MP along the XY plane is described.

[0099] Figure 5 as well as Figure 6 Each of the following is an example of a cross-sectional structure of a memory cell in a memory device representing an embodiment. Figure 4 Cross-sectional views of the V-V line and the VI-VI line. Figure 7 An example of the cross-sectional construction of the selection transistor of the memory device in an embodiment, along... Figure 4 A cross-sectional view of line VII-VII.

[0100] like Figure 5 As shown, a circular core film 40 is provided at the center of the memory pillar MP in the XY plane, which includes the conductive layer 22 and the resistance-changing film 42. The resistance-changing film 42 surrounds the side surface of the core film 40 in a concentric circle. The insulating film 43 surrounds the side surface of the resistance-changing film 42 in a concentric circle. The semiconductor film 44 surrounds the side surface of the insulating film 43 in a concentric circle. The insulating film 45 surrounds the side surface of the semiconductor film 44 in a concentric circle. Furthermore, the conductive layer 22 surrounds the side surface of the insulating film 45.

[0101] On the other hand, such as Figure 6As shown, a circular core film 40 is provided at the center of the memory pillar MP in the XY plane, which includes the conductive layer 22 and the conductive film 41. The conductive film 41 surrounds the side surfaces of the core film 40 in a concentric circle. The semiconductor film 44 surrounds the side surfaces of the conductive film 41 in a concentric circle. The insulating film 45 surrounds the side surfaces of the semiconductor film 44 in a concentric circle. Furthermore, the conductive layer 22 surrounds the side surfaces of the insulating film 45.

[0102] With the above configuration, the portion of the memory column MP that intersects with a conductive layer 22 can function as a resistance changing element RC and a switching element SW connected in parallel.

[0103] In addition, such as Figure 7 As shown, a circular core film 46 is provided at the center of the memory pillar MP in the XY plane containing the conductive layer 23. A semiconductor film 44 surrounds the side surface of the core film 46 in a concentric circle. An insulating film 45 surrounds the side surface of the semiconductor film 44 in a concentric circle. Furthermore, the conductive layer 23 surrounds the side surface of the insulating film 45.

[0104] With the configuration described above, the portion of the memory pillar MP that intersects with the conductor layer 23 can function as a select transistor STD.

[0105] 1.2 Actions

[0106] Next, the operation of the memory device in the embodiment will be explained. Furthermore, in the following description, there are instances where constituent elements related to the memory cell MC that are the object of the operation are labeled "selected," while constituent elements unrelated to the memory cell MC that are the object of the operation are labeled "non-selected," thus distinguishing between them.

[0107] 1.2.1 Write Action

[0108] Figure 8 This is a timing diagram illustrating an example of a write operation in a memory device according to an implementation method. Figure 8 The diagram illustrates an example of the time variation of the voltages applied to the select gate line SGD, word line WL, bit line BL, and source line SL when writing data to the memory cell MC.

[0109] like Figure 9As shown, up to time T10, the select gate line SGD, word line WL, bit line BL, and source line SL are all in the ready state. Specifically, in the ready state, voltage VSS is supplied to the select gate line SGD, bit line BL, and source line SL, and voltage VPP is supplied to the word line WL. Voltage VSS, for example, is 0V, which is the voltage that can turn off the switching element SW and the select transistor STD. Voltage VPP, for example, is higher than voltage VSS, which is the voltage that can turn on the switching element SW and the select transistor STD. Therefore, up to time T10, all select transistor STDs are in the off state, and all switching elements SW are in the on state.

[0110] At time T10, the row decoder module 15 applies voltages VPP and VSS to the selected selection gate line SGD and the non-selected selection gate line SGD, respectively. As a result, the selected selection transistor STD becomes on, and the non-selected selection transistor STD becomes off. Therefore, the memory string MS connected to the selection bit line BL is turned on (selected).

[0111] Furthermore, the line decoder module 15 applies voltages VSS and VPP to the select word line WL and the non-select word line WL, respectively. As a result, the switching elements SW of the select memory cell MC and the non-select memory cell MC in the select memory string MS become the off state and the on state, respectively.

[0112] The sensor amplifier module 16 applies a voltage VWRITE to the select bit line BL. This causes current to flow through the memory cells MC within the select memory string MS. Specifically, in the select memory cells MC of the select memory string MS, current flows through the resistance changing element RC, and in all the remaining non-select memory cells MC, current flows through the switching element SW. Furthermore, the voltage VWRITE is, for example, lower than the voltage VPP, a voltage that can melt the alloy within the resistance changing element RC. Therefore, a current based on the voltage VWRITE flows through the resistance changing element RC of the select memory cell MC, causing the temperature to rise and the alloy within the element to melt.

[0113] At time T20, the sensor amplifier module 16 changes the voltage of the selection bit line BL from VWRITE to VSS. Here, when the resistance changing element RC is switched to a high-resistance state (making it a reset state), the sensor amplifier module 16 rapidly decreases the voltage of the selection bit line BL. As a result, the resistance changing element RC of the selection memory cell MC becomes amorphous and switches to a high-resistance state. On the other hand, when the resistance changing element RC is switched to a low-resistance state (making it a set state), the sensor amplifier module 16 slowly decreases the voltage of the selection bit line BL compared to the reset state. As a result, the resistance changing element RC of the selection memory cell MC becomes crystalline and switches to a low-resistance state.

[0114] At time T30, the line decoder module 15 and the sensor amplifier module 16 will select the gate line SGD, word line WL, bit line BL and source line SL and return them to the ready state respectively.

[0115] The above steps complete the data writing operation to the selected memory unit MC.

[0116] 1.3.2 Reading Action

[0117] Figure 9 This is a timing diagram illustrating an example of a read operation in a memory device according to an implementation method. Figure 9 The diagram illustrates an example of the time variation of the voltages applied to the select gate line SGD, word line WL, bit line BL, and source line SL when data is read from the memory cell MC.

[0118] like Figure 9 As shown, until time T50, the gate line SGD, word line WL, bit line BL, and source line SL are in the ready state.

[0119] At time T50, the line decoder module 15 applies voltages VPP and VSS to the selected selection gate line SGD and the non-selected selection gate line SGD, respectively. As a result, the selected selection transistor STD becomes on, and the non-selected selection transistor STD becomes off. Therefore, the memory string MS connected to the selection bit line BL is selected.

[0120] Furthermore, the line decoder module 15 applies voltages VSS and VPP to the select word line WL and the non-select word line WL, respectively. As a result, the switching elements SW of the select memory cell MC and the non-select memory cell MC in the select memory string MS become off and on, respectively.

[0121] The sensor amplifier module 16 applies a voltage VREAD to the select bit line BL. This causes current to flow through the memory cells MC within the select memory string MS. Specifically, in the select memory cells MC of the select memory string MS, current flows through the resistance changing element RC, and in all the remaining non-select memory cells MC, current flows through the switching element SW. Furthermore, the voltage VREAD is, for example, lower than the voltage VPP, and is a voltage sufficient to allow a sufficiently large current to flow through the resistance changing element RC within a range that prevents the alloy within the resistance changing element RC from melting.

[0122] At time T60, the sensor amplifier module 16 stops driving the selection bit line BL. When the resistance changing element RC of the selection memory cell MC is in a high-resistance state (i.e., reset state), the current flowing through the selection memory cell MC becomes relatively small. Therefore, after a predetermined time has elapsed from time T60, the voltage of the selection bit line BL hardly changes from the voltage VREAD. On the other hand, when the resistance changing element RC of the selection memory cell MC is in a low-resistance state (i.e., set state), the current flowing through the selection memory cell MC becomes relatively large. Therefore, after a predetermined time has elapsed from time T60, the voltage of the selection bit line BL significantly decreases from the voltage VREAD.

[0123] The sensor amplifier module 16 senses the different voltage changes on the selection bit line BL caused by the different resistance states of the resistance element RC in the selection memory unit MC. Therefore, the data stored in the selection memory unit MC can be read.

[0124] At time T70, if the sensor amplifier module 16 confirms that data has been read from the selection memory cell MC, it supplies voltage VSS to the selection bit line BL.

[0125] At time T80, the line decoder module 15 and the sensor amplifier module 16 will select the gate line SGD, word line WL, bit line BL and source line SL and return them to the ready state respectively.

[0126] The above steps complete the data reading operation from the selected memory unit MC.

[0127] 1.3 Manufacturing Method of Memory Cell Array

[0128] Figures 10-25 These are cross-sectional views illustrating an example of the cross-sectional structure during the manufacturing process of the memory device according to the embodiments. The illustrated cross-sectional structure shows a configuration similar to... Figure 4 The corresponding region. The following is an example of the manufacturing process of the memory cell array 10 in the memory device 3.

[0129] First, such as Figure 10 As shown, an insulating layer 30 is formed on the upper surface of the semiconductor substrate 20. Conductive layer 21 and insulating layer 31 are stacked in this order on the upper surface of insulating layer 30. Sacrificial layer 51 and insulating layer 32 are alternately stacked on the upper surface of insulating layer 31. Sacrificial layer 52 and insulating layer 33 are stacked in this order on the uppermost insulating layer 32. Thus, a stacked structure including sacrificial layers 51 and 52 is formed. The upper surface of the stacked structure is planarized, for example, by CMP (Chemical Mechanical Polishing). Sacrificial layers 51 and 52, for example, comprise silicon nitride.

[0130] Next, as Figure 11 As shown, a mask with openings corresponding to the memory pillar MP is formed using photolithography or similar methods. Furthermore, multiple holes H1 are formed by anisotropic etching of this mask, penetrating the insulating layers 31-33 and the sacrificial layers 51 and 52. At the bottom of each hole H1, a portion of the conductive layer 21 is exposed.

[0131] Next, as Figure 12 As shown, for example, by wet etching, the sacrificial layers 51 and 52 exposed on the sides of each hole H1 are recessed. Thus, in each hole H1, a recess is formed at the height at which the sacrificial layers 51 and 52 are formed.

[0132] Next, as Figure 13 As shown, an insulating film 45 and a protective film 53 are formed in each hole H1. The protective film 53 contains, for example, silicon nitride. In this process, the insulating film 45 and the protective film 53 are formed, for example, using ALD (Atomic Layer Deposition) or CVD (Chemical Vapor Deposition).

[0133] Next, as Figure 14 As shown, the protective film 53 formed on the bottom surface of each hole H1 is removed by anisotropic etching. This exposes a portion of the insulating film 45 on the bottom surface of each hole H1. In the anisotropic etching of the protective film 53 in this process, for example, RIE (Reactive Ion Etching) is used. Then, for example, a portion of the insulating film 45 exposed on the bottom surface of each hole H1 is selectively removed by wet etching. This exposes a portion of the conductive layer 21 on the bottom surface of each hole H1. After removing the insulating film 45 on the bottom surface of each hole H1, the protective film 53 is removed.

[0134] Next, as Figure 15As shown, a semiconductor film 44 is formed as a continuous film in each hole H1. The semiconductor film 44 may also contain 1E19cm －3 Impurities such as phosphorus (P) and boron (B) are present, but undoped silicon (Si) is preferred. During the formation of the semiconductor film 44, the depressions (hereinafter referred to as "depressions") at the heights where the sacrificial layers 51 and 52 are formed are not completely filled. Therefore, after the formation of the semiconductor film 44, depressions exist at the heights where the sacrificial layers 51 and 52 are formed in each hole H1.

[0135] Next, as Figure 16 As shown, an insulating film 43 is formed as a continuous film in each hole H1. During the formation of the insulating film 43, the depressions in each hole H1 are filled by the insulating film 43. In the formation of the insulating film 43 in this process, for example, ALD (Atomic Layer Deposition) is used.

[0136] Next, as Figure 17 As shown, a portion of the insulating film 43 in each hole H1 is removed. Thus, in each hole H1, the portion of the insulating film 43 formed in the recess is removed. Furthermore, by removing a portion of the insulating film 43, a recess is formed again at the height of the sacrificial layers 51 and 52 within each hole H1.

[0137] Next, as Figure 18 As shown, a conductive film 41 is formed by silicideling a portion of the semiconductor film 44 in each hole H1. Specifically, for example, nickel is supplied to the holes H1 by CVD, thereby silicideling the semiconductor film 44 from the exposed surface. Thus, the conductive film 41 divides the semiconductor film 44 into portions between the sacrificial layer 51 and the insulating film 43, and between the sacrificial layer 52 and the insulating film 43. Furthermore, in the layers formed by the sacrificial layers 51 and 52, the conductive film 41 is preferably grown on the side of the sacrificial layer 51 and the side of the sacrificial layer 52, compared to the insulating film 43. This improves the characteristics of the Schottky barrier transistor as a switching element SW.

[0138] Next, as Figure 19 As shown, a resistance-changing film 42 is formed in each hole H1 as a continuous film. During the formation of the resistance-changing film 42, the depressions in each hole H1 are filled by the resistance-changing film 42.

[0139] Next, as Figure 20As shown, a portion of the resistance-changing film 42 in each hole H1 is removed. Thus, in each hole H1, the portion of the resistance-changing film 42 formed in the depression is removed. However, the depression within each hole H1 remains filled with the resistance-changing film 42. In this way, by dividing the resistance-changing film 42 according to the layers formed by each sacrificial layer 51 and 52, the thermal retention characteristics of the resistance-changing film 42 are improved. Therefore, memory cell driving can be achieved with less write current, i.e., lower power consumption. Afterwards, the die film 40 is filled in each hole H1.

[0140] Next, as Figure 21 As shown, a mask with openings corresponding to the component SLT is formed using photolithography or similar methods. Then, anisotropic etching is performed on this mask to form, for example, slits H2 penetrating the insulating layers 31-33 and the sacrificial layers 51 and 52. Thus, the stacked structure is divided into blocks (BLK). In the anisotropic etching process of this step, for example, a re-etching process (RIE) is used.

[0141] Next, sacrificial layers 51 and 52 are selectively removed via slit H2 by wet etching based on thermal phosphoric acid, etc. The stacked structure with sacrificial layers 51 and 52 removed is maintained by filling multiple holes H1. Then, a conductor is filled into the space where sacrificial layers 51 and 52 have been removed via slit H2. In the formation of the conductor in this process, for example, CVD is used.

[0142] Subsequently, the conductors formed inside the slit H2 are removed by etching, and the conductors formed in adjacent wiring layers are separated. This forms multiple conductor layers 22 that function as word lines WL0 to WL7, and a conductor layer 23 that functions as the select gate line SGD. Furthermore, the conductor layers 22 and 23 formed in this process may also contain a barrier metal. In this case, during the formation of the conductors after the removal of sacrificial layers 51 and 52, for example, tungsten is formed after titanium nitride is used as a barrier metal. This forms the multilayer wiring structure LS.

[0143] Next, as Figure 22 As shown, the insulating portion (spacer SP) is formed to cover the side and bottom surfaces of the slit H2. Furthermore, a portion of the spacer SP located at the bottom of the slit H2 is removed, exposing a portion of the conductive layer 21 at the bottom of the slit H2. Then, a conductor (contact LI) is formed within the slit H2, and the conductor formed outside the slit H2 is removed, for example, by CMP.

[0144] Next, as Figure 23As shown, a portion of the core film 40 is removed by an etching process to form a hole H3. The bottom of the hole H3 is located between the conductive layer 23 and the uppermost conductive layer 22. Furthermore, the semiconductor film 44 is exposed in the layer on the side of the hole H3 where the conductive layer 23 is formed.

[0145] Next, as Figure 24 As shown, the core film 46 is embedded in the hole H3. Thus, the memory column MP is formed.

[0146] Next, as Figure 25 As shown, a component SHE is formed by dividing the conductor layer 23 in the stacked wiring structure LS into multiple parts.

[0147] The above-described manufacturing process forms the stacked wiring structure LS of the memory cell array 10. Furthermore, the manufacturing process described above is merely an example and is not limited to it. For example, other processes may be inserted between the manufacturing processes, or some processes may be omitted or unified. Moreover, the manufacturing processes may be replaced to the extent possible.

[0148] 1.4 Effects of the Implementation Method

[0149] According to the embodiment, memory cells MC0 to MC7 are formed as memory pillars MP and are connected in series along the Z direction. This allows for the three-dimensional stacking of memory cells MC. Therefore, the integration density of the memory cell array 10 can be increased.

[0150] Furthermore, the semiconductor film 44 and the corresponding conductive layer 22 are arranged separately in the XY plane. The resistance-changing film 42 is disposed on the opposite side of the conductive layer 22 relative to the semiconductor film 44. The conductive film 41 has an upper end that is connected to the semiconductor film 44 and the resistance-changing film 42 of the upper memory cell MC, and a lower end that is connected to the semiconductor film 44 and the resistance-changing film 42 of the lower memory cell MC. Thus, the switching element SW and the resistance-changing element RC of a certain memory cell MC can be connected in parallel with respect to other memory cells MC. Therefore, when the switching element SW is in the on state, the corresponding resistance-changing element RC can be deselected. Furthermore, when the switching element SW is in the off state, the corresponding resistance-changing element RC can be selected.

[0151] Furthermore, the multiple resistance-changing elements RC corresponding to the multiple memory cells MC arranged along the Z direction are formed in a mutually separate manner. Thus, the multiple resistance-changing elements RC within the same memory string MS are physically separated from each other. Therefore, during write and read operations, the influence of interference from adjacent memory cells MC can be reduced. Consequently, the characteristics of the memory cells can be improved.

[0152] Furthermore, the conductive film 41 is formed by silicideting a portion of the semiconductor film 44. Thus, the conductive film 41 becomes a metal film containing nickel silicide or nickel disilicide. Therefore, the junction between the conductive film 41 and the semiconductor film 44 can be a Schottky junction. Consequently, the switching element SW can function as a Schottky barrier transistor.

[0153] Furthermore, the semiconductor film 44 and the resistance-changing film 42 are concentrically disposed within the hole H1. The semiconductor film 44 is formed relative to the central axis of the hole H1 at a location further outward than the resistance-changing film 42. This allows the channel width of the switching element SW to be longer than the width of the resistance-changing element RC. Therefore, compared to the case where the channel width of the switching element SW is equal to the width of the resistance-changing element RC, the resistance value of the switching element SW when it is in the on state can be reduced. Consequently, compared to the case where the channel width of the switching element SW is equal to the width of the resistance-changing element RC, the current flowing through the select memory cell MC can be increased.

[0154] 2. Variations, etc.

[0155] Furthermore, while the above embodiments describe the source lines SL as being formed in a flat plate shape, the implementation is not limited to this. For example, the source lines SL may also be formed as multiple lines intersecting with the bit lines BL. Specifically, when the multiple bit lines BL are arranged along the X direction, the multiple source lines SL are arranged, for example, along the Y direction. Furthermore, the multiple source lines SL extend along the X direction respectively.

[0156] Furthermore, the above embodiments have been described using PCRAM, which stores data using a resistance-changing element whose resistance value changes due to a phase change of the element, as an example, but are not limited to this. For example, resistance-changing type memories, such as iPCRAM (Interfacial phase change random access memory) and ReRAM (Resistive Random Access Memory), can also be applied, using resistance-changing elements based on a different principle than PCRAM.

[0157] Several embodiments of the present invention have been described, but these embodiments are merely illustrative and are not intended to limit the scope of the invention. These embodiments can be implemented in various other ways, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments, and their variations, are included within the scope of the invention as defined in the claims and their equivalents, just as the scope and spirit of the invention are.

[0158] Explanation of reference numerals in the attached figures

[0159] 1…Memory system, 2…Memory controller, 3…Memory device, 10…Memory cell array, 11…Instruction register, 12…Address register, 13…Sequencer, 14…Driver module, 15…Line decoder module, 16…Sensor amplifier module, 20…Semiconductor substrate, 21, 22, 23, 24…Conductive layers, 30, 31, 32, 33, 34…Insulator layers, 40, 46…Core film, 41…Conductive film, 42…Resistivity change film, 43, 45…Insulator film, 44…Semiconductor film, 51, 52…Sacrificial layer, 53…Protective film

Claims

1. A memory device, characterized in that, have: The first conductive layer and the second conductive layer are arranged separately from each other along a first direction that intersects with the substrate; The first semiconductor film is arranged separately from the first conductor layer along a second direction that intersects the first direction; The second semiconductor film is arranged separately from the second conductor layer along the second direction; The first resistance-changing film is disposed on the opposite side of the first conductor layer, relative to the first semiconductor film; The second resistance-changing film is disposed on the opposite side of the second conductor layer relative to the second semiconductor film; as well as The first conductive film has a first end connected to the first semiconductor film and the first resistance-changing film, and a second end connected to the second semiconductor film and the second resistance-changing film.

2. The memory device according to claim 1, characterized in that, The first conductive film comprises nickel silicide or nickel disilicide. The first semiconductor film and the second semiconductor film comprise silicon.

3. The memory device according to claim 1, characterized in that, It also includes an insulating film disposed between the first conductive layer and the first semiconductor film, and between the second conductive layer and the second semiconductor film.

4. The memory device according to claim 1, characterized in that, Viewed along the first direction, the first resistance-changing film, the first semiconductor film, and the first conductive film are arranged in a concentric circle.

5. The memory device according to claim 1, characterized in that, The first end of the first conductive film is aligned with the first resistance-changing film along the first direction, and with the first semiconductor film along the second direction. The second end of the first conductive film is aligned with the second resistance-changing film along the first direction, and with the second semiconductor film along the second direction.

6. The memory device according to claim 1, characterized in that, The first end of the first conductive film intersects with the first conductive layer. The second end of the first conductive film intersects with the second conductive layer.

7. The memory device according to claim 1, characterized in that, The first semiconductor film and the second semiconductor film are arranged separately from each other along the first direction.

8. The memory device according to claim 1, characterized in that, The first resistance-changing film and the second resistance-changing film are arranged separately from each other along the first direction.

9. The memory device according to claim 1, characterized in that, The first conductive layer is located on the substrate side closer to the second conductive layer. The memory device also includes: The third conductor layer is arranged separately from the first conductor layer along the first direction on the substrate side, which is closer to the first conductor layer than the first conductor layer. as well as The second conductive film has a first end connected to the first semiconductor film and the first resistance change film, and a second end connected to the third conductive layer.

10. The memory device according to claim 1, characterized in that, The first conductive layer is located on the substrate side closer to the second conductive layer. The memory device also includes: The fourth conductor layer is arranged separately from the second conductor layer along the first direction on the opposite side of the substrate compared to the second conductor layer; The third semiconductor film is arranged separately from the fourth conductor layer along the second direction; as well as The third conductive film has a first end connected to the second semiconductor film and the second resistance change film, and a second end connected to the third semiconductor film.

11. The memory device according to claim 1, characterized in that, It also includes a control circuit, which is configured as follows: In the action of changing the resistance value of the second resistance-changing film, A first voltage is applied to the first conductive layer. A second voltage lower than the first voltage is applied to the second conductive layer. Current flows selectively through the first semiconductor film and the first resistance-changing film via the first conductive film, and current flows selectively through the second resistance-changing film and the second resistance-changing film.

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