A phase-locked loop frequency calibration apparatus and method
By combining phase-locked loop (PLL) closed-loop locking with VCO linear tuning, and utilizing phase detection signals and counters to optimize PLL frequency calibration, the problems of large errors and long calibration times are solved, achieving more accurate and efficient calibration.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- PINGJIE ELECTRONIC TECHNOLOGY (JIANGSU) CO LTD
- Filing Date
- 2023-02-22
- Publication Date
- 2026-07-03
AI Technical Summary
The existing technology for frequency calibration of phase-locked loops suffers from large errors and excessively long calibration times.
A method combining phase-locked loop (PLL) closed-loop locking and VCO linear tuning is adopted. The calibration time is adjusted using phase detection signals, and the initial calibration value is set through a process detector. The calibration word is determined by a counter and a comparator, thus optimizing the calibration process.
This reduces the error in the phase-locked loop frequency calibration process and shortens the calibration time.
Smart Images
Figure CN116800257B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of phase-locked loop (PLL) frequency calibration, and in particular to a PLL frequency calibration device and method. Background Technology
[0002] Open-loop calibration is based on counting the output of the voltage-controlled oscillator (VCO) after frequency division, and then comparing it with the target count value for calibration. The counting error directly affects the calibration result.
[0003] Open-loop calibration often requires separate bias design to provide the VCO with the appropriate control voltage during the calibration process. However, some closed-loop calibrations have fixed waiting times at each step, resulting in excessively long total calibration times.
[0004] Therefore, to address the problems of large errors and excessively long calibration times in the existing phase-locked loop frequency calibration process, there is an urgent need to provide a new calibration device or method. Summary of the Invention
[0005] The purpose of this invention is to provide a phase-locked loop (PLL) frequency calibration device and method, which can reduce the error caused by the PLL frequency calibration process and reduce the calibration time.
[0006] To achieve the above objectives, the present invention provides the following solution:
[0007] A phase-locked loop frequency calibration device includes: a phase-locked loop, an automatic frequency calibrator, a process detector, a counter, a comparator, and a lock detection circuit;
[0008] The process detector is connected to the automatic frequency calibrator; the automatic frequency calibrator is connected to the counter, the phase-locked loop, and the comparator; the counter is connected to the lock detection circuit; the lock detection circuit is connected to the phase-locked loop; and the phase-locked loop is connected to the comparator.
[0009] The process detector is used to send the initial value of the frequency control word to the automatic frequency calibrator; the automatic frequency calibrator sends reset1 = 1 to the counter according to the initial value of the frequency control word;
[0010] The phase-locked loop begins locking based on the initial value of the frequency control word;
[0011] The lock detection circuit detects the phase detection signal output by the phase-locked loop after locking, and outputs Lock_Done = 1 when the phase detection signal no longer changes; the counter performs an AND operation between reset1 and Lock_Done, resets, and starts counting.
[0012] The automatic frequency calibrator is also used to determine the calibration word based on the counter's readback indication and the Fast and Slow signals determined by the comparator based on the output voltage of the phase-locked loop after counting a set time.
[0013] Optionally, the phase-locked loop includes: an oscillator, a loop filter, a charge pump, a differential integral modulator, a multimode frequency divider, and a frequency and phase detector;
[0014] The output terminals of the oscillator and the differential-integral modulator are both connected to the input terminal of the multimode divider; the output terminals of the multimode divider and the crystal oscillator are both connected to the input terminal of the frequency and phase detector; the output terminal of the frequency and phase detector is connected to the input terminal of the charge pump; the output terminal of the charge pump is connected to the input terminal of the loop filter; and the output terminal of the loop filter is connected to the input terminals of the comparator and the oscillator.
[0015] Optionally, the oscillator is a current-starved ring oscillator.
[0016] Optionally, the load of the oscillator is a switched capacitor array using thermometer codes.
[0017] A phase-locked loop (PLL) frequency calibration method is provided for implementing the aforementioned PLL frequency calibration device. The calibration method includes:
[0018] The process detector sends the initial value of the frequency control word to the automatic frequency calibrator;
[0019] The automatic frequency calibrator sends reset1=1 to the counter based on the initial value of the frequency control word, at which point the counter has not started counting;
[0020] The phase-locked loop (PLL) begins locking based on the initial value of the frequency control word.
[0021] The lock detection circuit detects the phase detection signal output by the phase-locked loop after locking, and outputs Lock_Done = 1 when the phase detection signal no longer changes;
[0022] The counter performs an AND operation between reset1 and Lock_Done, resets itself, and begins counting.
[0023] After the automatic frequency calibrator counts for a set time, it determines the calibration word based on the counter's readback indication and the Fast and Slow signals determined by the comparator based on the output voltage of the phase-locked loop. It then replaces the initial value of the frequency control word with the calibration word and returns to the automatic frequency calibrator, which sends reset1=1 to the counter based on the initial value of the frequency control word. At this point, the counter has not started counting.
[0024] A storage medium storing computer program instructions thereon, characterized in that the method is implemented when the computer program instructions are executed by a processor.
[0025] An electronic device includes a memory and a processor, the memory storing a computer program and the processor running the computer program to cause the electronic device to perform the method according to the method.
[0026] According to specific embodiments provided by the present invention, the present invention discloses the following technical effects:
[0027] This invention provides a phase-locked loop (PLL) frequency calibration device and method, which utilizes a combination of PLL closed-loop locking and linear tuning of the VCO oscillator within the PLL to reduce calibration error; and uses the phase detection status signal during the locking process to adjust the calibration time. This invention reduces the error caused by the PLL frequency calibration process and minimizes the calibration time. Attached Figure Description
[0028] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0029] Figure 1 This is a schematic diagram of a phase-locked loop frequency calibration device provided by the present invention.
[0030] Figure 2 This is a schematic diagram of the phase-locked loop frequency calibration scheme. Detailed Implementation
[0031] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.
[0032] The purpose of this invention is to provide a phase-locked loop (PLL) frequency calibration device and method, which can reduce the error caused by the PLL frequency calibration process and reduce the calibration time.
[0033] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.
[0034] like Figure 1 and Figure 2 As shown, the phase-locked loop frequency calibration device provided by the present invention includes: a phase-locked loop, an automatic frequency calibrator, a process detector, a counter, a comparator, and a lock detection circuit.
[0035] The process detector is connected to the automatic frequency calibrator; the automatic frequency calibrator is connected to the counter, the phase-locked loop, and the comparator; the counter is connected to the lock detection circuit; the lock detection circuit is connected to the phase-locked loop; and the phase-locked loop is connected to the comparator.
[0036] The process detector is used to send the initial value of the frequency control word to the automatic frequency calibrator; the automatic frequency calibrator sends reset1 = 1 to the counter according to the initial value of the frequency control word;
[0037] The phase-locked loop begins locking based on the initial value of the frequency control word;
[0038] The lock detection circuit detects the phase detection signal output by the phase-locked loop after locking, and outputs Lock_Done = 1 when the phase detection signal no longer changes; the counter performs an AND operation between reset1 and Lock_Done, resets, and starts counting.
[0039] The automatic frequency calibrator is also used to determine the calibration word based on the counter's readback indication and the Fast and Slow signals determined by the comparator based on the output voltage of the phase-locked loop after counting a set time.
[0040] The phase-locked loop includes: an oscillator, a loop filter, a charge pump, a differential integral modulator, a multi-mode frequency divider, and a frequency and phase detector;
[0041] The output terminals of the oscillator and the differential-integral modulator are both connected to the input terminal of the multimode divider; the output terminals of the multimode divider and the crystal oscillator are both connected to the input terminal of the frequency and phase detector; the output terminal of the frequency and phase detector is connected to the input terminal of the charge pump; the output terminal of the charge pump is connected to the input terminal of the loop filter; and the output terminal of the loop filter is connected to the input terminals of the comparator and the oscillator.
[0042] The RC values of the LPF are all relative to the power supply, Vctrl is inversely proportional to the input phase difference, and Fvco is inversely proportional to Vctrl. The PLL locks to different control voltages under different frequency control words. By comparing and detecting the range of the output control voltage, it can be determined whether the control word is optimal. In most cases, it is desirable to be located near the midpoint between the VCO transfer curve and the charge pump linear range. This range can be set by setting the thresholds of two comparators. Finding the VCO control words corresponding to VH and VL corresponds to the fastest and slowest frequency control words, respectively. Calculating these two control words yields the VCO control word at the target control voltage, i.e., the calibration result. For example, one can directly calculate the average of the two critical control words and choose to round up or down based on the actual simulation results of the VCO.
[0043] To ensure that the calibration word obtained from the calculation locks the phase-locked loop at the expected control voltage as much as possible, it is necessary to ensure that Fvco changes as linearly as possible with the control word. The oscillator is a current-starved ring oscillator.
[0044] The current value of each stage is relatively constant, and the load uses a switched capacitor array with thermometer code, so Fvco changes linearly with the control word.
[0045] The process detector is used to set the initial value of the control word for each calibration, thereby reducing the number of searches.
[0046] As a specific embodiment, the present invention also provides a phase-locked loop (PLL) frequency calibration method for implementing the aforementioned PLL frequency calibration device, characterized in that the calibration method includes:
[0047] S1. The process detector sends the initial value of the frequency control word to the automatic frequency calibrator;
[0048] S2. The automatic frequency calibrator sends reset1=1 to the counter based on the initial value of the frequency control word. At this time, the counter has not started counting.
[0049] S3. The phase-locked loop begins locking based on the initial value of the frequency control word;
[0050] S4. The lock detection circuit detects the phase detection signal output by the phase-locked loop after locking, and outputs Lock_Done = 1 when the phase detection signal no longer changes;
[0051] S5. The counter performs an AND operation between reset1 and Lock_Done, resets itself, and starts counting;
[0052] S6. After the automatic frequency calibrator counts the set time, it determines the calibration word based on the counter's readback indication and the Fast and Slow signals determined by the comparator based on the output voltage of the phase-locked loop; and replaces the initial value of the frequency control word with the calibration word, returning to S2.
[0053] As another embodiment, the present invention also provides a storage medium having computer program instructions stored thereon, which implement the method when the computer program instructions are executed by a processor.
[0054] As another embodiment, the present invention also provides an electronic device, including a memory and a processor, the memory being used to store a computer program, and the processor running the computer program to cause the electronic device to perform the method according to the method.
[0055] Based on the above description, the technical solution of the present invention, or the part that contributes to the prior art, or a part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods of the various embodiments of the present invention. The aforementioned computer storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory, random access memory, magnetic disks, or optical disks.
[0056] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on its differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. For the systems disclosed in the embodiments, since they correspond to the methods disclosed in the embodiments, the descriptions are relatively simple; relevant parts can be referred to the method section.
[0057] This document uses specific examples to illustrate the principles and implementation methods of the present invention. The descriptions of the above embodiments are only for the purpose of helping to understand the method and core ideas of the present invention. Furthermore, those skilled in the art will recognize that, based on the ideas of the present invention, there will be changes in the specific implementation methods and application scope. Therefore, the content of this specification should not be construed as a limitation of the present invention.
Claims
1. A phase-locked loop frequency calibration apparatus, characterized by, include: Phase-locked loop, automatic frequency calibrator, process detector, counter, comparator, and lock-in detection circuit; The process detector is connected to the automatic frequency calibrator; The automatic frequency calibrator is connected to the counter, the phase-locked loop, and the comparator respectively; the counter is connected to the lock detection circuit; the lock detection circuit is connected to the phase-locked loop; and the phase-locked loop is connected to the comparator. The process detector is used to send the initial value of the frequency control word to the automatic frequency calibrator; the automatic frequency calibrator sends reset1 = 1 to the counter according to the initial value of the frequency control word; The phase-locked loop begins locking based on the initial value of the frequency control word; The lock detection circuit detects the phase detection signal output by the phase-locked loop after locking, and outputs Lock_Done = 1 when the phase detection signal no longer changes; the counter performs an AND operation between reset1 and Lock_Done, resets, and starts counting. The automatic frequency calibrator is also used to determine the calibration word based on the counter's readback indication and the Fast and Slow signals determined by the comparator based on the output voltage of the phase-locked loop after counting a set time.
2. A phase-locked loop frequency calibration apparatus according to claim 1, wherein, The phase-locked loop includes: an oscillator, a loop filter, a charge pump, a differential integral modulator, a multi-mode frequency divider, and a frequency and phase detector; The output terminals of the oscillator and the differential-integral modulator are both connected to the input terminal of the multimode divider; the output terminals of the multimode divider and the crystal oscillator are both connected to the input terminal of the frequency and phase detector; the output terminal of the frequency and phase detector is connected to the input terminal of the charge pump; the output terminal of the charge pump is connected to the input terminal of the loop filter; and the output terminal of the loop filter is connected to the input terminals of the comparator and the oscillator.
3. The phase-locked loop frequency calibration device according to claim 2, characterized in that, The oscillator is a current-starved ring oscillator.
4. The phase-locked loop frequency calibration device according to claim 3, characterized in that, The load of the oscillator is a switched capacitor array using thermometer codes.
5. A phase-locked loop (PLL) frequency calibration method, used to implement the PLL frequency calibration device according to any one of claims 1-4, characterized in that, Calibration methods include: The process detector sends the initial value of the frequency control word to the automatic frequency calibrator; The automatic frequency calibrator sends reset1=1 to the counter based on the initial value of the frequency control word, at which point the counter has not started counting; The phase-locked loop (PLL) begins locking based on the initial value of the frequency control word. The lock detection circuit detects the phase detection signal output by the phase-locked loop after locking, and outputs Lock_Done = 1 when the phase detection signal no longer changes; The counter performs an AND operation between reset1 and Lock_Done, resets itself, and starts counting. After the automatic frequency calibrator counts for a set time, it determines the calibration word based on the counter's readback indication and the Fast and Slow signals determined by the comparator based on the output voltage of the phase-locked loop. It then replaces the initial value of the frequency control word with the calibration word and returns to the automatic frequency calibrator, which sends reset1=1 to the counter based on the initial value of the frequency control word. At this point, the counter has not started counting.
6. A storage medium storing computer program instructions thereon, characterized in that, The method of claim 5 is implemented when the computer program instructions are executed by the processor.
7. An electronic device, characterized in that, It includes a memory and a processor, the memory being used to store a computer program, and the processor running the computer program to cause the electronic device to perform the method according to claim 5.