A multi-channel ultrasonic pulsed synchronization method based on interpolation and autocorrelation detection

Abstract

This invention discloses a multi-channel ultrasonic pulse synchronization method based on interpolation and autocorrelation detection, belonging to the field of ultrasonic signal synchronization. The method includes: a transmitting FPGA generating a set of in-phase and quadrature signals and sending them to a receiving FPGA; the transmitting and receiving FPGAs respectively generating local bit synchronization clocks using the in-phase and quadrature signals; after the bit synchronization clocks are established, the transmitting FPGA sends a pulse sequence to the receiving FPGA that needs to establish synchronization; the transmitting and receiving FPGAs respectively detect the pulse sequence, and if the detection is successful, pull up the synchronization status indicator signal; if the synchronization status indicator signal is detected to be high, the chips of the ultrasonic system's transmission and acquisition boards controlled by the transmitting and receiving FPGAs are reset. This invention, as a multi-channel ultrasonic synchronization method, can achieve high-precision synchronization between multiple instruments under long-distance and large interference conditions, thus meeting the requirements for ultrasonic phased array detection.

Description

Technical Field

[0001] This invention relates to the field of ultrasonic signal synchronization, and in particular to a multi-channel ultrasonic pulse synchronization method, system, device, and medium based on interpolation and autocorrelation detection. Background Technology

[0002] Ultrasonic signals, as high-frequency, short-wavelength, easily generated, and highly directional signals, have wide applications in industrial, military, and medical fields. In the industrial field, ultrasonic nondestructive testing is a technique that uses ultrasonic waves to transmit signals to the sample being tested. The pulsed sound waves penetrate the sample, and by utilizing the difference in acoustic impedance between the air and the sample, a reflected echo signal is obtained. By analyzing the echo signal, the presence of defects in the sample can be determined.

[0003] While single-channel ultrasonic testing offers advantages such as simple principles and low system complexity, limitations in the near-field blind zone and beam spread angle make it difficult to meet detection requirements in complex environments. To address this issue, phased array technology is typically employed, using an array of piezoelectric ceramic wafers of identical shape and size. Each wafer independently transmits and receives beams, and the timing and phase are adjusted to control the phased array's acoustic field, achieving focusing or deflection.

[0004] Phased array ultrasound technology typically requires an ultrasound transmission and reception system with 16 or more channels, and each channel needs to be controlled independently. The increase in the number of channels inevitably leads to a multiplication of pin counts, resulting in a significant consumption of hardware resources from an instrumentation perspective. For example, an ultrasound system using an FPGA as the main control chip may lack the hardware resources to simultaneously control the ultrasound transmission and acquisition of more than four channels, necessitating signal synchronization between multiple ultrasound transmission and acquisition cards.

[0005] To achieve data synchronization between FPGAs, the first step is to generate a bit synchronization clock. Bit synchronization is generally implemented using two methods: the pilot insertion method and the direct method. The pilot method requires inserting a bit timing pilot signal, which is then extracted at the receiving end to achieve synchronization. However, this method is rarely used due to increased transmission power and spectral interference. The direct method is more widely used. It extracts the clock signal from the received digital signal or generates a locally generated clock signal through phase comparison and adjustment. A key method used is the phase-locked loop (PLL) method. The PLL method employs traditional PLL technology, using feedback control principles to change the frequency and phase of the sampling clock to adjust symbol synchronization. However, direct transmission of the clock signal over long distances is susceptible to interference. Summary of the Invention

[0006] To at least partially solve one of the technical problems existing in the prior art, the present invention aims to provide a multi-channel ultrasonic pulse synchronization method, system, device and medium based on interpolation and autocorrelation detection, which realizes high synchronization of transmission and reception between multiple channels of an FPGA-based ultrasonic system.

[0007] The technical solution adopted in this invention is:

[0008] A multi-channel ultrasonic pulse synchronization method based on interpolation and autocorrelation detection includes the following steps:

[0009] S1. A set of in-phase and quadrature signals is generated by the synchronous signal transmitting FPGA (hereinafter referred to as the transmitting FPGA) and sent to the synchronous signal receiving FPGA (hereinafter referred to as the receiving FPGA);

[0010] S2, the synchronous signal transmitting FPGA and the synchronous signal receiving FPGA both obtain the optimal sampling time through the in-phase signal and quadrature signal using an interpolation algorithm, which is used to generate the local bit synchronization clock;

[0011] S3. After the bit synchronization clock is established, the FPGA transmitting the synchronization signal sends a pulse sequence encoded by the generalized Barker code to the FPGA receiving the synchronization signal that needs to be synchronized.

[0012] S4, the FPGA at the synchronization signal transmitter and the FPGA at the synchronization signal receiver, respectively use the autocorrelation characteristics of the sharp single peak of the generalized Barker code to detect the pulse sequence. If the detection is successful, the synchronization status indicator signal will be pulled high.

[0013] S5. If the synchronization status indicator signal is detected to be high, the chips of the ultrasonic system transmission and acquisition board controlled by the FPGA at the synchronization signal transmitting end and the FPGA at the synchronization signal receiving end will be reset to ensure that the transmission and reception of ultrasonic signals between each channel are highly synchronized.

[0014] Further, step S1 includes:

[0015] S11. Modify the frequency control word information on the host computer according to the required local bit synchronization clock frequency.

[0016] S12. In the FPGA at the synchronization signal transmitting end, the modified frequency control word information is input to the DDS IP core connected by the local high-frequency clock through GPIO to indicate the frequency of the sine wave generated.

[0017] S13. The in-phase signal di and quadrature signal dq of the frequency are output from the DDS IP core of the FPGA at the synchronization signal transmitting end, and output to the FPGA at the synchronization signal receiving end through the connection line.

[0018] Further, step S2 includes:

[0019] S21. In the FPGA at the synchronous signal transmitting end and the FPGA at the synchronous signal receiving end, driven by their respective local clocks, the input in-phase signal di and quadrature signal dq are input into the interpolation filter module after passing through a first-level register. According to the interpolation interval uk output by the numerically controlled oscillator, the same frequency interpolation filter in-phase output yik and quadrature output yqk are obtained through the interpolator of the Farrow structure.

[0020] S22. In the FPGA at the synchronous signal transmitting end and the FPGA at the synchronous signal receiving end, driven by their respective local clocks, the numerically controlled oscillator counts down according to the timing error signal wk output by the loop filter. When the register value is less than 0, the strobe signal is output.

[0021] S23. In the FPGA at the synchronous signal transmitting end and the FPGA at the synchronous signal receiving end, under the drive of their respective local clocks, the error detection and loop filter modules receive the in-phase data yik and quadrature data yqk after interpolation filtering. When the strobe strobe signal is valid, the loop filter signal output wk is generated and the bit synchronization clock sync is output.

[0022] Further, step S3 includes:

[0023] S31. Input the generalized Barker code sequence required for synchronization into the host computer, and select the FPGA of the synchronization signal receiving end that needs to be synchronized.

[0024] S32. The FPGA at the synchronization signal transmitting end sends the generalized Barker code sequence to the FPGA at the synchronization signal receiving end, and pulls the check_start signal high to start the autocorrelation verification process.

[0025] Further, step S4 includes:

[0026] S41. When the check_start signal is high, the FPGA transmitting the synchronization signal and the FPGA receiving the synchronization signal start the search state module. Using the sharp single-peak autocorrelation characteristic of the generalized Barker code, the Hamming distance between the data in the shift register and the synchronization sequence is calculated. If the Hamming distance is less than the fault tolerance threshold, the search_over signal is pulled high.

[0027] S42. When the FPGA transmitting the synchronization signal and the FPGA receiving the synchronization signal participating in the synchronization start the verification state module when the search_over signal is high, the check_over signal is pulled high when all synchronization sequences pass the verification. If some sequences fail the verification, the research_check signal is pulled high and the search state module is restarted.

[0028] S43. When the check_over signal is high, the FPGA transmitting the synchronization signal and the FPGA receiving the synchronization signal that participates in the synchronization start the synchronization state module and generate a synchronization state indication pulse State_sync that is aligned with the last bit of the synchronization code.

[0029] Further, step S5 includes:

[0030] S51, the FPGA transmitting the synchronization signal and the FPGA receiving the synchronization signal send a reset signal to the corresponding ultrasonic system acquisition board when the synchronization status indication signal is detected to be high.

[0031] S52. When each ultrasonic system transmission and acquisition board in the entire system receives the reset signal, it resets the clock chip, ADC chip and DAC chip on its respective board, generates a synchronous sampling clock, and ensures that the transmission and reception of ultrasonic signals between each channel and multiple instruments are highly synchronized.

[0032] Furthermore, the ultrasonic system transmission and acquisition board includes analog-to-digital conversion circuit, digital-to-analog conversion circuit, programmable amplifier circuit, analog conditioning link, clock generation circuit, and power supply circuit. Under the FPGA control of the ultrasonic system transmission and acquisition board, the clock chip, ADC chip, and DAC chip related to synchronization are simultaneously reset to generate a synchronous sampling clock for data transmission and acquisition. This ensures that the ultrasonic signals transmitted and received by multiple channels or even multiple instruments participating in the entire synchronization process are highly synchronized, so as to facilitate phased array focusing, imaging, and other operations.

[0033] Another technical solution adopted in this invention is:

[0034] A multi-channel ultrasonic pulse synchronization system based on interpolation and autocorrelation detection includes:

[0035] The first module is used to generate a set of in-phase and quadrature signals from the synchronization signal transmitting FPGA and send them to the synchronization signal receiving FPGA.

[0036] The second module is used for both the FPGA transmitting and receiving the synchronization signal. Both FPGAs use the in-phase and quadrature signals to obtain the optimal sampling time using an interpolation algorithm to generate a local bit synchronization clock.

[0037] The third module is used to send a pulse sequence encoded by a generalized Barker code from the synchronization signal transmitting FPGA to the synchronization signal receiving FPGA that needs to establish synchronization after the bit synchronization clock is established.

[0038] The fourth module is used for the FPGA at the synchronization signal transmitting end and the FPGA at the synchronization signal receiving end. It uses the autocorrelation characteristics of the sharp single peak of the generalized Barker code to detect the pulse sequence. If the detection is successful, the synchronization status indicator signal will be pulled high.

[0039] The fifth module is used to reset the chips of the ultrasonic system transmission and acquisition boards controlled by the FPGA at the synchronization signal transmitting end and the FPGA at the synchronization signal receiving end if a high level is detected in the synchronization status indicator signal, so as to ensure that the transmission and reception of ultrasonic signals between each channel are highly synchronized.

[0040] Another technical solution adopted in this invention is:

[0041] A multi-channel ultrasonic pulse synchronization device based on interpolation and autocorrelation detection, comprising:

[0042] At least one processor;

[0043] At least one memory for storing at least one program;

[0044] When the at least one program is executed by the at least one processor, the at least one processor performs the method as described above.

[0045] Another technical solution adopted in this invention is:

[0046] A computer-readable storage medium storing a processor-executable program, which, when executed by a processor, is used to perform the method described above.

[0047] The beneficial effects of this invention are: as a method for multi-channel ultrasonic synchronization, this invention can achieve high-precision synchronization between multiple instruments under long distances and large interference, thereby meeting the requirements for ultrasonic phased array detection. Attached Figure Description

[0048] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following description is provided with accompanying drawings of the relevant technical solutions in the embodiments of the present invention or the prior art. It should be understood that the accompanying drawings described below are only for the purpose of clearly illustrating some embodiments of the technical solutions of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0049] Figure 1 This is a flowchart illustrating the implementation steps of a multi-channel ultrasonic pulse synchronization method based on interpolation and autocorrelation detection in an embodiment of the present invention.

[0050] Figure 2 This is a diagram showing the system hardware composition and key signal flow in an embodiment of the present invention;

[0051] Figure 3 This is a schematic diagram of a bit synchronization loop based on an interpolation algorithm in an embodiment of the present invention;

[0052] Figure 4 This is a schematic diagram illustrating the rate conversion principle of the interpolation algorithm in an embodiment of the present invention;

[0053] Figure 5 This is a schematic diagram of an interpolator based on the Farrow structure in an embodiment of the present invention;

[0054] Figure 6 This is a schematic diagram of two commonly used generalized Barker code sequences (octal representation) in embodiments of the present invention;

[0055] Figure 7 This is a schematic diagram of the autocorrelation function of a generalized Barker code sequence with a code length of 7 in an embodiment of the present invention;

[0056] Figure 8 This is a schematic diagram of the synchronization sequence search principle in an embodiment of the present invention;

[0057] Figure 9 This is a state transition diagram of the synchronization process in an embodiment of the present invention;

[0058] Figure 10 This is a diagram illustrating the reset process of the ultrasonic emission acquisition board in an embodiment of the present invention. Detailed Implementation

[0059] The embodiments of the present invention are described in detail below. Examples of these embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present invention, and should not be construed as limiting the present invention. The step numbers in the following embodiments are set only for ease of explanation, and there is no limitation on the order between the steps. The execution order of each step in the embodiments can be adaptively adjusted according to the understanding of those skilled in the art.

[0060] In the description of this invention, it should be understood that the orientation descriptions, such as up, down, front, back, left, right, etc., are based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limiting this invention.

[0061] In the description of this invention, "several" means one or more, "more than" means two or more, "greater than," "less than," and "exceeding" are understood to exclude the stated number, while "above," "below," and "within" are understood to include the stated number. The use of "first" and "second" in the description is merely for distinguishing technical features and should not be construed as indicating or implying relative importance, or implicitly indicating the number of indicated technical features, or implicitly indicating the order of the indicated technical features.

[0062] Furthermore, in the description of this invention, unless otherwise stated, "multiple" means two or more. "And / or" describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A alone, A and B simultaneously, or B alone. The character " / " generally indicates that the preceding and following related objects have an "or" relationship.

[0063] In the description of this invention, unless otherwise explicitly defined, terms such as "set up," "install," and "connect" should be interpreted broadly, and those skilled in the art can reasonably determine the specific meaning of the above terms in this invention in conjunction with the specific content of the technical solution.

[0064] To address existing technical challenges, this application employs an interpolation method to adjust bit timing without altering the local clock. The core of the interpolation method lies in obtaining the optimal sampling signal (generated by a digitally controlled oscillator) based on the input signal through interpolation. A timing error detector detects the phase difference between the local clock sampling time and the optimal sampling time to arrive at an optimal sampling time. By transmitting in-phase and quadrature signals, interference from external conditions is reduced, facilitating synchronization between instruments over long distances and under significant interference.

[0065] Autocorrelation, also known as sequence correlation, is the cross-correlation between a signal and itself at different points in time. Simply put, autocorrelation assesses the similarity between two observations of the same signal at different times by comparing them. The autocorrelation function is the average of the product of the signal and its time-shifted counterpart; it is a function of the time-shifted variable. The autocorrelation properties of sequences can be used to encode transmitted data into frame structures, enabling rapid verification and ensuring accurate synchronization.

[0066] Autocorrelation sequences mainly include generalized Barker code sequences and pseudo-random m-sequences, which exhibit sharp, unimodal autocorrelation characteristics, short lengths, and low resource consumption, making them easy to analyze. Barker codes, proposed by R.R. Barker in the early 1950s, are a special type of binary code. They are aperiodic sequences with excellent autocorrelation properties and can be used in data frame headers.

[0067] like Figure 1As shown, this embodiment provides a multi-channel ultrasonic pulse synchronization method based on interpolation and autocorrelation detection, specifically including the following steps:

[0068] A. A set of in-phase and quadrature signals is generated by the FPGA at the synchronization signal transmitting end and sent to the FPGA at the synchronization signal receiving end.

[0069] B. The FPGA at the transmitting and receiving ends of the synchronization signal obtains the optimal sampling time through the in-phase signal and the quadrature signal respectively using the interpolation algorithm, and generates the local bit synchronization clock respectively.

[0070] C. After the synchronization clock is established, the FPGA transmitting the synchronization signal sends a pulse sequence encoded by the generalized Barker code to the FPGA receiving the synchronization signal that needs to be synchronized.

[0071] D. The FPGA at the transmitting and receiving ends of the synchronization signal uses the autocorrelation characteristics of the sharp single peak of the generalized Barker code to detect the pulse sequence. If the detection is successful, the synchronization status indicator signal is pulled high.

[0072] E. If a high level is detected in the synchronization status indicator signal, the chips of the ultrasonic system transmission and acquisition boards controlled by the FPGA at the synchronization signal transmitting end and the receiving end will be reset to ensure that the transmission and reception of ultrasonic signals between each channel are highly synchronized.

[0073] Reference Figure 2 As an optional implementation, in step A, under the interactive control of the host computer, the FPGA at the synchronization signal transmitting end generates a set of in-phase and quadrature signals and sends them to the FPGA at the synchronization signal receiving end, etc. It is clarified that both the FPGA at the synchronization signal transmitting end and the FPGA at the synchronization signal receiving end control the corresponding transmission and acquisition boards, and the FPGA at the synchronization signal transmitting end and the FPGA at the synchronization signal receiving end play exactly the same role when controlling the transmission and acquisition boards. Specifically, step A includes steps A1-A3:

[0074] A1. Modify the frequency control word information on the host computer according to the required local bit synchronization clock frequency.

[0075] A2. In the FPGA at the synchronous signal transmitting end, the modified frequency control word information is input to the DDS IP core connected to the local high-frequency clock via GPIO to indicate the frequency of the sine wave.

[0076] A3. The in-phase signal di and quadrature signal dq of the frequency are output from the DDS IP core of the FPGA at the synchronization signal transmitting end, and output to the FPGA at the synchronization signal receiving end through the connection line.

[0077] Reference Figure 3 As an optional implementation, step B specifically includes steps B1-B3:

[0078] B1. In the FPGA at the synchronous signal transmitting and receiving ends, driven by their respective local clocks, the input in-phase signal di and quadrature signal dq are input into the interpolation filter module after passing through a first-level register. Based on the interpolation interval uk output by the numerically controlled oscillator, the same frequency interpolation filter in-phase output yik and quadrature output yqk are obtained through the interpolator of the Farrow structure.

[0079] B2. In the FPGA at the synchronous signal transmitting and receiving ends, driven by their respective local clocks, the numerically controlled oscillator counts down according to the timing error signal wk output by the loop filter. When the register value is less than 0, it outputs the strobe signal.

[0080] B3. In the FPGA at the synchronous signal transmitting and receiving ends, driven by their respective local clocks, the error detection and loop filter modules receive the in-phase data yik and quadrature data yqk after interpolation filtering. When the strobe strobe signal is valid, the loop filter signal output wk is generated and the bit synchronization clock sync is output.

[0081] Specifically, the interpolation filter is actually an interpolation algorithm. Its function is to obtain the optimal sampled value signal based on the input signal through interpolation. Since the sampling clock of the receiving end is not synchronized with the clock of the transmitting end, the value of the sampling point of the receiving clock may not be the required optimal sampled value. However, the interpolation algorithm can obtain the optimal sampled value based on the sampled signal value, as well as the sampling time signal and error signal sent by the CNC oscillator. The timing error detector is responsible for detecting the phase difference between the local clock sampling time and the optimal sampling time. The detected phase difference is filtered by the loop filter and then sent to the CNC oscillator to generate the next interpolation time.

[0082] Reference Figure 4 , Figure 4 The data rate conversion principle of the interpolation filter is demonstrated. Further, in step B1, under the drive of their respective local clocks in the FPGAs of the synchronous signal transmitter and receiver, the input in-phase signal di and quadrature signal dq are input to the interpolation filter module after passing through a first-level register. According to the interpolation interval uk output by the numerically controlled oscillator, the same frequency interpolation filter in-phase output yik and quadrature output yqk are obtained through the interpolator of the Farrow structure.

[0083] Furthermore, referring to Figure 4 Assume the receiving end has a fixed sampling clock period of T. S The symbol period is T, and the signal received by the interpolation filter is x(mT). S The sampling frequency is f s =1 / T SThrough a digital-to-analog converter and a filter h I After (t), a continuous-time output is obtained:

[0084]

[0085] For y(t), assume it is sampled again at each time t = kTi, where k is a positive integer and Ti is the interpolation period, which is synchronized with the symbol period, i.e., the ratio of T / Ti is an integer. The sampled data is y(kTi), then:

[0086]

[0087] Although a DAC and an analog filter are present in this rate conversion module, given the input sequence {x(m)}, the impulse response h of the interpolation filter... I (t) and the sampling time T of the input signal s The interpolation point can be achieved using the above formula, along with the output sampling time Ti.

[0088] Reference Figure 5 , Figure 5 This demonstrates a widely used cubic interpolator with a Farrow structure, which has three vertical branches f1, f2, f3 and one horizontal branch y. I (k), the calculation formulas are as follows:

[0089] f1=0.5x(m)-0.5x(m-1)-0.5x(m-2)+0.5x(m-3)

[0090] f2=1.5x(m)-0.5x(m-1)-0.5x(m-2)-0.5x(m-3)

[0091] f3 = x(m-2)

[0092] y I (k)=f1u(k)u(k)+f2u(k)+f3

[0093] Specifically, the Farrow interpolator is a structure close to that of an FIR filter, which is very easy to implement in FPGA. According to the principle of the Farrow structure, calculating an interpolation only requires four sampling points within one symbol period, or in other words, the input sampling signal only needs to be four times the symbol rate.

[0094] As an optional implementation, step C specifically includes steps C1-C2:

[0095] C1. Input the generalized Barker code sequence required for synchronization into the host computer, and select the FPGA that needs to perform the synchronization operation.

[0096] C2. The FPGA at the synchronization signal transmitting end sends the generalized Barker code sequence to the FPGA at the synchronization signal receiving end and pulls the check_start signal high to start the autocorrelation verification process.

[0097] Reference Figure 6 , Figure 6 Two commonly used generalized Barker code sequences (octal representation) are shown. Further step C1 includes inputting the required generalized Barker code sequence for synchronization into the host computer based on the commonly used sequences shown in the diagram, and selecting the FPGA (FPGA-based) synchronization signal receiver for which synchronization operation is required.

[0098] Specifically, refer to Figure 6 The listed sequences are all generalized Barker code sequences, which are aperiodic finite sequences. When calculating their autocorrelation function, in the case where the time delay j = 0 (i.e., the two sequences are perfectly aligned), all elements in the sequence participate in the correlation operation; in the case where j ≠ 0, only some elements in the sequence participate in the correlation operation, and its expression is:

[0099]

[0100] The autocorrelation function of such a non-periodic sequence is usually called the local autocorrelation function. This application uses the value of the local autocorrelation function for autocorrelation detection.

[0101] Reference Figure 7 Taking a generalized Barker code sequence with a code length of 7 as an example, it can be seen that the autocorrelation function of the generalized Barker code has a sharp single peak. Only when the sequence is perfectly aligned will the local autocorrelation function have a large value, which is convenient for detection.

[0102] As an optional implementation, step D specifically includes steps D1-D3:

[0103] D1. When the FPGA of the synchronization signal transmitter and the synchronization signal receiver participating in the synchronization is high, the search state module is started. The Hamming distance between the data in the shift register and the synchronization sequence is calculated by using the sharp single-peak autocorrelation characteristic of the generalized Barker code. If the Hamming distance is less than the fault tolerance threshold, the search_over signal is pulled high.

[0104] D2. When the FPGA at the synchronization signal transmitter and the synchronization signal receiver participating in the synchronization starts the verification state module when the search_over signal is high, the check_over signal is pulled high when all synchronization sequences pass the verification. If some sequences fail the verification, the research_check signal is pulled high and the search state module is restarted.

[0105] D3. When the FPGA of the synchronization signal transmitter and the synchronization signal receiver participating in the synchronization is high, the synchronization state module is started, and a synchronization state indication pulse State_sync is generated that is aligned with the last bit of the synchronization code.

[0106] Reference Figure 8 , Figure 8 The diagram illustrates the principle of synchronization sequence search under the condition of using a seven-bit generalized Barker code as the synchronization sequence. Further, in step D1, the synchronization signal transmitter and the FPGA participating in the synchronization start the search state module when the check_start signal is high. Utilizing the sharp single-peak autocorrelation characteristic of the generalized Barker code, the Hamming distance between the data in the shift register and the synchronization sequence is calculated. If the Hamming distance is less than the fault tolerance threshold, the search_over signal is pulled high.

[0107] Specifically, the Hamming distance is calculated using an XOR addition method. Based on the initial value of the Hamming distance between the set register data and the synchronization sequence (set to the synchronization code length, indicating the maximum difference from the synchronization code), the threshold h is actually the fault tolerance of the synchronization code group detection. When it is less than the fault tolerance threshold, the frame synchronization pulse signal is output, and the system enters the verification state module.

[0108] Reference Figure 9 , Figure 9 The state transition diagram of the synchronization process is shown. Further, in step D, the FPGA at the synchronization signal transmitting end and the receiving end respectively uses the autocorrelation characteristics of the sharp single peak of the generalized Barker code to detect the pulse sequence. If the detection is successful, the synchronization state indicator signal is pulled high.

[0109] In some alternative embodiments, the entire synchronization process can be divided into three states: search state, verification state, and synchronization state.

[0110] The search state occurs at the start of data reception or in the verification state if an unsynchronized sequence exists. If multiple consecutive unsynchronized sequences are found in the synchronization state, the system transitions to the search state. In the search state, the program continuously searches for the synchronization code in the data stream. When a sequence matching the synchronization code is found in the received bit stream, a pulse signal is output, indicating that the system has entered the frame synchronization verification state.

[0111] The verification state is when the sequence found in the search state is confirmed to be correct after N consecutive frames of synchronization codes. If so, the system immediately enters the synchronization state. Otherwise, it indicates that false synchronization has occurred, and the system needs to return to the search state to search for the frame synchronization code again.

[0112] The synchronization state means that the system is in a synchronized state. If there are no consecutive M frames of data that are out of sync, it will remain in the synchronization state. In order to prevent errors caused by external interference, the system will only enter the out-of-sync state and return to the search state if there are consecutive M frames of synchronization sequence mismatch.

[0113] Step E specifically includes steps E1-E2:

[0114] When the E1 synchronization signal transmitter and receiver FPGA detect that the synchronization status indicator signal is high, they send a reset signal to the ultrasonic system acquisition board they control respectively.

[0115] E2. When each ultrasonic transmission and acquisition board in the entire system receives the reset signal, it resets the clock chip, ADC chip and DAC chip on its respective board, generating a synchronous sampling clock to ensure a high degree of synchronization between the transmission and reception of ultrasonic signals between various channels and even multiple instruments.

[0116] Reference Figure 10 , Figure 10 The diagram illustrates the reset process of the ultrasonic transmission and acquisition board. Further, in step E, when the synchronization status indicator signal is detected to be high, the FPGA at the synchronization signal transmitter and receiver sends a reset signal to the ultrasonic system transmission and acquisition board it controls. Upon receiving the reset signal, each ultrasonic transmission and acquisition board in the system resets its clock chip, ADC chip, and DAC chip, generating a synchronous sampling clock to ensure a high degree of synchronization between the transmission and reception of ultrasonic signals across different channels and even multiple instruments.

[0117] This embodiment also provides a multi-channel ultrasonic pulse synchronization system based on interpolation and autocorrelation detection, including:

[0118] The first module is used to generate a set of in-phase and quadrature signals from the synchronization signal transmitting FPGA and send them to the synchronization signal receiving FPGA.

[0119] The second module is used for both the FPGA transmitting and receiving the synchronization signal. Both FPGAs use the in-phase and quadrature signals to obtain the optimal sampling time using an interpolation algorithm to generate a local bit synchronization clock.

[0120] The third module is used to send a pulse sequence encoded by a generalized Barker code from the synchronization signal transmitting FPGA to the synchronization signal receiving FPGA that needs to establish synchronization after the bit synchronization clock is established.

[0121] The fourth module is used for the FPGA at the synchronization signal transmitting end and the FPGA at the synchronization signal receiving end. It uses the autocorrelation characteristics of the sharp single peak of the generalized Barker code to detect the pulse sequence. If the detection is successful, the synchronization status indicator signal will be pulled high.

[0122] The fifth module is used to reset the chips of the ultrasonic system transmission and acquisition boards controlled by the FPGA at the synchronization signal transmitting end and the FPGA at the synchronization signal receiving end if a high level is detected in the synchronization status indicator signal, so as to ensure that the transmission and reception of ultrasonic signals between each channel are highly synchronized.

[0123] This embodiment of a multi-channel ultrasonic pulse synchronization system based on interpolation and autocorrelation detection can execute the multi-channel ultrasonic pulse synchronization method based on interpolation and autocorrelation detection provided in the method embodiment of the present invention. It can execute any combination of implementation steps of the method embodiment and has the corresponding functions and beneficial effects of the method.

[0124] This embodiment also provides a multi-channel ultrasonic pulse synchronization device based on interpolation and autocorrelation detection, including:

[0125] At least one processor;

[0126] At least one memory for storing at least one program;

[0127] When the at least one program is executed by the at least one processor, the at least one processor performs the following: Figure 1 The method shown.

[0128] This embodiment provides a multi-channel ultrasonic pulse synchronization device based on interpolation and autocorrelation detection, which can execute the multi-channel ultrasonic pulse synchronization method based on interpolation and autocorrelation detection provided in the method embodiment of the present invention. It can execute any combination of implementation steps of the method embodiment and has the corresponding functions and beneficial effects of the method.

[0129] This application also discloses a computer program product or computer program, which includes computer instructions stored in a computer-readable storage medium. A processor of a computer device can read the computer instructions from the computer-readable storage medium and execute the computer instructions, causing the computer device to perform... Figure 1 The method shown.

[0130] This embodiment also provides a storage medium storing instructions or programs that can execute the multi-channel ultrasonic pulse synchronization method based on interpolation and autocorrelation detection provided in the method embodiment of the present invention. When the instructions or programs are run, any combination of implementation steps of the method embodiment can be executed, and the method has the corresponding functions and beneficial effects.

[0131] In some alternative embodiments, the functions / operations mentioned in the block diagrams may not occur in the order shown in the operation diagrams. For example, depending on the functions / operations involved, two consecutively shown blocks may actually be executed substantially simultaneously, or the blocks may sometimes be executed in reverse order. Furthermore, the embodiments presented and described in the flowcharts of this invention are provided by way of example to provide a more comprehensive understanding of the technology. The disclosed methods are not limited to the operations and logic flows presented herein. Alternative embodiments are contemplated in which the order of various operations is altered and sub-operations described as part of a larger operation are executed independently.

[0132] Furthermore, although the invention has been described in the context of functional modules, it should be understood that, unless otherwise stated, one or more of the described functions and / or features may be integrated into a single physical device and / or software module, or one or more functions and / or features may be implemented in a separate physical device or software module. It is also understood that a detailed discussion of the actual implementation of each module is unnecessary for understanding the invention. Rather, given the properties, functions, and internal relationships of the various functional modules in the apparatus disclosed herein, the actual implementation of the module will be understood within the scope of conventional skill of an engineer. Therefore, those skilled in the art can implement the invention as set forth in the claims using ordinary techniques without excessive experimentation. It is also understood that the specific concepts disclosed are merely illustrative and not intended to limit the scope of the invention, which is determined by the full scope of the appended claims and their equivalents.

[0133] If the aforementioned functions are implemented as software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this invention, essentially, or the part that contributes to the prior art, or a portion of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this invention. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0134] The logic and / or steps represented in the flowchart or otherwise described herein, for example, can be considered as a sequenced list of executable instructions for implementing logical functions, and can be embodied in any computer-readable medium for use by, or in conjunction with, an instruction execution system, apparatus, or device (such as a computer-based system, a processor-included system, or other system that can fetch and execute instructions from, an instruction execution system, apparatus, or device). For the purposes of this specification, "computer-readable medium" can be any means that can contain, store, communicate, propagate, or transmit programs for use by, or in conjunction with, an instruction execution system, apparatus, or device.

[0135] More specific examples of computer-readable media (a non-exhaustive list) include: electrical connections (electronic devices) having one or more wires, portable computer disk drives (magnetic devices), random access memory (RAM), read-only memory (ROM), erasable and editable read-only memory (EPROM or flash memory), fiber optic devices, and portable optical disc read-only memory (CDROM). Furthermore, computer-readable media can even be paper or other suitable media on which the program can be printed, since the program can be obtained electronically, for example, by optically scanning the paper or other medium, followed by editing, interpreting, or otherwise processing as necessary, and then stored in computer memory.

[0136] It should be understood that various parts of the present invention can be implemented in hardware, software, firmware, or a combination thereof. In the above embodiments, multiple steps or methods can be implemented in software or firmware stored in memory and executed by a suitable instruction execution system. For example, if implemented in hardware, as in another embodiment, it can be implemented using any one or a combination of the following techniques known in the art: discrete logic circuits having logic gates for implementing logical functions on data signals, application-specific integrated circuits (ASICs) having suitable combinational logic gates, programmable gate arrays (PGAs), field-programmable gate arrays (FPGAs), etc.

[0137] In the foregoing description of this specification, references to terms such as "one embodiment," "another embodiment," or "some embodiments" indicate that a specific feature, structure, material, or characteristic described in connection with an embodiment or example is included in at least one embodiment or example of the present invention. In this specification, illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0138] Although embodiments of the invention have been shown and described, those skilled in the art will understand that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the invention, the scope of which is defined by the claims and their equivalents.

[0139] The above is a detailed description of the preferred embodiments of the present invention. However, the present invention is not limited to the above embodiments. Those skilled in the art can make various equivalent modifications or substitutions without departing from the spirit of the present invention. All such equivalent modifications or substitutions are included within the scope defined by the claims of this application.

Claims

1. A multi-channel ultrasonic pulsed synchronization method based on interpolation and autocorrelation detection, characterized in that, Includes the following steps: S1. A set of in-phase and quadrature signals is generated by the FPGA at the synchronization signal transmitting end and sent to the FPGA at the synchronization signal receiving end. S2, the synchronous signal transmitting FPGA and the synchronous signal receiving FPGA both obtain the optimal sampling time through the in-phase signal and quadrature signal using an interpolation algorithm to generate a local bit synchronization clock; S3. After the bit synchronization clock is established, the FPGA transmitting the synchronization signal sends a pulse sequence encoded by the generalized Barker code to the FPGA receiving the synchronization signal that needs to be synchronized. S4, the FPGA at the synchronization signal transmitter and the FPGA at the synchronization signal receiver, respectively use the autocorrelation characteristics of the sharp single peak of the generalized Barker code to detect the pulse sequence. If the detection is successful, the synchronization status indicator signal will be pulled high. S5. If the synchronization status indicator signal is detected to be high, the chips of the ultrasonic system transmission and acquisition board controlled by the FPGA at the synchronization signal transmitting end and the FPGA at the synchronization signal receiving end will be reset to ensure that the transmission and reception of ultrasonic signals between each channel are highly synchronized. Step S2 includes: S21. In the FPGA at the synchronous signal transmitting end and the FPGA at the synchronous signal receiving end, driven by their respective local clocks, the input in-phase signal di and quadrature signal dq are input into the interpolation filter module after passing through a first-level register; the interpolation filter module adopts an interpolator with a Farrow structure, and obtains interpolated filtered in-phase data yik and quadrature data yqk of the same frequency according to the interpolation interval uk output by the numerically controlled oscillator. S22. In the FPGA at the synchronous signal transmitting end and the FPGA at the synchronous signal receiving end, driven by their respective local clocks, the numerically controlled oscillator counts down according to the timing error signal wk output by the loop filter. When the register value is less than 0, the strobe signal is output. S23. In the FPGA at the synchronous signal transmitting end and the FPGA at the synchronous signal receiving end, under the drive of their respective local clocks, the error detection and loop filtering module, which consists of an error detector and a loop filter, receives the in-phase data yik and quadrature data yqk after interpolation filtering. When the strobe strobe signal is valid, the loop filter outputs the timing error signal wk and the bit synchronization clock sync.

2. A multi-channel ultrasonic pulsed synchronization method based on interpolation and autocorrelation detection according to claim 1, characterized in that, Step S1 includes: S11. Modify the frequency control word information on the host computer according to the required local bit synchronization clock frequency. S12. In the FPGA at the synchronization signal transmitting end, the modified frequency control word information is input to the DDS IP core connected by the local high-frequency clock through GPIO to indicate the frequency of the sine wave generated. S13. The in-phase signal di and quadrature signal dq of the frequency are output from the DDS IP core of the FPGA at the synchronization signal transmitting end, and output to the FPGA at the synchronization signal receiving end through the connection line.

3. A multi-channel ultrasonic pulsed synchronization method based on interpolation and autocorrelation detection according to claim 1, characterized in that, Step S3 includes: S31. Input the generalized Barker code sequence required for synchronization into the host computer, and select the FPGA of the synchronization signal receiving end that needs to be synchronized. S32. The FPGA at the synchronization signal transmitting end sends the generalized Barker code sequence to the FPGA at the synchronization signal receiving end, and pulls the check_start signal high to start the autocorrelation verification process.

4. A multi-channel ultrasonic pulsed synchronization method based on interpolation and autocorrelation detection according to claim 1, characterized in that, Step S4 includes: S41. When the check_start signal is high, the FPGA transmitting the synchronization signal and the FPGA receiving the synchronization signal start the search state module. Using the sharp single-peak autocorrelation characteristic of the generalized Barker code, the Hamming distance between the data in the shift register and the synchronization sequence is calculated. If the Hamming distance is less than the fault tolerance threshold, the search_over signal is pulled high. S42. When the FPGA transmitting the synchronization signal and the FPGA receiving the synchronization signal participating in the synchronization start the verification state module when the search_over signal is high, the check_over signal is pulled high when all synchronization sequences pass the verification. If some sequences fail the verification, the research_check signal is pulled high and the search state module is restarted. S43. When the check_over signal is high, the FPGA transmitting the synchronization signal and the FPGA receiving the synchronization signal that participates in the synchronization start the synchronization state module and generate a synchronization state indication pulse State_sync that is aligned with the last bit of the synchronization code.

5. A multi-channel ultrasonic pulsed synchronization method based on interpolation and autocorrelation detection according to claim 1, characterized in that, Step S5 includes: S51, the FPGA transmitting the synchronization signal and the FPGA receiving the synchronization signal send a reset signal to the corresponding ultrasonic system acquisition board when the synchronization status indication signal is detected to be high. S52. When each ultrasonic system transmission and acquisition board in the entire system receives the reset signal, it resets the clock chip, ADC chip and DAC chip on its respective board, generates a synchronous sampling clock, and ensures that the transmission and reception of ultrasonic signals between each channel and multiple instruments are highly synchronized.

6. The multi-channel ultrasonic pulse synchronization method based on interpolation and autocorrelation detection according to claim 1, characterized in that, The ultrasonic system transmission and acquisition board includes an analog-to-digital converter circuit, a digital-to-analog converter circuit, a programmable amplifier circuit, an analog conditioning link, a clock generation circuit, and a power supply circuit. Under the FPGA control of the ultrasonic system transmission and acquisition board, the clock chip, ADC chip, and DAC chip related to synchronization are simultaneously reset to generate a synchronous sampling clock for data transmission and acquisition, ensuring high synchronization of ultrasonic signals transmitted and received by multiple channels or even multiple instruments participating in the entire synchronization process.

7. A multi-channel ultrasonic pulse synchronization system based on interpolation and autocorrelation detection, used to implement the method described in any one of claims 1-6, characterized in that, include: The first module is used to generate a set of in-phase and quadrature signals from the synchronization signal transmitting FPGA and send them to the synchronization signal receiving FPGA. The second module is used for both the FPGA transmitting and receiving the synchronization signal. Both FPGAs use the in-phase and quadrature signals to obtain the optimal sampling time using an interpolation algorithm to generate a local bit synchronization clock. The third module is used to send a pulse sequence encoded by a generalized Barker code from the synchronization signal transmitting FPGA to the synchronization signal receiving FPGA that needs to establish synchronization after the bit synchronization clock is established. The fourth module is used for the FPGA at the synchronization signal transmitting end and the FPGA at the synchronization signal receiving end. It uses the autocorrelation characteristics of the sharp single peak of the generalized Barker code to detect the pulse sequence. If the detection is successful, the synchronization status indicator signal will be pulled high. The fifth module is used to reset the chips of the ultrasonic system transmission and acquisition boards controlled by the FPGA at the synchronization signal transmitting end and the FPGA at the synchronization signal receiving end if a high level is detected in the synchronization status indicator signal, so as to ensure that the transmission and reception of ultrasonic signals between each channel are highly synchronized.

8. A multi-channel ultrasonic pulsed synchronization device based on interpolation and autocorrelation detection, characterized by, include: At least one processor; At least one memory for storing at least one program; When the at least one program is executed by the at least one processor, the at least one processor implements the method according to any one of claims 1-6.

9. A computer-readable storage medium storing a processor-executable program, characterized in that, The processor-executable program, when executed by the processor, is used to perform the method as described in any one of claims 1-6.

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