Memory device and method of operation thereof

Abstract

Memory devices and methods of operating the same are provided herein. A memory device can include a memory block including a plurality of memory cells coupled with a plurality of word lines, a peripheral circuit configured to perform a read operation by applying a read voltage to a selected word line among the plurality of word lines and applying a first pass voltage to a target word line, wherein the target word line is adjacent to the selected word line among unselected word lines other than the selected word line, and control logic configured to lower the read voltage based on a read voltage change, and when the read voltage is lowered, lower the first pass voltage based on a pass voltage change, wherein the pass voltage change is less than the read voltage change.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2022-0036321, filed on March 23, 2022, with the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference. Technical Field

[0003] Various embodiments of this disclosure generally relate to electronic devices, and more specifically to memory devices and methods of operating such memory devices. Background Technology

[0004] A storage device is a device that stores data under the control of a host device such as a computer or smartphone. A storage device can include the storage device that stores the data and the storage controller that controls the storage device. Storage devices are classified as volatile storage devices and non-volatile storage devices.

[0005] Volatile memory devices are memory devices that store data only when power is supplied and lose the stored data when the power supply is interrupted. Examples of volatile memory devices can include static random access memory (SRAM) and dynamic random access memory (DRAM).

[0006] Non-volatile memory devices are memory devices that retain stored data even when the power supply is interrupted. Examples of non-volatile memory devices can include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), and flash memory.

[0007] A read operation is the process of retrieving data stored in a memory device. Specifically, a read operation may involve applying a read voltage to a selected word line and applying a voltage to an unselected word line. To reduce the time required for read operations, techniques are needed to accurately and quickly control the voltage level applied to the word lines. Summary of the Invention

[0008] One embodiment of this disclosure may provide a memory device. The memory device may include: a memory block including a plurality of memory cells coupled to a plurality of word lines; peripheral circuitry configured to perform a read operation by applying a read voltage to a selected word line among the plurality of word lines and applying a first pass voltage to a target word line, wherein the target word line is adjacent to the selected word line among unselected word lines other than the selected word line; and control logic configured to reduce a read voltage based on a read voltage change, and when the read voltage is reduced, to reduce the first pass voltage based on a pass voltage change, wherein the pass voltage change is less than the read voltage change.

[0009] One embodiment of this disclosure may provide a method for operating a memory device. The method may include: applying a read voltage to selected word lines among a plurality of word lines, and applying a pass voltage to unselected word lines, the selected word lines being coupled to memory blocks included in the memory device; reducing the read voltage based on a first voltage change; and, when the read voltage is reduced, reducing the pass voltage applied to a target word line adjacent to the selected word line among the unselected word lines based on a second voltage change, wherein the second voltage change is less than the first voltage change. Attached Figure Description

[0010] Figure 1 This is a diagram illustrating a memory system according to one embodiment.

[0011] Figure 2 This is a diagram illustrating the structure of a memory device according to one embodiment.

[0012] Figure 3 This is a diagram illustrating the structure of a memory block according to one embodiment.

[0013] Figure 4A and Figure 4B This is a diagram illustrating the threshold voltage distribution of a memory cell according to an embodiment of the present disclosure.

[0014] Figure 5A and Figure 5B This is a diagram illustrating the voltage applied to a word line according to one embodiment.

[0015] Figure 6A and Figure 6B This is a timing diagram illustrating the operation of a memory device according to one embodiment.

[0016] Figure 7 This is a diagram illustrating voltage variations according to one embodiment.

[0017] Figures 8A to 8E This is a diagram illustrating voltage variations according to one embodiment.

[0018] Figure 9 This is a flowchart illustrating the operation of a memory device according to one embodiment.

[0019] Figure 10 This is a block diagram illustrating a memory card using a memory system according to one embodiment.

[0020] Figure 11 This is a block diagram illustrating a solid-state drive (SSD) system that applies a memory system according to one embodiment.

[0021] Figure 12 This is a block diagram illustrating a user system using a memory system according to one embodiment. Detailed Implementation

[0022] The specific structural or functional descriptions of the embodiments of this disclosure set forth in this specification or application are illustrated to describe embodiments based on the concept of this disclosure. Embodiments based on the concept of this disclosure may be practiced in various forms and should not be construed as limited to the embodiments described in the specification or application.

[0023] Various embodiments of this disclosure relate to memory devices capable of reducing the time required for read operations, and methods of operating such memory devices.

[0024] Figure 1 This is a diagram illustrating a memory system according to one embodiment.

[0025] refer to Figure 1 The memory system 10 can operate in response to requests from the host 20. Specifically, the memory system 10 can perform operations corresponding to requests received from the host 20. In one example, when receiving data and a data storage request from the host 20, the memory system 10 can store the data therein. In other examples, when receiving a data read request from the host 20, the memory system 10 can provide the data stored therein to the host 20. For this purpose, the memory system 10 can be coupled to the host 20 via various communication schemes.

[0026] The memory system 10 can be implemented as any of various types of storage devices based on communication standards or data storage methods. For example, the memory system 10 can be implemented as a solid-state drive (SSD), multimedia card (MMC), embedded MMC (eMMC), reduced-size MMC (RS-MMC), micro-MMC storage device, secure digital card (SD) card, mini-SD card or micro-SD storage device, universal serial bus (USB) storage device, universal flash storage (UFS) device, PCMCIA (Personal Computer Memory Card International Association) type storage device, peripheral component interconnect (PCI) type storage device, PCI Express (PCI-E) type storage device, network attached storage (NAS), and wireless network storage device. The examples listed herein are merely embodiments, and the memory system 10 can be implemented as various types of storage devices, and is not limited to these embodiments.

[0027] Host 20 can be one of various electronic devices, such as desktop computers, laptops, smartphones, game consoles, televisions (TVs), tablets, set-top boxes, etc.

[0028] Boxes, washing machines, robots, refrigerators, AI speakers, wearable devices, central processing units (CPUs), accelerated processing units (APUs), graphics processing units (GPUs), and neural processing units (NPUs). Host 20 can send data, logical addresses, or various requests to memory system 10, or can receive data from memory system 10.

[0029] The memory system 10 can be used as the main memory device or auxiliary memory device of the host 20. The memory system 10 can be located inside or outside the host 20.

[0030] The memory system 10 may include a memory device 100 and a memory controller 200. Here, the number of memory devices 100 may be one or more. The memory device 100 and the memory controller 200 may be coupled to each other via a channel. The memory device 100 and the memory controller 200 may send / receive commands, addresses, or data via the channel.

[0031] Memory device 100 can store data. For example, memory device 100 can be implemented as any of various types of semiconductor memory devices. In one example, memory device 100 can be implemented as a NAND flash memory device, a vertical NAND flash memory device, a NOR flash memory device, a static random access memory (SRAM) device, a dynamic RAM (DRAM) device, or a synchronous dynamic RAM (SDRAM).

[0032] The device includes, but is not limited to, Double Data Rate (DDR) SDRAM devices, Low Power DDR (LPDDR) SDRAM devices, Graphics DRAM (GDRAM) devices, Rambus DRAM (RDRAM) devices, Ferroelectric RAM (FeRAM) devices, Magnetoresistive RAM (MRAM) devices, Phase Change Memory (PCM) devices, Spin Torque Magnetoresistive RAM (STT-MRAM) devices, and Resistive RAM (ReRAM) devices. In the following description, for ease of description, it is assumed that memory device 100 is a NAND flash memory device.

[0033] Memory device 100 may include at least one memory block. Each memory block may include multiple pages. A page may include multiple memory cells. That is, each memory block may include multiple memory cells. Here, each memory cell may be the smallest unit for storing data. In one embodiment, a memory cell may be implemented using a transistor that includes a control gate, an insulating layer, and a floating gate. For example, when a programming voltage is applied to the control gate of a memory cell, electrons can be stored in the floating gate of the memory cell through tunneling. In this case, the threshold voltage of the memory cell may vary based on the number of electrons stored in the floating gate. The threshold voltage of the memory cell may belong to any of a plurality of programming states with different voltage ranges. The programming state of the memory cell may indicate the value of the data stored in the memory cell.

[0034] The memory controller 200 can control the overall operation of the memory device 100. For example, the memory controller 200 can control the memory device 100 to perform programming operations to store data, reading operations to request stored data, or erasing operations to erase stored data.

[0035] In one embodiment, memory controller 200 can control memory device 100 such that memory device 100 performs programming, reading, or erasing operations in response to requests received from host 20. For example, when receiving a data storage request, data read request, or data erase request from host 20, memory controller 200 can generate a command corresponding to the data storage request, read request, or erase request. Furthermore, when receiving a logical address from host 20, memory controller 200 can translate the logical address into a physical address. Here, the physical address may be a unique identifier indicating a memory block or page included in memory device 100. Memory controller 200 can send the physical address along with a command to memory device 100.

[0036] In one embodiment, during a programming operation, the memory controller 200 can provide the memory device 100 with programming commands, addresses, and data. Here, the address can be a physical address. When receiving programming commands, addresses, and data from the memory controller 200, the memory device 100 can perform a programming operation to store page data in the page selected by the address.

[0037] In one embodiment, during a read operation, the memory controller 200 may provide a read command and address to the memory device 100. When receiving the read command and address from the memory controller 200, the memory device 100 may perform a read operation that provides page data stored in the page selected by the address to the memory controller 200.

[0038] In one embodiment, during an erase operation, the memory controller 200 may provide an erase command and address to the memory device 100. When receiving the erase command and address from the memory controller 200, the memory device 100 may perform an erase operation to delete the page data stored in the memory block selected by the address.

[0039] In other embodiments, regardless of the request received from host 20, memory controller 200 can control memory device 100 to perform programming, reading, or erasing operations internally. For example, memory controller 200 can control memory device 100 to perform wear leveling, read recycling, or garbage collection. To this end, memory controller 200 can internally generate commands, addresses, and data, and can send commands, addresses, and data to memory device 100.

[0040] The memory device 100 can store data based on various types of data storage schemes. For example, data storage schemes may include single-level cell (SLC), multi-level cell (MLC), three-level cell (TLC), and four-level cell (QLC) schemes. An SLC scheme can be used to store one bit in a memory cell. An MLC scheme can be used to store two bits in a memory cell. A TLC scheme can be used to store three bits in a memory cell. A QLC scheme can be used to store four bits in a memory cell.

[0041] In the SLC scheme, a memory cell can have one of two programming states based on the memory cell's threshold voltage. Here, each of the two programming states can indicate one of two binary values, such as "1" and "0". That is, a memory cell can store one of two binary values. In this case, the number of read voltage levels required to distinguish the two programming states from each other can be 1.

[0042] In the case of an MLC scheme, a memory cell can have one of four programming states based on the threshold voltage of the memory cell. Each of the four programming states can indicate one of four binary values, such as "11", "10", "01", and "00". That is, a memory cell can store one of four binary values. In this case, the number of read voltage levels required to distinguish the four programming states from each other can be 3.

[0043] Similarly, in the TLC scheme, a memory cell can have one of eight programming states based on the memory cell's threshold voltage, and each of the eight programming states can correspond to one of eight binary values, such as "111" to "000". In this case, the number of read voltage levels required to distinguish the eight programming states from one another can be 7. In the QLC scheme, a memory cell can have one of 16 programming states based on the memory cell's threshold voltage, and each of the 16 programming states can correspond to one of 16 binary values, such as "1111" to "0000". In this case, the number of read voltage levels required to distinguish the 16 programming states from one another can be 15.

[0044] The memory device 100 can perform a read operation to read data stored in a memory cell. The read operation can be an operation of applying a read voltage to a selected word line and applying a pass voltage to an unselected word line. The pass voltage can be a voltage used to turn on the channel of the unselected memory cell during the read operation.

[0045] The memory device 100 can perform read operations based on an underdrive scheme. An underdrive scheme can be a method of gradually reducing the read voltage level during a read operation. For example, an underdrive scheme can be a scheme for gradually reducing the read voltage so that the read voltage level changes from the highest of a plurality of preset levels to the second highest level. Here, the memory cell read based on the underdrive scheme can be a memory cell that stores data using a scheme such as an MLC scheme, a TLC scheme, or a QLC scheme.

[0046] When the read voltage decreases, the memory device 100 can decrease the pass voltage applied to the target word line directly adjacent to the selected word line along with the read voltage. That is, the memory device 100 can decrease the pass voltage applied to the target word line synchronously with the time point of the read voltage decrease. Here, the change in pass voltage (amount of change) can be less than the change in read voltage (amount of change). According to the above embodiments of this disclosure, the memory device 100 can reduce the time required for read operations. Embodiments of this disclosure will be described in detail below with reference to the accompanying drawings.

[0047] Figure 2 This is a diagram illustrating the structure of a memory device according to one embodiment.

[0048] refer to Figure 2 The memory device 100 may include a memory cell array 110, peripheral circuitry 120, and control logic 130.

[0049] The memory cell array 110 may include multiple memory blocks BLK1 to BLKz. Individual memory blocks may be configured to have the same structure. In the following description, for convenience, any one of the multiple memory blocks BLK1 to BLKz will be described in detail.

[0050] A memory block BLKz may include multiple pages. Each page may include a memory cell. That is, a memory block BLKz may include multiple memory cells. The multiple memory cells may be arranged in a two-dimensional (2D) plane or in a three-dimensional (3D) vertical structure. Here, each memory cell may be a semiconductor memory element. In one embodiment, each memory cell may be a non-volatile memory element.

[0051] The memory block BLKz can be coupled to the address decoder 121 of the peripheral circuitry 120 via row lines RL. Here, row lines RL can include multiple word lines. That is, the memory block BLKz can be coupled to multiple word lines. Here, a page in the memory block BLKz can be coupled to one word line. That is, the memory cells included in a page can be collectively coupled to one word line. Simultaneously, each page included in the memory block BLKz can be coupled to bit lines BL1 to BLm. Bit lines BL1 to BLm can be respectively coupled to the page buffers PB1 to PBm of the peripheral circuitry 120. (See later...) Figure 3 This describes the detailed structure of the memory block BLKz.

[0052] The peripheral circuit 120 can operate under the control of the control logic 130. The peripheral circuit 120 can perform programming operations, reading operations, or erasing operations.

[0053] The peripheral circuit 120 may include an address decoder 121, a voltage generator 122, a read and write circuit 123, a data input / output circuit 124, and a sensing circuit 125.

[0054] Address decoder 121 can be coupled to memory cell array 110 via row lines RL. For example, refer to Figure 2 and Figure 3The row line RL may include a drain select line DSL, multiple word lines WL1 to WL16, a source select line SSL, and a source line SL. In one embodiment, the address decoder 121 may include components such as a row decoder, a column decoder, and an address buffer.

[0055] Address decoder 121 can operate under the control of control logic 130. In one example, address decoder 121 can receive address ADDR from control logic 130. Address decoder 121 can decode the block address and page address included in the received address ADDR. Here, the block address can indicate a specific memory block. The page address can indicate a specific page or a specific word line. That is, a specific memory block can be selected based on the block address, and a specific page or a specific word line can be selected based on the page address. Address decoder 121 can apply an operating voltage Vop to the selected memory block or a selected page within the selected memory block. The operating voltage Vop can be provided from voltage generator 122.

[0056] Voltage generator 122 can generate various types of operating voltage Vop using an external power supply provided to memory device 100. Here, the external power supply can be a backup power supply included in memory system 10 or the power supply of host 20. The operating voltage Vop can include one of a voltage for programming operations, a voltage for reading operations, and a voltage for erasing operations. The voltage for programming operations can include a programming voltage, a programming pass voltage, a verification voltage, and a verification pass voltage. The voltage for reading operations can include a read voltage, a first pass voltage, and a second pass voltage. The voltage for erasing operations can include a first erase voltage and a second erase voltage. Voltage generator 122 can operate under the control of control logic 130. For example, when receiving an operation signal OPSIG from control logic 130, voltage generator 122 can transmit the operating voltage Vop corresponding to the operation signal OPSIG to address decoder 121.

[0057] The read and write circuitry 123 may include multiple page buffers PB1 to PBm. Each of the multiple page buffers PB1 to PBm may be coupled to the memory cell array 110 via corresponding bit lines of multiple bit lines BL1 to BLm. For example, the first page buffer PB1 may be commonly coupled via the first bit line BL1 to a memory cell indicating a first column included in each of the multiple memory blocks BLK1 to BLK2. Each of the multiple page buffers PB1 to PBm may temporarily store data DATA. For this purpose, each of the multiple page buffers PB1 to PBm may be implemented using various memory elements such as latching circuitry.

[0058] The read and write circuit 123 can operate under the control of the control logic 130. In one embodiment, the read and write circuit 123 can perform an operation corresponding to a buffer control signal PBSIGNALS received from the control logic 130. For example, in response to the buffer control signal PBSIGNALS, the read and write circuit 123 can apply a voltage corresponding to the data DATA to each of the multiple bit lines BL1 to BLm, or can sense the voltage of each of the multiple bit lines BL1 to BLm, and then read the data DATA. In this way, the data DATA temporarily stored in the multiple page buffers PB1 to PBm can be stored in a specific area of ​​the memory cell array 110, or alternatively, the data DATA stored in a specific area of ​​the memory cell array 110 can be read and temporarily stored in the multiple page buffers PB1 to PBm. Here, the specific area can be a page indicated by a page address.

[0059] Data input / output circuit 124 can be coupled to read and write circuit 123 via data line DL. Data input / output circuit 124 may include multiple input / output buffers for receiving input data DATA. Data input / output circuit 124 can operate in response to control signals output from control logic 130. For example, when receiving a control signal from control logic 130, data input / output circuit 124 can output temporarily stored data DATA to read and write circuit 123 via data line DL, or it can output temporarily stored data DATA to memory controller 200 via a channel.

[0060] Sensing circuit 125 can generate a reference voltage in response to an enable bit signal VRYBIT received from control logic 130. Sensing circuit 125 can output either a pass signal PASS or a failure signal FAIL to control logic 130 based on the result of comparing the sensed voltage VPB received from read and write circuit 123 with the reference voltage. Here, the pass signal PASS can indicate success in a programming pulse operation or a read operation. The failure signal FAIL can indicate failure in a programming pulse operation or a read operation.

[0061] Control logic 130 can control the overall operation of memory device 100. Control logic 130 can control peripheral circuitry 120 to perform programming, reading, or erasing operations in response to commands CMD and addresses ADDR received from memory controller 200. Here, command CMD can be a programming command, a reading command, or an erasing command. For this purpose, control logic 130 can be coupled to peripheral circuitry 120. For example, control logic 130 can be coupled to address decoder 121, voltage generator 122, read and write circuitry 123, data input / output circuitry 124, and sensing circuitry 125.

[0062] In one embodiment, upon receiving a programming command and address ADDR from memory controller 200, control logic 130 can control peripheral circuitry 120 to perform a programming operation that stores data DATA in the selected page corresponding to address ADDR. Here, data DATA may include data corresponding to one or more pages. In one example, in a TLC scheme, data DATA may include least significant bit (LSB) page data, middle significant bit (CSB) page data, and most significant bit (MSB) page data. In one example, in an MLC scheme, data DATA may include LSB page data and MSB page data.

[0063] In one embodiment, control logic 130 can control peripheral circuitry 120 to perform programming operations based on an Incremental Step Pulse Programming (ISPP) scheme. For example, an ISPP-based programming operation may include multiple programming cycles. Each programming cycle may include a programming pulse operation and a programming verification operation executed sequentially. A programming pulse operation may be an operation that applies a programming voltage to a selected page to change a threshold voltage. A programming verification operation may be an operation that applies a verification voltage to the selected page to verify whether the programming pulse operation was successful or failed. When the result of the verification operation indicates that the programming pulse operation was successful, control logic 130 may terminate the programming operation. When the result of the verification operation indicates that the programming pulse operation failed, control logic 130 may control peripheral circuitry 120 to execute subsequent programming cycles with increasing programming voltage levels.

[0064] In one embodiment, when a read command and address ADDR are received from the memory controller 200, the control logic 130 can control the peripheral circuitry 120 to perform a read operation to read data DATA stored in the selected page corresponding to address ADDR. Furthermore, the control logic 130 can control the peripheral circuitry 120 to send the data DATA read from the selected page to the memory controller 200.

[0065] For example, when receiving a read command and address ADDR from memory controller 200, control logic 130 can control peripheral circuitry 120 to apply a read voltage to the selected page in memory block BLKz corresponding to address ADDR, and to apply a pass voltage to the unselected pages in memory block BLKz. Furthermore, control logic 130 can control peripheral circuitry 120 to send the read page data to memory controller 200.

[0066] Meanwhile, some of the memory blocks BLK1 to BLK2 can be system memory blocks or content-addressable memory (CAM) blocks. System memory blocks or CAM blocks can store information related to the operation of memory device 100. For example, information related to the operation of memory device 100 may include the default level of the programming voltage, the default level of the read voltage, information about bad blocks, the number of failure bits, etc.

[0067] Control logic 130 can apply voltages to the selected word line and the unselected word line in a progressive manner during a read operation. Specifically, control logic 130 can reduce the read voltage based on a read voltage change during the read operation. Furthermore, when the read voltage decreases, control logic 130 can reduce a first pass voltage based on a pass voltage change. Here, the pass voltage change can be less than the read voltage change. The read voltage can be the voltage applied to the selected word line, and the first pass voltage can be the voltage applied to a target word line among the unselected word lines that is directly adjacent to the selected word line.

[0068] When the read voltage decreases, control logic 130 can maintain the second pass voltage. Here, the second pass voltage can be the voltage applied to a word line other than the target word line among the unselected word lines.

[0069] In one embodiment, control logic 130 may include operation controller 131 and table storage unit 133.

[0070] The operation controller 131 can control the peripheral circuit 120 to perform a read operation. Specifically, the operation controller 131 can control the peripheral circuit 120 to perform a read operation, which applies a read voltage to a selected word line among multiple word lines and applies a first pass voltage to a target word line directly adjacent to the selected word line among the unselected word lines. Here, the multiple word lines can be coupled to a memory block BLKz. The selected word line can be a word line selected from the multiple word lines by address ADDR. The unselected word line can be a word line among the multiple word lines that was not selected by address ADDR.

[0071] The table storage unit 133 can store voltage information, which includes values ​​of read voltage changes and values ​​of pass voltage changes corresponding to multiple reference times. For example, the voltage information may include information such as a first value of read voltage change corresponding to a first reference time, a first value of pass voltage change corresponding to the first reference time, a second value of read voltage change corresponding to a second reference time, and a second value of pass voltage change corresponding to the second reference time. Here, each reference time may be a preset time, a time point, or a time period.

[0072] In one embodiment, the operation controller 131 can control the timing of applying the read voltage and the pass voltage. The operation controller 131 can control the level of the read voltage and the level of each pass voltage.

[0073] When the read voltage decreases, the operation controller 131 can reduce the read voltage based on the change in read voltage, and can also reduce the first pass voltage based on the change in pass voltage, where the change in pass voltage is less than the change in read voltage. That is, the operation controller 131 can control the peripheral circuit 120 to reduce both the read voltage and the first pass voltage at the same time. In one embodiment, whenever the read voltage decreases, the operation controller 131 can control the peripheral circuit 120 to reduce the first pass voltage.

[0074] In one embodiment, the operation controller 131 can sense the state of selected memory cells coupled to the selected word line by applying a read voltage having a first voltage level to the selected word line. Specifically, the operation controller 131 can control the peripheral circuitry 120 to apply a read voltage having the first voltage level to the selected word line, apply a first pass voltage to a target word line among the unselected word lines, and apply a second pass voltage to the remainder of the unselected word lines. Furthermore, the operation controller 131 can receive from the peripheral circuitry 120 the result of sensing the state of selected memory cells coupled to the selected word line among a plurality of memory cells based on the first voltage level. The sensing result may include information relating to memory cells coupled to the selected word line that have a threshold voltage equal to or greater than the first voltage level, or memory cells that have a threshold voltage less than the first voltage level. Here, the first voltage level may correspond to a programming state.

[0075] After the state of the selected memory cell is sensed, the operation controller 131 can reduce the read voltage from a first voltage level to a second voltage level based on the read voltage change. When the read voltage decreases, the operation controller 131 can reduce the first pass voltage based on the pass voltage change. Here, the first voltage level can be a voltage level higher than the second voltage level. When the read voltage decreases, the operation controller 131 can control the peripheral circuitry 120 to maintain the second pass voltage. Furthermore, the operation controller 131 can sense the state of the selected memory cell coupled to the selected word line based on the second voltage level.

[0076] Figure 3 This is a diagram illustrating the structure of a memory block according to one embodiment.

[0077] refer to Figure 3The memory block BLKz may include multiple memory cells MC1 to MC16 coupled to multiple word lines WL1 to WL16. The memory block BLKz may include multiple strings. Since multiple strings can be configured similarly, the string ST coupled to the first bit line BL1 will be described as an example.

[0078] The first end of string ST can be coupled to any one of multiple bit lines BL1 to BLm. For example, the first end of string ST can be coupled to the first bit line BL1. The second end of string ST can be coupled to the source line SL. Here, a source line SL can be coupled to multiple strings, and a bit line can be coupled to a single string.

[0079] The string ST may include a source selection transistor SST coupled in series with each other between the source line SL and the first bit line BL1, a plurality of memory cells MC1 to MC16, and a drain selection transistor DST. In one embodiment, the string ST may include at least one source selection transistor SST and at least one drain selection transistor DST, and may also include more memory cells than the memory cells MC1 to MC16 shown in the figure.

[0080] The gate of the source-select transistor SST can be coupled to the source-select line SSL, and the gate of the drain-select transistor DST can be coupled to the drain-select line DSL. The source of the source-select transistor SST can be coupled to the source line SL, and the drain of the drain-select transistor DST can be coupled to the first bit line BL1.

[0081] The gates of multiple memory cells MC1 to MC16 can be coupled to multiple word lines WL1 to WL16 respectively. Memory cells MC1 to MC16 can be arranged between the source selection transistor SST and the drain selection transistor DST, and coupled in series to the source selection transistor SST and the drain selection transistor DST.

[0082] A memory block BLKz can include multiple pages. A page PG can be defined as a group of memory cells commonly coupled to the same word line. Here, a page PG can be a set of memory cells corresponding to a unit on which a programming or read operation is performed. A memory block BLKz can be a set of memory cells corresponding to a unit on which an erase operation is performed.

[0083] Page PGs can store page data. The number of page data segments can be determined based on the number of bits of data stored in each memory cell. In one example, in the SLC scheme, one page data segment can be stored in one page PG. In one example, in the MLC scheme, two page data segments can be stored in one page PG. In one example, in the TLC scheme, three page data segments can be stored in one page PG.

[0084] Figure 4A and Figure 4B This is a diagram illustrating the threshold voltage distribution of a memory cell according to an embodiment of the present disclosure.

[0085] refer to Figure 4A Each memory cell programmed via the MLC scheme can have a threshold voltage corresponding to the first threshold voltage distribution 410. In this case, each memory cell can have one programming state among multiple programming states P0 to P3 corresponding to its threshold voltage. The multiple programming states P0 to P3 can include programming states 0 to 3. Among the multiple programming states P0 to P3, the third programming state P3 can be the highest state, while programming state 0 can be the lowest state. Here, programming state 0 can be the erase state in which each memory cell returns to the result of performing an erase operation.

[0086] refer to Figure 4B Each memory cell programmed via the TLC scheme can have a threshold voltage corresponding to the second threshold voltage distribution 420. Each memory cell can have one programming state among a plurality of programming states P0 to P7 corresponding to its threshold voltage. The plurality of programming states P0 to P7 can include programming states 0 through 7. Among the plurality of programming states P0 to P7, the 7th programming state P7 can be the highest state, and programming state 0 can be the lowest state. Here, programming state 0 can be the erase state in which each memory cell returns to the result of performing an erase operation.

[0087] In one embodiment, in the case of an MLC scheme, the memory device 100 can identify the corresponding programming state of a memory cell coupled to a selected word line by applying a read voltage having a first voltage level R1 to a third voltage level R3 to the selected word line. For example, the memory device 100 can identify the corresponding programming state of the memory cell while gradually decreasing the read voltage. That is, the read voltage can be gradually decreased such that the higher programming state among multiple programming states is sensed first. Furthermore, whenever the voltage level of the read voltage decreases, the memory device 100 can decrease the voltage level of the first pass voltage applied to the target word line. The target word line can be a word line directly adjacent to the selected word line.

[0088] In detail, control logic 130 can control peripheral circuit 120 to apply a read voltage with a third voltage level R3 to selected word lines among multiple word lines coupled to memory block BLKz, and to unselected word lines by applying voltage. Here, memory cells with a threshold voltage lower than the third voltage level R3 can be turned on. That is, a current-carrying path can be formed in memory cells with a threshold voltage lower than the third voltage level R3. At the same time, memory cells with a threshold voltage higher than the third voltage level R3 can be turned off. That is, a path may not be formed in memory cells with a threshold voltage higher than the third voltage level R3. In this case, control logic 130 can identify that the turned-off memory cell has a third programming state P3.

[0089] Furthermore, control logic 130 can control peripheral circuitry 120 to apply a read voltage with a second voltage level R2 to selected word lines among multiple word lines coupled to memory block BLKz, and to unselected word lines. Here, control logic 130 can reduce the read voltage level from a third voltage level R3 to a second voltage level R2. Furthermore, when the read voltage decreases, control logic 130 can decrease the level of the first pass voltage applied to the target word line among the unselected word lines. Furthermore, when the read voltage and the first pass voltage levels decrease, control logic 130 can maintain the level of the second pass voltage applied to the word lines other than the target word line among the unselected word lines. In this case, memory device 100 can identify that, among memory cells other than those with a third programming state P3, the turned-off memory cells have a second programming state P2.

[0090] Furthermore, control logic 130 can control peripheral circuitry 120 to apply a read voltage with a first voltage level R1 to selected word lines among multiple word lines coupled to memory block BLKz, and to apply a voltage to unselected word lines. Here, control logic 130 can reduce the read voltage level from a second voltage level R2 to a first voltage level R1. Furthermore, when the read voltage decreases, control logic 130 can reduce the level of a first pass voltage applied to the target word line among the unselected word lines. Furthermore, when the read voltage and the first pass voltage levels decrease, control logic 130 can maintain the level of a second pass voltage. In this case, control logic 130 can identify that among memory cells other than those with a third programming state P3 or a second programming state P2, the turned-off memory cell has a first programming state P1. Furthermore, control logic 130 can identify that the turned-on memory cell has a 0th programming state P0.

[0091] Similarly, in the case of a TLC scheme, the memory device 100 can identify the corresponding programming state of the memory cell coupled to the selected word line by applying a read voltage having a first voltage level R1 to a seventh voltage level R7 to the selected word line.

[0092] Figure 5A and Figure 5B This is a diagram illustrating the voltage applied to a word line according to one embodiment. Here, Figure 5A Table 510 shows the read voltage VR applied to the selected word line Sel_WL and the pass voltages VRpass1 and VRpass2 applied to the unselected word lines Unsel_WLs during a read operation. Figure 5B The illustration shows memory block 520 coupled with the selected word line Sel_WL and the unselected word lines Unsel_WLs.

[0093] refer to Figure 5A and Figure 5B When receiving a read command and address ADDR from the memory controller 200, the control logic 130 can determine the selected word line Sel_WL and the unselected word line Unsel_WLs based on the address ADDR.

[0094] The selected word line Sel_WL can be one of the multiple word lines WL1 to WLz coupled to memory block 520, indicated by address ADDR. The unselected word lines Unsel_WLs can be any of the multiple word lines WL1 to WLz coupled to memory block 520 other than the selected word line Sel_WL. For example, when the selected word line Sel_WL is the nth word line WLn, the unselected word lines Unsel_WLs can include the first word lines WL1 to the (n-1)th word lines WLn-1 and the (n+1)th word lines WLn+1 to the zth word lines WLz.

[0095] Here, control logic 130 can determine the (n+1)th word line WLn+1 and the (n-1)th word line WLn-1, which are directly adjacent to the selected word line Sel_WL, among the unselected word lines Unsel_WLs, as target word lines WLn+1 and WLn-1. Furthermore, control logic 130 can determine the word lines in the unselected word lines Unsel_WLs other than the target word lines WLn+1 and WLn-1 as other word lines (Other WLs). In other words, other word lines (Other WLs) can be the remaining word lines. In one embodiment, when the selected word line Sel_WL is the nth word line WLn, the remaining word lines can be word lines other than the target word lines WLn+1 and WLn-1 and the selected word line Sel_WL.

[0096] Memory cells MCn+1 and MCn-1 coupled to target word lines WLn+1 and WLn-1 can have a closest positional relationship with respect to memory cells MCn coupled to the selected word line WLn. This closest positional relationship indicates the shortest distance between memory cells. Therefore, the level of the through voltage applied to target word lines WLn+1 and WLn-1 can affect the threshold voltage of the memory cell MCn coupled to the selected word line WLn or the selected word line WLn itself.

[0097] Furthermore, control logic 130 can control peripheral circuitry 120 to perform read operations. For example, a read operation could be an operation of applying a read voltage VR to the nth word line WLn, applying a first pass voltage VRpass1 to target word lines WLn+1 and WLn-1 directly adjacent to the selected word line Sel_WL in the unselected word lines Unsel_WLs, and applying a second pass voltage VRpass2 to other word lines Other WLs in the unselected word lines Unsel_WLs.

[0098] In one embodiment, control logic 130 may reduce the voltage level of read voltage VR from a first voltage level to a second voltage level based on a read voltage change, and may also reduce the voltage level of a first pass voltage VRpass1 based on the pass voltage change when the voltage level of read voltage VR decreases. Here, the first voltage level may be a voltage level higher than the second voltage level. In one embodiment, the first voltage level may be a voltage level used to sense a first programming state among a plurality of programming states, and the second voltage level may be a voltage level used to sense a second programming state, in which the second programming state is lower than the first programming state.

[0099] Specifically, control logic 130 can progressively reduce the voltage level of the read voltage VR during the read operation, such that the voltage level is one of multiple voltage levels. Each of the multiple voltage levels can be a level preset to read one of multiple programming states. That is, control logic 130 can reduce the voltage level of the read voltage VR based on the read voltage change at each step. Here, the steps can be distinguished from each other based on a reference time.

[0100] During a read operation, when the read voltage VR decreases, control logic 130 may decrease the voltage level of the first pass voltage VRpass1. That is, control logic 130 may decrease the voltage level of the first pass voltage VRpass1 based on the pass voltage change at each step. Here, the pass voltage change may have a value lower than the read voltage change. In one embodiment, during a read operation, whenever the read voltage VR decreases, control logic 130 may decrease the voltage level of the first pass voltage VRpass1. Simultaneously, during a read operation, when the read voltage VR decreases, control logic 130 may maintain the voltage level of the second pass voltage VRpass2.

[0101] In one embodiment, whenever any of a plurality of reference times is reached, control logic 130 may reduce the voltage level of the read voltage VR based on the value of the read voltage change corresponding to a reference time. Furthermore, when the read voltage VR decreases, control logic 130 may reduce the voltage level of the first pass voltage VRpass1 based on the value of the pass voltage change corresponding to any reference time.

[0102] In one embodiment, when a first reference time among a plurality of reference times is reached, control logic 130 may reduce the voltage level of the read voltage VR based on a first value of the read voltage change corresponding to the first reference time. Furthermore, when the voltage level of the read voltage VR decreases, control logic 130 may reduce the voltage level of the first through voltage VRpass1 based on a first value of the through voltage change corresponding to the first reference time. The time point at which the read voltage VR decreases may be the first reference time. In one embodiment, the first value of the through voltage change may be a value obtained by multiplying a first ratio value by the first value of the read voltage change.

[0103] Furthermore, when a second reference time is reached after a first reference time, control logic 130 can reduce the voltage level of the read voltage VR based on a second value of the read voltage change corresponding to the second reference time. Additionally, when the read voltage VR decreases, control logic 130 can reduce the voltage level of the first through voltage VRpass1 based on a second value of the through voltage change corresponding to the second reference time. The time point at which the read voltage VR decreases can be the second reference time. In one embodiment, the second value of the through voltage change can be a value obtained by multiplying a second ratio value by the second value of the read voltage change.

[0104] In one embodiment, the first ratio value may be equal to or greater than the second ratio value. In other embodiments, the first ratio value may be less than or equal to the second ratio value.

[0105] Although Figure 5B In the diagram, one of the memory cells MC1 to MCz coupled to the first line BL1 is shown as being included in one page (one of PG1 to PGz), but this configuration is provided for ease of description only and can be modified and practiced in cases where two or more memory cells are included in one page (one of PG1 to PGz).

[0106] Figure 6A and Figure 6B This is a timing diagram illustrating the operation of a memory device according to one embodiment.

[0107] refer to Figure 6A and Figure 6B According to one embodiment, the memory device 100 can store voltage level information. In one example, the level information can be stored in a table storage unit 133. In another example, the level information can be stored in a CAM block of the memory device 100. When a read command is received, the memory device 100 according to one embodiment can apply an electrical current corresponding to the corresponding word line coupled to the memory block by using the level information.

[0108] Data is read using compression. For example, level information can be read in the form of... Figure 6A The format shown is used for storage. When operations are performed using level information, such as... Figure 6B The graph shown indicates the level of the actual voltage sensed. Here, Figure 6A and Figure 6B The example shown is reading data stored in an MLC scheme.

[0109] The level information may include information related to the voltage levels corresponding to the multiple time intervals T1 to T4, respectively. For example, in the case of an MLC scheme, the multiple time intervals T1 to T4 may include a first time interval T1 to a fourth time interval T4. In this case,

[0110] The first time interval T1 can be the time interval for performing an overcharge operation. The second time interval T2 to the fourth time interval T4 can be the time interval for performing a read operation. An overcharge operation can be an operation that applies a voltage equal to or higher than the voltage level applied during the read operation. Simultaneously, the voltage level information can be stored as data in various forms, such as graphs or tables.

[0111] In one embodiment, the level information may include information relating to voltage levels r1, r2, and r3 of the read voltages VR applied to the second to fourth time intervals T2 to T4, voltage levels p11, p12, and p13 of the first pass voltage VRpass1, and voltage levels p21, p22, and p23 of the second pass voltage VRpass2. In one embodiment, the level information may also include information relating to peak levels r0, p10, and p20 of an overcharge voltage applied during the first time interval T1. The overcharge voltage may be a voltage applied during the first time interval T1 to the selected word line Sel_WL, the target word line, and other word lines. Peak levels r0, p10, and p20 may include a first peak level r0, a second peak level p10, and a third peak level p20. In one example, the first peak level r0, the second peak level p10, and the third peak level p20 may be equal to each other. In one example, the first peak level...

[0112] Level r0, the second peak level p10, and the third peak level p20 can be different from each other. In one example, at least two of the first peak level r0, the second peak level p10, and the third peak level p20 can be equal to each other.

[0113] The voltage levels r1, r2, and r3 of the read voltage VR can include a first voltage level r1, a second voltage level r2, and a third voltage level r3. The first voltage level r1 of the read voltage VR can indicate the magnitude of the read voltage VR applied to the selected word line Sel_WL during the second time period T2. The second voltage level r2 of the read voltage VR can indicate the magnitude of the read voltage VR applied to the selected word line Sel_WL during the third time period T3, which follows the second time period T2. The third voltage level r3 of the read voltage VR can indicate the magnitude of the read voltage VR applied to the selected word line Sel_WL during the fourth time period T4, which follows the third time period T3.

[0114] The first voltage level r1 of the read voltage VR can be less than the first peak level r0 of the overcharge voltage. The second voltage level r2 of the read voltage VR can be less than the first voltage level r1. The third voltage level r3 of the read voltage VR can be less than the second voltage level r2. That is, the voltage levels r1, r2, and r3 of the read voltage VR can be gradually decreased in the order of the first voltage level r1, the second voltage level r2, and the third voltage level r3. In this case, the memory device 100 can sense a memory cell with a relatively high threshold voltage by using the read voltage VR with the first voltage level r1 during the second time period T2. The memory device 100 can sense a memory cell with a relatively intermediate threshold voltage by using the read voltage VR with the second voltage level r2 during the third time period T3. The memory device 100 can sense a memory cell with a relatively low threshold voltage by using the read voltage VR with the third voltage level r3 during the fourth time period T4.

[0115] The voltage levels p11, p12, and p13 of the first pass voltage VRpass1 may include a first voltage level p11, a second voltage level p12, and a third voltage level p13. The first voltage level p11 of the first pass voltage VRpass1 may indicate the magnitude of the first pass voltage VRpass1 applied to the target word line during the second time period T2. The second voltage level p12 may indicate the magnitude of the first pass voltage VRpass1 applied to the target word line during the third time period T3. The third voltage level p13 may indicate the magnitude of the first pass voltage VRpass1 applied to the target word line during the fourth time period T4.

[0116] The first voltage level p11 of the first through voltage VRpass1 can be less than the second peak level p10 of the overcharge voltage. The second voltage level p12 of the first through voltage VRpass1 can be less than the first voltage level p11. The third voltage level p13 of the first through voltage VRpass1 can be less than the second voltage level p12. That is, the voltage levels p11, p12, and p13 of the first through voltage VRpass1 can be progressively reduced in the order of first voltage level p11, second voltage level p12, and third voltage level p13. However, this configuration is only one embodiment and can be modified and practiced in a form where at least two of the first voltage level p11, second voltage level p12, and third voltage level p13 are equal to each other.

[0117] In one embodiment, the values ​​dp1, dp2, and dp3 of the voltage changes can be determined based on reading the values ​​dr1, dr2, and dr3 of the voltage changes.

[0118] The values ​​drl, dr2, and dr3 for reading voltage changes can include a first value drl, a second value dr2, and a third value dr3. Specifically, the first value dr1 for reading voltage changes can be the difference between the first peak level r0 of the overcharge voltage and the first voltage level r1 of the read voltage VR at the first time point t1, and the first value dp1 for reading voltage changes can be the difference between the second peak level p10 of the overcharge voltage and the first voltage level p11 of the first pass voltage VRpass1 at the first time point t1. The second value dr2 for reading voltage changes can be the difference between the first voltage level r1 and the second voltage level r2 of the read voltage VR at the second time point t2, and the second value dp2 for reading voltage changes can be the difference between the first voltage level p11 and the second voltage level p12 of the first pass voltage VRpass1 at the second time point t2. The third value of the voltage change dr3 can be read at the third time point t3, which is the difference between the second voltage level r2 and the third voltage level r3 of the voltage VR. The third value of the voltage change dp3 can be read at the third time point t3, which is the difference between the second voltage level p12 and the third voltage level p13 of the first voltage VRpass1.

[0119] The voltage levels p21, p22, and p23 of the second pass voltage VRpass2 may include a first voltage level p21, a second voltage level p22, and a third voltage level p23. The first voltage level p21 of the second pass voltage VRpass2 may indicate the magnitude of the second pass voltage VRpass2 applied to the word line Other WLs among the unselected word lines Unsel_WLs during the second time period T2. The second voltage level p22 may indicate the magnitude of the second pass voltage VRpass2 applied to the word line Other WLs among the unselected word lines Unsel_WLs during the third time period T3. The third voltage level p23 may indicate the magnitude of the second pass voltage VRpass2 applied to the word line Other WLs among the unselected word lines Unsel_WLs during the fourth time period T4.

[0120] The first voltage level p21 of the second through voltage VRpass2 can be less than or equal to the third peak level p20 of the overcharge voltage. The second voltage level p22 of the second through voltage VRpass2 can be equal to the first voltage level p21. The third voltage level p23 of the second through voltage VRpass2 can be equal to the second voltage level p22. That is, the voltage levels p21, p22, and p23 of the second through voltage VRpass2 can be maintained at the same levels as the first voltage level p21, the second voltage level p22, and the third voltage level p23.

[0121] According to the detailed embodiment, the control logic 130 can perform operations by using level information when a read command and address ADDR are received. Here, it is assumed that address ADDR indicates the nth word line or the nth page coupled to the nth word line WLn.

[0122] In this case, control logic 130 can determine the nth word line WLn indicated by address ADDR as the selected word line Sel_WL. Furthermore, control logic 130 can determine the (n+1)th word line WLn+1 and the (n-1)th word line WLn-1 adjacent to the nth word line Sel_WL among the unselected word lines Unsel_WLs as target word lines WLn+1 and WLn-1. Additionally, control logic 130 can determine the word lines other than the target word lines WLn+1 and WLn-1 among the unselected word lines Unsel_WLs as Other word lines. Here, the unselected word lines Unsel_WLs can include word lines other than the selected word line Sel_WL among the multiple word lines included in the memory block.

[0123] At time point t0, control logic 130 can control peripheral circuitry 120 to perform an overcharge operation that applies an overcharge voltage to the selected word line Sel_WL, the target word lines WLn+1 and WLn-1, and other word lines Other WLs. Here, the overcharge voltage can be a voltage applied before performing the read operation.

[0124] Control logic 130 can increase the overcharge voltage level until it reaches peak levels r0, p10, and p20. The overcharge voltage can be a voltage applied before the read operation to allow the voltage level applied to each word line to quickly reach the target level, and this can be advantageous because the time required for the read operation can be shortened. For example, the time period for performing the overcharge operation can be a first time period T1, and the time period for performing the read operation can include second to fourth time periods T2 to T4.

[0125] In one embodiment, the peak level r0 of the overcharge voltage applied to the selected word line Sel_WL, the peak level p10 of the overcharge voltage applied to the target word lines WLn+1 and WLn-1, and the peak level p20 of the overcharge voltage applied to other word lines (Other WLs) can be equal to each other. In this case, each peak level can be a voltage level for turning on the channel of the corresponding memory cell. For example, the peak level can be the voltage level of the second pass voltage VRpass2 held during a read operation. However, this configuration is only one embodiment, and at least two of the peak levels r0 of the overcharge voltage applied to the selected word line Sel_WL, p10 of the overcharge voltage applied to the target word lines WLn+1 and WLn-1, and p20 of the overcharge voltage applied to other word lines (Other WLs) can be different voltage levels.

[0126] At the first time point t1, control logic 130 can control peripheral circuit 120 to perform a read operation. In one embodiment, the first time point t1 can be the time when the overcharge voltage level reaches the reference level or a time point thereafter. For example, the reference... Figure 6B In one embodiment, control logic 130 may increase the level of the overcharge voltage applied to the selected word line Sel_WL until the overcharge voltage level reaches a reference level. Here, the reference level may be the peak level r0. When the overcharge voltage level reaches the reference level, control logic 130 may control the peripheral circuitry 120 to perform a read operation.

[0127] In one embodiment, at a first time point tl, control logic 130 may control peripheral circuitry 120 to apply a read voltage VR to the selected word line Sel_WL, apply a first pass voltage VRpass1 to the target word lines WLn+1 and WLn-1, and apply a second pass voltage VRpass2 to the other word lines Other WLs. In one embodiment, the read voltage VR, the first pass voltage VRpass1, and the second pass voltage VRpass2 may be voltages reduced from the voltage level of an overcharge voltage.

[0128] In one embodiment, at a first time point t1 at the start of the second time period T2, control logic 130 can control peripheral circuitry 120 to apply a read voltage VR with a first voltage level r1 to the selected word line Sel_WL, where the first voltage level r1 decreases based on a first value dr1 of the read voltage change. The first value dr1 of the read voltage change can be a preset value indicating the difference between a first peak level r0, representing an overcharge voltage, and the first voltage level r1 of the read voltage VR. In this case, control logic 130 can control peripheral circuitry 120 to apply a first pass voltage VRpass1 with a first voltage level p11, decreasing based on a first value dp1 of the pass voltage change, to target word lines WLn+1 and WLn-1. The first value dp1 of the pass voltage change can be a preset value indicating the difference between a second peak level p10, representing an overcharge voltage, and the first voltage level p11 of the first pass voltage VRpass1.

[0129] After the first time point tl, the voltage level of the selected word line Sel_WL can be reduced based on a first value drl of the read voltage change, and then maintained at the first voltage level rl. In this case, the voltage levels of the target word lines WLn+1 and WLn-1 can be reduced based on a first value dp1 of the voltage change, and then maintained at the first voltage level p11. The voltage levels of the other word lines Other WLs can be maintained at the first voltage level p21. In one embodiment, the first value dp1 of the voltage change can be less than the first value dr1 of the read voltage change. In other embodiments, the first value dp1 of the voltage change can be equal to the first value dr1 of the read voltage change. Furthermore, the control logic 130 can sense memory cells in the selected memory cells coupled to the selected word line Sel_WL that have a programming state corresponding to the first voltage level r1. For example, in the case of an MLC, the programming state corresponding to the first voltage level r1 can be Figure 4A The third programming state P3 is shown.

[0130] At the second time point t2, control logic 130 can reduce the read voltage VR based on a second value dr2 of the read voltage change. When the read voltage VR decreases, control logic 130 can reduce the first pass voltage VRpass1 based on a second value dp2 of the pass voltage change.

[0131] After the second time point t2, the voltage level of the selected word line Sel_WL can be reduced based on a second value dr2 of the read voltage change, and then maintained at the second voltage level r2. In this case, the voltage levels of the target word lines WLn+1 and WLn-1 can be reduced based on a second value dp2 of the voltage change, and then maintained at the second voltage level p12. The voltage levels of the other word lines Other WLs can be maintained at the second voltage level p22. In one embodiment, the second value dp2 of the voltage change can be less than the second value dr2 of the read voltage change. In other embodiments, the second value dp2 of the voltage change can be equal to the second value dr2 of the read voltage change. Furthermore, the control logic 130 can sense a memory cell in the selected memory cell coupled to the selected word line Sel_WL that has a programming state corresponding to the second voltage level r2. For example, in the case of an MLC, the programming state corresponding to the second voltage level r2 can be... Figure 4A The second programming state P2 is shown.

[0132] At the third time point t3, control logic 130 can reduce the read voltage VR based on the third value dr3 of the read voltage change. When the read voltage VR decreases, control logic 130 can reduce the first pass voltage VRpass1 based on the third value dp3 of the pass voltage change.

[0133] After the third time point t3, the voltage level of the selected word line Sel_WL can be reduced based on the third value dr3 of the read voltage change, and then maintained at the third voltage level r3. In this case, the voltage levels of the target word lines WLn+1 and WLn-1 can be reduced based on the third value dp3 of the voltage change, and then maintained at the third voltage level p13. The voltage levels of the other word lines Other WLs can be maintained at the third voltage level p23. In one embodiment, the third value dp3 of the voltage change can be less than the third value dr3 of the read voltage change. In other embodiments, the third value dp3 of the voltage change can be equal to the third value dr3 of the read voltage change. Furthermore, the control logic 130 can sense memory cells in the selected memory cells coupled to the selected word line Sel_WL that have a programming state corresponding to the third voltage level r3. For example, in the case of an MLC scheme, the programming state corresponding to the third voltage level r3 can be as follows: Figure 4AThe first programming state P1 or the 0th programming state P0 is shown.

[0134] At the same time, refer to Figure 6B The time from the first time point t1 to the point where the level of the read voltage VR changes from the reference level r0 to the first voltage level r1, the time from the second time point t2 to the point where the level of the read voltage VR changes from the first voltage level r1 to the second voltage level r2, and the time from the third time point t3 to the point where the level of the read voltage VR changes from the second voltage level r2 to the third voltage level r3 can correspond to the delay time required for the delayed read operation. According to one embodiment of this disclosure, the level of the first pass voltage VRpass1 applied to the target word lines WLn+1 and WLn-1 adjacent to the selected word line Sel_WL can be reduced together at the synchronization time, and thus has the advantage of reducing the delay time.

[0135] According to one embodiment, the first through voltage VRpass1 may have a voltage level higher than the lower limit level ref. Here, the lower limit level may be a level at which the channel of the memory cell can be turned on and can be preset. For example, when the difference between the level of the first through voltage VRpass1 and the through voltage change value is determined to be less than or equal to the lower limit level ref, the control logic 130 may adjust the first through voltage VRpass1 to have the lower limit level ref.

[0136] Figure 7 This is a diagram illustrating voltage variations according to one embodiment.

[0137] refer to Figure 7 The table storage unit 133 can store first voltage information 710. The first voltage information 710 may include information related to the level change of the read voltage VR and the level change of the first pass voltage VRpass1. For example, the first voltage information 710 may include the values ​​dr1 to dr3 of the read voltage change and the values ​​dp1 to dp3 of the pass voltage change corresponding to a plurality of reference times t1 to t3.

[0138] In one embodiment, the first voltage information 710 may include a first value dr1 of the read voltage change corresponding to a first reference time t1, a second value dr2 of the read voltage change corresponding to a second reference time t2, and a third value dr3 of the read voltage change corresponding to a third reference time t3. In another embodiment, the first voltage information 710 may include a first value dp1 of the through voltage change corresponding to the first reference time t1, a second value dp2 of the through voltage change corresponding to the second reference time t2, and a third value dp3 of the through voltage change corresponding to the third reference time t3.

[0139] In this scenario, at the first reference time t1, the operation controller 131 can reduce the read voltage VR based on a first value drl of the read voltage change, and reduce the first through voltage VRpass1 based on a first value dpl of the through voltage change. Subsequently, at the second reference time t2, the operation controller 131 can reduce the read voltage VR based on a second value dr2 of the read voltage change, and reduce the first through voltage VRpass1 based on a second value dp2 of the through voltage change. Subsequently, at the third reference time t3, the operation controller 131 can reduce the read voltage VR based on a third value dr3 of the read voltage change, and reduce the first through voltage VRpass1 based on a third value dp3 of the through voltage change.

[0140] In one embodiment, the first value of the voltage change, dp1, can be less than the first value of the voltage change, drl. The second value of the voltage change, dp2, can be less than the second value of the voltage change, dr2. The third value of the voltage change, dp3, can be less than the third value of the voltage change, dr3.

[0141] In other embodiments, the first value of the voltage change, dp1, can be equal to the first value of the voltage change, drl. The second value of the voltage change, dp2, can be equal to the second value of the voltage change, dr2. The third value of the voltage change, dp3, can be equal to the third value of the voltage change, dr3.

[0142] Simultaneously, the first voltage information 710 can be modified and implemented to include a configuration that reads the voltage levels r1, r2, and r3 of the voltage VR instead of reading the values ​​dr1, dr2, and dr3 of the voltage changes. Furthermore, the first voltage information 710 can be modified and implemented to include a first voltage change...

[0143] The voltage levels p11, p12, and p13 of VRpass1 are configured instead of the second value dp2 through voltage changes.

[0144] Meanwhile, the number of values ​​included in the first voltage information 710 can be modified and implemented in various ways based on schemes such as MLC, TLC or QLC.

[0145] Figures 8A to 8E This is a diagram illustrating voltage variations according to one embodiment.

[0146] refer to Figure 8A and Figure 8B The table storage unit 133 can store the second voltage information 810. For example, the second voltage information 810 may include the values ​​dr1 to dr3 corresponding to multiple reference times t1 to t3 and the values ​​dp1 to dp3 corresponding to the voltage changes.

[0147] In one embodiment, the second voltage information 810 may include a first value drl of the read voltage change corresponding to the first reference time tl, and a current value drl corresponding to the first reference time tl.

[0148] The first value of the overvoltage change dpl, the second value of the read voltage change corresponding to the second reference time t2 dr2, the second value of the through voltage change corresponding to the second reference time t2 dp2, the third value of the read voltage change corresponding to the third reference time t3 dr3, and the third value of the through voltage change corresponding to the third reference time t3 dp3.

[0149] In one embodiment, the second voltage information 810 may include multiple reference times tl

[0150] The values ​​of the voltage changes corresponding to t3 are drl to dr3 and the ratio values ​​wl to w3. In this case, the values ​​of the voltage changes dp1 to dp3 can be determined by multiplying the ratio values ​​w1 to w3 by the values ​​of the voltage changes dr1 to dr3. Each of the ratio values ​​w1 to w3 can be a value greater than 0 and less than 1. Each of the ratio values ​​w1 to w3 can be a preset value.

[0151] According to one embodiment, such as Figure 8A and Figure 8B As shown, the first ratio value w1, the second ratio value w2, and the third ratio value w3 can be the same value. In this case, as in the first curve 820, when the read voltage VR decreases based on the first value dr1 of the read voltage change at the first reference time t1, the first pass voltage VRpass1 can decrease based on the first value dp1 of the pass voltage change obtained by multiplying the first ratio value w1 by the first value dr1 of the read voltage change at the first reference time t1. In this way, the level of the first pass voltage VRpass1 that decreases at subsequent reference times t2 and t3 can be determined.

[0152] According to one embodiment, such as Figure 8A and Figure 8C As shown, the first ratio value w1 can be set to a value greater than the second ratio value w2, and the second ratio value w2 can be set to a value greater than the third ratio value w3. According to one embodiment, as... Figure 8A and Figure 8D As shown, the third ratio value w3 can be set to a value greater than the second ratio value w2, and the second ratio value w2 can be set to a value greater than the first ratio value w1.

[0153] According to one embodiment, such as Figure 8A and Figure 8EAs shown, at least two of the multiple ratio values ​​w1 to w3 can be the same value. For example, the first ratio value w1 can be set to a value greater than the second ratio value w2, and the second ratio value w2 can be set to a value equal to the third ratio value w3. In other examples, the first ratio value w1 can be set to a value equal to the second ratio value w2, and the second ratio value w2 can be set to a value greater than the third ratio value w3.

[0154] Figure 9 This is a flowchart illustrating the operation of a memory device according to one embodiment.

[0155] refer to Figure 9 The method of operating the memory device 100 may include: step S910, applying a read voltage VR to a selected word line Sel_WL among a plurality of word lines WL1 to WLz coupled to a memory block included in the memory device 100, and applying through voltages VRpass1 and VRpass2 to unselected word lines Unsel_WLs; step S920, reducing the read voltage VR based on a first voltage change; and step S930, when the read voltage VR is reduced, reducing the through voltage VRpass1 applied to target word lines WLn+1 and WLn-1 directly adjacent to the selected word line Sel_WL among the unselected word lines Unsel_WLs based on a second voltage change, wherein the second voltage change is less than the first voltage change.

[0156] Specifically, in step S910, a read voltage VR can be applied to the selected word line Sel_WL among the plurality of word lines WL1 to WLz, and voltages VRpass1 and VRpass2 can be applied to the unselected word lines Unsel_WLs. The plurality of word lines WL1 to WLz can be coupled to a memory block included in the memory device 100. The selected word line Sel_WL can be the word line among the plurality of word lines WL1 to WLz corresponding to an address received by the memory device 100. The unselected word lines Unsel_WLs can be the word lines among the plurality of word lines WL1 to WLz other than the selected word line Sel_WL. Voltages VRpass1 and VRpass2 can include a first voltage VRpass1 and a second voltage VRpass2.

[0157] In one embodiment, an overcharge voltage may be applied to each of the selected word lines Sel_WL, target word lines WLn+1 and WLn-1, and other word lines OtherWLs before the read voltage VR and the pass voltages VRpass1 and VRpass2 are applied.

[0158] In one embodiment, after the overcharge voltage has been applied, the level of the overcharge voltage can be increased until the overcharge level reaches a reference level. Furthermore, when the overcharge voltage level has reached the reference level, a read voltage VR having a level equal to the reference level minus the read voltage change can be applied to the selected word line Sel_WL. Additionally, when a read voltage VR with a decreased level is applied to the selected word line Sel_WL, a first pass voltage VRpass1 having a level equal to the reference level minus the pass voltage change can be applied to the target word lines WLn+1 and WLn-1. In this case, the level of the second pass voltage VRpass2 applied to the word lines Other WLs among the unselected word lines Unsel_WLs can be maintained.

[0159] Here, the reference level can be a higher level than the voltage level preset to sense multiple programming states. In the case of an MLC scheme, the voltage level used for reading can be preset to a first voltage level, a second voltage level, and a third voltage level. Here, the voltage levels can decrease in order from the first voltage level to the third voltage level. Here, the reference level can be a level higher than the first voltage level.

[0160] In one embodiment, the state of a selected memory cell coupled to the selected word line Sel_WL among a plurality of memory cells included in a memory block can be sensed by applying a read voltage VR having a first voltage level to the selected word line Sel_WL. Here, the first voltage level may be a level corresponding to the difference between a reference level and a change in the read voltage.

[0161] Furthermore, at step S920, the read voltage VR can be reduced based on a first voltage change. Here, the first voltage change can be the read voltage change described above. In one embodiment, the read voltage VR can be reduced based on the first voltage change each time a preset reference time has elapsed. The level of the read voltage VR can be reduced based on the value of the first voltage change corresponding to the reference time.

[0162] Furthermore, in step S930, when the read voltage VR decreases, the first pass voltage VRpassl applied to the target word lines WLn+1 and WLn-1 directly adjacent to the selected word line Sel_WL in the unselected word lines Unsel_WLs can be reduced based on a second voltage change. The second voltage change can be less than the first voltage change. Here, the second voltage change can be the aforementioned pass voltage change.

[0163] In one embodiment, the value obtained by multiplying a ratio value less than 1 by the first voltage change can be determined as the second voltage change.

[0164] In this case, when the read voltage VR decreases, the level of the second pass voltage VRpass2 applied to the word line Other WLs in the unselected word line Unsel_WLs can be maintained.

[0165] Furthermore, a step of reducing the read voltage VR can be performed such that, after the state of the selected memory cell is sensed, the read voltage VR can decrease from a first voltage level to a second voltage level based on a first voltage change. Here, the first voltage level can be a level higher than the second voltage level.

[0166] In one embodiment, the first voltage level may be a voltage level for sensing a first programming state among a plurality of programming states, and the second voltage level may be a voltage level for sensing a second programming state among a plurality of programming states, wherein the second programming state is lower than the first programming state.

[0167] In one embodiment, when the read voltage VR decreases after a reference time has elapsed, the read voltage VR may decrease based on a first voltage change, and the first pass voltage VRpassl applied to the target word lines WLn+1 and WLn-1 may decrease based on a second voltage change. Here, the reference time may be a preset time.

[0168] As described above, when the read voltage decreases, the memory device 100 and the method for operating the memory device 100 according to embodiments of the present disclosure can reduce the first pass voltage VRpass1 applied to the target word lines WLn+1 and WLn-1, which are directly adjacent to the selected word line Sel_WL, along with the read voltage. That is, the memory device 100 and the method for operating the memory device 100 according to embodiments of the present disclosure can reduce the first pass voltage VRpass1 applied to the target word lines WLn+1 and WLn-1, along with the read voltage, synchronously with the time point when the read voltage decreases. Therefore, the voltage difference between the directly adjacent selected word line Sel_WL and the target word lines WLn+1 and WLn-1 can be reduced, and thus the capacitance induced between the word lines can be removed. As a result, the level of the read voltage applied to the selected word line Sel_WL can quickly reach a specific level.

[0169] Furthermore, the voltage change of the first through voltage VRpassl can be less than the voltage change of the read voltage VR. Specifically, when the through voltage change is large, the effective channel length of the selected memory cell coupled to the selected word line Sel_WL or the threshold voltage of the selected memory cell changes, which may lead to a problem of deterioration in the reliability of data read from the selected memory cell. The embodiments of this disclosure can effectively prevent the above-mentioned problems.

[0170] Figure 10 This is a block diagram illustrating a memory card using a memory system according to one embodiment.

[0171] refer to Figure 10 The memory card 2000 may include a memory device 2100, a memory controller 2200, and a connector 2300.

[0172] The memory device 2100 can perform programming operations to store data, reading operations to retrieve data, or erasing operations to delete data. In one embodiment, the memory device 2100 can be implemented as any of a variety of non-volatile memory devices, such as electrically erasable programmable ROM (EEPROM), NAND flash memory, NOR flash memory, phase-change RAM (PRAM), resistive RAM (ReRAM), ferroelectric RAM (FRAM), and spin-transfer torque magnetoresistive RAM (STT-MRAM). (See above reference) Figure 1 The description of memory device 100 can be applied in the same way to memory device 2100, and repeated descriptions of it will be omitted.

[0173] Memory controller 2200 can control memory device 2100. For example, memory controller 2200 can execute instructions for controlling memory device 2100. Memory controller 2200 can control memory device 2100 to perform programming operations, read operations, or erase operations. Memory controller 2200 can transfer data, commands, etc., between memory device 2100 and a host via communication. In one embodiment, memory controller 2200 may include components such as RAM, a processor, a host interface, a memory interface, and error correction circuitry. References above. Figure 1 The description of memory controller 200 also applies to memory controller 2200, and repeated descriptions of it will be omitted.

[0174] The memory controller 2200 can communicate with external devices via connector 2300. The memory controller 2200 can communicate with external devices (e.g., a host) based on a specific communication protocol. In one embodiment, the memory controller 2200 can communicate with external devices via at least one of various interface protocols, such as Universal Serial Bus (USB), Multimedia Card (MMC), Embedded MMC (eMMC), Peripheral Component Interconnect (PCI), PCI-express (PCI-E), Advanced Technology Attachment (ATA) protocol, Serial ATA (SATA), Parallel ATA (PATA), Small Computer System Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronics (IDE), Firewire, Universal Flash Memory (UFS), Wi-Fi, Bluetooth, and Non-Volatile Memory Express (NVMe) protocol. In one embodiment, connector 2300 can be defined by at least one of the aforementioned communication protocols. The memory device 2100 and the memory controller 2200 can be integrated into a single semiconductor device to form a memory card. For example, memory device 2100 and memory controller 2200 can be integrated into a single semiconductor device and then manufactured in the form of a memory card, such as a compact flash card, smart media card, memory stick, multimedia card, SD card, or universal flash storage (UFS).

[0175] Figure 11 This is a block diagram illustrating a solid-state drive (SSD) system that applies a memory system according to one embodiment.

[0176] refer to Figure 11 The SSD 3000 may include multiple non-volatile memory devices 3100_1 to 3100_n, an SSD controller 3200, a signal connector 3010, a power connector 3020, an auxiliary power supply 3030, and a buffer memory 3040.

[0177] The SSD 3000 can communicate with the host 3300 via signal connector 3010. Signal connector 3010 can be implemented in the form of an interface compliant with various communication methods. For example, signal connector 3010 can be one of various interfaces compliant with communication methods, such as Serial ATA (SATA) interface, mini-SATA (mSATA) interface, PCI Express (PCIe) interface, and M.2 interface.

[0178] Multiple first non-volatile memory devices 3100_1 can be coupled to the SSD controller 3200 via a first channel CH1, multiple second non-volatile memory devices 3100_2 can be coupled to the SSD controller 3200 via a second channel CH2, and multiple non-volatile memory devices 3100_n can be coupled to the SSD controller 3200 via an nth channel CHn. Therefore, the SSD controller 3200 can communicate in parallel with the non-volatile memory devices coupled to it via independent channels.

[0179] Meanwhile, the above references Figure 1 The description of memory device 100 can be equally applied to each of the plurality of non-volatile memory devices 3100_1 to 3100_n, and repeated descriptions thereof will be omitted below. References above Figure 1 The description of memory controller 200 can be applied equivalently to SSD controller 3200, and its repeated description is omitted below.

[0180] External power can be supplied to the SSD 3000 from the host 3300 via power connector 3020. An auxiliary power supply 3030 can be coupled to the host 3300 via power connector 3020. The auxiliary power supply 3030 can be supplied with power from the host 3300 and can be charged. When the power supply from the host 3300 is not successfully implemented, the auxiliary power supply 3030 can supply power to the SSD 3000. In one embodiment, the auxiliary power supply 3030 can be located inside or outside the SSD 3000. For example, the auxiliary power supply 3030 can be located within the motherboard or provide auxiliary power to the SSD 3000.

[0181] Buffer memory 3040 can be used as a buffer memory for SSD 3000. For example, buffer memory 3040 can temporarily store data received from host 3300 or data received from multiple non-volatile memory devices 3100_1 to 3100_n, or it can temporarily store metadata (e.g., mapping tables) of non-volatile memory devices 3100_1 to 3100_n. Buffer memory 3040 may include volatile memory devices such as DRAM, SDRAM, DDR SDRAM, LPDDR SDRAM, and GRAM, or non-volatile memory devices such as FRAM, ReRAM, STT-MRAM, and PRAM.

[0182] Figure 12 This is a block diagram illustrating a user system using a memory system according to one embodiment.

[0183] refer to Figure 12The user system 4000 may include an application processor 4100, a memory module 4200, a network module 4300, a storage module 4400, and a user interface 4500.

[0184] Application processor 4100 can run user system 4000, operating system (OS), or components included in user programs. In one embodiment, application processor 4100 may include controllers, interfaces, graphics engines, etc., for controlling components included in user system 4000. Application processor 4100 may be provided as a system-on-a-chip (SoC).

[0185] The memory module 4200 can be used as the main memory, working memory, buffer memory, or cache memory of the user system 4000. The memory module 4200 may include volatile RAM, such as DRAM, SDRAM, DDR SDRAM, DDR2 SDRAM, DDR3 SDRAM, LPDDR SDRAM, LPDDR2 SDRAM, and LPDDR3 SDRAM; or non-volatile RAM, such as PRAM, ReRAM, MRAM, and FRAM. In one embodiment, the application processor 4100 and the memory module 4200 may be packaged based on a stacked package (POP) and can then be provided as a single semiconductor package.

[0186] Network module 4300 can communicate with external devices. In one embodiment, network module 4300 can support wireless communication, such as Code Division Multiple Access (CDMA), Global System for Mobile Communications (GSM), Wideband CDMA (WCDMA), CDMA-2000, Time Division Multiple Access (TDMA), Long Term Evolution (LTE), WiMAX, Wireless LAN (WLAN), UWB, Bluetooth, or Wi-Fi. In one embodiment, network module 4300 may be included in application processor 4100.

[0187] Storage module 4400 can store data. For example, storage module 4400 can store data received from application processor 4100. Alternatively, storage module 4400 can send the data stored in storage module 4400 to application processor 4100. In one embodiment, storage module 4400 can be implemented as a non-volatile semiconductor memory device, such as phase-change RAM (PRAM), magnetic RAM (MRAM), resistive RAM (RRAM), NAND flash memory, NOR flash memory, or NAND flash memory with a 3D structure. In one embodiment, storage module 4400 can be provided as a removable storage medium (removable drive), such as a memory card or an external drive of user system 4000.

[0188] In one embodiment, the above reference Figure 1 The description of memory system 10 can be equally applied to memory module 4400. For example, memory module 4400 may include multiple non-volatile memory devices. Hereinafter, reference is made to... Figure 1 The description of memory device 100 can be equally applied to each of the plurality of nonvolatile memory devices.

[0189] User interface 4500 may include an interface for inputting data or instructions to application processor 4100 or outputting data to external devices. In one embodiment, user interface 4500 may include user input interfaces such as a keyboard, keypad, buttons, touch panel, touch screen, touchpad, touch ball, camera, microphone, gyroscope sensor, vibration sensor, and piezoelectric element. User interface 4500 may include user output interfaces such as liquid crystal display (LCD), organic light-emitting diode (OLED) display device, active matrix OLED (AMOLED) display device, LED, speaker, and monitor.

[0190] According to embodiments of this disclosure, a memory device capable of reducing the time required for read operations, and a method for operating the memory device, are provided. Furthermore, the time required for the read voltage to reach a specific level can be shortened.

Claims

1. A memory device, comprising: A memory block comprises multiple memory cells coupled to multiple word lines; The peripheral circuitry is configured to perform a read operation by applying a read voltage to a selected word line among the plurality of word lines and applying a first pass voltage to a target word line, wherein the target word line is adjacent to the selected word line among the unselected word lines other than the selected word line. as well as The control logic is configured as follows: The read voltage is reduced based on the change in read voltage, and When the read voltage decreases, the first through voltage is reduced based on the voltage change. The voltage change is less than the reading voltage change.

2. The memory device of claim 1, wherein the control logic is configured to control the peripheral circuitry to apply a second pass voltage to the remaining word lines among the unselected word lines, and to maintain the level of the second pass voltage when the read voltage decreases. The remaining word lines are the word lines other than the target word line and the selected word line.

3. The memory device of claim 2, wherein the control logic is configured to control the peripheral circuitry to apply an overcharge voltage to the selected word line, the target word line, and the remaining word lines before the read operation is performed.

4. The memory device of claim 3, wherein the control logic is configured to: Increase the level of the overcharge voltage until the level of the overcharge voltage reaches the reference level, and When the level of the overcharge voltage reaches the reference level, the read voltage having a level that is the level of the read voltage change minus the reference level is applied to the selected word line, and the first pass voltage having a level that is the level of the pass voltage change minus the reference level is applied to the target word line.

5. The memory device according to claim 1, wherein the control logic includes: An operation controller is configured to, after sensing the state of a selected memory cell coupled to the selected word line among the plurality of memory cells by applying the read voltage having a first voltage level to the selected word line, reduce the read voltage from the first voltage level to a second voltage level based on the read voltage change, and reduce the first pass voltage based on the pass voltage change when the read voltage decreases.

6. The memory device according to claim 5, wherein: The first voltage level is the voltage level used to sense the first programming state among multiple programming states. The second voltage level is used to sense the voltage level of the second programming state among the plurality of programming states, and The second programming state is lower than the first programming state.

7. The memory device of claim 1, wherein the control logic comprises: The table storage unit is configured to store voltage information, which includes the values ​​of the read voltage changes and the values ​​of the pass voltage changes corresponding to multiple reference times.

8. The memory device of claim 7, wherein the control logic is configured to: When a first reference time among the plurality of reference times is reached, the read voltage is reduced based on a first value of the read voltage change corresponding to the first reference time, and when the read voltage decreases, the first through voltage is reduced based on a first value of the through voltage change corresponding to the first reference time. When a second reference time, which is after the first reference time, is reached among the plurality of reference times, the read voltage is reduced based on a second value of the read voltage change corresponding to the second reference time, and when the read voltage is reduced, the first pass voltage is reduced based on a second value of the pass voltage change corresponding to the second reference time.

9. The memory device according to claim 8, wherein: The first value obtained by the voltage change is a value obtained by multiplying a first ratio value by the first value of the voltage change read. The second value obtained by the voltage change is a value obtained by multiplying the second ratio value by the second value of the voltage change.

10. The memory device of claim 9, wherein the first ratio value is equal to or greater than the second ratio value.

11. The memory device of claim 9, wherein the first ratio value is less than or equal to the second ratio value.

12. The memory device of claim 7, wherein the control logic is configured to: Whenever any of the plurality of reference times is reached, the read voltage is reduced based on the value of the read voltage change corresponding to the reference time, and when the read voltage is reduced, the first pass voltage is reduced based on the value of the pass voltage change corresponding to the reference time.

13. A method of operating a memory device, comprising: A read voltage is applied to a selected word line among multiple word lines, and a voltage is applied to an unselected word line, the selected word line being coupled to a memory block included in the memory device; The read voltage is reduced based on a first voltage change; as well as When the read voltage decreases, based on the second voltage change, the pass voltage applied to the target word line adjacent to the selected word line among the unselected word lines is reduced. The second voltage change is less than the first voltage change.

14. The method of claim 13, further comprising: When the read voltage decreases, maintain the level of the pass voltage applied to the remaining word lines among the unselected word lines. The remaining word lines are the word lines other than the target word line and the selected word line.

15. The method of claim 14, further comprising: Before the read voltage and the pass voltage are applied, an overcharge voltage is applied to the selected word line, the target word line, and the remaining word lines.

16. The method of claim 15, wherein applying the read voltage and the pass voltage comprises: Increase the level of the overcharge voltage until the level of the overcharge voltage reaches the reference level. When the level of the overcharge voltage reaches the reference level, The read voltage, having a level that is the level of the reference level minus the first voltage change, is applied to the selected word line, and The pass voltage, having a level that is the level of the reference level minus the second voltage change, is applied to the target word line.

17. The method of claim 13, further comprising: By applying the read voltage, having a first voltage level, to the selected word line, the state of the selected memory cell coupled to the selected word line among the plurality of memory cells included in the memory block is sensed. The reduction of the read voltage includes: after the state of the selected memory cell is sensed, reducing the read voltage from the first voltage level to the second voltage level based on the first voltage change.

18. The method of claim 17, wherein: The first voltage level is the voltage level used to sense the first programming state among multiple programming states. The second voltage level is used to sense the voltage level of the second programming state among the plurality of programming states, and The second programming state is lower than the first programming state.

19. The method of claim 13, further comprising: The second voltage change is determined by multiplying a ratio less than 1 by the first voltage change.

20. The method of claim 13, further comprising: When the reference time has elapsed since the point at which the read voltage decreased. The read voltage is reduced based on the first voltage change, and The pass voltage applied to the target word line is reduced based on the second voltage change.

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