Analog switch circuit

Abstract

The application provides an analog switch circuit, which comprises a first NMOS tube, a second NMOS tube, a first PMOS tube, a second PMOS tube, a first resistor, an input signal end and an output signal end. When the switch is closed, the first NMOS tube and the second NMOS tube are closed, the first resistor is pulled up, the first PMOS tube and the second PMOS tube are turned off, and at this time, the switch is completely closed and no leakage occurs.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit design, and more particularly to an analog switching circuit. Background Technology

[0002] Analog switches, also known as analog switches, primarily perform signal switching functions in signal chains. They use MOSFETs to switch the signal chain on or off; because their function is similar to a switch but implemented using analog devices, they are called analog switches. Due to their low power consumption, high speed, lack of mechanical contacts, small size, and long lifespan, they are widely used in various automatic control systems and electronic digital products.

[0003] Traditional CMOS analog switches typically use a parallel connection of NMOS and PMOS transistors, allowing signals to pass through equally smoothly in both directions. The structure usually includes a gate circuit to control the conduction and cutoff of the NMOS and PMOS transistors; the NMOS conducts when the gate voltage is positive and cuts off when the gate voltage is negative, while the PMOS conducts vice versa. Since the switch does not select the direction of current flow, there is no distinction between input and output terminals. The advantages of CMOS switches are rail-to-rail dynamic range, bidirectional operation, and constant on-resistance despite input voltage changes. However, in practical applications, when the input signal is higher than the power supply voltage, the PMOS transistor in the analog switch structure can leak current to the power supply VCC due to the parasitic diode. Furthermore, when the input signal is higher than the power supply voltage and exceeds the threshold voltage of the PMOS transistor, the PMOS transistor in the analog switch structure turns on, resulting in leakage current from the input to the output. Therefore, the electrical performance of traditional analog switches is affected and urgently needs improvement. Summary of the Invention

[0004] This invention provides an analog switch circuit that can effectively prevent reverse leakage and improve the electrical performance of the device.

[0005] To achieve the above objectives, the present invention provides an analog switching circuit, comprising: a first NMOS transistor, a second NMOS transistor, a first PMOS transistor, a second PMOS transistor, a first resistor, an input signal terminal, and an output signal terminal; wherein, the source of the first NMOS transistor is connected to the input signal terminal and the drain of the first PMOS transistor, the substrate of the first NMOS transistor is grounded, and the drain of the first NMOS transistor is connected to the drain of the second PMOS transistor and connected to the output signal terminal; the sources of the first PMOS transistor and the second PMOS transistor are connected to the substrate; one end of the first resistor is connected to the source of the first PMOS transistor and the second PMOS transistor, and the other end is connected to the gate of the first PMOS transistor and the second PMOS transistor, and connected to the drain of the second NMOS transistor; the gates of the first NMOS transistor and the second NMOS transistor are connected to the signal terminal, and the substrate of the second NMOS transistor is connected to the source and grounded.

[0006] Optionally, the analog switching circuit further includes: a third PMOS transistor, a second resistor, a third NMOS transistor, and a pulse generation circuit; the source of the third PMOS transistor is connected to the substrate and in parallel with the first resistor, that is, the source is connected to the source of the first PMOS transistor and the source of the second PMOS transistor, and the drain is connected to the gate of the first PMOS transistor and the gate of the second PMOS transistor; one end of the second resistor is connected to the source of the third PMOS transistor, and the other end is connected to the gate of the third PMOS transistor; the source of the third NMOS transistor is connected to the substrate and grounded, the drain of the third NMOS transistor is connected to the gate of the third PMOS transistor, and the gate of the third NMOS transistor is connected to the signal of the pulse generation circuit.

[0007] Optionally, the pulse generation circuit includes a first NOT gate, a second NOT gate, a capacitor, a NAND gate, and an AND gate. The input signal is input to the first NOT gate, the output of the first NOT gate is connected to the input of the second NOT gate, the second NOT gate and the input signal serve as the two input terminals of the NAND gate, the output terminal of the NAND gate and the input signal serve as the two input terminals of the AND gate, and the output terminal of the AND gate is connected to the gate of the third NMOS transistor. One end of the capacitor is connected to the output terminal of the first NOT gate, and the other end is grounded.

[0008] Optionally, the threshold voltages of both the first PMOS transistor and the second PMOS transistor are greater than or equal to 0.7V and less than or equal to 0.8V.

[0009] Optionally, the resistance of the first resistor is greater than or equal to 5 megohms.

[0010] Optionally, the resistance of the second resistor is greater than or equal to 500 kilohms.

[0011] Compared with the prior art, the technical solution of the present invention has the following advantages:

[0012] When the switch is closed, the first NMOS transistor and the second NMOS transistor are turned off, and the first resistor is pulled up, causing the first PMOS transistor and the second PMOS transistor to turn off. At this time, the switch is completely turned off and no leakage current will occur.

[0013] Furthermore, because the first resistor has a relatively large resistance, the turn-off speeds of the first and second PMOS transistors are affected. Therefore, a third PMOS transistor, a second resistor, a third NMOS transistor, and a pulse generation circuit are added. When the switch needs to be turned off, the pulse generation circuit generates a short pulse to turn on the third NMOS transistor, which in turn turns on the third PMOS transistor, thus quickly turning off the first and second PMOS transistors. This improves the electrical performance of the analog switching device and prevents reverse leakage. Attached Figure Description

[0014] Figure 1 This is a schematic diagram of an SPDT circuit structure that utilizes a traditional CMOS analog switch;

[0015] Figure 2 This is a schematic diagram of an analog switch circuit structure according to an embodiment of the present invention;

[0016] Figure 3 This is a schematic diagram of an embodiment of the present invention applied to an SPDT circuit structure;

[0017] Figure 4 This is a schematic diagram of a pulse generation circuit structure according to an embodiment of the present invention;

[0018] Figure 5 yes Figure 4 The waveform diagram of the pulse generation circuit is shown. Detailed Implementation

[0019] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0020] Figure 1 This is a schematic diagram of a SPDT (Single-Pole Double-Throw) circuit structure that utilizes traditional CMOS analog switches. As shown in the figure, the SPDT circuit structure includes: analog switches SW1 and SW2; NOT gates INV1, INV2, INV3, and INV4; AND gates AND1 and AND2; and signal terminals OE, SEL, IN, OUT1, and OUT2. Specifically, analog switch SW1 includes NMOS transistor MN1 and PMOS transistor MP1; analog switch SW2 includes NMOS transistor MN2 and PMOS transistor MP2.

[0021] Continue to refer to Figure 1 The power supply VCC supplies power to NOT gates INV1, INV2, INV3, INV4, AND gates AND1 and AND2. The signal SEL terminal is the input terminal of NOT gate INV1, and the output terminal of NOT gate INV1 serves as the input terminal of INV2. The signal terminal OE and the output terminal of NOT gate INV1 serve as the two input terminals of AND gate AND1. The signal terminal OE and the output terminal of NOT gate INV2 serve as the two input terminals of AND gate AND2. The output terminal of AND gate AND1 is connected to the gate of NMOS transistor MN1 and also serves as the input terminal of NOT gate INV3. The output terminal of AND gate AND2 is connected to the gate of NMOS transistor MN2 and also serves as the input terminal of NOT gate INV4. The output terminal of NOT gate INV3 is connected to the gate of PMOS transistor MP1. The output terminal of 4 is connected to the gate of the PMOS transistor MP2; the source of the NMOS transistor MN1 is connected to the drain of the PMOS transistor MP1 and connected to the signal terminal IN, the drain of the NMOS transistor MN1 is connected to the source of the PMOS transistor MP1 and connected to the signal terminal OUT1; the source of the NMOS transistor MN2 is connected to the drain of the PMOS transistor MP2 and connected to the signal terminal IN, the drain of the NMOS transistor MN2 is connected to the source of the PMOS transistor MP2 and connected to the signal terminal OUT2; the substrates of the NMOS transistors MN1 and MN2 are grounded, and the substrates of the PMOS transistors MP1 and MP2 are connected to the power supply VCC.

[0022] The working principle of the SPDT circuit is analyzed below. The signal terminal OE is the enable signal terminal. When the signal terminal OE is high and the signal terminal SEL is 1, the output signal of the NOT gate INV1 is 0, which makes the output of the AND gate AND1 0, causing the NMOS transistor MN1 to turn off. The signal after passing through the NOT gate INV3 is 1, causing the PMOS transistor MP1 to turn off, i.e., the analog switch SW1 is turned off. The output terminal of the NOT gate INV2 is 1, turning on the NMOS transistor MN2 and the PMOS transistor MP2, turning on the analog switch SW2, and connecting the signal terminals IN and OUT2.

[0023] When the signal terminal OE is high and the signal terminal SEL is 0, the output signal of the NOT gate INV2 is 0, which makes the output of the AND gate AND2 0, causing the NMOS transistor MN2 to turn off. The signal after passing through the NOT gate INV4 is 1, causing the PMOS transistor MP2 to turn off, i.e., the analog switch SW2 is turned off. When the output of the NOT gate INV1 is 1, the NMOS transistor MN1 and the PMOS transistor MP1 are turned on, the analog switch SW1 is turned on, and the signal terminals IN and OUT1 are connected.

[0024] like Figure 1 The following problems may occur when analog switches SW1 and SW2 are used:

[0025] First, when the voltage at signal terminal IN, signal terminal OUT1, or signal terminal OUT2 is higher than the threshold voltage of PMOS transistors MP1 and MP2 compared to VCC (for example, when VCC is 3.3V and signal terminal IN is 5V), signal terminal SEL is 0, switch SW1 is on, switch SW2 is off, and PMOS transistor MP2 should be off. However, the drain voltage of PMOS transistor MP2 is 5V, and the gate and N-well voltage is 3.3V. At this time, the voltage drop across the PN junction between the drain and substrate of PMOS transistor MP2 is 1.7V, which is forward biased and causes leakage to VCC. In addition, the voltage drop between the drain and gate of PMOS transistor MP2 is 1.7V, which is greater than the threshold voltage of the PMOS transistor, so PMOS transistor MP2 is on, causing the IN signal to leak to OUT2. For example, when VCC is 3.3V and signal terminal OUT1 is 5V, signal terminal SEL is 1, switch SW2 is turned on and switch SW1 is turned off. At this time, the voltage drop across the PN junction between the source and N-well of PMOS transistor MP1 in switch SW1 is 1.7V, which is forward biased and causes leakage to VCC. In addition, the voltage drop between the drain and gate of PMOS transistor MP2 is 1.7V, which is greater than the threshold voltage of PMOS transistor, so MP2 is turned on, causing the IN terminal signal to leak to OUT1.

[0026] Secondly, when VCC is floating, if there is an input voltage at signal terminal IN, signal terminal OUT1, or signal terminal OUT2, for example, when the voltage at signal terminal IN is 1V, the parasitic diode of PMOS transistor MP1 in switch SW1 will conduct. At this time, leakage current will leak from signal terminal OUT1 to VCC, causing switches SW1 and SW2 to be in a weak conduction or weak shutdown state, resulting in the IN terminal signal leaking to OUT1 or OUT2.

[0027] To solve the above problems, the present invention provides an analog switching circuit, such as... Figure 2The diagram shown is a schematic of an analog switch circuit structure according to an embodiment of the present invention. This embodiment includes: a first NMOS transistor MN01, a second NMOS transistor MN02, a first PMOS transistor MP01, a second PMOS transistor MP02, a first resistor R01, an input signal terminal IN01 and an output signal terminal OUT01, and an enable signal terminal OE01; wherein, the source of the first NMOS transistor MN01 is connected to the input signal terminal IN01 and the drain of the first PMOS transistor MP01, the substrate of the first NMOS transistor MN01 is grounded, and the drain of the first NMOS transistor MN01 is connected to the drain of the second PMOS transistor MP02. The drains are connected to the output signal terminal OUT01; the sources and substrates of the first PMOS transistor MP01 and the second PMOS transistor MP02 are connected; one end of the first resistor R01 is connected to the source of the first PMOS transistor MP01 and the second PMOS transistor MP02, and the other end is connected to the gate of the first PMOS transistor MP01 and the second PMOS transistor MP02, and connected to the drain of the second NMOS transistor MN02; the gates of the first NMOS transistor MN01 and the second NMOS transistor MN02 are connected to the signal terminal, and the substrate and source of the second NMOS transistor MN02 are connected to ground.

[0028] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, the following description is provided in conjunction with the accompanying drawings. Figure 3 A specific embodiment of the present invention will be described in detail below. Figure 3 This is a schematic diagram of an embodiment of the present invention, showing the application of an analog switching circuit to an SPDT circuit.

[0029] like Figure 3 As shown, the SPDT (Single-Pole Double-Throw) circuit structure includes: signal terminals OE, SEL, IN, OUT11, OUT21, SW11, and SW12. SW11 includes: NOT gates INV11, INV12, INV13, AND gate AND11, NMOS transistors MN11, MN12, MN13, PMOS transistors MP11, MP12, MP13, resistors R11 and R12, and pulse generation circuit UREOS1. SW12 includes: NOT gate INV14, AND gate AND21, NMOS transistors MN21, MN22, MN23, PMOS transistors MP21, MP22, MP23, resistors R21 and R22, and pulse generation circuit UREOS2. All diodes shown in the figure are parasitic diodes.

[0030] Continue to refer to Figure 3The power supply VCC powers the aforementioned NOT gate and AND gate circuits. The signal SEL terminal is the input terminal of NOT gate INV11, and the output terminal of NOT gate INV11 serves as the input terminal of INV12. The signal terminal OE and the output terminal of NOT gate INV11 serve as the two input terminals of AND gate AND11. The signal terminal OE and the output terminal of NOT gate INV12 serve as the two input terminals of AND gate AND21. The output terminal of AND gate AND11 is connected to the gate of NMOS transistor MN11 and also serves as the input terminal of NOT gate INV13. The output terminal of AND gate AND21 is connected to the gate of NMOS transistor MN21 and also serves as the input terminal of NOT gate INV14. The output terminal of NOT gate INV13 serves as the input terminal of pulse generation circuit UREOS1, and the output terminal of NOT gate INV14 serves as the input terminal of pulse generation circuit UREOS2.

[0031] The source of the NMOS transistor MN11 is connected to the input signal terminal IN and the drain of the PMOS transistor MP11. The substrate of the NMOS transistor MN11 is grounded. The drain of the NMOS transistor MN11 is connected to the drain of the PMOS transistor MP12 and connected to the output signal terminal OUT11. The sources and substrates of the PMOS transistors MP11 and MP12 are connected. One end of the resistor R11 is connected to the source of the PMOS transistors MP11 and MP12, and the other end is connected to the gate of the PMOS transistors MP11 and MP12, and connected to the drain of the NMOS transistor MN12. The gates of the NMOS transistors MN11 and MN12 are connected to the output terminal of the AND gate AND11. The substrate and source of the NMOS transistor MN12 are connected and grounded.

[0032] The source of the PMOS transistor MP13 is connected to the substrate and in parallel with the resistor R11. That is, the source is connected to the source of both PMOS transistors MP11 and MP12, and the drain is connected to the gate of both PMOS transistors MP11 and MP12. One end of the resistor R12 is connected to the source of the PMOS transistor MP12, and the other end is connected to the gate of the PMOS transistor MP13. The source of the NMOS transistor MN13 is connected to the substrate and grounded. The drain of the NMOS transistor MN13 is connected to the gate of the PMOS transistor MP13, and the gate of the NMOS transistor MN13 is connected to the signal output of the pulse generation circuit UREOS1.

[0033] The source of the NMOS transistor MN21 is connected to the input signal terminal IN and the drain of the PMOS transistor MP21. The substrate of the NMOS transistor MN21 is grounded. The drain of the NMOS transistor MN21 is connected to the drain of the PMOS transistor MP22 and connected to the output signal terminal OUT21. The sources and substrates of the PMOS transistors MP21 and MP22 are connected. One end of the resistor R21 is connected to the source of the PMOS transistors MP21 and MP22, and the other end is connected to the gate of the PMOS transistors MP21 and MP22, and connected to the drain of the NMOS transistor MN22. The gates of the NMOS transistors MN21 and MN22 are connected to the output terminal of the AND gate AND21. The substrate and source of the NMOS transistor MN22 are connected and grounded.

[0034] The source of the PMOS transistor MP23 is connected to the substrate and in parallel with the resistor R21. That is, the source is connected to the source of both PMOS transistors MP21 and MP22, and the drain is connected to the gate of both PMOS transistors MP21 and MP22. One end of the resistor R22 is connected to the source of the PMOS transistor MP22, and the other end is connected to the gate of the PMOS transistor MP23. The source of the NMOS transistor MN13 is connected to the substrate and grounded. The drain of the NMOS transistor MN23 is connected to the gate of the PMOS transistor MP23, and the gate of the NMOS transistor MN23 is connected to the signal output of the pulse generation circuit UREOS2.

[0035] Specifically, such as Figure 4 The diagram shown is a schematic of the pulse generation circuit structure according to an embodiment of the present invention. The pulse generation circuit UREOS1 includes a first NOT gate INV41, a second NOT gate INV42, a capacitor C, a NAND gate NAND1, and an AND gate AND41. The input signal IN4 is input to the first NOT gate INV41, and the output of the first NOT gate INV41 is connected to the input of the second NOT gate INV42. The second NOT gate INV42 and the input signal IN4 serve as the two input terminals of the NAND gate NAND1. The output terminal of the NAND gate NAND1 and the input signal IN4 serve as the two input terminals of the AND gate AND41. The output terminal OUT4 of the AND gate AND41 is connected to the gate of the NMOS transistor MN13. One end of the capacitor C is connected to the output terminal of the first NOT gate INV41, and the other end is grounded. Similarly, the structure of the pulse generation circuit UREOS2 is the same as that of UREOS1, and will not be described again here.

[0036] Figure 5 yes Figure 4 The waveform diagram of the pulse generation circuit is shown. Figure 3 , Figure 4 As shown, when the enable signal terminal OE is high, and the signal terminal SEL changes from 1 to 0, the signal output after passing through the NOT gate INV11 and the NOT gate INV12 is 0. The enable signal terminal OE and the signal terminal SEL serve as the two input signals of the AND gate AND21, so the output signal of the AND gate AND21 is 0. After passing through the NOT gate INV14, the input signal of the pulse generation circuit UREOS1 is 1. At this time, the input terminal IN4 reaches the rising edge, and the NOT gate INV41 and the NOT gate... The delay unit composed of INV42 and the capacitor C causes the signal to be delayed. During the delay period, both input signals of the AND gate AND41 are 1, and the signal OUT4 changes from 0 to 1. When the delay ends, after the output signal N1 passes through the NAND gate NAND1, the output signal N2 changes from 1 to 0, and the signal OUT4 changes from 1 to 0. Therefore, during the delay period tdly, the pulse generation circuit UREOS2 generates a short pulse. Specifically, the delay period tdly is between 20ns and 50ns.

[0037] The following is about Figure 3 The working principle of the SPDT circuit shown is analyzed. The signal terminal OE is the enable signal terminal. When signal terminal OE is high and signal terminal SEL is 0, the output signal of the NOT gate INV11 is 1, making the output of the AND gate AND11 1, thus enabling the NMOS transistor MN1. The signal after passing through NOT gate INV13 is 0, enabling the NMOS transistor MN12, and the PMOS transistors MP11 and MP12 are also enabled. At this time, if the voltage at signal terminal IN is positive, the analog switch SW11 is turned on. To reduce the leakage current caused by signal terminal IN or signal terminal OUT11 when the switch is turned on, specifically, the resistance value of resistor R11 is greater than or equal to 5 megohms.

[0038] When the output of NOT gate INV12 is 0 and one input of AND gate AND21 is 0, the output is 0. This turns off NMOS transistors MN21 and MN22. Resistor R21 pulls up, turning off PMOS transistors MP21 and MP22, thus completely turning off switch SW12. Because the resistance of resistor R11 is relatively large, it affects the turn-off speed of PMOS transistors MP21 and MP22. However, the short pulse generated by pulse generation circuit UREOS2 turns on NMOS transistor MN23, which in turn turns on PMOS transistor MP23, thereby quickly turning off PMOS transistors MP21 and MP22, achieving the purpose of quickly turning off switch SW12.

[0039] Therefore, the present invention solves the problem of leakage current caused by the conduction of the parasitic diode of the PMOS transistor in the analog switch, thereby improving the electrical performance of the analog switch.

[0040] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. An analog switching circuit, characterized in that, include: A first NMOS transistor, a second NMOS transistor, a first PMOS transistor, a second PMOS transistor, a first resistor, an input signal terminal, and an output signal terminal; wherein, the source of the first NMOS transistor is connected to the input signal terminal and the drain of the first PMOS transistor, the substrate of the first NMOS transistor is grounded, the drain of the first NMOS transistor is connected to the drain of the second PMOS transistor and connected to the output signal terminal; the sources of the first PMOS transistor and the second PMOS transistor are connected to the substrate; one end of the first resistor is connected to the source of the first PMOS transistor and the second PMOS transistor, and the other end is connected to the gate of the first PMOS transistor and the second PMOS transistor and connected to the drain of the second NMOS transistor; the gates of the first NMOS transistor and the second NMOS transistor are connected to the signal terminal, and the substrate of the second NMOS transistor is connected to the source and grounded; The analog switch circuit further includes: a third PMOS transistor, a second resistor, a third NMOS transistor, and a pulse generation circuit; the source of the third PMOS transistor is connected to the substrate and in parallel with the first resistor, that is, the source is connected to the sources of the first PMOS transistor and the second PMOS transistor, and the drain is connected to the gates of the first PMOS transistor and the second PMOS transistor; one end of the second resistor is connected to the source of the third PMOS transistor, and the other end is connected to the gate of the third PMOS transistor; the source of the third NMOS transistor is connected to the substrate and grounded, the drain of the third NMOS transistor is connected to the gate of the third PMOS transistor, and the gate of the third NMOS transistor is connected to the signal output of the pulse generation circuit.

2. The analog switching circuit as described in claim 1, characterized in that, The pulse generation circuit includes a first NOT gate, a second NOT gate, a capacitor, a NAND gate, and an AND gate. An input signal is input to the first NOT gate, the output of the first NOT gate is connected to the input of the second NOT gate, the second NOT gate and the input signal serve as the two input terminals of the NAND gate, the output terminal of the NAND gate and the input signal serve as the two input terminals of the AND gate, and the output terminal of the AND gate is connected to the gate of the third NMOS transistor. One end of the capacitor is connected to the output terminal of the first NOT gate, and the other end is grounded.

3. The analog switching circuit as described in claim 1, characterized in that, The threshold voltages of both the first PMOS transistor and the second PMOS transistor are greater than or equal to 0.7V and less than or equal to 0.8V.

4. The analog switching circuit as described in claim 1, characterized in that, The resistance of the first resistor is greater than or equal to 5 megohms.

5. The analog switching circuit as described in claim 1, characterized in that, The resistance of the second resistor is greater than or equal to 500 kilohms.

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