A method to improve the consistency of wire dicing data for large silicon wafers

Abstract

This invention provides a method to improve the consistency of wire-cutting data for large silicon wafers, addressing the problem that existing testing methods cannot provide consistent test data with the wire-cutting direction as the initial position for process debugging and R&D needs. A method is proposed that solves the wire-cutting data consistency problem by changing the initial test position and aligning the test path with the cutting direction, thus facilitating process adjustment and optimization of processing parameters. The initial test angle β is adjusted so that the angle α between the initial test angle and the notch direction is equal to β. The thickness steepness of the test data along the cutting direction is calculated to characterize the impact of cutting on the silicon wafer morphology.

Description

Technical Field

[0001] This invention relates to a testing method for improving the consistency of wire-cut silicon wafer data. The method mainly includes adjusting the starting position of the silicon wafer data test after wire-cutting by using the cutting angle as a reference angle, thereby obtaining test data consistency data with the cutting direction as the initial angle, and then calculating the thickness steepness of the cutting direction to characterize the effect of cutting on the silicon wafer morphology. Background Technology

[0002] With the increasing performance requirements of semiconductor components and the gradual improvement of manufacturing processes, the flatness requirements for silicon wafers are also becoming more stringent. Therefore, how to characterize the flatness and related parameters of silicon wafers during the production process is of great significance to silicon wafer manufacturing.

[0003] Non-contact testing methods for silicon wafers are widely used due to their advantages such as not damaging the wafer surface, ease of use, and fast testing speed. Among them, the electronic capacitance method for thickness measurement is a common technique. The principle of this method is to assume that the silicon wafer is an ideal and uniform dielectric, that is, the dielectric constant of the silicon wafer being measured and at all points across its entire area is the same or similar. Figure 1 This is a schematic diagram illustrating the principle of thickness measurement using the capacitance method.

[0004] like Figure 1 As shown, Probe A and B are capacitive sensor probes; s The probe area; D The distance between probes A and B is a fixed value; a is the distance between probe A and the silicon wafer surface; b is the distance between probe B and the silicon wafer surface. During equipment debugging, it is also necessary to ensure that a and b are as equal as possible to guarantee the accuracy of the measurement results. t Let be the thickness of the silicon wafer. During testing, the silicon wafer is positioned between probe A and probe B. Assume the dielectric constant of the silicon wafer is , the dielectric constant of air is , and the capacitance without the silicon wafer is . C 0 When the silicon wafer is placed between probe A and probe B, the capacitance is C

[0005]

[0006] When a high-frequency AC signal is input between the upper and lower capacitance probes, a high-frequency electric field is generated, and current flows through the capacitor, forming a standard linear circuit within the device. The change in current can then be measured. Assuming there is no silicon wafer, the current value is... I 0 When testing the silicon wafer, the current is I AC voltage is U The frequency is f ,but:

[0007]

[0008] It can be deduced that,

[0009]

[0010] From Equation 5, it can be seen that when D At a given point, the thickness of a silicon wafer is determined by the current flowing through it. By solving the equations, the thickness information at that point can be obtained. By moving the silicon wafer, the thickness information at other locations on the wafer can be obtained.

[0011] When the testing method is line scan, existing post-dicing flatness testing uses the Notch as the initial position. Since the dicing direction and the Notch position are not correlated, this method cannot reflect the impact of the dicing direction on process parameters of interest. Furthermore, dicing has a significant impact on the flatness data of silicon wafers. Therefore, reasonable and consistent testing and characterization of the flatness data of post-dicing silicon wafers are extremely important. Summary of the Invention

[0012] To improve the consistency testing of large silicon wafer wire cutting data and better address the issue that conventional flatness testing cannot characterize the skewness of the cutting direction during production, this invention optimizes process parameters and achieves this through the following methods.

[0013] This paper proposes a method to solve the data consistency problem in wire EDM by changing the initial test position and aligning the test path with the cutting direction. This facilitates process adjustment and optimization of machining parameters. Figure 2 As shown, when the test path is as illustrated, the cutting direction is not completely consistent with the Notch direction. Figure 3 This will lead to a situation where the test data is not correlated with the cutting direction in the actual test results. When the angle between the line mark direction and the notch is α, and the starting angle of the silicon wafer test is β, by adjusting β to make α=β, the test pattern will remain consistent with the cutting direction in the actual test results, and the consistency of the test data will be greatly improved.

[0014] Take the thickness profile test data in the cutting direction, see Figure 5 The following calculations are performed to determine the thickness steepness.

[0015]

[0016] In the formula, Space This represents the sampling length, meaning the thickness steepness is calculated within that length range. Thk (x) For position x The thickness of the silicon wafer is a function of its position x.

[0017] SpaceThe value range is 5~10mm. Selecting a suitable Space value allows for adjustments to symmetrical positions along the cutting direction. Thk dq calculate. Attached Figure Description

[0018] Figure 1 Schematic diagram of thickness measurement using capacitance method;

[0019] Figure 2 Schematic diagram of flatness test pattern after cutting;

[0020] Figure 3 Diagram showing the location of the line marks and the notch;

[0021] Figure 4 . Improved line marks and notch location illustration;

[0022] Figure 5 . Schematic diagram of thickness steepness calculation;

[0023] Figure 6 Example of thickness profile and thickness steepness of two silicon wafers. Implementation

[0024] Example

[0025] Two different silicon wafers were selected, ensuring that their thickness, curvature, warpage, and other parameters were relatively similar. The angle between the notch and the notch direction was adjusted to α. When the initial testing angle β was used, β was adjusted to make α = β. Then, the thickness profile test data along the cutting direction was collected, and the thickness steepness was calculated as follows.

[0026]

[0027] In the formula, Space This represents the sampling length, meaning the thickness steepness is calculated within that length range. Thk (x) For position x The thickness of the silicon wafer is a function of its position x. (Take...) Space The diameter is 6 mm. Symmetrical positions along the cutting direction are -146 mm, -75 mm, 0 mm, 75 mm, and 146 mm. Thk dqCalculations and analysis show that under conventional flatness testing conditions, there is no significant difference between the two silicon wafers. However, data calculated using the testing method of this invention reveals that the silicon wafer exhibits a greater steepness at the start and end of the cutting process, gradually decreasing towards the center from the radius. Furthermore, the maximum steepness data was obtained at the start and end of the cutting process in both cutting operations. Analysis of data from -150mm to -75mm shows that wafer 2 has a higher steepness and a faster change. The process can be improved by comparing the differences in steepness data between the two cutting processes to ensure process stability.

Claims

1. A method for improving the consistency testing of wire dicing data for large silicon wafers, characterized in that, The angle between the cutting mark and the notch is α, and the initial angle of the silicon wafer test is β. β is adjusted to make β=α. Then, the thickness steepness is calculated based on the test data along the cutting direction to characterize the effect of cutting on the silicon wafer morphology. The thickness profile test data along the cutting direction is taken, and the calculation formula is as follows: In the formula, Space represents the sampling length, i.e., the steepness of the thickness is calculated within the sampling length range, and the value of Space is between 5mm and 10mm; Thk (x) Let x be the thickness of the silicon wafer at position x.

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