Gate drive circuit and display device

Abstract

The application provides a gate driving circuit and a display device, and relates to the technical field of display, and aims to solve the problem that the falling time of multi-stage output gate driving signals is inconsistent in the gate driving circuit adopting the GOA technology. The shift register unit in the gate driving circuit comprises a pull-up node, a compensation module and at least two output modules. Each output module is coupled with the pull-up node, a corresponding first clock signal line and a corresponding gate driving signal output end. The compensation module is coupled with a second clock signal line and the pull-up node, and is used for controlling whether the compensation module is connected to the second clock signal transmitted by the second clock signal line under the control of the pull-up node. The compensation module and the output module have the same structure, and the first clock signals transmitted by the first clock signal lines coupled with the at least two output modules and the second clock signals transmitted by the second clock signal lines are sequentially in the effective level.

Description

Technical Field

[0001] This invention relates to the field of display technology, and more particularly to a gate driving circuit and a display device. Background Technology

[0002] In the display industry, to reduce the cost of display panel materials and achieve narrow bezel designs, more gate drive circuits are adopting GOA (Gate on Array) technology. This technology integrates the gate drive circuit onto the array substrate. In gate drive circuits using GOA technology, the shift registers included are called GOA cells.

[0003] The GOA cell structure is relatively complex and still occupies a lot of edge space. In order to further optimize the edge design, multi-stage output GOA cells are particularly important. However, in related technologies, the fall time of the gate drive signal of multi-stage output is inconsistent. Summary of the Invention

[0004] The purpose of this invention is to provide a gate driving circuit and a display device to solve the problem of inconsistent fall times of gate driving signals output by multiple stages in a gate driving circuit using GOA technology.

[0005] To achieve the above objectives, the present invention provides the following technical solution:

[0006] A first aspect of the present invention provides a gate driving circuit, including a shift register unit, the shift register unit comprising: a pull-up node, a compensation module, and at least two output modules;

[0007] Each of the output modules is coupled to the pull-up node, the corresponding first clock signal line and the corresponding gate drive signal output terminal, and is used to control the electrical connection between the corresponding first clock signal line and the gate drive signal output terminal to be turned on or off under the control of the pull-up node; the gate drive signal output terminals coupled to the at least two output modules output gate drive signals in sequence.

[0008] The compensation module is coupled to the second clock signal line and the pull-up node respectively, and is used to control whether the compensation module is connected to the second clock signal transmitted by the second clock signal line under the control of the pull-up node; the compensation module has the same structure as the output module, and the first clock signal transmitted by each first clock signal line coupled to the at least two output modules and the second clock signal transmitted by the second clock signal line are sequentially at an effective level.

[0009] Optionally, the output module includes an output transistor and an output control capacitor. The gate of the output transistor is coupled to the pull-up node, the first terminal of the output transistor is coupled to a corresponding first clock signal line, and the second terminal of the output transistor is coupled to a corresponding gate drive signal output terminal. The first terminal of the output control capacitor is coupled to the gate of the output transistor, and the second terminal of the output control capacitor is coupled to the second terminal of the output transistor. The capacitance between the output transistor and the pull-up node is a*Ctft+m1, where a is the channel width of the output transistor, Ctft is the parasitic capacitance of the output transistor, and m1 is the capacitance of the output control capacitor.

[0010] The compensation module includes a compensation transistor and a compensation capacitor. The gate of the compensation transistor is coupled to the pull-up node, the first terminal of the compensation transistor is coupled to the second clock signal line, the second terminal of the compensation transistor is coupled to the second terminal of the compensation capacitor, and the first terminal of the compensation capacitor is coupled to the gate of the compensation transistor. The capacitance between the compensation transistor and the pull-up node is b*Ctft2+m2, where b is the channel width of the compensation transistor, Ctft2 is the parasitic capacitance of the compensation transistor, and m2 is the capacitance of the compensation capacitor; a*Ctft+m1=b*Ctft2+m2.

[0011] Optionally, the shift register unit includes: a decoder module, a node set module, a pre-control module, a node control module, and a reset module; the shift register unit further includes: a control node and a pull-down node;

[0012] The node setting module is coupled to a first level signal line, a third clock signal line, a reset signal line, a pull-up node, a second level signal line, and a pull-down node, respectively. It is used to control the electrical connection between the first level signal line and the pull-down node to be turned on or off under the control of the third clock signal line and the reset signal line; it is also used to control the electrical connection between the pull-down node and the second level signal line to be turned on or off under the control of the pull-up node.

[0013] The pre-control module is coupled to the second clock signal line, the first level signal line, the output terminal of the decoder module, the reset signal line, the second level signal line, the control node, and the pull-up node, respectively, and is used to control the electrical connection between the control node and the pull-up node to be turned on or off under the control of the second clock signal line, the output terminal of the decoder module, and the reset signal line.

[0014] The node control module is coupled to the fourth clock signal line, the first level signal line and the control node respectively, and is used to control the electrical connection between the first level signal line and the control node to be turned on or off under the control of the fourth clock signal line.

[0015] The reset module is coupled to the control node, the pull-up node, the pull-down node, the plurality of gate drive signal output terminals, and the second level signal line, respectively. It is used to control the electrical connection between the control node, the pull-up node, any one of the plurality of gate drive signal output terminals, and the second level signal line under the control of the pull-down node. It is also used to control the electrical connection between the pull-down node and the second level signal line under the control of the pull-up node.

[0016] Optionally, the compensation module is also coupled to the pull-down node and the second level signal line respectively, and is also used to control whether the compensation module is connected to the second level signal transmitted by the second level signal line.

[0017] Optionally, the shift register unit further includes:

[0018] A first auxiliary pull-down module is coupled to the third clock signal line, the pull-up node, and the second level signal line, respectively, and is used to control the electrical connection between the pull-up node and the second level signal line to be turned on or off under the control of the third clock signal line.

[0019] Optionally, the pre-control module includes: a second capacitor, a twelfth transistor, a fourteenth transistor, a seventeenth transistor, and a twenty-second transistor;

[0020] The first terminal of the second capacitor is coupled to the first level signal line;

[0021] The gate of the twelfth transistor is coupled to the output terminal of the decoder module, the first terminal of the twelfth transistor is coupled to the second clock signal line, and the second terminal of the twelfth transistor is coupled to the second terminal of the second capacitor.

[0022] The gate of the fourteenth transistor is coupled to the second clock signal line, the first terminal of the fourteenth transistor is coupled to the first level signal line, and the second terminal of the fourteenth transistor is coupled to the second terminal of the second capacitor.

[0023] The gate of the seventeenth transistor is coupled to the reset signal line, the first terminal of the seventeenth transistor is coupled to the second terminal of the second capacitor, and the second terminal of the seventeenth transistor is coupled to the second level signal line;

[0024] The gate of the twentieth transistor is coupled to the second terminal of the second capacitor, the first terminal of the twentieth transistor is coupled to the control node, and the second terminal of the twentieth transistor is coupled to the pull-up node.

[0025] Optionally, the shift register unit further includes:

[0026] The first leakage protection module is coupled to the first level signal line, the second terminal of the second capacitor, the output terminal of the decoder module, and the second terminal of the twelfth transistor. Under the control of the second terminal of the second capacitor, the first leakage protection module controls the conduction or disconnection of the electrical connection between the first level signal line and the second terminal of the twelfth transistor. It is also used to control the conduction or disconnection of the electrical connection between the second terminal of the twelfth transistor and the second terminal of the second capacitor under the control of the output terminal of the decoder module.

[0027] Optionally, the first leakage protection module includes: a thirteenth transistor and a fifteenth transistor;

[0028] The gate of the thirteenth transistor is coupled to the output terminal of the decoder module, the first terminal of the thirteenth transistor is coupled to the second terminal of the twelfth transistor, and the second terminal of the thirteenth transistor is coupled to the second terminal of the second capacitor.

[0029] The gate of the fifteenth transistor is coupled to the second terminal of the second capacitor, the first terminal of the fifteenth transistor is coupled to the first level signal line, and the second terminal of the fifteenth transistor is coupled to the second terminal of the twelfth transistor.

[0030] Optionally, the shift register unit further includes:

[0031] The second leakage protection module is coupled to the reset signal line, the first terminal of the seventeenth transistor, and the second terminal of the second capacitor, respectively. It is used to control the conduction or disconnection of the electrical connection between the first terminal of the seventeenth transistor and the second terminal of the second capacitor under the control of the reset signal line. The second terminal of the fifteenth transistor is also coupled to the first terminal of the seventeenth transistor.

[0032] Optionally, the reset module includes: a twenty-first transistor, a twenty-fifth transistor, and a plurality of output reset transistors;

[0033] The gate of the 21st transistor is coupled to the pull-down node, the first terminal of the 21st transistor is coupled to the control node, and the second terminal of the 21st transistor is coupled to the second level signal line;

[0034] The gate of the 25th transistor is coupled to the pull-down node, the first terminal of the 25th transistor is coupled to the pull-up node, and the second terminal of the 25th transistor is coupled to the second level signal line;

[0035] The gate of the output reset transistor is coupled to the pull-down node, the second terminal of the output reset transistor is coupled to the second level signal line, and the first terminal of the output reset transistor is coupled to the corresponding gate drive signal output terminal.

[0036] Optionally, the shift register unit further includes: a third leakage protection module; the third leakage protection module is coupled to the pull-up node, the first level signal line and the pull-down node respectively;

[0037] The third leakage protection module is also coupled to the control node and the first terminal of the 21st transistor respectively; and / or, the third leakage protection module is also coupled to the first terminal of the 25th transistor;

[0038] The third leakage protection module is used, under the control of the pull-up node, to control the connection between the first level signal line and the first terminal of the 21st transistor to be turned on or off; and is also used, under the control of the pull-down node, to control the connection between the control node and the first terminal of the 21st transistor to be turned on or off; and / or,

[0039] The third leakage protection module is used to control the connection between the first level signal line and the first terminal of the twenty-fifth transistor under the control of the pull-up node; it is also used to control the connection between the pull-up node and the first terminal of the twenty-fifth transistor under the control of the pull-down node.

[0040] Optionally, the third leakage protection module includes a twenty-third transistor, and the third leakage protection module further includes a twentyth transistor and / or a twenty-fourth transistor;

[0041] The gate of the 23rd transistor is coupled to the pull-up node, the first terminal of the 23rd transistor is coupled to the first level signal line, and the second terminal of the 23rd transistor is coupled to the first terminal of the 21st transistor and / or the first terminal of the 25th transistor.

[0042] The gate of the twentieth transistor is coupled to the pull-down node, the first terminal of the twentieth transistor is coupled to the control node, and the second terminal of the twentieth transistor is coupled to the first terminal of the twentieth eleventh transistor.

[0043] The gate of the 24th transistor is coupled to the pull-down node, the first terminal of the 24th transistor is coupled to the pull-up node, and the second terminal of the 24th transistor is coupled to the first terminal of the 25th transistor.

[0044] Optionally, the decoder module includes a plurality of decoder transistors, the gate of the decoder transistors being coupled to the input terminal of the decoder module, the first terminal of the decoder transistors being coupled to the third clock signal line, and the second terminal of the decoder transistors being coupled to the output terminal of the decoder module.

[0045] The node setting module includes a first transistor, an eleventh transistor, and a sixteenth transistor. The gate of the first transistor is coupled to the third clock signal line, the first terminal of the first transistor is coupled to the first level signal line, and the second terminal of the first transistor is coupled to the pull-down node. The gate of the eleventh transistor is coupled to the pull-up node, the first terminal of the eleventh transistor is coupled to the pull-down node, and the second terminal of the eleventh transistor is coupled to the second level signal line. The gate of the sixteenth transistor is coupled to the reset signal line, the first terminal of the sixteenth transistor is coupled to the first level signal line, and the second terminal of the sixteenth transistor is coupled to the pull-down node.

[0046] The node control module includes a nineteenth transistor, the gate of which is coupled to the fourth clock signal line, the first terminal of which is coupled to the first level signal line, and the second terminal of which is coupled to the control node.

[0047] Optionally, the shift register unit further includes: a second auxiliary pull-down module, which is coupled to the second clock signal line, the output terminal of the decoder module, and the second level signal line, respectively, and is used to control the electrical connection between the output terminal of the decoder module and the second level signal line under the control of the second clock signal line.

[0048] Based on the technical solution of the gate driving circuit, a second aspect of the present invention provides a display device including the aforementioned gate driving circuit.

[0049] In the technical solution provided by this invention, the shift register unit includes a compensation module and at least two output modules. By setting the compensation module and the output modules to have the same structure, the load generated by the compensation module and the output modules relative to the pull-up node is the same. By setting the first clock signal transmitted by each first clock signal line coupled to the at least two output modules and the second clock signal transmitted by each second clock signal line to be at an effective level sequentially, it is possible to ensure that the rising edge of the second clock signal arrives when the falling edge of the first clock signal output from the penultimate first clock signal line arrives. In this way, the effect of the falling edge of the first clock signal output from the penultimate first clock signal line on the pull-up node can be canceled out by the rising edge of the second clock signal, thereby ensuring that the falling time of the gate drive signal output from the gate drive signal output terminal coupled to each output module is consistent.

[0050] In the technical solution provided by the embodiments of the present invention, by controlling each of the output modules and the compensation module simultaneously through the pull-up node, not only is the fall time of the gate drive signal output by each gate drive signal output terminal consistent, but the shift register unit also has a simplified structure, which is beneficial to the development of high resolution and narrow bezel of display products. Attached Figure Description

[0051] The accompanying drawings, which are included to provide a further understanding of the invention and form part of this invention, illustrate exemplary embodiments of the invention and are used to explain the invention, but do not constitute an undue limitation of the invention. In the drawings:

[0052] Figure 1 This is a schematic diagram of the first circuit structure of the shift register unit provided in an embodiment of the present invention;

[0053] Figure 2 This is a schematic diagram of the second circuit structure of the shift register unit provided in an embodiment of the present invention;

[0054] Figure 3 A schematic diagram of the third circuit structure of the shift register unit provided in an embodiment of the present invention;

[0055] Figure 4 This is a timing diagram of the shift register unit provided in an embodiment of the present invention;

[0056] Figure 5 A simulation diagram illustrating the gate drive signals output by multiple output modules provided in an embodiment of the present invention;

[0057] Figure 6 Timing diagrams of multiple shift register units provided in embodiments of the present invention;

[0058] Figure 7This is a schematic diagram of the cascading of multiple shift register units provided in an embodiment of the present invention. Detailed Implementation

[0059] To further illustrate the gate driving circuit and display device provided in the embodiments of the present invention, a detailed description is provided below with reference to the accompanying drawings.

[0060] Please see Figure 1 , Figure 4 , Figure 5 and Figure 6 This invention provides a gate driving circuit, including a shift register unit, which includes a pull-up node Q1, a compensation module 10, and at least two output modules 11.

[0061] Each of the output modules 11 is connected to the pull-up node Q1, and the corresponding first clock signal line (e.g., Figure 1 (CLKA, CLKA1, CLKA2, CLKA3) and their corresponding gate drive signal output terminals (e.g., ... Figure 1 The SCout(i), SCout(i+1), SCout(i+2), and SCout(i+3) are coupled to control the electrical connection between the corresponding first clock signal line and the gate drive signal output terminal under the control of the pull-up node Q1; the at least two output modules 11 output gate drive signals sequentially from the corresponding coupled gate drive signal output terminals.

[0062] The compensation module 10 is connected to the second clock signal line (e.g., Figure 1 The compensation module 10 is coupled to the pull-up node Q1 and is used to control whether the compensation module 10 is connected to the second clock signal transmitted by the second clock signal line under the control of the pull-up node Q1; the compensation module 10 has the same structure as the output module 11, and the first clock signal transmitted by each first clock signal line coupled to the at least two output modules 11 is (e.g., CLKB in the above-mentioned clock signal line). Figure 6 CLKE1, CLKE2, CLKE3, CLKE4) and the second clock signal transmitted by the second clock signal line (such as CLKE1, CLKE2, CLKE3, CLKE4) Figure 6 CLKE5 in the middle is in the active level in sequence.

[0063] During the output phase P4, the potential of the pull-up node Q1 is maintained at a high level and can be coupled to a higher voltage. The effective levels (such as high level) of the multiple first clock signals transmitted by the multiple first clock signal lines arrive sequentially. The multiple output modules 11 control the multiple gate drive signal output terminals to output gate drive signals sequentially. The compensation module 10 is configured to connect to the second clock signal transmitted by the second clock signal line under the control of the pull-up node Q1.

[0064] For example, the first clock signal transmitted on each of the first clock signal lines coupled to the at least two output modules 11 and the second clock signal transmitted on each of the second clock signal lines are sequentially at an active level. The rising edge of the second clock signal arrives when the falling edge of the first clock signal output from the penultimate first clock signal line arrives.

[0065] When the gate driving circuit is applied in a display device, the shift register unit included in the gate driving circuit is coupled to the scan lines in the display device. For example, the shift register unit includes four output modules 11, each coupled to one of the four scan lines. The size of the output transistors included in each output module 11 is determined by the load of the scan line. With consistent scan line loads, to ensure consistent fall times, it is only necessary to ensure that the voltage of the pull-up node Q1 is consistent when each output module 11 is outputting. Assuming the effective level overlap rate of each of the first clock signals is 50%, the potential of the pull-up node Q1 remains unchanged before and after the output of the first three output modules 11. However, when the fourth output module 11 outputs, the falling edge of the first clock signal transmitted by the first clock signal line coupled to the third output module 11 arrives. This falling edge will affect the potential of the pull-up node Q1, requiring other signals to cancel out this effect.

[0066] like Figure 5 The diagram shown is a simulation schematic of the gate drive signals output by the multiple output modules 11 provided in an embodiment of the present invention. Figure 5 The first row of the timing diagram shows the timing of the pull-up node Q1. The second to fourth rows are timing diagrams of the gate drive signals output sequentially by each output module 11. It can be seen that the fall time of each gate drive signal is 0.82 microseconds.

[0067] As can be seen from the specific structure of the display substrate, the gate driving circuit provided in this embodiment of the invention includes a shift register unit comprising a compensation module 10 and at least two output modules 11. By setting the compensation module 10 and the output module 11 to have the same structure, the load generated by the compensation module 10 and the output module 11 relative to the pull-up node Q1 is the same. By setting the first clock signal transmitted by each first clock signal line coupled to the at least two output modules 11 and the second clock signal transmitted by the second clock signal line to be at an effective level in sequence, it is possible to achieve that when the falling edge of the first clock signal output by the penultimate first clock signal line arrives, the rising edge of the second clock signal arrives. In this way, the effect of the falling edge of the first clock signal output by the penultimate first clock signal line on the pull-up node Q1 can be canceled by the rising edge of the second clock signal, thereby ensuring that the falling time of the gate driving signal output by the gate driving signal output terminal coupled to each output module 11 is consistent.

[0068] In the gate driving circuit provided in this embodiment of the invention, the pull-up node Q1 simultaneously controls each of the output modules 11 and the compensation module 10, which not only ensures that the fall time of the gate driving signal output by each gate driving signal output terminal is consistent, but also ensures that the shift register unit has a simplified structure, which is beneficial to the development of high resolution and narrow bezel of display products.

[0069] like Figure 1 As shown, in some embodiments, the output module 11 includes output transistors (such as the twenty-sixth transistor T26, the twenty-eighth transistor T28, the thirtieth transistor T30, and the thirty-second transistor T32) and output control capacitors (such as the third capacitor C3, the fourth capacitor C4, the fifth capacitor C5, and the sixth capacitor C6). The gate of the output transistor is coupled to the pull-up node Q1, the first terminal of the output transistor is coupled to the corresponding first clock signal line, and the second terminal of the output transistor is coupled to the corresponding gate drive signal output terminal. The first terminal of the output control capacitor is coupled to the gate of the output transistor, and the second terminal of the output control capacitor is coupled to the second terminal of the output transistor. The capacitance between the output transistor and the pull-up node Q1 is a*Ctft+m1, where a is the channel width of the output transistor, Ctft is the parasitic capacitance of the output transistor, and m1 is the capacitance of the output control capacitor.

[0070] The compensation module 10 includes a compensation transistor T34 and a compensation capacitor C7. The gate of the compensation transistor T34 is coupled to the pull-up node Q1. The first terminal of the compensation transistor T34 is coupled to the second clock signal line. The second terminal of the compensation transistor T34 is coupled to the second terminal of the compensation capacitor C7. The first terminal of the compensation capacitor C7 is coupled to the gate of the compensation transistor T34. The capacitance between the compensation transistor T34 and the pull-up node Q1 is b*Ctft2+m2, where b is the channel width of the compensation transistor T34, Ctft2 is the parasitic capacitance of the compensation transistor T34, and m2 is the capacitance of the compensation capacitor C7; a*Ctft+m1=b*Ctft2+m2.

[0071] For example, in order to ensure that the compensation module 10 does not occupy too much layout space of the shift register unit, the position of the compensation transistor T34 can be set closer to the bottom edge of the display device, and the capacitance value of the compensation capacitor C7 can be set to be larger, so as to ensure that when the rising edge of the second clock signal arrives, the effect of the falling edge of the first clock signal on the pull-up node Q1 can be canceled.

[0072] The above setting a*Ctft+m1=b*Ctft2+m2 ensures that the load generated by the compensation module 10 and the output module 11 relative to the pull-up node Q1 is the same. This further enables the effect of the falling edge of the first clock signal output from the penultimate first clock signal line on the pull-up node Q1 to be canceled by the rising edge of the second clock signal, thereby ensuring that the falling time of the gate drive signal output from the gate drive signal output terminal coupled to each output module 11 is consistent.

[0073] Please see Figure 1 In some embodiments, the shift register unit includes: a decoder module 12, a node set module 13, a pre-control module 14, a node control module 15, and a reset module 16; the shift register unit also includes: a control node Q and a pull-down node QB;

[0074] The node setting module 13 is connected to the first level signal line VGH and the third clock signal line (e.g., ...). Figure 1 The circuit consists of CLKC, a reset signal line TRS, a pull-up node Q1, a second-level signal line VGL, and a pull-down node QB. Under the control of the third clock signal line and the reset signal line TRS, it controls the electrical connection between the first-level signal line VGH and the pull-down node QB to be turned on or off. It also controls the electrical connection between the pull-down node QB and the second-level signal line VGL to be turned on or off under the control of the pull-up node Q1.

[0075] The pre-control module 14 is respectively connected to the second clock signal line (e.g. Figure 1 The following are the components: CLKB, the first level signal line VGH, the output terminal of the decoder module 12, the reset signal line TRS, the second level signal line VGL, the control node Q, and the pull-up node Q1 are coupled together to control the electrical connection between the control node Q and the pull-up node Q1 under the control of the second clock signal line, the output terminal of the decoder module 12, and the reset signal line TRS.

[0076] The node control module 15 is connected to the fourth clock signal line (e.g., Figure 1 In the CLKD), the first level signal line VGH is coupled to the control node Q, and is used to control the electrical connection between the first level signal line VGH and the control node Q to be turned on or off under the control of the fourth clock signal line.

[0077] The reset module 16 is coupled to the control node Q, the pull-up node Q1, the pull-down node QB, the plurality of gate drive signal output terminals, and the second level signal line VGL, respectively. It is used to control the electrical connection between the control node Q, the pull-up node Q1, the plurality of gate drive signal output terminals, and the second level signal line VGL under the control of the pull-down node QB. It is also used to control the electrical connection between the pull-down node QB and the second level signal line VGL under the control of the pull-up node Q1.

[0078] like Figure 4 As shown in the figure, the driving method of the shift register unit includes the following stages:

[0079] Phase 1: Overall Reset Phase P1;

[0080] The reset signal transmitted by the reset signal line TRS is at an effective level, for example, a high level. The node setting module 13, under the control of the reset signal line TRS, controls the electrical connection between the first level signal line VGH and the pull-down node QB, sets the pull-down node QB high, and discharges the control node Q and the pull-up node Q1. The pre-control module 14, under the control of the reset signal line TRS, discharges the P node in the pre-control module 14. In the first stage, except for the reset signal, all other signals are at ineffective levels, such as a low level.

[0081] Phase 2: P node high-level phase P2;

[0082] The reset signal transmitted by the reset signal line TRS remains at an inactive level, for example, a low level, during the scan period. As the rising edge of the second clock signal transmitted by the second clock signal line arrives, the potential of node P is set high. The third clock signal transmitted by the third clock signal line is at an active level, for example, a high level. Since all inputs to decoder module 12 are low, the pull-down unit (i.e., the twelfth transistor T12) of node P in node set module 13 is cut off, allowing node P to remain at a high potential.

[0083] Phase 3: The electrical state of control node Q and pull-up node Q1 is high during phase P3;

[0084] Since node P remains at a high potential, the pre-control module 14 connects the electrical connection between the control node Q and the pull-up node Q1. The fourth clock signal transmitted by the fourth clock signal line is at an effective level, such as a high level. Under the control of the fourth clock signal line, the node control module 15 controls the electrical connection between the first level signal line VGH and the control node Q, pulling the potential of the control node Q and the pull-up node Q1 high. Under the control of the pull-up node Q1, the node setting module 13 controls the electrical connection between the pull-down node QB and the second level signal line VGL, pulling the potential of the pull-down node QB low.

[0085] Phase 4: Output Phase P4;

[0086] The potential of pull-up node Q1 is maintained at a high level and can be coupled to a higher voltage. Multiple first clock signal lines (e.g., CLKA, CLKA1, CLKA2, CLKA3) transmit multiple first clock signals (e.g., ... Figure 6 When the effective levels (e.g., high level) of CLKE1, CLKE2, CLKE3, and CLKE4 in the output module 11 arrive sequentially, the multiple output modules 11 control the multiple gate drive signal output terminals to sequentially output gate drive signals (e.g., high level). Figure 6 SCout1, SCout2, SCout3, and SCout4 in the above; the compensation module 10 is configured under the control of the pull-up node Q1 to access the second clock signal transmitted on the second clock signal line (e.g., SCout1, SCout2, SCout3, and SCout4 in the above); Figure 6 (CLKE5 in the middle).

[0087] Phase 5: Node Reset Phase (P5)

[0088] As the third clock signal transmitted on the third clock signal line reaches a high level, the pull-down node QB is pulled high again, and the reset module 16 controls the control node Q and the pull-up node Q1 to be pulled low, keeping the output low.

[0089] like Figure 6 and Figure 7The diagram illustrates the connection of five shift register units (GOA1, GOA2, GOA3, GOA4, GOA5). Each group of four shift register units forms a shift register group, and each shift register unit drives four rows of sub-pixels. The strobe signals of each shift register unit within a group are connected in the same way, meaning the input connections of the decoder module 12 in each shift register unit within the group are identical. The gate driving circuit provided in this embodiment of the invention can perform zone control and resolution adjustment without cascading.

[0090] like Figure 6 and Figure 7 As shown, it should be noted that D0-D7 and D0'-D7' represent the decoding signals input to the decoder module 12, and D0'-D7' are the inverted signals of D0-D7. SCout1, SCout2, SCout3, and SCout4 represent the four gate drive signal outputs of the first shift register unit. SCout5, SCout6, SCout7, and SCout8 represent the four gate drive signal outputs of the second shift register unit. SCout9, SCout10, SCout11, and SCout12 represent the four gate drive signal outputs of the third shift register unit. SCout13, SCout14, SCout15, and SCout16 represent the four gate drive signal outputs of the fourth shift register unit. SCout17, SCout18, SCout19, and SCout20 represent the four gate drive signal outputs of the fifth shift register unit.

[0091] like Figure 6 and Figure 7 As shown, it should be noted that CLKE1 to CLKE16 represent the first clock signals transmitted via the first clock signal lines coupled to each shift register unit. CLK, CLK1, CLK2, and CLK3 represent the ports of each output module 11 connected to the first clock signal lines. The timing of the second clock signal line is the same as that of the first clock signal CLKE5. The timing of the third clock signal line is the same as that of the first clock signal CLKE9. The timing of the fourth clock signal line is the same as that of the first clock signal CLKE13. CLKD1 to CLKD4 represent the fourth clock signals connected to the fourth clock signal lines.

[0092] For example, the decoding signals connected to the input terminal of the decoder module 12 include: D0 to D7, and the inverted signals D0'-D7' of D0 to D7, a total of 16 signals, which can drive a display with any resolution of no more than 16*2^8 lines.

[0093] For example, in each shift register unit, when each gate drive signal output terminal outputs a gate drive signal, the potential of the pull-up node Q1 satisfies uniformity.

[0094] like Figure 3 As shown, in some embodiments, the compensation module 10 is also coupled to the pull-down node QB and the second level signal line VGL, respectively, and is also used to control whether the compensation module 10 is connected to the second level signal transmitted by the second level signal line VGL.

[0095] For example, the compensation module 10 further includes a thirty-fifth transistor T35, the gate of which is coupled to the pull-down node QB, the first terminal of which is coupled to the second terminal of the thirty-fourth transistor T34, and the second terminal of which is coupled to the second level signal line VGL.

[0096] The above configuration ensures that when the pull-down node QB resets the gate drive signal output terminal, the compensation module 10 can also access the second level signal transmitted by the second level signal line VGL. This not only ensures the working stability of the compensation module 10, but also allows the compensation module 10 to have the same structure as the output module 11 part and the reset module 16 part (i.e., the output reset transistor) that are correspondingly coupled to each gate drive signal output terminal in the output module 11, thereby better ensuring the uniformity of the pull-up node Q1 in the output stage.

[0097] like Figure 1 As shown, in some embodiments, the shift register unit further includes:

[0098] The first auxiliary pull-down module 17 is coupled to the third clock signal line (e.g., CLKC), the pull-up node Q1, and the second level signal line VGL, respectively, and is used to control the conduction or disconnection of the electrical connection between the pull-up node Q1 and the second level signal line VGL under the control of the third clock signal line.

[0099] In the second stage, the second clock signal transmitted by the second clock signal line and the third clock signal transmitted by the third clock signal line are sequentially at an effective level, such as a high level. Under the control of the third clock signal line, the node setting module 13 controls the conduction of the electrical connection between the pull-down node QB and the first level signal line VGH, pulling the potential of the pull-down node QB high. Under the control of the third clock signal line, the first auxiliary pull-down module 17 controls the conduction of the electrical connection between the pull-up node Q1 and the second level signal line VGL, pulling the potential of the pull-up node Q1 low.

[0100] For example, the first auxiliary pull-down module 17 includes a thirty-sixth transistor T36, the gate of which is coupled to the third clock signal line, the first terminal of which is coupled to the pull-up node Q1, and the second terminal of which is coupled to the second level signal line VGL.

[0101] The above configuration allows the potential of the pull-up node Q1 to be pulled down more effectively in the second stage, preventing the pull-up node Q1 from affecting the potential of the pull-down node QB through the node setting module 13 (such as the eleventh transistor T11 in the node setting module 13), which helps the potential of the pull-down node QB to be raised better in the second stage.

[0102] like Figure 1 As shown, in some embodiments, the pre-control module 14 includes: a second capacitor C2, a twelfth transistor T12, a fourteenth transistor T14, a seventeenth transistor T17, and a twenty-second transistor T22;

[0103] The first terminal of the second capacitor C2 is coupled to the first level signal line VGH;

[0104] The gate of the twelfth transistor T12 and the output terminal of the decoder module 12 (e.g.) Figure 1 The first terminal of the twelfth transistor T12 is coupled to the second clock signal line (such as CLKB), and the second terminal of the twelfth transistor T12 is coupled to the second terminal of the second capacitor C2.

[0105] The gate of the fourteenth transistor T14 is coupled to the second clock signal line, the first terminal of the fourteenth transistor T14 is coupled to the first level signal line VGH, and the second terminal of the fourteenth transistor T14 is coupled to the second terminal of the second capacitor C2.

[0106] The gate of the seventeenth transistor T17 is coupled to the reset signal line TRS, the first terminal of the seventeenth transistor T17 is coupled to the second terminal of the second capacitor C2, and the second terminal of the seventeenth transistor T17 is coupled to the second level signal line VGL.

[0107] The gate of the twelfth transistor T22 is coupled to the second terminal of the second capacitor C2, the first terminal of the twelfth transistor T22 is coupled to the control node Q, and the second terminal of the twelfth transistor T22 is coupled to the pull-up node Q1.

[0108] like Figure 2 As shown, in some embodiments, the shift register unit further includes:

[0109] The first leakage protection module 18 is coupled to the first level signal line VGH, the second terminal of the second capacitor C2, the output terminal of the decoder module 12, and the second terminal of the twelfth transistor T12. Under the control of the second terminal of the second capacitor C2, the first leakage protection module 18 is used to control the conduction or disconnection of the electrical connection between the first level signal line VGH and the second terminal of the twelfth transistor T12. It is also used to control the conduction or disconnection of the electrical connection between the second terminal of the twelfth transistor T12 and the second terminal of the second capacitor C2 under the control of the output terminal of the decoder module 12.

[0110] like Figure 2 As shown, in some embodiments, the first leakage protection module 18 includes: a thirteenth transistor T13 and a fifteenth transistor T15;

[0111] The gate of the thirteenth transistor T13 is coupled to the output terminal of the decoder module 12, the first terminal of the thirteenth transistor T13 is coupled to the second terminal of the twelfth transistor T12, and the second terminal of the thirteenth transistor T13 is coupled to the second terminal of the second capacitor C2.

[0112] The gate of the fifteenth transistor T15 is coupled to the second terminal of the second capacitor C2, the first terminal of the fifteenth transistor T15 is coupled to the first level signal line VGH, and the second terminal of the fifteenth transistor T15 is coupled to the second terminal of the twelfth transistor T12.

[0113] For example, the thirteenth transistor T13 controls whether the second terminal of the twelfth transistor T12 is electrically connected to the second terminal of the second capacitor C2.

[0114] The above configuration allows the fifteenth transistor T15 to conduct when the twelfth transistor T12 is in the off state but leakage occurs, writing the high-level signal transmitted by the first level signal line VGH into the first terminal of the thirteenth transistor T13, so that the thirteenth transistor T13 can be completely turned off, thereby effectively preventing the twelfth transistor T12 from leaking current to the P node.

[0115] like Figure 2 As shown, in some embodiments, the shift register unit further includes:

[0116] The second leakage protection module 19 is coupled to the reset signal line TRS, the first terminal of the seventeenth transistor T17, and the second terminal of the second capacitor C2, respectively. Under the control of the reset signal line TRS, the second module 19 controls the conduction or disconnection of the electrical connection between the first terminal of the seventeenth transistor T17 and the second terminal of the second capacitor C2. The second terminal of the fifteenth transistor T15 is also coupled to the first terminal of the seventeenth transistor T17.

[0117] For example, the second leakage protection module 19 includes an eighteenth transistor T18, the gate of which is coupled to the reset signal line TRS, the first terminal of which is coupled to the second terminal of the second capacitor C2, and the second terminal of which is coupled to the first terminal of the seventeenth transistor T17.

[0118] The above configuration allows the fifteenth transistor T15 to conduct when the seventeenth transistor T17 is in the off state but leakage occurs, writing the high-level signal transmitted by the first level signal line VGH into the second terminal of the eighteenth transistor T18, so that the eighteenth transistor T18 can be completely turned off, thereby further preventing the seventeenth transistor T17 from leaking current to the P node.

[0119] like Figure 1 As shown, in some embodiments, the reset module 16 includes: a twenty-first transistor T21, a twenty-fifth transistor T25, and a plurality of output reset transistors (e.g., a twenty-seventh transistor T27, a twenty-ninth transistor T29, a thirty-first transistor T31, and a thirty-third transistor T33).

[0120] The gate of the 21st transistor T21 is coupled to the pull-down node QB, the first terminal of the 21st transistor T21 is coupled to the control node Q, and the second terminal of the 21st transistor T21 is coupled to the second level signal line VGL.

[0121] The gate of the 25th transistor T25 is coupled to the pull-down node QB, the first terminal of the 25th transistor T25 is coupled to the pull-up node Q1, and the second terminal of the 25th transistor T25 is coupled to the second level signal line VGL.

[0122] The gate of the output reset transistor is coupled to the pull-down node QB, the second terminal of the output reset transistor is coupled to the second level signal line VGL, and the first terminal of the output reset transistor is coupled to the corresponding gate drive signal output terminal.

[0123] like Figure 2As shown, in some embodiments, the shift register unit further includes: a third leakage protection module 20; the third leakage protection module 20 is coupled to the pull-up node Q1, the first level signal line VGH and the pull-down node QB respectively;

[0124] The third leakage protection module 20 is also coupled to the control node Q and the first terminal of the 21st transistor T21 respectively; and / or, the third leakage protection module 20 is also coupled to the first terminal of the 25th transistor T25;

[0125] The third leakage protection module 20 is used, under the control of the pull-up node Q1, to control the electrical connection between the first level signal line VGH and the first terminal of the 21st transistor T21 to be turned on or off; and is also used, under the control of the pull-down node QB, to control the electrical connection between the control node Q and the first terminal of the 21st transistor T21 to be turned on or off; and / or,

[0126] The third leakage protection module 20 is used to control the electrical connection between the first level signal line VGH and the first terminal of the twenty-fifth transistor T25 under the control of the pull-up node Q1; it is also used to control the electrical connection between the pull-up node Q1 and the first terminal of the twenty-fifth transistor T25 under the control of the pull-down node QB.

[0127] For example, the third leakage protection module 20 includes a twenty-third transistor T23, and the third leakage protection module 20 also includes a twentieth transistor T20 and / or a twenty-fourth transistor T24;

[0128] The gate of the 23rd transistor T23 is coupled to the pull-up node Q1, the first terminal of the 23rd transistor T23 is coupled to the first level signal line VGH, and the second terminal of the 23rd transistor T23 is coupled to the first terminal of the 21st transistor T21 and / or the first terminal of the 25th transistor T25.

[0129] The gate of the twentieth transistor T20 is coupled to the pull-down node QB, the first terminal of the twentieth transistor T20 is coupled to the control node Q, and the second terminal of the twentieth transistor T20 is coupled to the first terminal of the twentieth transistor T21.

[0130] The gate of the 24th transistor T24 is coupled to the pull-down node QB, the first terminal of the 24th transistor T24 is coupled to the pull-up node Q1, and the second terminal of the 24th transistor T24 is coupled to the first terminal of the 25th transistor T25.

[0131] The above configuration allows the twentieth transistor T20 and / or the twenty-fourth transistor T24 to conduct, and the twenty-third transistor T23 to conduct, when the twentieth transistor T21 and / or the twenty-fifth transistor T25 are in the off state but leakage occurs. This allows the high-level signal transmitted by the first level signal line VGH to be written to the second terminal of the twentieth transistor T20 and / or the second terminal of the twenty-fourth transistor T24, enabling the twentieth transistor T20 and / or the twenty-fourth transistor T24 to be completely turned off. This avoids leakage from the twentieth transistor T21 to the control node Q and avoids leakage from the twenty-fifth transistor T25 to the upward pull-up node Q1.

[0132] It should be noted that when the shift register unit includes the first leakage protection module 18, the second leakage protection module 19 and the third leakage protection module 20, it can be applied to oxide backplanes.

[0133] like Figure 1 As shown, in some embodiments, the decoder module 12 includes a plurality of decoder transistors (e.g., a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, an eighth transistor T8, and a ninth transistor T9). The gate of each decoder transistor is coupled to the input terminal of the decoder module 12, the first terminal of each decoder transistor is coupled to the third clock signal line (e.g., CLKC), and the second terminal of each decoder transistor is coupled to the output terminal of the decoder module 12.

[0134] The node setting module 13 includes a first transistor T1, an eleventh transistor T11, and a sixteenth transistor T16. The gate of the first transistor T1 is coupled to the third clock signal line (e.g., CLKC), the first terminal of the first transistor T1 is coupled to the first level signal line VGH, and the second terminal of the first transistor T1 is coupled to the pull-down node QB. The gate of the eleventh transistor T11 is coupled to the pull-up node Q1, the first terminal of the eleventh transistor T11 is coupled to the pull-down node QB, and the second terminal of the eleventh transistor T11 is coupled to the second level signal line VGL. The gate of the sixteenth transistor T16 is coupled to the reset signal line TRS, the first terminal of the sixteenth transistor T16 is coupled to the first level signal line VGH, and the second terminal of the sixteenth transistor T16 is coupled to the pull-down node QB.

[0135] The node control module 15 includes a nineteenth transistor T19, the gate of which is coupled to the fourth clock signal line, the first terminal of which is coupled to the first level signal line VGH, and the second terminal of which is coupled to the control node Q.

[0136] like Figure 1 As shown, the plurality of decoder transistors include a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, an eighth transistor T8, and a ninth transistor T9.

[0137] For example, the shift register unit further includes a first capacitor C1, a first end of which is coupled to the pull-down node QB, and a second end of which is coupled to the second level signal line VGL.

[0138] like Figure 1 As shown, it is worth noting that the size of the output transistors (such as the 26th transistor T26, the 28th transistor T28, the 30th transistor T30, and the 32nd transistor T32) is determined by the load of their coupled gate lines. Since the gate line loads are all the same, in order to ensure that the fall time of the gate drive signal is consistent, it is only necessary to ensure that the gate line voltage (i.e., the potential of the pull-up node Q1) is consistent when each gate drive signal output terminal outputs the gate drive signal. Assuming that the waveform overlap rate of the gate drive signal output terminals is 50%, the potential of the pull-up node Q1 can remain unchanged before and after the first 3 rows of output. However, when the 32nd transistor T32 starts to output, the potential of the pull-up node Q1 drops due to the falling edge of the 30th transistor T30, and there is no rising edge of other output transistors to cancel it out. Therefore, when the 32nd transistor T32 outputs, a compensation module 10 needs to be introduced. The compensation transistor T34 and the compensation capacitor C7 in the compensation module 10 can be set to be exactly the same as the 32nd transistor T32 and the output control capacitor C6.

[0139] like Figure 3 As shown, in some embodiments, the compensation module 10 includes a thirty-fifth transistor T35, the gate of which is coupled to the pull-down node QB, the first terminal of which is coupled to the second terminal of the thirty-fourth transistor, and the second terminal of which is coupled to the second level signal line VGL.

[0140] The above configuration ensures that when the pull-down node QB resets the gate drive signal output terminal, the thirty-fifth transistor is turned on and connected to the second level signal transmitted by the second level signal line VGL. This not only ensures the working stability of the compensation module 10, but also allows the compensation module 10 to have the same structure as the output module 11 part (i.e., the output sub-module) and the reset module 16 part (i.e., the output reset transistor) that are correspondingly coupled to each gate drive signal output terminal in the output module 11, thereby better ensuring the uniformity of the Q1 node in the output stage.

[0141] like Figure 2 As shown, in some embodiments, the shift register unit further includes: a second auxiliary pull-down module 21, which is coupled to the second clock signal line (such as CLKB), the output terminal of the decoder module 12, and the second level signal line VGL, respectively, and is used to control the electrical connection between the output terminal of the decoder module 12 and the second level signal line VGL under the control of the second clock signal line.

[0142] For example, the second auxiliary pull-down module 21 includes a tenth transistor T10, the gate of which is coupled to the second clock signal line, the first terminal of which is coupled to the output terminal of the decoder module 12, and the second terminal of which is electrically connected to the second level signal line VGL.

[0143] In the second stage, under the control of the second clock signal line, the second auxiliary pull-down module 21 controls the electrical connection between the output terminal of the decoder module 12 and the second level signal line VGL, further pulling down the potential of the output terminal of the decoder module 12.

[0144] This invention also provides a display device, including the gate driving circuit provided in the above embodiments.

[0145] For example, the display device includes an organic light-emitting diode display device, but is not limited thereto.

[0146] It should be noted that the display device can be any product or component with display function, such as a television, monitor, digital photo frame, mobile phone, or tablet computer. The display device also includes flexible circuit boards, printed circuit boards, and backplanes.

[0147] In the gate drive circuit provided in the above embodiment, the shift register unit includes a compensation module and at least two output modules. By setting the compensation module and the output module to have the same structure, the load generated by the compensation module and the output module relative to the pull-up node is the same. By setting the first clock signal transmitted by each first clock signal line coupled to the at least two output modules and the second clock signal transmitted by the second clock signal line to be at an effective level in sequence, it is possible to ensure that the rising edge of the second clock signal arrives when the falling edge of the first clock signal output by the penultimate first clock signal line arrives. In this way, the effect of the falling edge of the first clock signal output by the penultimate first clock signal line on the pull-up node can be canceled by the rising edge of the second clock signal, thereby ensuring that the falling time of the gate drive signal output by the gate drive signal output terminal coupled to each output module is consistent.

[0148] In the gate driving circuit provided in the above embodiments, the pull-up node simultaneously controls each of the output modules and the compensation module, which not only ensures that the fall time of the gate driving signal output by each gate driving signal output terminal is consistent, but also ensures that the shift register unit has a simplified structure, which is beneficial to the development of high resolution and narrow bezel of display products.

[0149] The display device provided in the embodiments of the present invention, when including the above-described gate driving circuit, also has the above-described beneficial effects, which will not be repeated here.

[0150] It should be noted that, in the embodiments of the present invention, "same layer" can refer to film layers located on the same structural layer. Alternatively, for example, film layers located on the same layer can be layer structures formed by using the same film deposition process to form a specific pattern, and then patterning the film layer using the same photomask through a single patterning process. Depending on the specific pattern, the single patterning process may include multiple exposure, development, or etching processes, and the specific pattern in the formed layer structure can be continuous or discontinuous. These specific patterns may also be at different heights or have different thicknesses.

[0151] In the various method embodiments of the present invention, the sequence numbers of each step are not intended to limit the order of the steps. For those skilled in the art, any changes in the order of the steps without creative effort are also within the scope of protection of the present invention.

[0152] It should be noted that the various embodiments in this specification are described in a progressive manner, and the same or similar parts between the various embodiments can be referred to mutually. Each embodiment focuses on describing the differences from other embodiments. In particular, the method embodiments are basically similar to the product embodiments, so the description is relatively simple, and the relevant parts can be referred to the description of the product embodiments.

[0153] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this invention pertains. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as “comprising” or “including” mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. Terms such as “connection,” “coupled,” or “linked” are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. Terms such as “upper,” “lower,” “left,” and “right” are used only to indicate relative positional relationships; these relative positional relationships may change accordingly when the absolute position of the described object changes.

[0154] It is understandable that when a component such as a layer, film, region, or substrate is referred to as being "above" or "below" another component, the component may be "directly" located "above" or "below" the other component, or there may be intermediate components present.

[0155] In the description of the above embodiments, specific features, structures, materials, or characteristics may be combined in any suitable manner in one or more embodiments or examples.

[0156] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A gate driving circuit, characterized in that, It includes a shift register unit, which includes: a pull-up node, a compensation module, and at least two output modules; Each of the output modules is coupled to the pull-up node, the corresponding first clock signal line and the corresponding gate drive signal output terminal, and is used to control the electrical connection between the corresponding first clock signal line and the gate drive signal output terminal to be turned on or off under the control of the pull-up node; the gate drive signal output terminals coupled to the at least two output modules output gate drive signals in sequence. The compensation module is coupled to the second clock signal line and the pull-up node respectively, and is used to control whether the compensation module is connected to the second clock signal transmitted by the second clock signal line under the control of the pull-up node; the compensation module has the same structure as the output module, and the first clock signal transmitted by each first clock signal line coupled to the at least two output modules and the second clock signal transmitted by the second clock signal line are sequentially at an effective level; The output module includes an output transistor and an output control capacitor. The gate of the output transistor is coupled to the pull-up node, the first terminal of the output transistor is coupled to the corresponding first clock signal line, and the second terminal of the output transistor is coupled to the corresponding gate drive signal output terminal. The first terminal of the output control capacitor is coupled to the gate of the output transistor, and the second terminal of the output control capacitor is coupled to the second terminal of the output transistor. The capacitance between the output transistor and the pull-up node is a*Ctft+m1, where a is the channel width of the output transistor, Ctft is the parasitic capacitance of the output transistor, and m1 is the capacitance of the output control capacitor. The compensation module includes a compensation transistor and a compensation capacitor. The gate of the compensation transistor is coupled to the pull-up node, the first terminal of the compensation transistor is coupled to the second clock signal line, the second terminal of the compensation transistor is coupled to the second terminal of the compensation capacitor, and the first terminal of the compensation capacitor is coupled to the gate of the compensation transistor. The capacitance between the compensation transistor and the pull-up node is b*Ctft2+m2, where b is the channel width of the compensation transistor, Ctft2 is the parasitic capacitance of the compensation transistor, and m2 is the capacitance of the compensation capacitor; a*Ctft+m1=b*Ctft2+m2.

2. The gate driving circuit according to claim 1, characterized in that, The shift register unit includes: a decoder module, a node set module, a pre-control module, a node control module, and a reset module; the shift register unit also includes: a control node and a pull-down node; The node setting module is coupled to a first level signal line, a third clock signal line, a reset signal line, a pull-up node, a second level signal line, and a pull-down node, respectively. It is used to control the electrical connection between the first level signal line and the pull-down node to be turned on or off under the control of the third clock signal line and the reset signal line; it is also used to control the electrical connection between the pull-down node and the second level signal line to be turned on or off under the control of the pull-up node. The pre-control module is coupled to the second clock signal line, the first level signal line, the output terminal of the decoder module, the reset signal line, the second level signal line, the control node, and the pull-up node, respectively, and is used to control the electrical connection between the control node and the pull-up node to be turned on or off under the control of the second clock signal line, the output terminal of the decoder module, and the reset signal line. The node control module is coupled to the fourth clock signal line, the first level signal line and the control node respectively, and is used to control the electrical connection between the first level signal line and the control node to be turned on or off under the control of the fourth clock signal line. The reset module is coupled to the control node, the pull-up node, the pull-down node, a plurality of gate drive signal output terminals, and the second level signal line, respectively. It is used to control the electrical connection between the control node, the pull-up node, any one of the plurality of gate drive signal output terminals, and the second level signal line under the control of the pull-down node. It is also used to control the electrical connection between the pull-down node and the second level signal line under the control of the pull-up node.

3. The gate driving circuit according to claim 2, characterized in that, The compensation module is also coupled to the pull-down node and the second level signal line respectively, and is also used to control whether the compensation module is connected to the second level signal transmitted by the second level signal line.

4. The gate driving circuit according to claim 2, characterized in that, The shift register unit further includes: A first auxiliary pull-down module is coupled to the third clock signal line, the pull-up node, and the second level signal line, respectively, and is used to control the electrical connection between the pull-up node and the second level signal line to be turned on or off under the control of the third clock signal line.

5. The gate driving circuit according to claim 2, characterized in that, The pre-control module includes: a second capacitor, a twelfth transistor, a fourteenth transistor, a seventeenth transistor, and a twenty-second transistor; The first terminal of the second capacitor is coupled to the first level signal line; The gate of the twelfth transistor is coupled to the output terminal of the decoder module, the first terminal of the twelfth transistor is coupled to the second clock signal line, and the second terminal of the twelfth transistor is coupled to the second terminal of the second capacitor. The gate of the fourteenth transistor is coupled to the second clock signal line, the first terminal of the fourteenth transistor is coupled to the first level signal line, and the second terminal of the fourteenth transistor is coupled to the second terminal of the second capacitor. The gate of the seventeenth transistor is coupled to the reset signal line, the first terminal of the seventeenth transistor is coupled to the second terminal of the second capacitor, and the second terminal of the seventeenth transistor is coupled to the second level signal line; The gate of the twentieth transistor is coupled to the second terminal of the second capacitor, the first terminal of the twentieth transistor is coupled to the control node, and the second terminal of the twentieth transistor is coupled to the pull-up node.

6. The gate driving circuit according to claim 5, characterized in that, The shift register unit further includes: The first leakage protection module is coupled to the first level signal line, the second terminal of the second capacitor, the output terminal of the decoder module, and the second terminal of the twelfth transistor. Under the control of the second terminal of the second capacitor, the first leakage protection module controls the conduction or disconnection of the electrical connection between the first level signal line and the second terminal of the twelfth transistor. It is also used to control the conduction or disconnection of the electrical connection between the second terminal of the twelfth transistor and the second terminal of the second capacitor under the control of the output terminal of the decoder module.

7. The gate driving circuit according to claim 6, characterized in that, The first leakage protection module includes: a thirteenth transistor and a fifteenth transistor; The gate of the thirteenth transistor is coupled to the output terminal of the decoder module, the first terminal of the thirteenth transistor is coupled to the second terminal of the twelfth transistor, and the second terminal of the thirteenth transistor is coupled to the second terminal of the second capacitor. The gate of the fifteenth transistor is coupled to the second terminal of the second capacitor, the first terminal of the fifteenth transistor is coupled to the first level signal line, and the second terminal of the fifteenth transistor is coupled to the second terminal of the twelfth transistor.

8. The gate driving circuit according to claim 7, characterized in that, The shift register unit further includes: The second leakage protection module is coupled to the reset signal line, the first terminal of the seventeenth transistor, and the second terminal of the second capacitor, respectively. It is used to control the conduction or disconnection of the electrical connection between the first terminal of the seventeenth transistor and the second terminal of the second capacitor under the control of the reset signal line. The second terminal of the fifteenth transistor is also coupled to the first terminal of the seventeenth transistor.

9. The gate driving circuit according to claim 2, characterized in that, The reset module includes: a twenty-first transistor, a twenty-fifth transistor, and multiple output reset transistors; The gate of the 21st transistor is coupled to the pull-down node, the first terminal of the 21st transistor is coupled to the control node, and the second terminal of the 21st transistor is coupled to the second level signal line; The gate of the 25th transistor is coupled to the pull-down node, the first terminal of the 25th transistor is coupled to the pull-up node, and the second terminal of the 25th transistor is coupled to the second level signal line; The gate of the output reset transistor is coupled to the pull-down node, the second terminal of the output reset transistor is coupled to the second level signal line, and the first terminal of the output reset transistor is coupled to the corresponding gate drive signal output terminal.

10. The gate driving circuit according to claim 9, characterized in that, The shift register unit further includes: a third leakage protection module; the third leakage protection module is coupled to the pull-up node, the first level signal line and the pull-down node respectively; The third leakage protection module is also coupled to the control node and the first terminal of the 21st transistor respectively; and / or, the third leakage protection module is also coupled to the first terminal of the 25th transistor; The third leakage protection module is used, under the control of the pull-up node, to control the connection between the first level signal line and the first terminal of the 21st transistor to be turned on or off; and is also used, under the control of the pull-down node, to control the connection between the control node and the first terminal of the 21st transistor to be turned on or off; and / or, The third leakage protection module is used to control the connection between the first level signal line and the first terminal of the twenty-fifth transistor under the control of the pull-up node; it is also used to control the connection between the pull-up node and the first terminal of the twenty-fifth transistor under the control of the pull-down node.

11. The gate driving circuit according to claim 10, characterized in that, The third leakage protection module includes a twenty-third transistor, and the third leakage protection module also includes a twentyth transistor and / or a twenty-fourth transistor; The gate of the 23rd transistor is coupled to the pull-up node, the first terminal of the 23rd transistor is coupled to the first level signal line, and the second terminal of the 23rd transistor is coupled to the first terminal of the 21st transistor and / or the first terminal of the 25th transistor. The gate of the twentieth transistor is coupled to the pull-down node, the first terminal of the twentieth transistor is coupled to the control node, and the second terminal of the twentieth transistor is coupled to the first terminal of the twentieth eleventh transistor. The gate of the 24th transistor is coupled to the pull-down node, the first terminal of the 24th transistor is coupled to the pull-up node, and the second terminal of the 24th transistor is coupled to the first terminal of the 25th transistor.

12. The gate driving circuit according to claim 2, characterized in that, The decoder module includes a plurality of decoder transistors, the gate of the decoder transistors being coupled to the input terminal of the decoder module, the first terminal of the decoder transistors being coupled to the third clock signal line, and the second terminal of the decoder transistors being coupled to the output terminal of the decoder module. The node setting module includes a first transistor, an eleventh transistor, and a sixteenth transistor. The gate of the first transistor is coupled to the third clock signal line, the first terminal of the first transistor is coupled to the first level signal line, and the second terminal of the first transistor is coupled to the pull-down node. The gate of the eleventh transistor is coupled to the pull-up node, the first terminal of the eleventh transistor is coupled to the pull-down node, and the second terminal of the eleventh transistor is coupled to the second level signal line. The gate of the sixteenth transistor is coupled to the reset signal line, the first terminal of the sixteenth transistor is coupled to the first level signal line, and the second terminal of the sixteenth transistor is coupled to the pull-down node. The node control module includes a nineteenth transistor, the gate of which is coupled to the fourth clock signal line, the first terminal of which is coupled to the first level signal line, and the second terminal of which is coupled to the control node.

13. The gate driving circuit according to claim 2, characterized in that, The shift register unit further includes a second auxiliary pull-down module, which is coupled to the second clock signal line, the output terminal of the decoder module, and the second level signal line, respectively, and is used to control the electrical connection between the output terminal of the decoder module and the second level signal line under the control of the second clock signal line.

14. A display device, characterized in that, Includes the gate drive circuit as described in any one of claims 1 to 13.

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