Bit flipping decoder using dynamic bit flipping criteria

Abstract

The present disclosure relates to bit flip decoder using dynamic bit flip criteria. Methods, systems, and apparatuses include receiving a codeword stored in a memory device. Syndrome information and an energy function value are determined for a bit of the codeword. The syndrome information from a plurality of values is used to select a bit flip criterion. The bit of the codeword is flipped when the energy function value of the bit of the codeword satisfies the bit flip criterion. A corrected codeword resulting from the flip of the bit is returned.

Description

Technical Field

[0001] This disclosure generally relates to error correction in memory devices, and more specifically, to a bit-flip decoder that selects and uses dynamic bit-flip criteria. Background Technology

[0002] The memory subsystem may include one or more memory devices for storing data. For example, the memory devices may be non-volatile memory devices and volatile memory devices. Generally, a host system may utilize the memory subsystem to store data at the memory devices and retrieve data from the memory devices. Summary of the Invention

[0003] In one aspect, this disclosure relates to a method comprising: receiving a codeword stored in a memory device; determining checksum information of the codeword; selecting a bit-flipping criterion from a plurality of values ​​using the checksum information; determining an energy function value of a bit in the codeword; flipping each of one or more bits of the codeword in response to the energy function value of the bit satisfying the bit-flipping criterion; and returning a corrected codeword derived from the flipped bits of the codeword.

[0004] On the other hand, this disclosure relates to a non-transitory computer-readable storage medium comprising instructions that, when executed by a processing means, cause the processing means to: receive a codeword stored in a memory means; determine checksum information of the codeword; select a bit-flipping criterion from a plurality of values ​​using the checksum information; determine an energy function value of a bit of the codeword; flip each of one or more bits of the codeword in response to the energy function value of the bit satisfying the bit-flipping criterion; and return a corrected codeword derived from the flipped bits of the codeword.

[0005] On the other hand, this disclosure relates to a system comprising: a memory device; and a processing device operatively coupled to the memory device, the processing device being configured to: receive a codeword stored in the memory device; determine a number of parity violations of the codeword; select a bit-flipping criterion from a plurality of values ​​using the number of parity violations; determine an energy function value of a bit in the codeword; flip each of one or more bits of the codeword in response to the energy function value of the bit satisfying the bit-flipping criterion; and return a corrected codeword derived from the flipped bits of the codeword. Attached Figure Description

[0006] This disclosure will be more fully understood from the detailed description given below and from the accompanying drawings of various embodiments thereof. However, the drawings should not be construed as limiting this disclosure to the specific embodiments, but are for explanation and understanding only.

[0007] Figure 1This describes an example computing system including a memory subsystem according to some embodiments of the present disclosure.

[0008] Figure 2 This is a flowchart of an example method for bit flipping based on dynamic bit flipping criteria according to some embodiments of the present disclosure.

[0009] Figure 3 A block diagram illustrating an exemplary lookup table, according to some embodiments, that can be used to determine the energy function values ​​of bits in a codeword and bit-flipping criteria.

[0010] Figure 4 This is a flowchart of another example method of bit flipping based on dynamic bit flipping criteria according to some embodiments of the present disclosure.

[0011] Figure 5 This is a block diagram of an example computer system in which embodiments of this disclosure may be operated. Detailed Implementation

[0012] This disclosure relates to a bit-flipping decoder based on soft information. The memory subsystem may be a storage device, a memory module, or a hybrid of a storage device and a memory module. The following is in conjunction with... Figure 1 Describe examples of storage devices and memory modules. Generally, a host system may utilize a memory subsystem comprising one or more components, such as a memory device for storing data. The host system can provide data to be stored in the memory subsystem and can request data to be retrieved from the memory subsystem.

[0013] Memory devices can be non-volatile memory devices. A non-volatile memory device is a package of one or more dies. An example of a non-volatile memory device is a NAND flash memory device. The following section will discuss this further. Figure 1 Other examples of non-volatile memory devices are described. A die in a package may be assigned to one or more channels for communication with the memory subsystem controller. Each die may consist of one or more planes. Planes may be divided into logical units (LUNs). For some types of non-volatile memory devices (e.g., NAND devices), each plane consists of a set of physical blocks, which are groups of memory cells used to store data. A cell is an electronic circuit that stores information.

[0014] Depending on the cell type, a cell can store one or more bits of binary information and has various logic states related to the number of bits stored. Logic states can be represented by binary values ​​such as "0" and "1" or combinations of such values. Various types of cells exist, such as single-level cells (SLC), multi-level cells (MLC), three-level cells (TLC), and four-level cells (QLC). For example, an SLC can store one bit of information and has two logic states.

[0015] Low-density parity-check (LDPC) codes are commonly used for error correction in memory subsystems. LDPC codes are a class of efficient linear block codes that incorporate single-parity (SPC) codes. LDPC codes offer high error correction capabilities and performance approaching Shannon channel capacity. LDPC decoders utilize a "belief propagation" algorithm, which is based on iterative exchanges of reliability information (e.g., "beliefs"). The MinSum algorithm (MSA) (a simplified version of the belief propagation algorithm) can be used to decode LDPC codes. MSA-based decoders use relatively high energy (e.g., picojoules per bit) to decode codewords and are therefore less suitable for energy-sensitive applications (e.g., mobile applications). Bit-flip (BF) decoders have been introduced to address this issue. BF decoders use less energy per bit. However, BF decoders offer lower error correction capabilities compared to MSA-based decoders.

[0016] The BF decoder is an iterative decoder. In each iteration of the decoding process, the BF decoder uses a bit-flipping threshold to determine which bits to flip. The bit-flipping threshold (or flipping criterion) can be chosen to make the decoder more aggressive / less aggressive in terms of flipping more / fewer bits. For example, bits can be flipped based on a comparison of the energy function of each bit with the bit-flipping criterion. The value of the bit-flipping criterion determines the convergence rate of the decoder, and therefore the number of decoder iterations.

[0017] Most reads will typically have a low bit error rate, but occasional reads will have a higher bit error rate. At a higher bit error rate, the BF decoder uses more iterations to decode than at a lower bit error rate, resulting in variable latency. The BF decoder uses a fixed bit-flip criterion, which presents a trade-off between latency and performance in terms of false flips (flipping bits that were originally correct). A more aggressive bit-flip criterion generally reduces the number of iterations, resulting in less latency and higher throughput, but can also lead to more false flips, resulting in poorer performance / a higher codeword error rate (CWER) (the ratio / probability of the BF decoder failing to correct errors and triggering a series of error recovery steps). This is acceptable for decoding data with a low bit error rate, but unacceptable for data with a high bit error rate. A less aggressive bit-flip criterion is usually chosen because it reduces false flips and CWER, which is important for data with a high bit error rate, but at the cost of increased latency and reduced throughput—for example, for data with a low bit error rate.

[0018] This disclosure addresses the aforementioned and other shortcomings by dynamically adjusting the bit-flipping criterion of the BF decoder based on the estimated bit error rate. At higher bit error rates (e.g., in cases with numerous errors in the codeword), a less aggressive bit-flipping decoder will have higher correction capability (e.g., a less aggressive flipping criterion will result in a lower CWER). At lower bit error rates, the decoder can use an aggressive flipping criterion to flip bits more aggressively without risking a significant increase in CWER. The BF decoder can use checksum information calculated by iterations of the decoding process (e.g., the first iteration) as the estimated bit error rate, setting the bit-flipping criterion more aggressively for estimated bit rates at / below a threshold and less aggressively for estimated bit rates at / above a threshold. This dynamic adjustment results in reduced decoder latency, higher decoder throughput, and better Quality of Service (QoS).

[0019] Figure 1 This description describes an example computing system 100 including a memory subsystem 110 according to some embodiments of the present disclosure. The memory subsystem 110 may include media, such as one or more volatile memory devices (e.g., memory device 140), one or more non-volatile memory devices (e.g., memory device 130), or a combination thereof.

[0020] The memory subsystem 110 may be a storage device, a memory module, or a hybrid of a storage device and a memory module. Examples of storage devices include solid-state drives (SSDs), flash drives, universal serial bus (USB) flash drives, embedded multimedia controller (eMMC) drives, universal flash memory (UFS) drives, secure digital cards (SD cards), and hard disk drives (HDDs). Examples of memory modules include dual in-line memory modules (DIMMs), small outline DIMMs (SO-DIMMs), and various types of non-volatile dual in-line memory modules (NVDIMMs).

[0021] The computing system 100 may be a computing device, such as a desktop computer, laptop computer, web server, mobile device, vehicle (e.g., airplane, drone, train, car or other vehicle), Internet of Things (IoT) enabled device, embedded computer (e.g., a computer contained in a vehicle, industrial equipment or networked business device), or the computing device containing memory and processing device.

[0022] The computing system 100 may include a host system 120 coupled to one or more memory subsystems 110. In some embodiments, the host system 120 is coupled to different types of memory subsystems 110. Figure 1This describes an example of a host system 120 coupled to a memory subsystem 110. As used herein, “coupled to” or “coupled with” generally refers to a connection between components, which can be an indirect or direct communication connection (e.g., without an intermediary component), whether wired or wireless, including, for example, electrical, optical, magnetic, etc.

[0023] Host system 120 may include a processor chipset and a software stack executed by the processor chipset. The processor chipset may include one or more cores, one or more caches, a memory controller (e.g., an NVDIMM controller), and a storage protocol controller (e.g., a PCIe controller, a SATA controller). For example, host system 120 uses memory subsystem 110 to write data to memory system 110 and read data from memory system 110.

[0024] Host system 120 may be coupled to memory subsystem 110 via a physical host interface. Examples of physical host interfaces include (but are not limited to) Serial Advanced Technology Attachment (SATA) interface, Peripheral Component Interconnect Fast (PCIe) interface, Universal Serial Bus (USB) interface, Fibre Channel, Serial Attached SCSI (SAS), Small Computer System Interface (SCSI), Double Data Rate (DDR) memory bus, Dual In-line Memory Module (DIMM) interface (e.g., a DIMM slot interface supporting Double Data Rate (DDR)), Open NAND Flash Interface (ONFI), Double Data Rate (DDR), Low Power Double Data Rate (LPDDR), or any other interface. The physical host interface can be used to transfer data between host system 120 and memory subsystem 110. Host system 120 may further utilize an NVM Fast (NVMe) interface to access components (e.g., memory device 130) when memory subsystem 110 is coupled to host system 120 via a PCIe interface. The physical host interface provides an interface for transmitting control, address, data and other signals between the memory subsystem 110 and the host system 120. Figure 1 The memory subsystem 110 is described as an example. Generally, the host system 120 can access multiple memory subsystems via the same communication connection, multiple individual communication connections, and / or combinations of communication connections.

[0025] Memory devices 130 and 140 may include any combination of different types of non-volatile memory devices and / or volatile memory devices. Volatile memory devices (e.g., memory device 140) may be (but are not limited to) random access memory (RAM), such as dynamic random access memory (DRAM) and synchronous dynamic random access memory (SDRAM).

[0026] Some examples of non-volatile memory devices (e.g., memory device 130) include NAND flash memory and in-place write memory, such as three-dimensional cross-point ("3D cross-point") memory devices, which are cross-point arrays of non-volatile memory cells. The cross-point array of non-volatile memory can perform bit storage based on changes in volume resistance in conjunction with a stackable cross-grid data access array. Furthermore, in contrast to many flash-based memories, cross-point non-volatile memory can perform in-place write operations, where non-volatile memory cells can be programmed without prior erasing of the non-volatile memory cells. NAND flash memory includes, for example, two-dimensional NAND (2D NAND) and three-dimensional NAND (3D NAND).

[0027] Although a non-volatile memory device and a 3D cross-point array of non-volatile memory cells, such as NAND type memory (e.g., 2D NAND, 3D NAND), are described, the memory device 130 may be based on any other type of non-volatile memory, such as read-only memory (ROM), phase-change memory (PCM), self-select memory, other chalcogenide-based memory, ferroelectric transistor random access memory (FeTRAM), ferroelectric random access memory (FeRAM), magnetic random access memory (MRAM), spin-transfer torque (STT)-MRAM, conductive bridged RAM (CBRAM), resistive random access memory (RRAM), oxide-based RRAM (OxRAM), NOR flash memory, and electrically erasable programmable read-only memory (EEPROM).

[0028] The memory subsystem controller 115 (or, for simplicity, controller 115) can communicate with the memory device 130 to perform operations such as reading data, writing data, or erasing data at the memory device 130, and other such operations (e.g., in response to commands scheduled by controller 115 on the command bus). The memory subsystem controller 115 may include hardware such as one or more integrated circuits and / or discrete components, buffer memories, or combinations thereof. The hardware may include a digital circuit system with dedicated (i.e., hard-coded) logic to perform the operations described herein. The memory subsystem controller 115 may be a microcontroller, a dedicated logic circuit system (e.g., a field-programmable gate array (FPGA), an application-specific integrated circuit (ASIC), etc.), or another suitable processor.

[0029] The memory subsystem controller 115 may include a processing means 117 (processor) configured to execute instructions stored in local memory 119. In the illustrated example, the local memory 119 of the memory subsystem controller 115 includes embedded memory configured to store routines for performing various processes, operations, logical flows, and controlling the operations of the memory system 110, including handling communication between the memory subsystem 110 and the host system 120.

[0030] In some embodiments, local memory 119 may include memory registers that store memory pointers, fetched data, etc. Local memory 119 may also include read-only memory (ROM) for storing microcode. Although Figure 1 The instance memory subsystem 110 has been described as including a memory subsystem controller 115, but in another embodiment of this disclosure, the memory subsystem 110 does not include a memory subsystem controller 115 and may instead rely on external control (e.g., provided by an external host or by a processor or controller separate from the memory subsystem 110).

[0031] Generally, the memory subsystem controller 115 can receive commands or operations from the host system 120 and can translate these commands or operations into instructions or appropriate commands to achieve the desired access to memory devices 130 and / or 140. The memory subsystem controller 115 may be responsible for other operations, such as wear leveling operations, garbage collection operations, error detection and error correction code (ECC) operations, encryption operations, caching operations, and address translation between logical addresses (e.g., logical block addresses, namespaces) and physical addresses (e.g., physical block addresses) associated with memory device 130. The memory subsystem controller 115 may further include a host interface circuitry for communicating with the host system 120 via a physical host interface. The host interface circuitry can translate commands received from the host system into command instructions to access memory devices 130 and / or 140, and translate responses associated with memory devices 130 and / or 140 into information for the host system 120.

[0032] The memory subsystem 110 may also include additional circuitry or components not described. In some embodiments, the memory subsystem 110 may include caches or buffers (e.g., DRAM) and address circuitry (e.g., row decoders and column decoders) capable of receiving addresses from the memory subsystem controller 115 and decoding the addresses to access the memory device 130.

[0033] In some embodiments, memory device 130 includes a local media controller 135, which operates in conjunction with a memory subsystem controller 115 to perform operations on one or more memory cells of memory device 130. An external controller (e.g., memory subsystem controller 115) may externally manage memory device 130 (e.g., perform media management operations on memory device 130). In some embodiments, memory device 130 is a managed memory device, which is a native memory device combined with a local controller (e.g., local controller 135) for media management within the same memory device package. An example of a managed memory device is a managed NAND (MNAND) device.

[0034] The memory subsystem 110 includes an error corrector 113 that can perform error correction using a bit-flipping decoder that flips bits based on a dynamic bit-flipping criterion. In some embodiments, the controller 115 includes at least a portion of the error corrector 113. For example, the controller 115 may include a processor 117 (processing means) configured to execute instructions stored in local memory 119 for performing the operations described herein. In some embodiments, the error corrector 113 is part of the host system 120, an application, or an operating system.

[0035] In some embodiments, error corrector 113 is operable to encode and decode data stored in a memory device (e.g., an encoder and / or decoder). Encoding data using error correction codes (ECC) allows for the correction of erroneous data bits when data is retrieved from the memory device. For example, error corrector 113 may encode data received from host system 120 and store the data and parity bits as codewords in memory device 130. Error corrector 113 may further decode the data stored in memory device 130 to identify and correct erroneous bits in the data before transmitting the corrected data to host system 120. Although described as a single component capable of performing data encoding and decoding, error corrector 113 may be implemented as two or more separate components. In some embodiments, error corrector 113 encodes data according to low-density parity check (LDPC) codes. Error corrector 113 decodes the codewords stored in memory device 130 based on / using a BF decoder. As described below, error corrector 113 implements an enhanced BF decoder that performs bit-flip decoding based on a dynamic bit-flipping criterion.

[0036] In one embodiment, error corrector 113 receives a codeword stored in a memory device. Error corrector 113 performs error correction on the codeword over a set of iterations, for example, by flipping bits one or more times. Bits are flipped according to a comparison energy function and a dynamic bit-flipping criterion. Further details regarding the operation of error corrector 113 are described below.

[0037] In some embodiments, error corrector 113 implements a BF decoder that uses soft information to correct errors in codewords. A hard read is a read operation used to distinguish between various states to which a memory cell can be programmed. A hard read returns hard data, such as a number ("0" or "1") corresponding to the state determined by the read operation. Soft data associated with a read can be data other than the hard data obtained from the read operation. Some error correction code schemes use hard data (e.g., bits of the codeword itself) to detect and correct errors in the codeword. Other error correction code schemes can use both hard and soft data to decode the codeword. The use of each of the hard and soft data is described in detail below.

[0038] In some embodiments, the BF decoder defines energy functions for the bits of a codeword. The energy function assigns an energy function value to each codeword bit. The energy function value of a codeword bit can be considered an indication of the reliability information of the codeword bit. In some embodiments, the energy function value of a codeword bit can be determined based on the number of parity violations per codeword bit and channel information. Channel information is determined based on the current state of a bit (after one or more iterations of the BF decoder) relative to a bit read from a memory device (also called a hard bit). In some embodiments, a high energy function value for a bit (e.g., an energy function value greater than or equal to a threshold) indicates a more reliable bit, and a low energy function value for a bit (e.g., an energy function value less than a threshold) indicates a less reliable bit. In some embodiments, the energy function is defined such that when the current state of a bit matches a bit read from a memory device, the bit is considered more reliable (e.g., the energy function value of the bit increases based on whether the current state of the bit matches a hard bit), and when the current state of a bit does not match a bit read from a memory device, the bit is considered less reliable (e.g., the energy function value of the bit decreases). The BF decoder first flips the least reliable bit. While an embodiment will be described using a BF decoder where a high-energy function value indicates a highly reliable bit and a low-energy function value indicates a less reliable bit, and the BF decoder flips the bit with the lower energy function value, other embodiments are contemplated. For example, in some examples, a high-energy function value of a bit may indicate a less reliable bit, and a low-energy function value may indicate a highly reliable bit. In this exemplary embodiment, the BF decoder first flips the least reliable bit, i.e., the bit with the higher energy function value.

[0039] Figure 2 This is a flowchart of an example method 200 for providing bit flipping based on a dynamic bit flipping criterion. Method 200 can be executed by processing logic, which may include hardware (e.g., processing device, circuit system, dedicated logic, programmable logic, microcode, device hardware, integrated circuit, etc.), software (e.g., instructions that run or execute on the processing device), or a combination thereof. In some embodiments, method 200 is performed by… Figure 1Error corrector 113 is executed. Although shown in a specific sequence or order, the order of processes may be modified unless otherwise specified. Therefore, the illustrated embodiments should be understood as examples only, and the illustrated processes may be executed in different orders, and some processes may be executed in parallel. In addition, one or more processes may be omitted in various embodiments. Therefore, not all processes are required in every embodiment. Other process flows are possible.

[0040] At operation 205, the processing device receives a codeword from a memory device. In some embodiments, the codeword is received as a result of a read operation from the host system 120. The codeword comprises a combination of data bits and parity bits. The parity bits are stored in the memory device containing the data bits. The data bits and parity bits are hard data bits derived from a hard read of a memory cell to determine the state of the memory cell (e.g., "0" or "1").

[0041] In some embodiments, the processing device also receives soft information about the codewords. In addition to the bits of the codewords, the soft information may also include bits received from the memory device. In some embodiments, the memory device determines soft information for hard reads. In other embodiments, the memory device does not generate soft information and does not transmit soft information to the processing device. In some embodiments, the memory device generates and transmits soft information for some, but not all, of the codewords it transmits to the processing device. The soft information may indicate a confidence level regarding hard data bits. For example, the soft information may indicate a high confidence level that a hard data bit is correct, and the hard data bit may be referred to as a strong bit. Alternatively, the soft information may indicate a low confidence level in the hard data bits, and the hard data bit may be referred to as a weak bit.

[0042] In some embodiments, soft information indicates a specific voltage to which a memory cell is charged (where the memory cell is the memory cell from which hard data bits are read). For example, a hard data bit is less reliable (i.e., a weak bit) when the associated soft information of a hard data bit indicates that the memory cell is charged to a specific voltage near the boundary between two states, and a hard data bit is more reliable (i.e., a strong bit) when the associated soft information of a hard data bit indicates that the memory cell is charged to a specific voltage near the center of a voltage range corresponding to a state ("0" or "1"). In some embodiments, the soft information may include soft bits for each bit of the hard data bits in a codeword. The soft bits of a hard data bit indicate whether the hard data bit is strong or weak. For example, a soft bit may be "0" when its associated hard data bit is weak, and a soft bit may be "1" when its associated hard data bit is strong. In some embodiments, the number of bits in the soft information of a codeword is strictly less than the number of bits in the codeword. For example, the processing device may receive an index of a strong bit in the codeword. Alternatively, the processing device may receive an index of weak bits in the codeword to reduce the amount of information transmitted from the memory device 130 / 140 to the error corrector 113. In some embodiments, the soft information may contain more than one soft bit for each bit of the hard data bits used in the codeword. For example, when the soft information contains two soft bits, this results in four reliability levels for the bit, such as very weak, weak, strong, and very strong.

[0043] At operation 210, the processing device determines parity information for the codeword. For example, in the first iteration of decoding the codeword using a bit-flip decoder, the processing device performs one or more parity checks on the data bits and parity bits. In one embodiment, the parity information is the number of parity checks satisfied by the codeword. For example, the processing device may determine the number of parity checks satisfied per codeword. In another embodiment, the parity information is the number of parity checks not satisfied (i.e., parity violations of the codeword). In yet another embodiment, the parity information is a value based on the number of parity checks satisfied / not satisfied by the codeword, such as a weighted number of satisfied / not satisfied parity checks, an average number of satisfied / not satisfied parity checks by the codeword, a weighted average number of satisfied / not satisfied parity checks by the codeword, etc.

[0044] At operation 215, the processing device uses parity information to select a bit-flipping criterion. In one embodiment, the processing device uses the parity information as an estimate of the bit error rate (referred to herein as the raw bit error rate or RBER) of the codeword, and thus selects a more aggressive or less aggressive bit-flipping criterion based on the parity information. For example, the processing device may map the number of parity checks that are satisfied / not satisfied or the weighted number of parity checks that are satisfied / not satisfied in the codeword to a bit-flipping criterion value. In one embodiment, the processing device maps a range of satisfied / not satisfied parity values ​​to a single bit-flipping criterion, as in Figure 3 As shown in the image.

[0045] Figure 3 The diagram illustrates an exemplary lookup table 330 that can be used to select a bit-flipping criterion using parity information from a codeword with, for example, 100 parity bits. Although Figure 3 This describes a specific instance of a mapping between several non-compliant parity values ​​(i.e., parity violations) and bit-flip criterion values, but the instance described should be understood as an example only, and other mappings are possible. For example, a mapping may contain a larger number of non-compliant parity values, more than two bit-flip criterion values, a one-to-one mapping, etc.

[0046] As illustrated, the range of 0 to 40 non-satisfied parity 335 maps to a bit-flip criterion value of 10. In some embodiments, the bit-flip criterion is a threshold of the energy function. The processing device determines to flip a bit when the energy function value of a bit satisfies the bit-flip criterion / threshold. For example, the processing device may determine to flip a bit when the energy function value of a bit is less than or equal to the bit-flip criterion / threshold, and not to flip a bit when the energy function value of a bit is greater than the bit-flip criterion / threshold. A range of low non-satisfied parity (e.g., 0 to 40 out of 100 parity bits) represents a codeword with an estimated low RBER. For energy function values ​​falling in the range of 0 to 14, the bit-flip criterion 10 is an aggressive threshold that can result in a larger number of bit flips per iteration and shorter delays when decoding the codeword. For low estimated RBER, the risk of erroneous flips leading to decoding failure is low.

[0047] As explained, the range of 41 to 100 unsatisfied parity values ​​335 maps to a bit-flip criterion value of 6 340. A high range of unsatisfied parity values ​​indicates codewords with an estimated high RBER. For energy function values ​​falling within the range of 0 to 14, bit-flip criterion 6 is a conservative / less aggressive threshold. Therefore, the decoding process involves a smaller number of bit flips per iteration and a longer delay when decoding the codeword. However, with a high estimated RBER, the risk of incorrect flips leading to decoding failure is higher, thus a more conservative bit-flip criterion is justified and results in a lower codeword error rate.

[0048] return Figure 2At operation 220, the processing device determines the energy function value of the bits of the codeword without the presence of soft information about the bits. The energy function of the codeword bits can be considered an indication of the reliability information of the bits. The processing device can determine the energy function value of the bits based on the number of parity checks satisfied by the bits and the channel information of the bits. A higher number of parity checks satisfied indicates a more reliable bit and results in a higher energy function value for the bit. A lower number of parity checks satisfied (more parity violations) indicates a less reliable bit and results in a lower energy function value for the bit. The channel information is determined based on a comparison of the current state of the bit with the state of the bit when it is read from the memory device. For example, the channel information of the bit can be defined as the current state of the bit (which may have been flipped during one or more iterations of decoding) and the 1-XOR of the bit read from the memory device. When the current state of the bit matches the bit read from the memory device, the bit is considered more reliable. Therefore, the bit's energy function value is larger when the bit's current state matches the hard bit, compared to when the bit's current state has been flipped and is inconsistent with the hard bit received from the memory device. In some embodiments, the bit's energy function can be determined by adding the number of parity checks satisfied by the bit to the bit's channel information. In a non-limiting example, the energy function can be determined according to equation (1):

[0049] e (bit) = NumberSatisfiedParities (bits) + Channel Information (bits) (1)

[0050] The higher e (bit) indicates a more reliable bit, and the lower e (bit) indicates a less reliable bit.

[0051] In one embodiment, the processing device determines the energy function value of the bits of the codeword by retrieving energy function values ​​from a lookup table based on the number of parity bits satisfied and whether there is a match or mismatch between the current state of the bits and the hard bits received from the memory device. Figure 3 A block diagram illustrating an exemplary lookup table 320, which can be used to determine the bit energy function values ​​of a codeword according to some embodiments. Although Figure 3 Specific examples of the number of parity checks satisfied by the bits of a codeword and the energy function value are illustrated, but these examples should be understood as merely examples; other energy function values ​​and / or parity checks are possible. Additionally, exemplary lookup table 320 illustrates energy function values ​​based on soft information. Other embodiments use checksums and channel information but determine the energy function values ​​of the codeword bits in the absence of soft information. The energy function values ​​determined in the absence of soft information are referred to herein as default energy function values.

[0052] In embodiments where the processing device uses soft information to determine the energy function values ​​of bits in a codeword, the processing device uses or otherwise determines the energy function values ​​of bits in a codeword based on the number of parity checks satisfied by the bits, the channel information of the bits, and further based on the soft information associated with the bits. In some embodiments, the energy function values ​​of bits can be determined as described above and adjusted according to soft information. For example, a default energy function value for a bit (e(bit)) can be determined according to equation (1), and the processing device determines whether to add a soft information offset, subtract a soft information offset, or not apply a soft information offset based on whether the current state of the bit matches a hard bit.

[0053] In one embodiment, when the soft information indicator bit is strong and the current state of the bit matches a hard bit received from the memory device, an offset is added to the default energy function of the bit to increase the energy function value. Conversely, when the soft information indicator bit is strong and the current state of the bit does not match a hard bit, the offset is subtracted from the default energy function value. Furthermore, when the soft information indicator bit is weak, no offset is applied, and the energy function value of the bit is the default energy function value. Although the embodiment is described using an offset applied when the soft information indicator bit is strong, in other embodiments, an offset is applied when the soft information indicator bit is weak.

[0054] In one embodiment, the processing device determines the energy function value of a bit in a codeword by considering the number of parity bits satisfied, whether there is a match or mismatch between the current state and the hard bits received from the memory device, and further by retrieving energy function values ​​from a lookup table based on soft information associated with the bit. Table 320 contains exemplary energy function values ​​for bits that can be used in a codeword. The processing device determines the bit's energy function value based on the number of parity bits 325 associated with the bit, channel information 322 (whether the current state of the bit matches or mismatches the hard bits 324 or 323), and soft information indicating whether the confidence level in the hard bit is strong 326 / 328 or weak 327 / 329. In the illustrated example, the energy function value associated with a weak bit is the default energy function value (e.g., determined using equation (1)). Therefore, when the hard bit is weak, the bit's energy function value is determined based on the parity information and the channel information. For example, if a bit of a codeword has four satisfying parity checks 325, and its current state does not match the hard bits received from the memory device 323, and its soft information indicates it is weak 327, then the processing device determines the energy function value of the bit to be 10. In another example, if a bit of a codeword has four satisfying parity checks 325, its current state matches the hard bits received from the memory device 324, and its soft information indicates it is weak 329, then the processing device determines the energy function value of the bit to be 12.

[0055] In contrast, the energy function value associated with a strong bit is adjusted by adding or subtracting an offset from the default energy function value. As explained, when a hard bit is strong, the processing device determines the bit's energy function value by adding an offset to the default energy function value when there is a match between the hard bit and the current state of the bit. Conversely, when a hard bit is strong, the processing device determines the bit's energy function value by subtracting an offset from the default energy function value when there is a mismatch between the hard bit and the current state of the bit. For example, if a codeword has four satisfying parity checks 325, and its current state does not match the hard bit received from the memory device 323, and its soft information indicates that the hard bit is strong 326, the processing device determines the bit's energy function value to be 8 (which is the default energy function value 10 minus an offset of 2). In another instance, if the bits of a codeword have 4 satisfying parity checks 325, its current state matches the hard bits received from the memory device 324, and its soft information indicates that the hard bits are strong 328, then the processing device determines the bit's energy function value to be 14 (which corresponds to adding an offset of 2 to its default energy function value of 10).

[0056] Adjusting the bit energy function value based on soft information from the hard bits allows the processing device to distinguish between strong and weak bits and enhance the reliability of strong bits. For example, increasing the energy function of strong bits when a match exists increases the reliability of the bit and reduces the likelihood that the processing device will flip the bit away from the hard bit value. Similarly, decreasing the energy function of strong bits when a mismatch exists reduces the reliability of the bit and increases the likelihood that the bit will be flipped back to the hard bit value. Adjusting the energy function value based on soft information increases the correction capability of the BF decoder.

[0057] At operation 225, when the energy function value of a bit in the codeword satisfies the bit-flipping criterion, the processing device flips zero or more bits of the codeword. The processing device traverses the codeword in a predetermined order and evaluates each bit of the codeword based on its associated energy function value to determine whether to flip the bit. When the energy function value of a bit in the codeword does not satisfy the bit-flipping criterion, the processing device does not flip the bit. When the energy function value of a bit in the codeword satisfies the bit-flipping criterion, the processing device flips the bit. As described above, the processing device determines to flip a bit when the energy function value of a bit satisfies the bit-flipping criterion / threshold. For example, the processing device may determine to flip a bit when the energy function value of a bit is less than or equal to the bit-flipping threshold and determine not to flip a bit when the energy function value of a bit is greater than the bit-flipping threshold.

[0058] At operation 230, the processing device determines whether a stopping criterion is met. The stopping criterion may include an indication that no codeword errors were detected. In some embodiments, the stopping criterion may include a null parity check indicating that the codeword no longer contains erroneous bits (i.e., zero non-satisfied parity checks). In some embodiments, the stopping criterion may include a maximum number of iterations or a maximum time duration. For example, the processing device may be operable to perform a maximum number of iterations (e.g., 30 iterations, 40 iterations, 100 iterations, etc.), and when this number of iterations is reached without null parities, the processing device cannot correct bit errors in the codeword. When the stopping criterion is not met, the processing device performs another iteration. For example, when the stopping criterion is not met, method 200 returns to operation 210 to determine updated parity check information, updated bit-flipping criteria, updated energy function values, etc. When the stopping criterion is met, method 200 proceeds to operation 235.

[0059] At operation 235, the processing device outputs a corrected codeword (e.g., when there are zero non-satisfied parity checks) or a failure indication (e.g., when the processing device is unable to decode the codeword). For example, the processing device may transmit the corrected codeword or the failure indication to host 120.

[0060] Figure 4 This is a flowchart of another example of a bit-flipping method 400 based on a dynamic bit-flipping criterion. Method 400 can be executed by processing logic, which may include hardware (e.g., processing device, circuit system, dedicated logic, programmable logic, microcode, device hardware, integrated circuit, etc.), software (e.g., instructions that run or execute on the processing device), or a combination thereof. In some embodiments, method 400 is performed by… Figure 1 Error corrector 113 is executed. Although shown in a specific sequence or order, the order of processes may be modified unless otherwise specified. Therefore, the illustrated embodiments should be understood as examples only, and the illustrated processes may be executed in different orders, and some processes may be executed in parallel. In addition, one or more processes may be omitted in various embodiments. Therefore, not all processes are required in every embodiment. Other process flows are possible.

[0061] At operation 405, the processing device receives a codeword from the memory device. Similar to operation 205, the codeword may be received as the result of a read request from the host system 120, and the codeword contains a combination of data bits and parity bits. In some embodiments, the processing device also receives soft information about the codeword as described above.

[0062] At operation 410, the processing device determines the parity information of the codeword. For example, in the first iteration of decoding the codeword using a bit-flipping decoder, the processing device performs one or more parity checks. The processing device determines the parity information as described above with reference to operation 210.

[0063] At operation 415, the processing device uses the parity information sub-selection bit-flipping criteria. For example, the processing device maps several satisfied / unsatisfied parity checks to bit-flipping criteria, or selects bit-flipping criteria in other ways, as described above with reference to operation 215.

[0064] At operation 420, the processing device determines the energy function value of the bits of the codeword. In embodiments using soft information, the bit energy function value can be determined based on a default energy function value that is adjusted or not adjusted based on whether the bit is a strong or weak bit. For example, the determination of the energy function value can be performed as described above with reference to operation 220.

[0065] At operation 425, when the energy function value of a bit in the codeword satisfies the bit-flipping criterion, the processing device flips the bits of the codeword. The bit flipping can be performed as described above with reference to operation 225. For example, when a bit in the codeword does not satisfy the bit-flipping criterion, the bit is not flipped. When a bit in the codeword satisfies the bit-flipping criterion, the bit is flipped.

[0066] At operation 430, the processing device returns a corrected codeword derived from the bit flips of the codeword. In some embodiments, the corrected codeword is output to the host in response to a request to read data from the memory device. For example, the processing device returns the corrected codeword as described above with reference to operation 235.

[0067] Figure 5 An example machine illustrating computer system 500 is described, within which a set of instructions is executable to cause said machine to perform any or more of the methods discussed herein. In some embodiments, computer system 500 may correspond to a host system (e.g., Figure 1 The host system 120 includes, is coupled to, or utilizes a memory subsystem (e.g., Figure 1 The memory subsystem 110), or may be used to perform controller operations (e.g., execute an operating system to perform operations corresponding to...). Figure 1 (Operation of error corrector 113). In an alternative embodiment, the machine may be connected (e.g., networked) to other machines in a LAN, intranet, extranet, and / or the Internet. The computer may operate as a server or client machine in a client-server network environment, as a peer-to-peer machine in a peer-to-peer (or distributed) network environment, or as a server or client machine in a cloud computing infrastructure or environment.

[0068] The machine may be a personal computer (PC), tablet PC, set-top box (STB), personal digital assistant (PDA), cellular phone, network device, server, network router, switch, or bridge, or any machine capable of executing a set of instructions (sequentially or otherwise) specifying actions to be taken by said machine. Furthermore, while a single machine is described, the term "machine" should also be considered to include any collection of machines that individually or collectively execute a set (or more) of instructions to perform any or more of the methods discussed herein.

[0069] The example computer system 500 includes a processing device 502, a main memory 504 (e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM), such as synchronous DRAM (SDRAM) or Rambus DRAM (RDRAM), etc.), a static memory 506 (e.g., flash memory, static random access memory (SRAM), etc.), and a data storage device 518, which communicate with each other via a bus 530.

[0070] Processing device 502 represents one or more general-purpose processing devices, such as microprocessors, central processing units, or the like. More specifically, the processing device may be a Complex Instruction Set Computing (CISC) microprocessor, a Reduced Instruction Set Computing (RISC) microprocessor, a Very Long Instruction Word (VLIW) microprocessor, or a processor implementing other instruction sets, or a processor implementing a combination of instruction sets. Processing device 502 may also be one or more special-purpose processing devices, such as application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), digital signal processors (DSPs), network processors, or the like. Processing device 502 is configured to execute instructions 526 for performing the operations and steps discussed herein. Computer system 500 may further include a network interface device 508 for communicating via network 520.

[0071] Data storage system 518 may include machine-readable storage medium 524 (also called computer-readable medium) on which one or more sets of instructions 526 or software embodying any or more of the methods or functions described herein are stored. During execution of instructions 526 by computer system 500, instructions 526 may also reside wholly or at least partially in main memory 504 and / or processing device 502, which also constitute machine-readable storage medium. Machine-readable storage medium 524, data storage system 518, and / or main memory 504 may correspond to... Figure 1 The memory subsystem 110.

[0072] In one embodiment, instruction 526 includes instructions to implement a function corresponding to an error corrector (e.g., Figure 1The functionality of the error corrector 113). Although the machine-readable storage medium 524 is shown as a single medium in the exemplary embodiment, the term "machine-readable storage medium" should be considered to include a single medium or multiple media storing one or more sets of instructions. The term "machine-readable storage medium" should also be considered to include any medium capable of storing or encoding a set of instructions for machine execution and causing the machine to perform any or more of the methods of this disclosure. Therefore, the term "machine-readable storage medium" should be considered to include (but is not limited to) solid-state memory, optical media, and magnetic media.

[0073] Certain portions of the foregoing detailed description have been presented based on algorithms and symbolic representations of operations on data bits within computer memory. These algorithmic descriptions and representations are the most effective way for those skilled in the art of data processing to communicate the essence of their work to others skilled in the art. Here, an algorithm is generally considered to be a self-consistent sequence of operations that leads to a desired result. These operations are those requiring physical manipulation of physical quantities. Typically, but not necessarily, these quantities take the form of electrical or magnetic signals that can be stored, combined, compared, and otherwise manipulated. It has sometimes proven convenient to refer to these signals primarily for general reasons as bits, values, elements, symbols, characters, items, numbers, or the like.

[0074] However, it should be remembered that all these and similar terms should be associated with appropriate physical quantities and are merely convenient labels applied to those quantities. This disclosure may relate to the operation and processes of a computer system or similar electronic computing device that manipulates and transforms data represented as physical (electronic) numbers in the registers and memories of the computer system into physical quantities similarly represented as those in the computer system's memory or registers or other such information storage systems.

[0075] This disclosure also relates to apparatus for performing the operations described herein. Such apparatus may be specifically configured for its intended purpose, or it may comprise a general-purpose computer selectively activated or reconfigured by a computer program stored in a computer. For example, a computer system or other data processing system, such as controller 115, may perform computer-implemented methods 200 and 400 in response to its processor executing a computer program (e.g., a sequence of instructions) contained in memory or other non-transitory machine-readable storage media. This computer program may be stored in a computer-readable storage medium, such as (but not limited to) any type of disk, including floppy disks, optical disks, CD-ROMs and magneto-optical disks, read-only memory (ROM), random access memory (RAM), EPROM, EEPROM, magnetic cards or optical cards, or any type of media suitable for storing electronic instructions, each coupled to a computer system bus.

[0076] The algorithms and displays presented herein are not inherently related to any particular computer or other device. Various general-purpose systems can be used with the programs taught herein, or it may prove convenient to construct more specialized devices to perform the methods. The structures of various such systems will appear as described below. Furthermore, this disclosure is described without reference to any particular programming language. It will be understood that the teachings of this disclosure as described herein can be implemented using various programming languages.

[0077] This disclosure may be provided as a computer program product or software, which may include a machine-readable medium having instructions stored thereon, the instructions being usable to program a computer system (or other electronic device) to perform processes according to this disclosure. The machine-readable medium includes any mechanism for storing information in a machine-readable (e.g., computer-readable) form. In some embodiments, the machine-readable (e.g., computer-readable) medium includes machine-readable storage media, such as read-only memory (“ROM”), random access memory (“RAM”), disk storage media, optical storage media, flash memory components, etc.

[0078] In the foregoing description, embodiments of the present disclosure have been described with reference to specific examples. It will be apparent that various modifications can be made to the present disclosure without departing from the broader spirit and scope of the embodiments set forth in the appended claims. Therefore, the description and drawings should be considered illustrative rather than limiting.

Claims

1. A method comprising: receiving a codeword stored in a memory device; determining syndrome information for the codeword; selecting a bit flip threshold from a plurality of values by mapping the syndrome information to the bit flip threshold; determining an energy function value for a bit of the codeword; flipping each of one or more bits of the codeword in response to the energy function value for the bit satisfying the bit flip threshold; and returning a corrected codeword resulting from the flipping of the bits of the codeword.

2. The method of claim 1, wherein the syndrome information is a number of parity check violations detected in the codeword.

3. The method of claim 1, wherein selecting the bit flip threshold includes mapping the syndrome information to a parity check violation range and mapping the parity check violation range to the bit flip threshold.

4. The method of claim 1, wherein the corrected codeword results from a plurality of iterations of decoding, the plurality of iterations including a first iteration and a second iteration, and wherein the syndrome information is determined during the first iteration, the method further comprising: during the second iteration, determining updated syndrome information for the codeword; using the updated syndrome information, selecting an updated bit flip threshold from the plurality of values during the second iteration; during the second iteration, determining updated energy function values for bits of the codeword; and in response to the updated energy function values for the bits satisfying the updated bit flip threshold, flipping each of one or more bits of the codeword during the second iteration, wherein the corrected codeword further results from the flipping of the bits of the codeword during the second iteration.

5. The method of claim 1, further comprising: receiving soft information for the codeword from the memory device, wherein the soft information indicates whether one or more bits of the codeword are strong or weak; and in response to determining that the soft information indicates that a first bit of the codeword is strong and a current state of the first bit is different from a state of the first bit read from the memory device, decreasing a default energy function value to obtain an energy function value for the first bit.

6. The method of claim 1, further comprising: receiving soft information for the codeword from the memory device, wherein the soft information indicates whether one or more bits of the codeword are strong or weak; and in response to determining that the soft information indicates that a second bit of the codeword is strong and a current state of the second bit is the same as a state of the second bit read from the memory device, increasing a default energy function value to obtain an energy function value for the second bit.

7. The method of claim 1, wherein determining the energy function value for a bit of the codeword includes: retrieving an energy function value for a bit of the codeword from a lookup table based on a number of satisfied parity checks, whether a current state of the bit is the same as a state of the bit read from the memory device, and soft information associated with the bit.

8. A non-transitory computer-readable storage medium comprising instructions that, when executed by a processing device, cause the processing device to: receive a codeword stored in a memory device; determine syndrome information for the codeword; select a bit flip threshold from a plurality of values by mapping the syndrome information to the bit flip threshold; determine an energy function value for a bit of the codeword; flip each of one or more bits of the codeword in response to the energy function value for the bit satisfying the bit flip threshold; and return a corrected codeword resulting from the flipping of the bits of the codeword.

9. The non-transitory computer-readable storage medium of claim 8, wherein the syndrome information is a number of parity violations detected in the codeword.

10. The non-transitory computer-readable storage medium of claim 8, wherein selecting the bit flip threshold includes mapping the syndrome information to a parity violation range and mapping the parity violation range to the bit flip threshold.

11. The non-transitory computer-readable storage medium of claim 8, wherein the corrected codeword results from a plurality of iterations of decoding, the plurality of iterations including a first iteration and a second iteration, wherein the syndrome information is determined during the first iteration, and wherein the processing device is further to: determine updated syndrome information for the codeword during the second iteration; use the updated syndrome information to select an updated bit flip threshold from the plurality of values during the second iteration; determine updated energy function values for bits of the codeword during the second iteration; and flip each of one or more bits of the codeword during the second iteration in response to the updated energy function values for the bits satisfying the updated bit flip threshold, wherein the corrected codeword further results from the flipping of the bits of the codeword during the second iteration.

12. The non-transitory computer-readable storage medium of claim 8, wherein the processing device is further to: receive soft information for the codeword from the memory device, wherein the soft information indicates whether one or more bits of the codeword are strong or weak; and in response to determining that the soft information indicates that a first bit of the codeword is strong and a current state of the first bit is different from a state of the first bit read from the memory device, decrease a default energy function value to obtain an energy function value for the first bit.

13. The non-transitory computer-readable storage medium of claim 8, wherein the processing device is further to: receive soft information for the codeword from the memory device, wherein the soft information indicates whether one or more bits of the codeword are strong or weak; and in response to determining that the soft information indicates that a second bit of the codeword is strong and a current state of the second bit is the same as a state of the second bit read from the memory device, increase a default energy function value to obtain an energy function value for the second bit. ​ 14. The non-transitory computer-readable storage medium of claim 8, wherein determining the energy function value of a bit of the codeword includes: retrieving an energy function value of a bit of the codeword from a lookup table based on a number of satisfied parity checks, whether a current state of the bit is the same as a state of the bit read from the memory device, and soft information associated with the bit.

15. A system comprising: a memory device; and a processing device operably coupled with the memory device, the processing device to: receive a codeword stored in a memory device; determine a number of parity check violations of the codeword; select a bit flip threshold from a plurality of values by mapping the number of parity check violations to the bit flip threshold; determine an energy function value of a bit of the codeword; flip each of one or more bits of the codeword in response to the energy function value of the bit satisfying the bit flip threshold; and return a corrected codeword resulting from the flipping of the bits of the codeword.

16. The system of claim 15, wherein selecting the bit flip threshold includes mapping the number of parity check violations to a parity check violation range and mapping the parity check violation range to the bit flip threshold.

17. The system of claim 15, wherein the corrected codeword results from a plurality of iterations of decoding, the plurality of iterations including a first iteration and a second iteration, wherein the number of parity check violations is determined during the first iteration, and wherein the processing device is further to: during the second iteration, determine updated syndrome information of the codeword; using the updated syndrome information, select an updated bit flip threshold from the plurality of values during the second iteration; during the second iteration, determine updated energy function values of bits of the codeword; and flip each of one or more bits of the codeword during the second iteration in response to the updated energy function values of the bits satisfying the updated bit flip threshold, wherein the corrected codeword further results from the flipping of the bits of the codeword during the second iteration.

18. The system of claim 15, wherein the processing device is further to: receive soft information of the codeword from the memory device, wherein the soft information indicates whether one or more bits of the codeword are strong or weak; and in response to determining that the soft information indicates that a first bit of the codeword is strong and a current state of the first bit is different than a state of the first bit read from the memory device, decrease a default energy function value to obtain an energy function value of the first bit.

19. The system of claim 15, wherein the processing device is further to: receive soft information of the codeword from the memory device, wherein the soft information indicates whether one or more bits of the codeword are strong or weak; and in response to determining that the soft information indicates that a first bit of the codeword is weak and a current state of the first bit is different than a state of the first bit read from the memory device, increase a default energy function value to obtain an energy function value of the first bit. in response to determining that the soft information indicates that a second bit of the codeword is strong and that a current state of the second bit is the same as a state of the second bit read from the memory device, increasing a default energy function value to obtain an energy function value for the second bit.

20. The system of claim 15, wherein determining the energy function value for a bit of the codeword includes: retrieving an energy function value for a bit of the codeword from a lookup table based on a number of satisfied parity checks, whether a current state of the bit is the same as a state of the bit read from the memory device, and soft information associated with the bit.

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