Display panel, driving method and display device

Abstract

Embodiments of the present application provide a display panel and a driving method, and a display device. The display panel comprises a first substrate, a display medium layer, a light shielding structure layer, a plurality of pixel electrodes and a plurality of anti-peep electrodes. The display medium layer is located on one side of the first substrate, and the plurality of pixel electrodes and the plurality of anti-peep electrodes are both located between the first substrate and the display medium layer. The light shielding structure layer comprises a light shielding structure and a hollow part. In a direction Z perpendicular to the surface of the display panel, the anti-peep electrode overlaps the light shielding structure, and the pixel electrode overlaps the hollow part. The light shielding structure layer is located on the side of the anti-peep electrode facing the light-emitting surface of the display panel. In the embodiments of the present application, the display device provided by the embodiments of the present application can control the display mode of the display panel to switch between an anti-peep mode (first mode) and a non-anti-peep mode (second mode) by setting the anti-peep electrode and controlling whether the anti-peep electrode receives a voltage signal.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of display, and particularly relates to a display panel and a driving method, and a display device. BACKGROUND

[0002] With the continuous development of display technology, the anti-peep display has become one of the indispensable functions of the display device. The existing means for realizing the anti-peep display can be divided into three categories: white-state anti-peep, black-state anti-peep and setting an anti-peep film. Among them, the white-state anti-peep is concerned due to its low cost and wide application range.

[0003] However, the existing white-state anti-peep is at the expense of sacrificing large-angle light, which reduces the brightness of the display panel and increases the power consumption. The existing white-state anti-peep needs to use a light control structure, which increases the cost, the process difficulty or the thickness of the display panel.

[0004] CONTENT

[0005] Therefore, the embodiments of the present application provide a display panel, a driving method and a display device to solve the above problems.

[0006] In a first aspect, the embodiments of the present application provide a display panel, which comprises a first substrate, a display medium layer, a light shielding structure layer, a plurality of pixel electrodes and a plurality of anti-peep electrodes. The display medium layer is located on one side of the first substrate, and the plurality of pixel electrodes and the plurality of anti-peep electrodes are both located between the first substrate and the display medium layer. The light shielding structure layer comprises a light shielding part and a hollow part. In a direction perpendicular to the surface of the display panel, the anti-peep electrode overlaps the light shielding structure, and the pixel electrode overlaps the hollow part. The light shielding structure layer is located on the side of the anti-peep electrode facing the light-emitting surface of the display panel.

[0007] In a second aspect, the embodiments of the present application provide a driving method of a display panel, which is used for driving the display panel provided in the first aspect. The display mode of the display panel comprises a first mode and a second mode. The driving method comprises: in the first mode, controlling the pixel electrode and the anti-peep electrode to receive a voltage signal, so as to make the display panel display in a narrow viewing angle; and in the second mode, controlling the pixel electrode to receive the voltage signal and controlling the anti-peep electrode not to receive the voltage signal, so as to make the display panel display in a wide viewing angle.

[0008] In a third aspect, the embodiments of the present application provide a display device, which comprises the display panel provided in the first aspect.

[0009] In the embodiments of the present application, the display device provided by the embodiments of the present application can control the display mode of the display panel to switch between the anti-peep mode (the first mode) and the non-anti-peep mode (the second mode) by setting the anti-peep electrode and by controlling whether the anti-peep electrode receives the voltage signal. DRAWINGS

[0010] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings needed to be used in the embodiments will be briefly introduced as follows. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without any creative effort on the basis of these drawings.

[0011] Figure 1 A partial schematic view of a display panel is provided for the embodiments of the present application.

[0012] Figure 2 A partial schematic view of a display panel is provided for the embodiments of the present application. Figure 1 A partial schematic view of a display panel is provided for the embodiments of the present application.

[0013] Figure 3 A partial schematic view of a display panel is provided for the embodiments of the present application.

[0014] Figure 4 A partial schematic view of a display panel is provided for the embodiments of the present application.

[0015] Figure 5 A partial schematic view of a display panel is provided for the embodiments of the present application.

[0016] Figure 6 A partial schematic view of a display panel is provided for the embodiments of the present application.

[0017] Figure 7 A partial schematic view of a display panel is provided for the embodiments of the present application.

[0018] Figure 8 A partial schematic view of a display panel is provided for the embodiments of the present application.

[0019] Figure 9 A partial schematic view of a display panel is provided for the embodiments of the present application. Figure 1 An enlarged schematic view of the R1 region in FIG. 8 is shown.

[0020] Figure 10 A partial schematic view of a display panel is provided for the embodiments of the present application. Figure 9 A partial schematic view of a display panel is provided for the embodiments of the present application.

[0021] Figure 11 A partial schematic view of a display panel is provided for the embodiments of the present application.

[0022] Figure 12 A partial schematic view of a display panel is provided for the embodiments of the present application. Figure 11 A partial schematic view of a display panel is provided for the embodiments of the present application.

[0023] Figure 13 A partial schematic view of a display panel is provided for the embodiments of the present application.

[0024] Figure 14A partial schematic view of a display panel provided by an embodiment of the present application;

[0025] Figure 15 A partial schematic view of a display panel provided by an embodiment of the present application; Figure 14 A cross-sectional view of the first scan line along the direction of DD' in the display panel shown in FIG. 1;

[0026] Figure 16 A partial schematic view of a display panel provided by an embodiment of the present application;

[0027] Figure 17 A partial schematic view of a display panel provided by an embodiment of the present application; Figure 16 A cross-sectional view of the first scan line along the direction of EE' in the display panel shown in FIG. 2;

[0028] Figure 18 A partial cross-sectional schematic view of a display panel provided by an embodiment of the present application;

[0029] Figure 19 A partial cross-sectional schematic view of a display panel provided by an embodiment of the present application;

[0030] Figure 20 A partial cross-sectional schematic view of a display panel provided by an embodiment of the present application;

[0031] Figure 21 A partial cross-sectional schematic view of a display panel provided by an embodiment of the present application;

[0032] Figure 22 A partial schematic view of a display panel provided by an embodiment of the present application;

[0033] Figure 23 A partial schematic view of a display panel provided by an embodiment of the present application; Figure 22 A cross-sectional view along the direction of FF' in the display panel shown in FIG. 4;

[0034] Figure 24 A partial schematic view of a display panel provided by an embodiment of the present application;

[0035] Figure 25 A partial schematic view of a display panel provided by an embodiment of the present application;

[0036] Figure 26 A partial schematic view of a display panel provided by an embodiment of the present application;

[0037] Figure 27 A partial schematic view of a display panel provided by an embodiment of the present application;

[0038] Figure 28 A partial schematic view of a display panel provided by an embodiment of the present application; Figure 1 A driving timing corresponding to the display panel shown in FIG. 5;

[0039] Figure 29 A partial schematic view of a display panel provided by an embodiment of the present application; Figure 1 A driving timing corresponding to the display panel shown in FIG. 6;

[0040] Figure 30 This is a schematic diagram of a display device provided in an embodiment of this application.

Detailed Implementation Methods

[0041] To better understand the technical solution of this application, the embodiments of this application will be described in detail below with reference to the accompanying drawings.

[0042] It should be understood that the described embodiments are merely some, not all, of the embodiments in this application. All other embodiments obtained by those skilled in the art based on the embodiments in this application without inventive effort are within the scope of protection of this application.

[0043] The terminology used in the embodiments of this application is for the purpose of describing particular embodiments only and is not intended to be limiting of this application. The singular forms “a,” “the,” and “the” used in the embodiments of this application and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise.

[0044] It should be understood that the term "and / or" used in this article is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, and B existing alone. Additionally, the character " / " in this article generally indicates that the preceding and following related objects have an "or" relationship.

[0045] In the description of this specification, it should be understood that the terms "substantially", "approximately", "about", "about", "generally", "largely" used in the claims and embodiments of this application refer to values ​​that can be generally agreed upon within a reasonable range of process operations or tolerances, rather than a precise value.

[0046] It should be understood that although the terms "first," "second," etc., may be used to describe transistors, switches, data lines, and scan lines in the embodiments of this application, these transistors, switches, data lines, and scan lines should not be limited to these terms. These terms are only used to distinguish transistors, switches, data lines, and scan lines from one another. For example, without departing from the scope of the embodiments of this application, a first transistor may also be referred to as a second transistor, and similarly, a second transistor may also be referred to as a first transistor.

[0047] Through meticulous and in-depth research, the applicant in this case has provided a solution to the problems existing in the prior art.

[0048] Figure 1 This is a partial schematic diagram of a display panel provided in an embodiment of this application. Figure 2 for Figure 1A cross-sectional structure schematic diagram of the partial region shown along the AA' direction.

[0049] In the existing white-state privacy technology, a light control structure is usually introduced in the display panel to obtain collimated light, which can propagate into the eyes of the observer at the normal viewing angle and cannot propagate into the eyes of the observer at the large viewing angle, that is, can be seen by the observer at the normal viewing angle and cannot be seen by the observer at the large viewing angle, so that the display panel can realize privacy. The basic working principle of the light control structure is to hinder the light at the large viewing angle from being emitted, which means that a lot of light that can be used for light display is sacrificed, which can cause the brightness of the display panel to decrease. In order to increase the brightness, the driving voltage needs to be increased, which can cause the power consumption to increase. The light control structure can be a light shielding structure arranged in different layers and staggered, or can be a light control liquid crystal cell. However, the light shielding structure arranged in different layers and staggered increases the process difficulty of the display panel and increases the process flow, thereby increasing the cost. The light control liquid crystal cell also increases the cost, and the control of the light control liquid crystal cell increases the additional power consumption and increases the thickness of the display panel.

[0050] Based on the limitations in the existing white-state privacy technology, the display panel 10 provided in the embodiments of the present application combines Figure 1 and Figure 2 The display panel 10 includes a first substrate G1, a display medium layer M, a plurality of pixel electrodes E1, a privacy electrode E2, and a light shielding structure layer BM.

[0051] The display medium layer M is located on one side of the first substrate, and the pixel electrode E1 and the privacy electrode E2 are both located between the display medium layer M and the first substrate G1. Then the pixel electrode E1 and the privacy electrode E2 can both be conductive film layers arranged on the first substrate G1, and can be prepared by the same process method, for example, the same film forming method and the same etching process. The pixel electrode E1 and the privacy electrode E2 are both arranged on the first substrate G1, so that the signals required by the two can be directly transmitted by the signal lines on the first substrate G1, and the difficulty of obtaining signals by the privacy electrode E2 and the pixel electrode E1 is reduced.

[0052] When the state of the display medium layer M is different, the light incident to the display medium layer M can be controlled to be emitted in different states. The display medium layer M can be a liquid crystal layer, and the liquid crystal alignment deflection in the liquid crystal layer can change the propagation direction of the incident display light to control the display light to pass through or not to pass through the display medium layer M.

[0053] The pixel electrode E1 can receive a voltage signal and generate an electric field with the common electrode Com to control the display medium layer M to be in different states, thereby adjusting the transmittance of the display light in the display medium layer M, so that the display device forms a display picture.

[0054] The privacy electrode E2 can receive a voltage signal and generate an electric field with the common electrode Com to control the state of the display medium layer M, thereby changing the emission state of the display light emitted into the display medium layer M.

[0055] The display light passing through the display medium layer M includes first display light L1 and second display light L2, the first display light L1 is the display light whose emission state from the display medium layer M is affected by the pixel electrode E1, and the second display light L2 is the display light whose emission state from the display medium layer M is affected by the privacy electrode E2.

[0056] The light shielding structure layer BM includes a light shielding structure BM1 and a hollow part BM2, and the combination of Figure 1 and Figure 2 In the direction Z perpendicular to the surface of the display panel 10, the privacy electrode E2 overlaps with the light shielding structure BM1 and the pixel electrode E1 at least partially overlaps with the hollow part BM2.

[0057] In the direction Z perpendicular to the surface of the display panel 10, the hollow part overlaps with the pixel electrode E1, that is, the hollow part BM2 of the light shielding structure layer BM exposes at least part of the pixel electrode E1, so that at least part of the first display light L1 is emitted from the display panel to form a display picture. At the same time, in the direction Z perpendicular to the surface of the display panel 10, the light shielding structure of the light shielding structure layer BM overlaps with at least part of the wirings in the display area of the display panel 10, and the light shielding structure layer BM is located on the side of the wirings facing the light emitting surface of the display panel 10, which reduces the visibility of the part of the wirings in the display process of the display panel 10 and improves the display effect.

[0058] In the direction Z perpendicular to the surface on which the display panel 10 is located, the privacy electrode E2 overlaps the light shielding structure BM1 in the direction Z perpendicular to the surface on which the display panel 10 is located, and the light shielding structure BM1 at least partially shields the privacy electrode E2, so that the privacy electrode E2 is not observed by the human eye, and the visual effect is affected. In addition, the voltage received by the privacy electrode E2 causes the second display light L2 to be transmitted through the display medium layer M. Due to the shielding of the shielding structure BM1, the observer cannot see the second display light L2 at the normal viewing angle or a smaller viewing angle. Therefore, for the observer at the normal viewing angle or the narrow viewing angle, the display panel can normally display. However, the second display light L2 is emitted from the hollow part BM2, and the propagation angle of the second display light L2 emitted from the hollow part BM2 is large. Therefore, the observer at the large viewing angle can receive the second display light L2. That is, the observer can receive the light other than the light of the display image. The second display light L2 is interference light for the observer at the large viewing angle. Therefore, the display panel can achieve the privacy function. It should be noted that the second display light L2 can be backlight below the region where the privacy electrode E2 is located before being propagated to the display medium layer M. Alternatively, the second display light L2 can be backlight below the region where the adjacent pixel electrode E1 is located. That is, the second display light L2 transmitted through the display medium layer M can be from below the region where the privacy electrode E2 is located. Alternatively, the second display light L2 can be from below the region where the adjacent pixel electrode E1 is located.

[0059] In an embodiment of the present application, as shown in Figure 2 The privacy electrode E2 can be disposed in the same film layer as the pixel electrode E1, that is, the two are disposed in the same film layer. In the embodiment of the present application, the pixel electrode E1 and the privacy electrode E2 are disposed in the same film layer, so that they can be prepared in the same process. For example, the two can be completed in the same film forming process and the same etching process, thereby shortening the working period and reducing the cost.

[0060] In an embodiment of the present application, the display mode of the display panel 10 includes a first mode. As shown in Figure 2 In the first mode, at least part of the pixel electrode E1 and at least part of the privacy electrode E2 in the display panel 10 receive a voltage signal. In the first mode, at least part of the display panel 10 can emit the first display light L1, and the observer at the normal viewing angle or a smaller viewing angle can see the first display light L1. In addition, the observer at the large viewing angle can see the second display light L2. Therefore, the observer at the large viewing angle sees the display image disturbed by the second display light L2, and the display panel 10 displays in the narrow viewing angle.

[0061] Figure 3 A display principle diagram of a display panel is provided in an embodiment of the present application.

[0062] In one embodiment of this application, the display mode of the display panel 10 further includes a second mode. As shown in FIG. 03, in the second mode, at least some of the pixel electrodes E1 in the display panel 10 receive voltage signals while the privacy electrode E2 does not receive voltage signals. In the second mode, no second display light L2 is emitted from the display panel, so the display image visible to an observer at a wide viewing angle will not be interfered with by the second display light L2, and the display panel 10 displays with a wide viewing angle.

[0063] In this embodiment, the display panel 10 is configured to include two display modes, enabling the display panel 10 to switch between a privacy mode and a non-privacy mode, thereby enhancing the flexibility of the display panel 10 in privacy display and improving the privacy display effect.

[0064] Figure 4 This is a cross-sectional schematic diagram of a display panel provided in an embodiment of this application. Figure 5 This is a cross-sectional schematic diagram of another display panel provided in an embodiment of this application.

[0065] In this embodiment of the application, the display panel may further include a second substrate G2, a first substrate G1 and a second substrate G2 are disposed opposite to each other, a light-shielding structure layer BM is located between the first substrate G1 and the second substrate G2, and the light-shielding structure layer BM is disposed on the side of the first substrate G1 or the second substrate G2 facing the display medium layer M.

[0066] For example, such as Figure 4 As shown, the film layer containing the light-shielding structure layer BM is located on the side of the second substrate G2 facing the first substrate G1, and is located between the second substrate G2 and the display medium layer M.

[0067] For example, such as Figure 5 As shown, the film layer containing the light-shielding structure layer BM is located on the side of the first substrate G1 facing the second substrate G2, and is located between the first substrate G1 and the display medium layer M.

[0068] In the film layer where the light-shielding structure layer BM is located, the cutout portion BM2 can be filled with color resist CF. The color resist CF can block and filter most of the external ambient light from passing through the cutout portion BM2 and shining into the display panel 10, so as to avoid affecting the operation of the transistors and other structures inside the display panel 10.

[0069] It should be noted that, for ease of description, the second substrate G2 and the color resist CF, etc., are only mentioned in the appendix. Figure 4 Appendix Figure 5 This is reflected in the text.

[0070] The light-shielding structural layer BM can be made of metallic chromium or black resin; the material composition of the light-shielding structural layer BM is not limited here.

[0071] In an embodiment of the present application, as shown in Figure 1 , Figure 2 and Figure 3 , the light shielding structure BM1 completely covers the privacy electrode E2 in the direction Z perpendicular to the surface on which the display panel 10 is located. Then the second display light L2 can be more effectively prevented from being viewed by the observer at the normal viewing angle or the smaller viewing angle, so as to avoid the observer at the normal viewing angle or the smaller viewing angle from seeing the disturbed display screen, and improve the visual experience of the observer.

[0072] Figure 6 FIG. 2 is a partial schematic view of another display panel provided by an embodiment of the present application, Figure 7 FIG. 3 is a partial schematic view of a display panel provided by an embodiment of the present application, Figure 8 FIG. 4 is a partial schematic view of a display panel provided by an embodiment of the present application.

[0073] In an embodiment of the present application, the privacy electrode E2 is located between the adjacent pixel electrodes E1. Specifically, the display panel 10 includes a plurality of sub-pixels, the pixel electrodes E1 are included in the sub-pixels, and the privacy electrode E2 can be located between the adjacent sub-pixels. In combination with Figure 6 to Figure 8 , the privacy electrode E2 is located between the pixel electrodes E1 adjacent at least in the first direction X, and / or the privacy electrode E2 is located between the pixel electrodes E1 adjacent at least in the second direction Y, the first direction X and the second direction Y intersect, for example, the first direction X and the second direction Y are perpendicular.

[0074] In an implementation, as shown in Figure 6 , the privacy electrode E2 is located between the pixel electrodes E1 adjacent arranged in the first direction X, at this time the main part of the privacy electrode E2 can extend substantially in the second direction Y, then the privacy electrode E2 will not excessively occupy the space of the sub-pixel in the first direction X.

[0075] In an implementation, as shown in Figure 7 , the privacy electrode E2 is located between the pixel electrodes E1 adjacent arranged in the second direction Y, at this time the main part of the privacy electrode E2 can extend substantially in the first direction X, then the privacy electrode E2 will not excessively occupy the space of the sub-pixel in the second direction Y.

[0076] In an implementation, as shown in Figure 8As shown, the partial privacy electrode E2 is located between at least some of the pixel electrodes E1 arranged adjacent along the first direction X, and the partial privacy electrode E2 is located between at least some of the pixel electrodes E1 arranged adjacent along the second direction Y. The main part of the privacy electrode E2 between the pixel electrodes E1 arranged adjacent along the first direction X can extend substantially along the second direction Y, and the main part of the privacy electrode E2 between the pixel electrodes E1 arranged adjacent along the second direction Y can extend substantially along the first direction X.

[0077] It should be noted that the privacy electrode E2 is arranged between any pixel electrodes E1 arranged adjacent along the first direction X, or the privacy electrode E2 is arranged between some of the pixel electrodes E1 arranged adjacent along the first direction X.

[0078] It should be noted that the privacy electrode E2 is arranged between any pixel electrodes E1 arranged adjacent along the second direction Y, or the privacy electrode E2 is arranged between some of the pixel electrodes E1 arranged adjacent along the second direction Y.

[0079] In the embodiments of the present application, the privacy electrode E2 is arranged between the pixel electrodes E1 in adjacent sub-pixels, so that the space of the wiring area between adjacent sub-pixels is fully utilized.

[0080] Meanwhile, the privacy electrode E2 is adjacent to the pixel electrode E1, and for the observer under a large viewing angle, the second display light L2 more effectively interferes with the first display light L1, thereby improving the privacy effect. For example, when the pixel electrode E1 of a sub-pixel is adjacent to the privacy electrode E2, the second display light L2 corresponding to the privacy electrode E2 can more fully mix the first display light L1 emitted by the sub-pixel, and thus more effectively interferes with the first display light L1.

[0081] Figure 9 For Figure 1 An enlarged schematic view of the R1 region, Figure 10 For Figure 9 A schematic view of a cross section along the direction of BB'.

[0082] In combination Figure 1 With Figure 9 , Figure 10 As shown, the display panel 10 includes a data line D, a first switch SW1 and a second switch SW2. The privacy electrode E2 is electrically connected to the data line D through the first switch SW1, and the switching state of the first switch SW1 can control whether the privacy electrode E2 can receive the voltage signal on the data line D; the pixel electrode E1 is electrically connected to the data line D through the second switch SW2, and the switching state of the second switch SW2 can control whether the pixel electrode E1 can receive the voltage signal on the data line D.

[0083] For example, when the display panel 10 is in the anti-peep mode, the first switch SW1 and the second switch SW2 are both turned on, and the anti-peep electrode E2 and the pixel electrode E1 both receive the voltage signal transmission electric signal; when the display panel 10 is in the non-anti-peep mode, the first switch SW1 is turned off, and the second switch SW2 is turned on, the pixel electrode E1 receives the data voltage, and the anti-peep electrode E2 cannot receive the voltage signal.

[0084] It should be noted that the display panel 10 can realize regional anti-peep, that is, when the display panel 10 is in the anti-peep mode, part of the first switch SW1 is turned on, and the anti-peep electrode E2 electrically connected to the part of the first switch SW1 receives the voltage signal, so that the region where the anti-peep electrode E2 is located can realize anti-peep; the other part of the first switch SW1 is turned off, and the anti-peep electrode E2 electrically connected to the other part of the first switch SW1 cannot receive the voltage signal, so that the region where the anti-peep electrode E2 is located cannot realize anti-peep.

[0085] The data line D can be a straight line structure or a zigzag line structure including a bending part, but as shown in FIG. 1, the main part of the data line D extends along the second direction Y. Figure 6 to Figure 8

[0086] In an embodiment of the present application, in combination with Figure 1 and Figure 9 In the embodiment of the present application, at least one anti-peep electrode E2 and the pixel electrode E1 are respectively electrically connected to the same data line D through the first switch SW1 and the second switch SW2, so that at least part of the first switch SW1 and the second switch SW2 can be electrically connected to the same data line D. That is, at least part of the anti-peep electrode E1 can receive the same voltage signal as the pixel electrode E2. In combination with Figure 1 and Figure 9 The anti-peep electrode E2 is electrically connected to the data line D through the first switch SW1, and the data line D is electrically connected to the pixel electrode E1 through the second switch SW2.

[0087] The pixel electrode E1 and the anti-peep electrode E2 electrically connected to the same data line D through the first switch SW1 and the second switch SW2 respectively can be arranged adjacent to each other, which facilitates electrical connection.

[0088] In the embodiment, the data line D for transmitting the voltage signal to at least part of the anti-peep electrode E1 and the data line D for transmitting the voltage signal to the pixel electrode E2 can be shared, and the number of data lines D will not increase due to the arrangement of the anti-peep electrode E1, so that the wiring difficulty and driving difficulty of the display panel will not be increased.

[0089] In addition, the anti-peep electrode E2 sharing the data line D with the pixel electrode E1 can realize synchronous reception of the voltage signal with the pixel electrode in the anti-peep mode, which accelerates the response time of the anti-peep mode. ​

[0090] In a technical solution corresponding to the embodiment, part of the privacy prevention electrodes E2 share the data lines D with the pixel electrodes E1, and the other part of the privacy prevention electrodes E2 do not share the data lines D with the pixel electrodes E1. For example, the privacy prevention electrodes E2 located between the pixel electrodes E1 arranged adjacent along the first direction X can share the data lines D with the pixel electrodes E1, and the privacy prevention electrodes E2 located between the pixel electrodes E1 arranged adjacent along the second direction Y do not share the data lines D with the pixel electrodes E1.

[0091] In a technical solution corresponding to the embodiment, all the privacy prevention electrodes E2 share the data lines D with the pixel electrodes E1.

[0092] Figure 11 A partial schematic view of a display panel provided in the embodiment, Figure 12 For Figure 11 A cross-sectional view in the direction of CC’.

[0093] In an embodiment of the present application, in combination with Figure 11 and Figure 12 The display panel 10 further includes a first data line D1, a second data line D2, and a first switch SW1 and a second switch SW2. The privacy prevention electrodes E2 are electrically connected to the first data line D1 through the first switch SW1, and the pixel electrodes E1 are electrically connected to the second data line D2 through the second switch SW2. That is, among the plurality of data lines D included in the display panel, part of the data lines D are used to transmit voltage signals for the privacy prevention electrodes E2, and part of the data lines D are used to transmit voltage signals for the pixel electrodes E1. The data lines D used to transmit voltage signals for the privacy prevention electrodes E2 are the first data line D1, and the data lines D used to transmit voltage signals for the pixel electrodes E2 are the second data line D2.

[0094] In the embodiment of the present application, in the privacy prevention mode, the privacy prevention electrodes E2 and the pixel electrodes E1 respectively receive voltage signals transmitted by the first data line D1 and the second data line D2. The data signals received by the privacy prevention electrodes E2 can be different from or the same as the data signals received by the pixel electrodes E1, which can make the display panel have more flexible privacy prevention functions. For example, the voltage signals received by the privacy prevention electrodes E2 are flexibly adjustable, so that the brightness of the second display light L2 is more variable, and the display panel can have different privacy prevention modes.

[0095] In addition, the data lines D electrically connected to the privacy prevention electrodes E2 are different from the data lines D electrically connected to the pixel electrodes E1, which can avoid the load on the data lines D electrically connected to the pixel electrodes E1 being too large to cause the display effect to deteriorate.

[0096] For example, Figure 11 and Figure 12As shown, the first switch SW1 includes a first transistor T1, and the second switch SW2 includes a second transistor T2, that is, the first transistor T1 can be located between the privacy electrode E2 and the data line D for controlling the privacy electrode E2 to receive the voltage signal on the data line D, and the second transistor T2 can be located between the pixel electrode E1 and the data line D for controlling the pixel electrode E1 to receive the voltage signal on the data line D.

[0097] In combination Figure 11 with Figure 12 , the first transistor T1 includes a first pole SW11 (for example, a drain) and a second pole SW12 (for example, a source), and the second transistor T2 includes a first pole SW21 (for example, a drain) and a second pole SW22 (for example, a source). The privacy electrode E2 is electrically connected with the first pole SW11 of the first transistor T1, and the pixel electrode E1 is electrically connected with the first pole SW21 of the second transistor T2.

[0098] In an embodiment of the present application, in combination Figure 11 with Figure 12 As shown, when the privacy electrode E2 is electrically connected with the first data line D1 through the first switch SW1, and the pixel electrode E1 is electrically connected with the second data line D2 through the second switch SW2, the second pole SW12 of the first transistor T1 is electrically connected with the first data line D1, and the second pole SW22 of the second transistor T2 is electrically connected with the second data line D2.

[0099] In an embodiment of the present application, in combination Figure 9 and Figure 10 , when there are the privacy electrode E2 and the adjacent pixel electrode E1 respectively electrically connected with the same data line D through the first switch SW1 and the second switch SW2, at least one of the privacy electrode E2 and the adjacent pixel electrode E1 are respectively electrically connected with the first pole SW11 of the first transistor T1 and the first pole SW21 of the second transistor T2, and the second pole SW12 of the first transistor T1 and the second pole SW22 of the second transistor T2 are multiplexed and electrically connected with the same data line D. That is, the privacy electrode E2 and the pixel electrode E1 sharing the data line D are respectively electrically connected with the data line D through the first transistor T1 and the second transistor T2, and the second pole SW12 of the first transistor T1 and the second pole SW22 of the second transistor T2 are multiplexed.

[0100] The second pole SW12 of the first transistor T1 and the second pole SW22 of the second transistor T2 are multiplexed and electrically connected with the same data line D, so that the space occupied by the first transistor T1 and the second transistor T2 can be reduced.

[0101] As Figure 9 to Figure 12, the second transistor T2 can be a double-gate structure, so that the pixel electrode E1 can be charged quickly and accurately and the leakage current of the second transistor T2 can be reduced, the accuracy and stability of the voltage signal on the pixel electrode E1 are ensured, and the display effect is improved.

[0102] Since the accuracy and stability of the voltage signal on the privacy electrode E2 are not required to be high, in combination with Figure 1 and Figure 2 , the first transistor T1 can be a single-gate structure, so that the first transistor T1 occupies less space and the influence of the first transistor T1 on the layout of other structures in the display panel is reduced.

[0103] In an embodiment of the present application, as shown in Figure 1 , Figure 6 to Figure 8 and Figure 11 , the display panel 10 further includes a first scan line S1 and a second scan line S2, the control end of the first switch SW1 is electrically connected with the first scan line S1, and the control end of the second switch SW2 is electrically connected with the second scan line S2. The switching state of the first switch SW1 can be controlled by the signal transmitted by the first scan line S1, and the switching state of the second switch SW2 can be controlled by the signal transmitted by the second scan line. When the first switch SW1 includes the first transistor T1 and the second switch SW2 includes the second transistor T2, the first scan line S1 can be electrically connected with the gate of the first transistor T1, and the second scan line S2 can be electrically connected with the gate of the second transistor T2.

[0104] When the first scan line S1 and the second scan line S2 respectively control the first transistor T1 and the second transistor T2 to be in the on state, the display panel 10 enters the privacy mode; when the first scan line S1 controls the first transistor T1 to be off and the second scan line S2 controls the second transistor T2 to be on, the display panel 10 is in the non-privacy mode. In the embodiment of the present application, the first switch SW1 and the second switch SW2 are respectively controlled by the signals transmitted by the first scan line S1 and the second scan line S2, so that the privacy mode of the display panel 10 can be started more flexibly.

[0105] For example, when the display panel 10 is in the privacy mode, the first scan line S1 controls the first transistor T1 to be on, the second scan line S2 controls the second transistor T2 to be on, the first switch SW1 and the second switch SW2 are both on, and the privacy electrode E2 and the pixel electrode E1 both receive the voltage signal transmitted by the data line D. When the display panel 10 is in the non-privacy mode, the first scan line S1 controls the first transistor T1 to be off, the second scan line S2 controls the second transistor T2 to be on, the first switch SW1 is off and the second switch SW2 is on, so that the pixel electrode E1 receives the voltage signal transmitted by the data line D and the privacy electrode E2 does not receive the voltage signal transmitted by the data line D.

[0106] In an embodiment of the present application, as shown in Figure 9 and Figure 11 , the first scan line S1 and the second switch SW2 do not overlap in the direction Z perpendicular to the surface on which the display panel 10 is located, and the second scan line S2 and the first switch SW1 do not overlap, that is, the first scan line S1 electrically connected with the first switch SW1 and the second switch SW2 do not overlap in the direction Z perpendicular to the surface on which the display panel 10 is located, and the second scan line S2 electrically connected with the second switch SW2 and the first switch SW1 do not overlap in the direction Z perpendicular to the surface on which the display panel 10 is located.

[0107] When the first switch SW1 comprises the first transistor T1 and the second switch SW2 comprises the second transistor T2, the first scan line S1 and the second transistor T2 do not overlap in the direction Z perpendicular to the surface on which the display panel 10 is located, and the second scan line S2 and the first transistor T1 do not overlap in the direction Z perpendicular to the surface on which the display panel 10 is located.

[0108] When a transistor overlaps with a scan line electrically insulated therefrom, the signal on the scan line will interfere with the transistor overlapped but not connected therewith, thereby changing the signal output by the transistor and causing display abnormality of the display panel 10. In the embodiment of the present application, the second scan line S2 and the first transistor T1 do not overlap, which can weaken the influence of the second scan line S2 on the first transistor T1 and ensure that the privacy electrode E2 can receive effective voltage signals and the signal on the privacy electrode E2 is in a relatively stable working state. Similarly, the first scan line S1 and the second transistor T2 do not overlap, which can weaken the influence of the first scan line S1 on the second transistor T2 and ensure that the pixel electrode can receive effective voltage signals and the signal on the pixel electrode E1 is in a relatively stable working state.

[0109] In an embodiment of the present application, as shown in Figure 1 , Figure 6 to Figure 8 and Figure 11 , the display panel 10 further comprises a data line D, and the extension direction of the first scan line S1 is the same as the main extension direction of the data line D, that is, the extension direction of the first scan line S1 is substantially the same as the extension direction of the data line D. The extension direction of the second scan line S2 intersects with the extension direction of the first scan line S1, that is, the extension direction of the first scan line S1 intersects with the extension direction of the second scan line S2.

[0110] The extension directions of the first scan line S1 and the second scan line S2 are different, which facilitates that the two scan lines are respectively applicable to transistors in different setting modes and easy to realize the channel overlap of the two with the first transistor T1 and the second transistor T2 in different design modes to control the first transistor T1 and the second transistor T2.

[0111] In an embodiment of the present application, as shown inFigure 1 , Figure 6 to Figure 8 and Figure 11 As shown, along the direction Z perpendicular to the surface of the display panel, the first scan line S1 overlaps with the data line D, wherein the main body of the first scan line S1 can overlap with the data line D. By overlapping the first scan line S1 with the data line D, the excessive space occupied by the first scan line S1 in the first direction X can be reduced. It can be understood that the portion of the first scan line S1 that overlaps with the data line D can be located in a different conductive film layer than the data line D.

[0112] Figure 13 This is a partial schematic diagram of a display panel provided in an embodiment of this application.

[0113] In one embodiment of this application, such as Figure 13 As shown, the first scan line S1 includes a main body S1a and a protrusion S1b for electrical connection. Along the direction Z perpendicular to the surface of the display panel 10, the main body S1a at least partially overlaps with the data line D, and the protrusion S1b overlaps with the first switch SW1. That is, the first scan line S1 extends substantially along the extension direction of the data line D, and deflects towards the location of the first switch SW1 when it approaches it to achieve electrical connection with the control terminal of the first switch SW1, for example, to achieve electrical connection with the gate of the first transistor T1. For example, as... Figure 11 As shown, along the direction Z perpendicular to the surface of the display panel 10, the main body S1a of the first scan line S1 overlaps with the main body of the data line D, and the protrusion S1b overlaps with the first switch SW1 but does not overlap with the data line D.

[0114] In this embodiment, the main body S1a of the first scan line S1 overlaps at least partially with the data line D, which simplifies the wiring layout within the display panel 10. The protrusion S1b overlaps with the first switch SW1 but not with the data line D, thus enabling the first scan line S1 to control the first transistor T1 and reducing interference from the data line D to the first scan line S1.

[0115] Figure 14 This is a partial schematic diagram of a display panel provided in an embodiment of this application.

[0116] In one embodiment of this application, such as Figure 14 As shown, along the direction Z perpendicular to the surface of the display panel 10, the first scan line S1 and the data line D do not overlap.

[0117] In the embodiment of the present application, the projection of the first scan line S1 on the plane where the display panel 10 is located does not overlap with the projection of the data line D on the plane where the display panel 10 is located, which reduces the coupling capacitance between the data line D and the first scan line S1, and thus weakens the interference of the data line D on the signal transmitted by the first scan line S1. At this time, in the privacy mode, the first scan line S1 transmits a stable enable signal to control the first transistor T1 to be turned on, so that the privacy electrode E2 receives a stable driving voltage, and the privacy efficiency is maintained unchanged during the display process, thereby improving the privacy effect.

[0118] Figure 15 For Figure 14 the first scan line along the direction of D' D is shown in the cross section.

[0119] In an embodiment of the present application, in combination Figure 14 and Figure 15 As shown in the figure, when the extension direction of the first scan line S1 intersects with the extension direction of the second scan line S2, the first scan line S1 includes a first part S11 and a second part S12 which are electrically connected. In the direction Z perpendicular to the plane where the display panel 10 is located, the first part S11 overlaps with the second scan line S2 and the second part S12 does not overlap with the second scan line S2. The first part S11 is disposed in a different layer from the second scan line S2 and the second part S12 is disposed in the same layer as the second scan line S2. That is, the conductive film layer where the part of the first scan line S1 which does not overlap with the second scan line S2 is located is the same as the conductive film layer where the second scan line S2 is located. At this time, the part of the first scan line S1 which overlaps with the second scan line S2 is designed as a jumper, so as to avoid the short circuit of the first scan line S1 and the second scan line S2.

[0120] Figure 16 A partial schematic view of a display panel is provided in the embodiment of the present application.

[0121] In an embodiment of the present application, as shown in the figure, the extension direction of the first scan line S1 is parallel to the extension direction of the second scan line S2, so that in the direction Z perpendicular to the plane where the display panel 10 is located, the first scan line S1 does not overlap with the second scan line S2. For example, as shown in the figure, the first scan line S1 and the second scan line S2 both extend approximately along the first direction X. Figure 15 Figure 15

[0122] In the embodiment of the present application, by arranging the first scan line S1 and the second scan line S2 in parallel, the wiring arrangement in the display panel 10 is simplified. At the same time, in the direction Z perpendicular to the plane where the display panel 10 is located, the first scan line S1 does not overlap with the second scan line S2, which reduces the coupling interference between the first scan line S1 and the second scan line S2, avoids the miscontrol of the second scan line S2 on the first switch SW1, and avoids the miscontrol of the first scan line S1 on the second switch SW2. ​​

[0123] Figure 17 For Figure 16 A schematic view of a cross section along the direction of the first scan line in the middle.

[0124] In a technical solution corresponding to the embodiment, in combination with Figure 16 And Figure 17 The first scan line S1 and the second scan line S2 in the display panel 10 are arranged in the same layer, that is, the film layer in which the first scan line S1 is located is the same as the film layer in which the second scan line S2 is located.

[0125] In the embodiment, the first scan line S1 and the second scan line S2 are arranged in the same layer, thereby reducing the thickness of the display panel; meanwhile, the first scan line S1 and the second scan line S2 can be prepared in the same process, thereby saving cost and shortening the preparation period.

[0126] Figure 18 A schematic view of a partial cross section of a display panel provided in the embodiment, Figure 19 A schematic view of a partial cross section of a display panel provided in the embodiment.

[0127] In an embodiment of the present application, the first scan line S1 and the second scan line S2 can be arranged in different layers, and as shown in Figure 18 And Figure 19 The film layer in which the semiconductor layer T1C of the first transistor T1 and the semiconductor layer T2C of the second transistor T2 are located can be located between the film layer in which the first scan line S1 is located and the film layer in which the second scan line S2 is located. Among the first transistor T1 and the second transistor T2, one can be a bottom gate structure and the other can be a top gate structure. The semiconductor layer T2C of the second transistor T2 can be arranged in the same layer as the semiconductor layer T1C of the first transistor T1.

[0128] In an implementation manner, as shown in Figure 18 The first scan line S1 is located on the side of the semiconductor layer T1C included by the first transistor T1 away from the light emitting surface of the display panel, and the second scan line S2 is located on the side of the semiconductor layer T2C included by the second transistor T2 close to the light emitting surface of the display panel. That is, the first transistor T1 can be a bottom gate structure and the second transistor T2 can be a top gate structure.

[0129] In an implementation manner, as shown in Figure 19 The first scan line S1 is located on the side of the semiconductor layer T1C included by the first transistor T1 close to the light emitting surface of the display panel, and the second scan line S2 is located on the side of the semiconductor layer T2C included by the second transistor T2 away from the light emitting surface of the display panel. That is, the first transistor T1 can be a top gate structure and the second transistor T2 can be a bottom gate structure.

[0130] In the embodiment, the first scan line S1 and the second scan line S2 do not have a short circuit risk, and the two can have flexible setting positions according to the channel positions of the first transistor T1 and the second transistor T2.

[0131] In the embodiment, when the extension direction of the first scan line S1 is parallel to the extension direction of the main body of the data line D, for example, the two overlap in the direction Z perpendicular to the surface of the display panel, the first scan line S1 can be arranged on the side away from the film layer where the data line D is located relative to the film layer where the second scan line S1 is located, thereby reducing the signal interference between the first scan line S1 and the data line.

[0132] In the embodiment, when the extension direction of the first scan line S1 is parallel to the extension direction of the second scan line S2, the distance between the first scan line S1 and the second scan line S2 in the direction Z perpendicular to the surface of the display panel can be set to be farther, thereby reducing the signal interference between the two.

[0133] Figure 20 FIG. 1 is a schematic diagram of a partial cross-sectional structure of a display panel provided in an embodiment of the present application, Figure 21 FIG. 1 is a schematic diagram of a partial cross-sectional structure of a display panel provided in an embodiment of the present application.

[0134] In one embodiment of the present application, as shown in Figure 20 and Figure 21 , the display panel 10 further includes a data line D, and the data line D, the first scan line S1 and the second scan line S2 can be arranged in different layers, wherein the film layer where the first scan line S1 is located and the film layer where the second scan line S2 is located can be on the same side of the film layer where the data line D is located.

[0135] In one implementation, as shown in Figure 20 , the film layer where the first scan line S1 is located is between the film layer where the second scan line S2 is located and the film layer where the data line D is located.

[0136] In one implementation, as shown in Figure 21 , the film layer where the second scan line S2 is located is between the film layer where the first scan line S1 is located and the film layer where the data line D is located.

[0137] In the embodiment of the present application, the film layer where the first scan line S1 is located and the film layer where the second scan line S2 are located on the same side of the film layer where the data line D is located, and the distance between the first scan line S1 and the channel of the first transistor T1 in the direction Z perpendicular to the surface of the display panel is almost the same as the distance between the second scan line S2 and the channel of the second transistor T2 in the direction Z perpendicular to the surface of the display panel, and the first transistor T1 and the second transistor T2 can be controlled more effectively.

[0138] In one technical solution, as shown inFigure 20 and Figure 21 As shown in FIG. 1, the film layers where the first scan line S1 and the second scan line S2 are located are located on the side of the film layer where the data line D is located, facing the semiconductor layer T1C of the first transistor T1 and the semiconductor layer T2C of the second transistor T2.

[0139] Figure 22 FIG. 1 is a schematic diagram of a partial structure of a display panel according to an embodiment of the present application, Figure 23 for example, Figure 22 FIG. 2 is a schematic diagram of a cross section along the direction FF’ in FIG. 1. For the sake of clarity, Figure 22 and Figure 23 In some embodiments, some structures in the display panel are omitted, for example, the light shielding structure layer and the display medium layer are omitted.

[0140] In an embodiment of the present application, the display panel 10 further comprises a common electrode Com, which overlaps with at least two pixel electrodes E1 along the direction Z perpendicular to the surface where the display panel 10 is located. That is, the common electrode Com in the at least two sub-pixels provides a common voltage and the pixel electrodes E1 in the at least two sub-pixels can provide independent pixel voltages. Figure 22 and Figure 23 As shown in FIG. 1, the display panel 10 further comprises a common electrode Com, which overlaps with at least two pixel electrodes E1 along the direction Z perpendicular to the surface where the display panel 10 is located. That is, the common electrode Com in the at least two sub-pixels provides a common voltage and the pixel electrodes E1 in the at least two sub-pixels can provide independent pixel voltages.

[0141] In addition, the common electrode Com can also overlap with the privacy electrode E2 along the direction Z perpendicular to the surface where the display panel 10 is located. Then, the common electrode Com and the pixel electrode E1 and the privacy electrode E2 form an electric field to control the state of the display medium layer M, so that the transmittance of the display light is controllable.

[0142] In addition, the common electrode Com can also overlap with the privacy electrode E2 along the direction Z perpendicular to the surface where the display panel 10 is located. Then, the common electrode Com and the pixel electrode E1 and the privacy electrode E2 form an electric field to control the state of the display medium layer M, so that the transmittance of the display light is controllable.

[0143] In addition, the common electrode Com can also overlap with the privacy electrode E2 along the direction Z perpendicular to the surface where the display panel 10 is located. Then, the common electrode Com and the pixel electrode E1 and the privacy electrode E2 form an electric field to control the state of the display medium layer M, so that the transmittance of the display light is controllable.

[0144] The common electrode Com is usually provided with a notch, especially when the common electrode Com is located on the side of the pixel electrode E1 close to the light-emitting surface of the display panel. When the common electrode is located on the side of the pixel electrode E1 and the privacy electrode E2 close to the light-emitting surface of the display panel, if the common electrode Com is an electrode without a notch structure, the common electrode Com will shield the electric field between the pixel electrode E1, the privacy electrode E2 and the common electrode Com on the side of the common electrode Com away from the display medium layer M, so that the display medium layer M cannot be controlled.

[0145] Therefore, in the embodiment of the present application, the common electrode Com includes a first notch H1, and the first notch H1 overlaps the privacy electrode E2 along the direction Z perpendicular to the surface on which the display panel is located. The electric field formed by the common electrode Com and the privacy electrode E2 can control the display medium layer M through the first notch H1.

[0146] In addition, the common electrode Com can also include a second notch H2, and the second notch H2 overlaps the pixel electrode E1 along the direction Z perpendicular to the surface on which the display panel is located. The electric field formed by the common electrode Com and the pixel electrode E1 can control the display medium layer M through the second notch H2.

[0147] In an embodiment of the present application, as shown in Figure 14 the privacy electrode E2 does not overlap the data line D and does not overlap the first scan line S1 along the direction Z perpendicular to the surface on which the display panel 10 is located, and the first scan line S1 does not overlap the data line D.

[0148] In the embodiment of the present application, the privacy electrode E2 does not overlap the data line D and the first scan line S1, so that the signal on the privacy electrode E2 is weakened and is not interfered by the data line D and the first scan line S1, so that the privacy electrode E2 can maintain a stable voltage signal, avoid abnormal changes in the brightness of the second display light L2, and improve the privacy display effect.

[0149] Figure 24 A partial schematic view of a display panel is provided in an embodiment of the present application.

[0150] In an embodiment of the present application, as shown in Figure 24 the privacy electrode E2 at least partially overlaps the data line D and the first scan line S1 along the direction Z perpendicular to the surface on which the display panel 10 is located, so that the privacy electrode E2 occupies additional space in the display panel. For example, as shown in Figure 14 the main part of the privacy electrode E2 overlaps the main part of the data line D and overlaps the main part of the first scan line S1 along the direction Z perpendicular to the surface on which the display panel 10 is located.

[0151] In the embodiment of the present application, when the common electrode Com includes the first notch H1 overlapping the privacy electrode E2, the first notch H1 also overlaps at least one of the data line D and the first scan line S, but the portion of the data line D and / or the first scan line S overlapping the first notch H1 includes the privacy electrode E2 towards the side of the display medium layer M, so that the portion of the data line D and / or the first scan line S overlapping the first notch H1 will not cause miscontrol of the display medium layer M.

[0152] Figure 25 A partial schematic diagram of a display panel is provided in the embodiment of the present application, in order to clearly illustrate, Figure 25 part of the structure in the display panel is omitted, for example, the light shielding structure layer and the display medium layer are omitted.

[0153] In one embodiment of the present application, as Figure 25 shown, the display panel 10 includes a plurality of first scan lines S1, and at least part of the first scan lines S1 are electrically connected together. When at least part of the first scan lines S1 are electrically connected together, the first switches SW1 electrically connected by the first scan lines S1 can be simultaneously turned on and transmit voltage signals to the privacy electrodes E1, so that at least part of the privacy electrodes E2 can start working at the same time, i.e., the regions where the privacy electrodes E2 are located can simultaneously achieve privacy.

[0154] For example, as Figure 25 shown, the first scan line S1a is used to control the first privacy electrode E2a to work, the first scan line S1b is used to control the second privacy electrode E2b to work, and the first scan line S1a and the first scan line S1b are electrically connected together. Then the first privacy electrode E2a and the second privacy electrode E2b can start working at the same time, so that the regions near the first pixel electrode E1a and the second pixel electrode E1b can simultaneously achieve privacy.

[0155] In addition, at least part of the first scan lines S1 are electrically connected together, which can also reduce the driving difficulty of the first scan lines S1, and reduce the number of peripheral wires and / or peripheral circuits in the frame area of the display panel 10 electrically connected to the first scan lines S1 to achieve narrow frame display.

[0156] In one implementation form of the embodiment, all the first scan lines S1 are electrically connected together. Then all the regions provided with the privacy electrode E2 can simultaneously achieve privacy.

[0157] Figure 26 A partial schematic diagram of a display panel is provided in the embodiment of the present application.

[0158] In one implementation form of the embodiment, as Figure 26As shown, the plurality of first scan lines S1 of the display panel 10 includes first sub-scan lines Sa and second sub-scan lines Sb, that is, part of the plurality of first scan lines S1 are the first sub-scan lines Sa and part of the plurality of first scan lines S1 are the second sub-scan lines Sb. The first sub-scan lines Sa and the second sub-scan lines Sb can be arranged adjacently and alternately, or the plurality of first sub-scan lines Sa are arranged adjacently in sequence and the plurality of second sub-scan lines Sb are arranged adjacently in sequence.

[0159] At least two first sub-scan lines Sa are electrically connected and at least two second sub-scan lines Sb are electrically connected, and then the plurality of first sub-scan lines Sa can be electrically connected and the plurality of second sub-scan lines Sb can be electrically connected. In addition, the first sub-scan lines Sa and the second sub-scan lines Sb are electrically insulated.

[0160] In the embodiment of the present application, at least two first sub-scan lines Sa and at least two second sub-scan lines Sb are electrically connected respectively, so that part of the anti-peep electrodes E2 of the display panel 10 can work simultaneously and another part of the anti-peep electrodes E2 can work simultaneously.

[0161] In the present implementation, in some cases, part of the anti-peep electrodes E2 can work simultaneously and another part of the anti-peep electrodes E2 does not work, realizing partial anti-peep; in some cases, the anti-peep electrodes E2 of the display panel 10 can also work simultaneously. On the one hand, the working anti-peep electrodes E2 can be selected as needed to save power consumption; on the other hand, more flexible anti-peep can be realized.

[0162] In an embodiment of the present application, the display panel 10 includes sub-pixels of multiple colors, wherein the sub-pixels of multiple colors include green sub-pixels, as shown in the following figure. Figure 25 As shown, the pixel electrode E1 in the green sub-pixel is a green sub-pixel electrode E1b, and in the embodiment of the present application, the anti-peep electrode E2 is arranged adjacent to the green sub-pixel pixel electrode E1b.

[0163] For example, the sub-pixels of multiple colors also include red sub-pixels and blue sub-pixels, the pixel electrode E1 in the red sub-pixel is a red sub-pixel electrode E1a, and the pixel electrode E1 in the blue sub-pixel is a blue sub-pixel electrode E1c. As shown in the following figure. Figure 25 As shown, in the plane where the display panel 10 is located, the two anti-peep sub-electrodes E2 are located on both sides of the green sub-pixel pixel electrode E1b along the first direction X, and the anti-peep electrodes E2 can not be included between the red sub-pixel electrode E1a and the blue sub-pixel electrode E1c arranged adjacently along the first direction X.

[0164] In the embodiment of the present application, since the light emitted by the green sub-pixel Pg is more easily recognized by the human eye, the setting of the anti-peeping electrode E2 between the green sub-pixel and the sub-pixel adjacent thereto will generate more green second display light L2, and the observer under a large viewing angle is more likely to perceive the interference light and cannot distinguish the normal display picture, so the technical solution of the embodiment is more conducive to the realization of anti-peeping.

[0165] Figure 27 A partial schematic view of a display panel is provided in the embodiment of the present application.

[0166] In one embodiment of the present application, as shown in Figure 27 , the display panel 10 can be divided into a first area A1 and a second area A2 according to the distribution of the anti-peeping electrode E2, the first area A1 has no anti-peeping function and the second area A2 has the anti-peeping function.

[0167] Specifically, the first area A1 in the display panel 10 includes the pixel electrode E1, and the second area A2 includes the pixel electrode E1 and the anti-peeping electrode E2. The second area A2 can correspond to the edge area of the display panel 10.

[0168] In the embodiment of the present application, the setting of the first area A1 and the second area A2 divides the display panel 10 into an anti-peeping area and a non-anti-peeping area to meet the design requirements of anti-peeping display under different circumstances. For example, the display picture of the edge area of the display panel 10 is more likely to be peeped, and it is usually necessary to set the anti-peeping electrode E2 around the sub-pixel of the edge area of the display panel 10, and the edge area corresponds to the second area A2. The display picture of the central area of the display panel 10 is not easy to be peeped, so the anti-peeping electrode E2 can not be set in the first area A1 for the purpose of reducing the process difficulty and saving material cost.

[0169] The embodiment of the present application further provides a driving method of the display panel 10 for driving the display panel 10 in any of the above embodiments. The display mode of the display panel includes a first mode and a second mode. The driving method includes:

[0170] In the first mode, as shown in Figure 2 , the pixel electrode E1 and the anti-peeping electrode E2 are controlled to receive the voltage signal, so that the display panel 10 is in narrow viewing angle display;

[0171] In the second mode, as shown in Figure 3 , the pixel electrode E1 is controlled to receive the voltage signal and the anti-peeping electrode E2 is controlled not to receive the voltage signal, so that the display panel 10 is in wide viewing angle display.

[0172] The driving method provided by the embodiment of the present application can control the display mode of the display panel to switch between the anti-peep mode (first mode) and the non-anti-peep mode (second mode) by flexibly controlling whether the anti-peep electrode E2 receives the voltage signal.

[0173] In one embodiment of the present application, as shown in Figure 1 The display panel 10 further includes a data line D and first and second switches SW1 and SW2, and at least one anti-peep electrode E2 is electrically connected to the adjacent pixel electrode E1 through the first and second switches SW1 and SW2 and the same data line D.

[0174] A driving method corresponding to the embodiment is as follows:

[0175] In the first mode, the data line D is controlled to transmit a voltage signal, and the first and second switches SW1 and SW2 are controlled to be turned on, and the voltage signal transmitted by the data line D is transmitted to the anti-peep electrode E2 and the pixel electrode E1 through the turned-on first and second switches SW1 and SW2.

[0176] In the second mode, the data line D is controlled to transmit a voltage signal, the first switch SW1 is controlled to be turned off, and the second switch SW2 is controlled to be turned on, and the voltage signal transmitted by the data line D is transmitted to the pixel electrode E1 through the turned-on second switch SW2.

[0177] Figure 28 A driving timing corresponding to the display panel is as shown in Figure 1

[0178] The following takes an example in which the first and second switches SW1 and SW2 each include a first transistor T1 and a second transistor T2, and the first and second transistors T1 and T2 are both P-channel transistors.

[0179] As shown in Figure 28 In the first mode, the first and second scan lines S1 and S2 each transmit a low-level signal (enabling signal) to control the first and second switches SW1 and SW2 to be turned on, the data line D transmits a voltage signal, and the anti-peep electrode E2 and the pixel electrode E1 each receive the voltage signal transmitted by the data line D.

[0180] As shown in Figure 28 In the second mode, the first scan line S1 transmits a high-level signal (non-enabling signal) to control the first switch SW1 to be turned off, the second scan line S2 transmits a low-level signal (enabling signal) to control the second switch SW2 to be turned on, the data line D transmits a voltage signal, and the pixel electrode E1 receives the voltage signal transmitted by the data line D, and the anti-peep electrode E2 cannot receive the voltage signal.

[0181] When the first and second transistors T1 and T2 are both N-channel transistors, the driving method can be as follows:​

[0182] In the first mode, the first scan line S1 and the second scan line S2 both transmit high level signals (enabling signals) to control the first switch SW1 and the second switch SW2 to be turned on, the data line D transmits a voltage signal, and the peep-proof electrode E2 and the pixel electrode E1 both receive the voltage signal transmitted by the data line D.

[0183] As shown in FIG. 2B, in the second mode, the first scan line S1 transmits a low level signal (disabling signal) to control the first switch SW1 to be turned off, and the second scan line S2 transmits a high level signal (enabling signal) to control the second switch SW2 to be turned on, the data line D transmits a voltage signal, and the pixel electrode E1 receives the voltage signal transmitted by the data line D, and the peep-proof electrode E2 cannot receive the voltage signal. Figure 28 In an embodiment of the present application, as shown in FIG. 2C, the display panel 10 further includes a first data line D1, a second data line D2, a first switch SW1 and a second switch SW2. The peep-proof electrode E2 is electrically connected to the first data line D1 through the first switch SW1, and the pixel electrode E1 is electrically connected to the second data line D2 through the second switch SW2.

[0184] Figure 11 A driving method corresponding to the embodiment is as follows.

[0185] In the first mode, the first data line D1 and the second data line D2 are controlled to transmit voltage signals respectively, the first switch SW1 and the second switch SW2 are both controlled to be turned on, the voltage signal transmitted by the first data line D1 is transmitted to the peep-proof electrode E2 through the turned-on first switch SW1, and the voltage signal transmitted by the second data line D2 is transmitted to the pixel electrode E1 through the turned-on second switch.

[0186] In the second mode, the first data line D1 is controlled to stop transmitting the voltage signal and / or the first switch SW1 is controlled to be turned off, the second data line D2 is controlled to transmit the voltage signal, and the second switch SW2 is controlled to be turned on, and the voltage signal transmitted by the second data line D2 is transmitted to the pixel electrode E1 through the turned-on second switch SW2.

[0187] As shown in FIG. 3, a driving timing corresponding to the display panel is as follows.

[0188] Figure 29 The following takes an example in which the first switch SW1 and the second switch SW2 each include a first transistor T1 and a second transistor T2, and the first transistor T1 and the second transistor T2 are both P-channel transistors. Figure 11 As shown in FIG. 4A, in the first mode, the first scan line S1 and the second scan line S2 both transmit high level signals (enabling signals) to control the first transistor T1 and the second transistor T2 to be turned on, the data line D transmits a voltage signal, and the peep-proof electrode E2 and the pixel electrode E1 both receive the voltage signal transmitted by the data line D.

[0189] As shown in FIG. 4B, in the second mode, the first scan line S1 transmits a low level signal (disabling signal) to control the first transistor T1 to be turned off, and the second scan line S2 transmits a high level signal (enabling signal) to control the second transistor T2 to be turned on, the data line D transmits a voltage signal, and the pixel electrode E1 receives the voltage signal transmitted by the data line D, and the peep-proof electrode E2 cannot receive the voltage signal.

[0190] Figure 29 ​​As shown in the first mode, the first scan line S1 and the second scan line S2 both transmit low level signals (enable signals) to control the first switch SW1 and the second switch SW2 to open, the first data line D1 and the second data line D2 both transmit voltage signals, the voltage signal transmitted by the first data line D1 is received by the privacy electrode E2, and the voltage signal transmitted by the second data line D is received by the pixel electrode E1.

[0191] As shown in the second mode, the first scan line S1 transmits a high level signal (non-enable signal) to control the first switch SW1 to close, and the second scan line S2 transmits a low level signal (enable signal) to control the second switch SW2 to open, the first data line D1 transmits a voltage signal, and the second data line D2 does not transmit a voltage signal, the voltage signal transmitted by the data line D is received by the pixel electrode E1, and the privacy electrode E2 cannot receive a voltage signal. Figure 29 As shown in the second mode, the first scan line S1 transmits a high level signal (non-enable signal) to control the first switch SW1 to close, and the second scan line S2 transmits a low level signal (enable signal) to control the second switch SW2 to open, the first data line D1 transmits a voltage signal, and the second data line D2 does not transmit a voltage signal, the voltage signal transmitted by the data line D is received by the pixel electrode E1, and the privacy electrode E2 cannot receive a voltage signal.

[0192] As shown in the second mode, the first scan line S1 transmits a high level signal (non-enable signal) to control the first switch SW1 to close, and the second scan line S2 transmits a low level signal (enable signal) to control the second switch SW2 to open, the first data line D1 transmits a voltage signal, and the second data line D2 does not transmit a voltage signal, the voltage signal transmitted by the data line D is received by the pixel electrode E1, and the privacy electrode E2 cannot receive a voltage signal.

[0193] As shown in the second mode, the first scan line S1 transmits a high level signal (non-enable signal) to control the first switch SW1 to close, and the second scan line S2 transmits a low level signal (enable signal) to control the second switch SW2 to open, the first data line D1 transmits a voltage signal, and the second data line D2 does not transmit a voltage signal, the voltage signal transmitted by the data line D is received by the pixel electrode E1, and the privacy electrode E2 cannot receive a voltage signal.

[0194] Figure 29 As shown in the second mode, the first scan line S1 transmits a high level signal (non-enable signal) to control the first switch SW1 to close, and the second scan line S2 transmits a low level signal (enable signal) to control the second switch SW2 to open, the first data line D1 transmits a voltage signal, and the second data line D2 does not transmit a voltage signal, the voltage signal transmitted by the data line D is received by the pixel electrode E1, and the privacy electrode E2 cannot receive a voltage signal.

[0195] As shown in the second mode, the first scan line S1 transmits a high level signal (non-enable signal) to control the first switch SW1 to close, and the second scan line S2 transmits a low level signal (enable signal) to control the second switch SW2 to open, the first data line D1 transmits a voltage signal, and the second data line D2 does not transmit a voltage signal, the voltage signal transmitted by the data line D is received by the pixel electrode E1, and the privacy electrode E2 cannot receive a voltage signal. Figure 1 Figure 11 As shown in the second mode, the first scan line S1 transmits a high level signal (non-enable signal) to control the first switch SW1 to close, and the second scan line S2 transmits a low level signal (enable signal) to control the second switch SW2 to open, the first data line D1 transmits a voltage signal, and the second data line D2 does not transmit a voltage signal, the voltage signal transmitted by the data line D is received by the pixel electrode E1, and the privacy electrode E2 cannot receive a voltage signal. Figure 28 Figure 29 As shown in the second mode, the first scan line S1 transmits a high level signal (non-enable signal) to control the first switch SW1 to close, and the second scan line S2 transmits a low level signal (enable signal) to control the second switch SW2 to open, the first data line D1 transmits a voltage signal, and the second data line D2 does not transmit a voltage signal, the voltage signal transmitted by the data line D is received by the pixel electrode E1, and the privacy electrode E2 cannot receive a voltage signal.

[0196] As shown in the second mode, the first scan line S1 transmits a high level signal (non-enable signal) to control the first switch SW1 to close, and the second scan line S2 transmits a low level signal (enable signal) to control the second switch SW2 to open, the first data line D1 transmits a voltage signal, and the second data line D2 does not transmit a voltage signal, the voltage signal transmitted by the data line D is received by the pixel electrode E1, and the privacy electrode E2 cannot receive a voltage signal.

[0197] ​​​In the second mode, the first scan line S1 is controlled to transmit a non-enable signal and the non-enable signal controls the first switch SW1 to be off, the second scan line S2 is controlled to transmit a second non-enable signal and the second enable signal controls the second switch SW2 to be on.

[0198] Figure 30 A schematic diagram of a display device provided by an embodiment of the present application.

[0199] The present application provides a display device 20, as shown in Figure 30 The display device 20 includes the display panel 10 provided by the above embodiment and is driven by the driving method described in the above embodiment. The display device 20 can be a mobile phone, and in addition, the display device 20 can also be a computer, a television or other electronic equipment.

[0200] The display device 20 provided by the embodiment of the present application can control the display mode of the display panel to switch between the anti-peeping mode (the first mode) and the non-anti-peeping mode (the second mode) by setting the anti-peeping electrode E2 and by controlling whether the anti-peeping electrode E2 receives the voltage signal.

[0201] The above only describes the preferred embodiments of the present application and is not intended to limit the present application. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A display panel, characterized in that, include: First substrate; The display dielectric layer is located on one side of the first substrate. Multiple pixel electrodes and multiple privacy electrodes are located between the first substrate and the display medium layer; A light-shielding structure layer, comprising a light-shielding structure and a cutout portion; along a direction perpendicular to the surface of the display panel, the privacy electrode overlaps with the light-shielding structure and the pixel electrode overlaps with the cutout portion; wherein, the light-shielding structure layer is located on the side of the privacy electrode facing the light-emitting surface of the display panel; The display panel also includes a data cable and a first switch and a second switch; at least one of the privacy electrodes and the adjacent pixel electrodes are electrically connected to the same data cable through the first switch and the second switch, respectively; The control terminal of the first switch is electrically connected to the first scan line, and the control terminal of the second switch is electrically connected to the second scan line; The extension direction of the first scan line is the same as the extension direction of the main body of the data line, and the extension direction of the first scan line intersects the extension direction of the second scan line.

2. The display panel according to claim 1, characterized in that, The light-shielding structure covers the privacy electrode along a direction perpendicular to the surface of the display panel.

3. The display panel according to claim 1, characterized in that, The privacy electrode is disposed in the same layer as the pixel electrode.

4. The display panel according to claim 1, characterized in that, The first switch includes a first transistor, and the second switch includes a second transistor; At least one of the privacy electrodes and the adjacent pixel electrode are electrically connected to the first electrode of the first transistor and the first electrode of the second transistor, respectively, and the second electrode of the first transistor and the second electrode of the second transistor are multiplexed and electrically connected to the same data line.

5. The display panel according to claim 1, characterized in that, The display panel also includes a first data cable, a second data cable, a first switch, and a second switch; The privacy electrode is electrically connected to the first data line via the first switch, and the pixel electrode is electrically connected to the second data line via the second switch.

6. The display panel according to claim 1, characterized in that, Along the direction perpendicular to the surface of the display panel, the first scan line does not overlap with the second switch, and the second scan line does not overlap with the first switch.

7. The display panel according to claim 1, characterized in that, Along a direction perpendicular to the surface of the display panel, the first scan line overlaps with the data line.

8. The display panel according to claim 1, characterized in that, The first scan line includes an electrically connected main body and a protrusion; Along a direction perpendicular to the surface of the display panel, the main body overlaps at least partially with the data line, and the protrusion overlaps with the first switch.

9. The display panel according to claim 1, characterized in that, The first scan line includes a first part and a second part that are electrically connected, along a direction perpendicular to the surface of the display panel, wherein the first part overlaps with the second scan line and the second part does not overlap with the second scan line; The first part is disposed on a different layer from the second scan line, and the second part is disposed on the same layer as the second scan line.

10. The display panel according to claim 1, characterized in that, Along a direction perpendicular to the surface of the display panel, the privacy electrode does not overlap with the data line or the first scan line.

11. The display panel according to claim 1, characterized in that, Along a direction perpendicular to the surface of the display panel, the privacy electrode overlaps with at least one of the data line and the first scan line.

12. The display panel according to claim 1, characterized in that, The first switch includes a first transistor, and the second switch includes a second transistor; The first scan line is located on the side of the semiconductor layer included in the first transistor that is away from the light-emitting surface of the display panel, and the second scan line is located on the side of the semiconductor layer included in the second transistor that is close to the light-emitting surface of the display panel; or, The second scan line is located on the side of the semiconductor layer included in the second transistor that is away from the light-emitting surface of the display panel, and the first scan line is located on the side of the semiconductor layer included in the first transistor that is close to the light-emitting surface of the display panel.

13. The display panel according to claim 1, characterized in that, The display panel also includes a data cable; The film layer containing the first scan line is located between the film layer containing the second scan line and the film layer containing the data line; or, The film layer containing the second scan line is located between the film layer containing the first scan line and the film layer containing the data line.

14. The display panel according to claim 1, characterized in that, At least a portion of the first scan lines are electrically connected together.

15. The display panel according to claim 14, characterized in that, All the first scan lines are electrically connected together.

16. The display panel according to claim 14, characterized in that, The plurality of first scan lines include a first sub-scan line and a second sub-scan line, the first sub-scan line and the second sub-scan line are electrically insulated from each other, at least two of the first sub-scan lines are electrically connected and at least two of the second scan lines are electrically connected.

17. The display panel according to claim 1, characterized in that, The display panel also includes a common electrode, which overlaps with at least two of the pixel electrodes along a direction Z perpendicular to the surface of the display panel. The common electrode includes a first slit along a direction Z perpendicular to the surface of the display panel, and the first slit overlaps with the privacy electrode.

18. The display panel according to claim 1, characterized in that, The privacy electrode is located between at least partially adjacent pixel electrodes along a first direction, and / or the privacy electrode is located between at least partially adjacent pixel electrodes along a second direction; the first direction intersects the second direction.

19. The display panel according to claim 18, characterized in that, The plurality of pixel electrodes includes a green sub-pixel pixel electrode, and the privacy electrode is disposed adjacent to the green sub-pixel pixel electrode.

20. The display panel according to claim 18, characterized in that, The display panel includes a first area and a second area, wherein the privacy electrode is included in the second area and the privacy electrode is not included in the first area.

21. The display panel according to claim 1, characterized in that, The display panel has a first mode in which it displays with a narrow viewing angle; in the first mode, at least some of the pixel electrodes and at least some of the privacy electrodes receive voltage signals.

22. A driving method for a display panel, characterized in that, The method is used to drive the display panel according to any one of claims 1-21, wherein the display panel has a display mode including a first mode and a second mode; the driving method includes: In the first mode, both the pixel electrode and the privacy electrode are controlled to receive voltage signals so that the display panel displays with a narrow viewing angle; In the second mode, the pixel electrode is controlled to receive a voltage signal and the privacy electrode is controlled not to receive a voltage signal, so that the display panel can display with a wide viewing angle.

23. The driving method according to claim 22, characterized in that, The display panel further includes a data cable and a first switch and a second switch; at least one of the privacy electrodes and adjacent pixel electrodes are electrically connected to the same data cable via the first switch and the second switch, respectively; the driving method includes: In the first mode, the data line is controlled to transmit a voltage signal, and both the first switch and the second switch are controlled to be turned on. The voltage signal transmitted on the data line is transmitted to the privacy electrode and the pixel electrode through the turned-on first switch and second switch, respectively. In the second mode, the data line is controlled to transmit a voltage signal, the first switch is controlled to turn off and the second switch is controlled to turn on, and the voltage signal transmitted on the data line is transmitted to the pixel electrode through the turned-on second switch.

24. The driving method according to claim 22, characterized in that, The display panel further includes a first data line, a second data line, a first switch, and a second switch; the privacy electrode is electrically connected to the first data line via the first switch, and the pixel electrode is electrically connected to the second data line via the second switch; In the first mode, the first data line and the second data line are controlled to transmit voltage signals respectively, and the first switch and the second switch are both turned on. The voltage signal transmitted on the first data line is transmitted to the privacy electrode through the turned-on first switch, and the voltage signal transmitted on the second data line is transmitted to the pixel electrode through the turned-on second switch. In the second mode, the first data line is controlled to stop transmitting voltage signals and / or the first switch is controlled to turn off, the second data line is controlled to transmit voltage signals and the second switch is controlled to turn on, and the voltage signal transmitted on the second data line is transmitted to the pixel electrode through the turned-on second switch.

25. The driving method according to claim 23 or 24, characterized in that, The control terminal of the first switch is electrically connected to the first scan line, and the control terminal of the second switch is electrically connected to the second scan line; In the first mode, the first scan line is controlled to transmit a first enable signal and the first enable signal controls the first switch to turn on, and the second scan line is controlled to transmit a second enable signal and the second enable signal controls the second switch to turn on. In the second mode, the first scan line is controlled to transmit a de-enabled signal and the de-enabled signal controls the first switch to turn off, and the second scan line is controlled to transmit a second enabled signal and the second enabled signal controls the second switch to turn on.

26. A display device, characterized in that, Includes the display panel as described in any one of claims 1-21.

Images