Display panel and display device

Abstract

Embodiments of the present application provide a display panel and a display device. In the display panel, one of a first driving circuit and a second driving circuit is a light-emitting driving circuit, and the other is a scanning driving circuit; a first terminal is used for transmitting a first start signal, and a second terminal is used for transmitting a second start signal; the first start signal and the second start signal are driving signals of the first driving circuit and the second driving circuit respectively; a first input end of a reset circuit is coupled with the first terminal, a second input end of the reset circuit is coupled with the second terminal, and an output end of the reset circuit is coupled with a start signal receiving end of the first driving circuit; and the reset circuit is used for resetting the first start signal and outputting the first start signal when a level matching of the first start signal and the second start signal is abnormal. The present application can reset the abnormal first start signal, so that the first start signal received by the first driving circuit and the second start signal received by the second driving circuit are matched with each other, thereby normally driving the pixel circuit and avoiding display abnormality.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of display, in particular to a display panel and a display device. BACKGROUND

[0002] At present, a display panel is driven by a display driving chip providing signals to the display panel. The internal modules of the display driving chip are easily disturbed by external noise or affected by static electricity, leading to abnormal signals output by the logic circuit. The display panel receiving the abnormal signals will result in display abnormality. SUMMARY

[0003] Embodiments of the present application provide a display panel and a display device to solve the problem of display abnormality caused by the display panel receiving abnormal signals in the prior art.

[0004] In a first aspect, embodiments of the present application provide a display panel, comprising:

[0005] The first driving circuit and the second driving circuit each comprise a plurality of cascaded shift registers; one of the first driving circuit and the second driving circuit is a light-emitting driving circuit, and the other is a scanning driving circuit.

[0006] The first terminal is used for transmitting a first start signal, and the second terminal is used for transmitting a second start signal; the first start signal is a driving signal of the first driving circuit, and the second start signal is a driving signal of the second driving circuit.

[0007] The reset circuit has a first input end coupled to the first terminal, a second input end coupled to the second terminal, and an output end coupled to a start signal receiving end of the first driving circuit; the reset circuit is used for resetting the first start signal and outputting the first start signal when the levels of the first start signal and the second start signal are abnormal.

[0008] In a second aspect, based on the same inventive concept, embodiments of the present application further provide a display device comprising the display panel provided by any of the embodiments of the present application.

[0009] The display panel and the display device provided by the embodiments of the present application have the following beneficial effects: the display panel is provided with a reset circuit, two input ends of the reset circuit are connected to a first terminal and a second terminal respectively, and an output end of the reset circuit is connected to a start signal receiving end of a first driving circuit; the reset circuit is used for resetting a first start signal and outputting the first start signal to the start signal receiving end of the first driving circuit when the levels of the first start signal and a second start signal are abnormal. The first start signal is reset by the reset circuit, which can ensure that the first start signal received by the first driving circuit and the second start signal received by the second driving circuit are matched with each other, so as to normally drive a pixel circuit and avoid display abnormality. Attached Figure Description

[0010] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0011] Figure 1 A schematic diagram of a display panel provided in an embodiment of the present invention;

[0012] Figure 2 A schematic diagram of a pixel circuit provided in an embodiment of the present invention;

[0013] Figure 3 for Figure 2 Timing diagram of the pixel circuit provided in the embodiment;

[0014] Figure 4 A schematic diagram for matching the first and second start signals;

[0015] Figure 5 A schematic diagram of a reset circuit structure provided in an embodiment of the present invention;

[0016] Figure 6 A schematic diagram of a reset circuit structure provided in an embodiment of the present invention;

[0017] Figure 7 This is a simplified schematic diagram of another display panel provided in an embodiment of the present invention;

[0018] Figure 8 This is a schematic diagram of the waveforms of the first starting signal before and after the filtering circuit.

[0019] Figure 9 A schematic diagram of a filter circuit provided in an embodiment of the present invention;

[0020] Figure 10 This is a schematic diagram of a display device provided in an embodiment of the present invention. Detailed Implementation

[0021] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0022] The terminology used in the description of the embodiments herein is for the purpose of describing particular embodiments only and is not intended to be limiting thereof. As used in the description of the embodiments and the appended claims, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.

[0023] The prior art display driving chip has high integration, and cannot set anti-static protection elements for all signals. In addition, due to the requirements of the customer's whole machine, the layout space of the flexible circuit board is limited, and there is no space to increase the anti-static protection elements. When the display driving chip is disturbed by static electricity, the internal circuit logic is chaotic, and the output light-emitting control signal or scanning signal is abnormal, which will cause display abnormalities.

[0024] In order to solve the problems existing in the prior art, the embodiments of the present application provide a display panel, a reset circuit is arranged in the display panel, the reset circuit is coupled with a signal terminal, and the reset circuit is used to reset abnormal signals, so that the abnormal signals are restored to normal signals and then output to a driving circuit, so as to avoid display abnormalities of the display panel.

[0025] Figure 1 A display panel provided by the embodiments of the present application is shown in FIG. 1. Figure 1 As shown in FIG. 1, the display panel includes a display area AA and a non-display area NA, the display area AA includes a plurality of sub-pixels sp, the sub-pixel sp includes a light-emitting device and a pixel circuit, the light-emitting device is an organic light-emitting device or an inorganic light-emitting device, the non-display area NA is provided with a first driving circuit 10 and a second driving circuit 20, the first driving circuit 10 and the second driving circuit 20 respectively include a plurality of cascaded shift registers, and the shift register can be any one in the prior art. After the input end of the first stage shift register in the first driving circuit 10 receives a first start signal, the multiple-stage shift registers in the first driving circuit 10 sequentially output an enable signal. After the input end of the first stage shift register in the second driving circuit 20 receives a second start signal, the multiple-stage shift registers in the second driving circuit 20 sequentially output an enable signal. One of the first driving circuit 10 and the second driving circuit 20 is a light-emitting driving circuit, and the other is a scanning driving circuit; the pixel circuit can be any one in the prior art, the shift register in the scanning driving circuit provides a scanning signal for the pixel circuit, and the shift register in the light-emitting driving circuit provides a light-emitting control signal for the pixel circuit.

[0026] Figure 1The illustration only shows the first driving circuit 10 and the second driving circuit 20 located on the same side of the display area AA. In other embodiments, the first driving circuit 10 and the second driving circuit 20 are located on opposite sides of the display area AA. In still other embodiments, the display panel includes two first driving circuits 10 and two second driving circuits 20, with the two first driving circuits 10 located on opposite sides of the display area AA and the two second driving circuits 20 located on opposite sides of the display area AA.

[0027] In this embodiment of the invention, the pixel circuit can be an aTbC structure, where a and b are positive integers, T represents a transistor, and C represents a capacitor. Taking a pixel circuit with a = 7 and b = 1, i.e., a 7T1C structure, as an example. Figure 2 This is a schematic diagram of a pixel circuit provided in an embodiment of the present invention. Figure 3 for Figure 2 Timing diagram of the pixel circuit provided in the embodiment. (e.g.) Figure 2 As shown, the pixel circuit includes a driving transistor Tm, a gate reset transistor M1, an electrode reset transistor M2, a data writing transistor M3, a threshold compensation transistor M4, a first light-emitting control transistor M5, a second light-emitting control transistor M6, and a storage capacitor Cst. The first terminal of the gate reset transistor M1 receives a reset signal Ref, and the second terminal of the gate reset transistor M1 is coupled to the gate of the driving transistor Tm. The gate of the gate reset transistor M1 receives a first scan signal S1. The first terminal of the data writing transistor M3 receives a data signal Vdata, and the second terminal of the data writing transistor M3 is coupled to the first terminal of the driving transistor Tm. The threshold compensation transistor M4 is connected in series between the gate and the second terminal of the driving transistor Tm. The gates of both the data writing transistor M3 and the threshold compensation transistor M4 receive a second scan signal S2. The driving transistor Tm is connected in series between the first light-emitting control transistor M5 and the second light-emitting control transistor M6. The gates of both the first light-emitting control transistor M5 and the second light-emitting control transistor M6 receive a light-emitting control signal E. Additionally, the first plate of the storage capacitor Cst and the first electrode of the first light-emitting control transistor M5 receive the positive power supply signal Pvdd. The second electrode of the second light-emitting control transistor M6 is coupled to the first electrode of the light-emitting device PD, and the second electrode of the light-emitting device PD receives the negative power supply signal Pvee. The first electrode of the electrode reset transistor M2 receives the reset signal Ref, and the second electrode of the electrode reset transistor M2 is coupled to the first electrode of the light-emitting device PD. The gate of the electrode reset transistor M2 receives either the first scan signal S1 or the second scan signal S2.

[0028] Combination Figure 3 Use the illustrated timing diagram to understand Figure 2Working principle of the middle pixel circuit. The working period of the pixel circuit includes a reset stage t1, a data writing stage t2 and a light emitting stage t3. The first node N1 is reset in the reset stage t1, the data voltage is written to the first node N1 in the data writing stage t2, and the driving transistor Tm generates a driving current under the control of the potential of the first node N1 in the light emitting stage t3 and provides the driving current to the light emitting device PD. Among them, the first scan signal S1 and the second scan signal S2 are provided by the adjacent two stages of the shift register of the scan driving circuit, and the light emitting control signal E is provided by the light emitting driving circuit.

[0029] As shown in Figure 1 The display panel further includes a first terminal 31, a second terminal 32 and a reset circuit 40, which are located in the non-display area NA. The first terminal 31 is used to transmit a first start signal, and the second terminal 32 is used to transmit a second start signal; the first start signal is a driving signal of the first driving circuit 10, and the second start signal is a driving signal of the second driving circuit 20. Among them, the first start signal and the second start signal are provided by the display driving chip. The non-display area NA of the display panel further includes a plurality of terminals not shown, and the terminals on the display panel are coupled with the display driving chip. In some embodiments, the display driving chip is directly bound to the non-display area NA of the display panel, and the display driving chip outputs signals to the terminals, and provides signals to the lines in the display panel through the terminals to drive the display panel to display. In another embodiment, the flexible circuit board is bound to the terminals on the display panel, and the display driving chip is fixed on the flexible circuit board, and the display driving chip outputs signals to the terminals through the lines on the flexible circuit board.

[0030] The first input end of the reset circuit 40 is coupled with the first terminal 31, the second input end of the reset circuit 40 is coupled with the second terminal 32, and the output end of the reset circuit 40 is coupled with the start signal receiving end of the first driving circuit 10; the reset circuit 40 is used to reset and output the first start signal when the level cooperation of the first start signal and the second start signal is abnormal. The second terminal 32 is also coupled with the start signal receiving end of the second driving circuit 20. The input end of the first stage shift register in the first driving circuit 10 is the start signal receiving end, and similarly, the input end of the first stage shift register in the second driving circuit 20 is the start signal receiving end.

[0031] The first start signal and the second start signal are provided by a display driving chip, and the display driving chip provides the first start signal and the second start signal to circuit lines in the display panel via the first terminal 31 and the second terminal 32. However, when the internal module of the display driving chip is affected by static electricity, the logic circuit will output abnormal start signals. For example, when the first start signal is abnormal, the display will be abnormal due to the abnormal level matching of the first start signal and the second start signal.

[0032] The display panel provided by the embodiment of the present application is provided with a reset circuit 40, two input ends of the reset circuit 40 are connected with the first terminal 31 and the second terminal 32 respectively, and an output end is connected with a start signal receiving end of the first driving circuit 10. The reset circuit 40 is used for resetting the first start signal and outputting the first start signal to the start signal receiving end of the first driving circuit 10 when the level matching of the first start signal and the second start signal is abnormal. The first start signal is reset by the reset circuit 40, so that the first start signal received by the first driving circuit 10 and the second start signal received by the second driving circuit 20 can be matched with each other, thereby normally driving the pixel circuit and avoiding display abnormality.

[0033] According to the above Figure 3 pixel circuit working timing diagram, the matching timing diagram of the start signals of the scan driving circuit and the light emitting driving circuit can be determined. Taking the first start signal STV1 as the start signal for driving the light emitting driving circuit and the second start signal STV2 as the start signal for driving the scan driving circuit as an example, Figure 4 is a schematic diagram for matching the first start signal and the second start signal. As shown in Figure 4 , the matching of the first start signal STV1 and the second start signal STV2 includes three cases: the first start signal STV1 is high and the second start signal STV2 is low at the same time, the first start signal STV1 is high and the second start signal STV2 is high, and the first start signal STV1 is low and the second start signal STV2 is high. That is, when the first start signal STV1 is low and the second start signal STV2 is low at the same time, the level matching of the first start signal STV1 and the second start signal STV2 is abnormal, which will cause display abnormality.

[0034] In some embodiments, as shown in Figure 4 , the first start signal STV1 and the second start signal STV2 are composed of high level signals and low level signals respectively. The reset circuit 40 is used for resetting the first start signal STV1 to a high level signal and outputting the first start signal STV1 when the first start signal STV1 and the second start signal STV2 are both low level signals in the same period. Figure 4In the embodiment, the first start signal STV1 is the start signal for driving the light-emitting driving circuit, the second start signal STV2 is the start signal for driving the scanning driving circuit, the first driving circuit 10 is the light-emitting driving circuit, the second driving circuit 20 is the scanning driving circuit, and the reset circuit 40 is configured to reset the abnormal potential of the start signal of the light-emitting driving circuit, so that the level of the start signal of the light-emitting driving circuit can be normally matched with the level of the start signal of the scanning driving circuit, thereby ensuring the normal driving of the pixel circuit and avoiding display abnormality.

[0035] In some other embodiments, the first start signal STV1 is the start signal for driving the scanning driving circuit, the second start signal STV2 is the start signal for driving the light-emitting driving circuit, the first driving circuit 10 is the scanning driving circuit, the second driving circuit 20 is the light-emitting driving circuit, and the reset circuit 40 is configured to reset the abnormal potential of the start signal of the scanning driving circuit, so that the level of the start signal of the scanning driving circuit can be normally matched with the level of the start signal of the light-emitting driving circuit, thereby ensuring the normal driving of the pixel circuit and avoiding display abnormality.

[0036] In some embodiments, Figure 5 FIG. 1 is a structural schematic diagram of a reset circuit according to an embodiment of the present application, Figure 5 The first input end IN1 and the second input end IN2 of the reset circuit 40 and the output end OUT are shown in FIG. 1. The first input end IN1 receives the first start signal, and the second input end IN2 receives the second start signal. As shown in FIG. 1, the reset circuit 40 includes a determination module 41 and a reset module 42, and the control end of the reset module 42 is coupled with the output end of the determination module 41. Figure 5 The determination module 41 is configured to determine the level matching condition of the received first start signal and second start signal, and send a reset control signal to the reset module 42 when the determination is abnormal. In combination with FIG. 2, Figure 4The level matching diagram of the schematic first start signal STV1 and the second start signal STV2 is used for understanding that the determination module 41 is used for determining as abnormal when the received first start signal STV1 and the second start signal STV2 are both low level in the same period, and sending a reset control signal to the reset module 42. The reset module 42 provides the first start signal STV1 after reset to the output end OUT of the reset circuit 40 under the control of the reset control signal. Wherein, the reset module 42 provides the first start signal STV1 to the output end OUT of the reset circuit 40 after resetting the first start signal STV1 from low level to high level. The determination module 41 and the reset module 42 are provided in the embodiment to reset the first start signal STV1 to a level signal that can match the second start signal STV2, so as to ensure that the level of the start signal of the first driving circuit can normally cooperate with the level of the start signal of the second driving circuit, thereby ensuring the normal driving of the pixel circuit and avoiding display abnormality.

[0037] As shown in Figure 5 The determination module 41 includes an OR gate 411, and the OR gate 411 is used for determining as abnormal when the received first start signal STV1 and the second start signal STV2 are both low level signals in the same period, and outputting a reset control signal to the control end of the reset module 42, and the reset control signal is a low level signal. The first input end of the OR gate 411 is connected to the first input end IN1 of the reset circuit 40 to receive the first start signal, and the second input end of the OR gate 411 is connected to the second input end IN2 of the reset circuit 40 to receive the second start signal. When at least one of the first input end and the second input end of the OR gate 411 receives a high level, the output end outputs a high level; when all the input ends of the OR gate 411 receive a low level, the output end outputs a low level. In the embodiment, the OR gate 411 is used for determining the level cooperation abnormality of the first start signal and the second start signal, and outputting a low level reset control signal to the control end of the reset module 42 when the first start signal and the second start signal are both low level, so as to control the reset module 42 to reset the first start signal.

[0038] As shown in Figure 6As shown, the reset module 42 includes an inverter 421 and a first transistor 422; an input end of the inverter 421 is coupled with the first input end of the reset circuit 40, and an output end of the inverter 421 is coupled with a first end of the first transistor 422; a control end of the first transistor 422 is coupled with the output end of the determination module 41, and a second end of the first transistor 422 is coupled with the output end of the reset circuit 40; the inverter 421 is configured to invert the phase of the first start signal STV1 and provide the first end of the first transistor 422, and the first transistor 422 is configured to be turned on under the control of the reset control signal. In this embodiment, the reset module 42 includes the inverter 421 and the first transistor 422, and the structure of the reset module 42 is simple. When the first start signal and the second start signal are both low, the control end of the reset module 42 outputs a low reset control signal, and the first transistor 422 is a p-type transistor and is turned on under the control of the low signal. When the first start signal is low, the inverter 421 converts the low signal into a high signal and provides the first end of the first transistor 422, and when the first transistor 422 is turned on, the high first start signal is provided to the output end OUT of the reset circuit 40, so that the reset circuit 40 resets the low first start signal to a high first start signal, so that the level matching of the first start signal and the second start signal is normal.

[0039] In some embodiments, Figure 6 A reset circuit structure diagram is provided for the embodiments of the present application, as shown in Figure 6 As shown, the reset circuit 40 further includes a non-reset module 43, and a control end of the non-reset module 43 is coupled with the output end of the determination module 41; the determination module 41 is further configured to determine the level matching of the received first start signal STV1 and second start signal STV2 in the same period, and send a non-reset control signal to the non-reset module 43 when the determination is normal; and the non-reset module 43 is configured to directly provide the received first start signal STV1 to the output end OUT of the reset circuit 40 under the control of the non-reset control signal. In combination with Figure 4 As shown in the schematic level matching diagram of the first start signal STV1 and the second start signal STV2, the determination module 41 is configured to determine that the level matching of the first start signal STV1 and the second start signal STV2 is normal when both of them are high or one is high and the other is low in the same period, and send a non-reset control signal to the non-reset module 43. The non-reset module 43 does not change the phase of the first start signal STV1, but directly outputs the first start signal STV1. That is, when the level matching of the first start signal STV1 and the second start signal STV2 is normal, the reset circuit 40 can directly output the received first start signal STV1.

[0040] As shown in Figure 6 The determination module 41 includes an OR gate 411, which is used to determine that the first start signal STV1 and the second start signal STV2 are normal when both of them are high signals or one is a high signal and the other is a low signal in the same period, and outputs a non-reset control signal to the control end of the non-reset module 43. The non-reset control signal is a high signal. In this embodiment, the OR gate 411 is used to determine the level cooperation of the first start signal STV1 and the second start signal STV2. When the level cooperation of the first start signal STV1 and the second start signal STV2 is normal, a high non-reset control signal is output to the control end of the non-reset module 43, so that the non-reset module 43 is used to directly output the first start signal STV1 to the output end OUT of the reset circuit 40.

[0041] As shown in Figure 6 The non-reset module 43 includes a second transistor 431, the control end of the second transistor 431 is coupled with the output end of the determination module 41, the first end of the second transistor 431 is coupled with the first input end IN1 of the reset circuit 40, and the second end of the second transistor 431 is coupled with the output end OUT of the reset circuit 40. The second transistor 431 is used to conduct the first end and the second end under the control of the non-reset control signal. The second transistor 431 is an n-type transistor. The second transistor 431 in the non-reset module 43 only plays a role of a switch, and has a simple structure. When the determination module 41 determines that the level cooperation of the first start signal STV1 and the second start signal STV2 is normal, a high signal is output to the control end of the non-reset module 43, and the second transistor 431 is turned on under the control of the high signal, so that the first input end IN1 and the output end OUT of the reset circuit 40 are conducted, that is, the non-reset module 43 is used to directly output the first start signal STV1 to the output end OUT of the reset circuit 40.

[0042] In some embodiments, Figure 7 Another display panel provided by the embodiment of the present application is shown in a simplified schematic diagram, Figure 7 Only part of the structure and the connection relationship in the display panel are shown. As shown in Figure 7As shown, the display panel also includes a filtering circuit 50, which is connected between the first terminal 31 and the first input terminal of the reset circuit 40. The filtering circuit 50 is used to correct the amplitude of the first start signal STV1. The filtering circuit 50 has no effect on the first start signal STV1 within the normal amplitude range. In this embodiment of the invention, a filtering circuit 50 is provided. Before the reset circuit 40 receives the first start signal STV1, it first corrects any abnormal voltage amplitude of the first start signal STV1, and then the reset circuit 40 resets the level of the first start signal STV1. The filtering circuit 50 ensures that the voltage amplitude of the first start signal STV1 received by the first driving circuit 10 meets the requirements, thereby ensuring that the first start signal received by the first driving circuit 10 and the second start signal received by the second driving circuit 20 are matched, thus driving the pixel circuit normally and avoiding display abnormalities.

[0043] In one embodiment, taking the first start signal as the start signal required by the scan driving circuit as an example, the low-level signal output by the shift register in the scan driving circuit controls the pixel circuit to operate in the light-emitting stage. However, if low-level noise is superimposed during the high-level signal period of the first start signal, it may cause the shift register to output a low level at the time when it should output a high level, thus causing the light-emitting control transistor (such as...) in the pixel circuit to... Figure 2 The first light-emitting control transistor M5 and the second light-emitting control transistor M6 were abnormally turned on.

[0044] Figure 8 This is a schematic diagram of the waveforms of the initial signal before and after the filtering circuit. For example... Figure 8 As shown, STV1-1 is the first start signal received by the filter circuit 50, and STV1-2 is the first start signal output after being processed by the filter circuit 50. Due to electrostatic interference, the first start signal STV1-1 provided to the first terminal by the display driver chip is superimposed with sinusoidal noise. After being processed by the filter circuit 50, the low voltage part of the noise in the first start signal STV1-1 can be filtered out, thereby preventing the abnormal low-level signal output by the shift register in the scan driver circuit from causing the light-emitting control transistor to turn on abnormally.

[0045] In some implementations... Figure 9 A schematic diagram of a filter circuit provided in an embodiment of the present invention, such as... Figure 9As shown, the filter circuit 50 comprises a comparator 51, a current-limiting resistor 52 and a bidirectional transient diode 53; a first input end of the comparator 51 is coupled with the first terminal 31, a second input end of the comparator 51 is grounded, and an output end of the comparator 51 is coupled with a first end of the current-limiting resistor 52; a second end of the current-limiting resistor 52 and a first end of the bidirectional transient diode 53 are coupled with a first input end of the reset circuit 40, and a second end of the bidirectional transient diode 53 is grounded. The filter circuit 50 provided by the embodiment has simple structure, is easy to manufacture and occupies small space, and can correct the amplitude of the first start signal STV1 and has no effect on the first start signal STV1 within the normal amplitude.

[0046] Based on the same inventive concept, the embodiment of the present application also provides a display device, Figure 10 The display device provided by the embodiment of the present application is shown in a schematic diagram as Figure 10 As shown, the display device comprises the display panel 100 provided by any of the embodiments of the present application. The structure of the display panel 100 has been described in the above embodiments, and will not be repeated here. The display device provided by the embodiment of the present application may be, for example, a mobile phone, a computer, a tablet, a television or other electronic equipment.

[0047] The above only describes the preferred embodiments of the present application, and is not intended to limit the present application. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

[0048] Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present application, and not to limit them; although the present application has been described in detail with reference to the above embodiments, those skilled in the art should understand that: it can still modify the technical solutions recorded in the above embodiments, or make equivalent replacement to part or all of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A display panel, characterized in that, The display panel includes: A first driving circuit and a second driving circuit, each including multiple cascaded shift registers; one of the first driving circuits and the second driving circuit is a light-emitting driving circuit and the other is a scanning driving circuit. A first terminal and a second terminal, wherein the first terminal is used to transmit a first start signal and the second terminal is used to transmit a second start signal; the first start signal is a drive signal of the first drive circuit and the second start signal is a drive signal of the second drive circuit. A reset circuit, wherein a first input terminal of the reset circuit is coupled to the first terminal, a second input terminal of the reset circuit is coupled to the second terminal, and an output terminal of the reset circuit is coupled to the start signal receiving terminal of the first driving circuit; the reset circuit is used to reset and output the first start signal when the level coordination between the first start signal and the second start signal is abnormal; The reset circuit includes a determination module and a reset module, wherein the control terminal of the reset module is coupled to the output terminal of the determination module; The determination module is used to determine the level coordination between the received first start signal and the second start signal, and when the determination is abnormal, it sends a reset control signal to the reset module. The reset module, under the control of the reset control signal, provides the first start signal after reset to the output terminal of the reset circuit.

2. The display panel according to claim 1, characterized in that, The first start signal and the second start signal are respectively composed of a high-level signal and a low-level signal; The reset circuit is used to reset the first start signal to a high level signal and output it when both the first start signal and the second start signal are low level signals during the same time period.

3. The display panel according to claim 1, characterized in that, The determination module includes an OR gate, which is used to determine an abnormality when the first start signal and the second start signal are both low-level signals in the same time period, and output the reset control signal to the control terminal of the reset module. The reset control signal is a low-level signal.

4. The display panel according to claim 3, characterized in that, The reset module includes an inverter and a first transistor; the input terminal of the inverter is coupled to the first input terminal of the reset circuit, and the output terminal of the inverter is coupled to the first terminal of the first transistor; the control terminal of the first transistor is coupled to the output terminal of the determination module, and the second terminal of the first transistor is coupled to the output terminal of the reset circuit. The inverter is used to invert the phase of the first start signal and provide it to the first terminal of the first transistor, and the first transistor is used to turn on its first and second terminals under the control of the reset control signal.

5. The display panel according to claim 1, characterized in that, The reset circuit also includes a non-reset module, the control terminal of which is coupled to the output terminal of the determination module; The determination module is also used to determine the level coordination between the received first start signal and the second start signal within the same time period, and when the determination is normal, send a non-reset control signal to the non-reset module. The non-reset module, under the control of the non-reset control signal, directly provides the received first start signal to the output terminal of the reset circuit.

6. The display panel according to claim 5, characterized in that, The determination module includes an OR gate, which is used to determine that the signal is normal when the first start signal and the second start signal are both high-level signals or one is high-level signal and the other is low-level signal during the same time period, and outputs the non-reset control signal to the control terminal of the non-reset module. The non-reset control signal is a high-level signal.

7. The display panel according to claim 5, characterized in that, The non-reset module includes a second transistor, the control terminal of which is coupled to the output terminal of the determination module, the first terminal of which is coupled to the first input terminal of the reset circuit, and the second terminal of which is coupled to the output terminal of the reset circuit; the second transistor is used to turn on its first and second terminals under the control of the non-reset control signal.

8. The display panel according to claim 1, characterized in that, The display panel further includes a filtering circuit connected between the first terminal and the first input terminal of the reset circuit. The filtering circuit is used to correct the amplitude of the first start signal.

9. The display panel according to claim 8, characterized in that, The filter circuit includes a comparator, a current-limiting resistor, and a bidirectional transient diode; The first input terminal of the comparator is coupled to the first terminal, the second input terminal of the comparator is grounded, and the output terminal of the comparator is coupled to the first terminal of the current-limiting resistor. The second end of the current-limiting resistor and the first end of the bidirectional transient diode are coupled to the first input terminal of the reset circuit, and the second end of the bidirectional transient diode is grounded.

10. A display device, characterized in that, Includes the display panel as described in any one of claims 1 to 9.

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