Display device and driving method of display device

Abstract

The application discloses a display device and a driving method thereof, relates to the technical field of overcurrent, and is characterized in that a standby gate drive circuit is arranged on a chip on film, and the standby gate drive circuit is connected with a clock signal output end through a switch module, so that when the current of the clock signal output from the clock signal output end is equal to or greater than a preset current, the clock signal is introduced into a display panel through the standby gate drive circuit by the opened switch module, and meanwhile, the situation that the two original gate drive circuits are short-circuited to cause the chip on film to be burnt out is avoided when the current of the clock signal input through another original gate drive circuit adjacent to the original gate drive circuit is also equal to or greater than the preset current, so that the function of preventing the chip on film from being burnt out is considered, and the normal display of the display panel is ensured.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of overcurrent protection, in particular to a display device and a driving method of the display device. BACKGROUND

[0002] The chip on film is an important component of the display panel, and the chip on film is bonded on the panel and the printed circuit board through a thin film by the source driving chip. The chip on film transmits the input clock signal to the GOA (Gate on Array) circuit to realize the function of the gate row-by-row scanning, so that the internal timing output of the GOA is normal, and the normal display of the display panel is ensured.

[0003] However, the existing chip on film is prone to burnout. When the input current of the two adjacent gate driving lines in the chip on film exceeds the bearable current value, the two gate driving lines will be short-circuited, a large amount of heat will be generated, the chip on film will be burned out, and the display image will be abnormal.

[0004] In view of the above abnormal situation, the conventional method is to select a level conversion chip with overcurrent protection function. When the number of large currents detected by the level conversion chip within a specified time reaches the protection specification, the level conversion chip will automatically break the circuit, thereby preventing the chip on film from burning out. However, at this time, there is no clock signal transmitted to the GOA to drive the display panel, and the normal display of the display image cannot be realized. SUMMARY

[0005] The main purpose of the present application is to provide a display device and a driving method of the display device, which aims to solve the technical problem that the conventional scheme for preventing the chip on film from burning out cannot simultaneously prevent burning out and realize normal display of the display image.

[0006] To achieve the above purpose, the present application provides a display device, comprising:

[0007] a circuit board and a display panel, and a chip on film connected between the two;

[0008] a clock signal output end and a switch module are arranged on the circuit board;

[0009] a standby gate driving line and an original gate driving line are arranged on the chip on film, the original gate driving line is directly connected with the clock signal output end, and the standby gate driving line is connected with the clock signal output end through the switch module;

[0010] when the current of the clock signal output from the clock signal output end is less than a preset current, the switch module is closed, and the clock signal is input into the display panel through the original gate driving line;

[0011] When the current of the clock signal output from the clock signal output terminal is greater than or equal to a preset current, the switch module is opened, and the clock signal is input to the display panel through the backup gate drive line.

[0012] Optionally, the switch module comprises a resistor and a first field effect transistor.

[0013] One end of the resistor is connected to the clock signal output terminal, the other end of the resistor is connected to the control end of the first field effect transistor, the input end of the first field effect transistor is connected to the clock signal output terminal, and the output end of the first field effect transistor is connected to the input end of the backup gate drive line.

[0014] Optionally, the first to M original gate drive lines are sequentially arranged on the COF, and the first to M original gate drive lines are used for receiving the first to M clock signals, respectively.

[0015] The switch module comprises a first switch module and a second switch module.

[0016] The backup gate drive line comprises a first backup gate drive line connected to the first switch module and a second backup gate drive line connected to the second switch module.

[0017] The first switch module can receive the clock signals numbered with odd numbers in the first to M clock signals, and the second switch module can receive the clock signals numbered with even numbers in the first to M clock signals.

[0018] Optionally, the circuit board and the display panel are sequentially connected with N COFs, and the backup gate drive line and the original gate drive line are arranged on the first COF and the Nth COF.

[0019] Optionally, the width of the backup gate drive line is greater than the width of the original gate drive line.

[0020] Optionally, the display panel is provided with a reserved channel, and the input end of the reserved channel is connected to the output end of the backup gate drive line.

[0021] Optionally, the number of the reserved channels is consistent with the number of the backup gate drive lines, and the reserved channels are arranged at positions corresponding to the positions of the COFs provided with the backup gate drive lines on the display panel.

[0022] The application further provides a driving method of a display device, which comprises the following steps.

[0023] detecting a current change of the clock signal;

[0024] determining a preset current, comparing a current size relationship between the clock signal and the preset current,

[0025] determining a transmission mode of the clock signal based on the current size relationship, so as to transmit the clock signal to the display panel and drive the display panel.

[0026] Optionally, the transmission mode includes a backup transmission mode, and the step of determining the transmission mode of the clock signal based on the current size relationship includes:

[0027] in a case where the current of the clock signal is equal to or greater than the preset current, determining that the transmission mode is the backup transmission mode;

[0028] in the backup transmission mode, a switch module is opened, and the clock signal is input to the display panel through the backup gate drive circuit.

[0029] Optionally, the transmission mode further includes an original transmission mode, and the step of determining the transmission mode of the clock signal based on the current size relationship includes:

[0030] in a case where the current of the clock signal is less than the preset current, determining that the transmission mode is the original transmission mode;

[0031] in the original transmission mode, a switch module is closed, and the clock signal is input to the display panel through an original gate drive circuit.

[0032] The application sets the backup gate drive circuit on the chip on film, and connects the backup gate drive circuit with the clock signal output end through the switch module, so that when the current of the clock signal output from the clock signal output end is equal to or greater than the preset current, the clock signal is introduced to the display panel through the opened switch module and the backup gate drive circuit, thereby avoiding introducing the clock signal with the current equal to or greater than the preset current to the original gate drive circuit, preventing the original gate drive circuit from being burned out and causing the clock signal to be unable to be normally output to the display panel, and avoiding the situation that when another clock signal with the current equal to or greater than the preset current is introduced to the original gate drive circuit adjacent to the original gate drive circuit, the two burned-out original gate drive circuits are short-circuited, causing the chip on film to be burned out, and ensuring the display panel to normally display the clock signal. BRIEF DESCRIPTION OF DRAWINGS

[0033] Figure 1 is a terminal structure schematic diagram of a hardware running environment related to an embodiment scheme of the application;

[0034] Figure 2 A module schematic diagram of the connection relationship between the spare gate driving line and the original gate driving line and the clock signal output terminal of the present application;

[0035] Figure 3 A circuit schematic diagram of the connection relationship between the spare gate driving line and the original gate driving line and the clock signal output terminal of the present application;

[0036] Figure 4 A circuit schematic diagram of the connection relationship between the spare gate driving line and the original gate driving line and the clock signal output terminal of the present application;

[0037] Figure 5 A structure schematic diagram of the display device of the present application;

[0038] Figure 6 A structure schematic diagram of the spare gate driving line and the original gate driving line arranged on the chip of the present application;

[0039] Figure 7 A flow schematic diagram of the driving method embodiment of the display device of the present application.

[0040] Explanation of the reference signs:

[0041] Reference Name 10 Display panel COF Chip on film CK Clock signal output end 20 Switching module 20① First switching module 20② Second switching module L1 Original gate drive line L2 Backup gate drive line R Resistance M1 First field effect transistor L3 Original channel L4 Reserved channel 40 Circuit board

[0042] The object of the present application, the function features and the advantages will be further explained by combining the embodiments and referring to the drawings. DETAILED DESCRIPTION

[0043] It should be understood that the specific embodiments described herein are merely intended to explain the present application and not to limit the present application.

[0044] As Figure 1 shown, Figure 1 is a terminal structure schematic diagram of the hardware running environment involved in the embodiment scheme of the present application.

[0045] The driving method of the display device of the embodiment of the present application applies the carrier as the display device, such as Figure 1As shown, the display device can include a processor 1001, such as a CPU, a network interface 1004, a user interface 1003, a memory 1005, and a communication bus 1002. The communication bus 1002 is used to realize the connection communication between the components. The user interface 1003 can include a display area (Display), an input unit such as a keyboard (Keyboard), and the optional user interface 1003 can also include a standard wired interface, a wireless interface. The network interface 1004 can optionally include a standard wired interface, a wireless interface (such as a WI-FI interface). The memory 1005 can be a high-speed RAM memory, or a stable memory (non-volatile memory) such as a disk memory. The memory 1005 can also be an optional storage device independent of the aforementioned processor 1001.

[0046] The optional display device can also include a camera, an RF (Radio Frequency, radio frequency) circuit, a sensor, an audio circuit, a WiFi module, and the like. Among them, the sensor such as a light sensor, a motion sensor, and other sensors. Specifically, the light sensor can include an ambient light sensor and a proximity sensor, wherein the ambient light sensor can adjust the brightness of the display screen according to the brightness of the ambient light, and the proximity sensor can turn off the display screen and / or backlight when the mobile terminal is moved to the ear. As a kind of motion sensor, the gravity acceleration sensor can detect the size of acceleration in each direction (generally three axes), and can detect the size and direction of gravity when at rest, which can be used for identifying the posture of the mobile terminal. Application (such as horizontal and vertical screen switching, related games, magnetometer posture calibration), vibration recognition related functions (such as pedometer, knocking), etc. Of course, the mobile terminal can also be configured with a gyroscope, a barometer, a hygrometer, a thermometer, an infrared sensor and other sensors, which will not be repeated here.

[0047] Those skilled in the art can understand that Figure 1 The display device structure shown in the figure does not constitute a limitation on the display device, and can include more or fewer components than the figure, or combine certain components, or different component arrangements.

[0048] As Figure 1 As shown, the memory 1005 as a kind of computer storage medium can include an operating system, a network communication module, and a user interface module.

[0049] In Figure 1 As shown in the terminal, the network interface 1004 is mainly used to connect the background server and communicate data with the background server; the user interface 1003 is mainly used to connect the client (user end) and communicate data with the client; and the processor 1001 can be used to execute the driving method of the display device according to the memory 1005.

[0050] Referring to Figure 2 , Figure 2 is a module schematic diagram of the connection relationship between the backup gate drive line L2 and the original gate drive line L1 and the clock signal output end CK, comprising:

[0051] The circuit board 40 and the display panel 10, and the chip on film COF (refer to Figure 5 ) connected therebetween, the circuit board 40 is provided with a clock signal output end CK and a switch module 20, and the chip on film COF is provided with a backup gate drive line L2 and an original gate drive line L1. Continue to refer to Figure 2 , the original gate drive line L1 is directly connected with the clock signal output end CK, and the backup gate drive line L2 is connected with the clock signal output end CK through the switch module 20;

[0052] When the current of the clock signal output by the clock signal output end CK is less than the preset current, the switch module 20 is closed, and the clock signal is connected to the display panel 10 through the original gate drive line L1; when the current of the clock signal output by the clock signal output end CK is greater than or equal to the preset current, the switch module 20 is opened, and the clock signal is connected to the display panel 10 through the backup gate drive line L2.

[0053] The purpose of the embodiment is to prevent the short circuit caused by the connection of the two adjacent original gate drive lines L1 on the circuit board to the overloading current.

[0054] The embodiment proposes to set the gate drive line on the chip on film COF, specifically, on the basis of the original gate drive line L1, a new gate drive line is added, the added new gate drive line is used as a backup gate drive line L2, and the original gate drive line L1 is used to directly connect the clock signal to the display panel 10 through the original gate drive line L1 when the current of the clock signal output by the clock signal output end CK is less than the preset current, the backup gate drive line L2 is used to open the switch module 20 connected between the clock signal output end CK and the backup gate drive line L2 based on the current of the clock signal when the current of the clock signal output by the clock signal output end CK is equal to or greater than the preset current, and the clock signal is connected to the display panel 10 through the backup gate drive line L2 via the switch module 20, so as to avoid the burning caused by the connection of the original gate drive line L1 to the overloading current, and also avoid the short circuit of the two burned original gate drive lines L1 when another original gate drive line L1 adjacent to the original gate drive line L1 also connects the clock signal with a current equal to or greater than the preset current, and the burning of the chip on film COF.

[0055] The preset current is set according to a maximum current value that the original gate drive line L1 can bear in actual application.

[0056] Specifically, referring to FIG. 1, Figure 3 As shown in FIG. 1, the switch module 20 includes a resistor R and a first field effect transistor M1.

[0057] One end of the resistor R is connected to the clock signal output terminal CK, the other end of the resistor R is connected to the control terminal of the first field effect transistor M1, the input terminal of the first field effect transistor M1 is connected to the clock signal output terminal CK, and the output terminal of the first field effect transistor M1 is connected to the input terminal of the standby gate drive line L2.

[0058] The switch module 20 is described in combination with Figure 3 When the current of the clock signal output by the clock signal output terminal CK reaches or is greater than the preset current, at this time, the current is converted into an input voltage by the resistor R and output to the control terminal of the first field effect transistor M1, so that the first field effect transistor M1 is turned on, so that the input terminal of the first field effect transistor M1 starts to access the clock signal, and the accessed clock signal is output to the standby gate drive line L2 through the output terminal of the first field effect transistor M1, so that the switch module 20 opens the access of the clock signal to the standby gate drive line L2 when the current of the accessed clock signal is equal to or greater than the preset current, avoiding the burnout of the chip on film (COF) caused by the flow of the clock signal into the original gate drive line L1, while ensuring that the clock signal can be normally transmitted to the display panel 10, and taking into account the effects of preventing burnout and normal display of the display picture.

[0059] When the current of the clock signal output by the clock signal output terminal CK is less than the preset current, at this time, the resistor R can still convert the current of the clock signal into an input voltage and output the converted input voltage to the control terminal of the first field effect transistor M1, but because the input voltage does not reach the turn-on voltage of the first field effect transistor M1, the first field effect transistor M1 is in a closed state at this time, avoiding the situation that the original gate drive line L1 and the standby gate drive line L2 simultaneously access the same clock signal, causing the GOA circuit on the display panel 10 to receive repeated clock signals and resulting in timing disorder of the clock signal.

[0060] It should be noted that the first field effect transistor M1 in the embodiment is an N-type field effect transistor.

[0061] In some embodiments, the number of standby gate drive lines L2 can be equal to the number of original gate drive lines L1, that is, one standby gate drive line L2 only serves as a standby transmission path for one original gate drive line L1, and one standby gate drive line L2 can only receive one kind of clock signal, which is conducive to improving the accuracy of signal transmission.

[0062] In some embodiments, the number of backup gate drive lines L2 can be less than the number of original gate drive lines L1, one backup gate drive line L2 can serve as a backup transmission path for multiple original gate drive lines L1, and one backup gate drive line L2 can receive multiple clock signals, which is conducive to reducing the number of backup gate drive lines L2 and ensuring that the size of the chip on film COF remains within a small range. This will be described in detail below.

[0063] Specifically, in combination with reference to Figures 4-6 , the chip on film COF is sequentially provided with a first original gate drive line to an Mth original gate drive line, and the first original gate drive line to the Mth original gate drive line are respectively used to receive a first clock signal to an Mth clock signal.

[0064] Referring to Figure 4 , the switch module 20 includes a first switch module 20 and a second switch module 20, the backup gate drive line L2 includes a first backup gate drive line L2 connected to the first switch module 20, and a second backup gate drive line L2 connected to the second switch module 20;

[0065] Among them, the first switch module 20 can receive the first clock signal to the Mth clock signal numbered as odd; the second switch module 20 can receive the first clock signal to the Mth clock signal numbered as even.

[0066] Referring to Figure 4 It can be seen that the essential circuit structure of the first switch module 20 and the second switch module 20 is the same, and the difference is that the backup gate drive line L2 accessed by them is different.

[0067] Referring to Figure 4 It can be seen that the switch module 20 provided on the chip on film COF in the embodiment is sequentially accessed to the backup gate drive line L2 according to the clock signal output end CK number.

[0068] In the original chip on film COF, the chip on film COF is sequentially provided with a first original gate drive line to an Mth original gate drive line, and the first original gate drive line to the Mth original gate drive line are respectively used to receive a first clock signal to an Mth clock signal. For example, referring to Figure 6The first original gate drive line L11, the second original gate drive line L12, the third original gate drive line L13, the fourth original gate drive line L14, the fifth original gate drive line L15 and the sixth original gate drive line L16 are sequentially arranged on the chip on film COF, and the first original gate drive line L11 to the sixth original gate drive line L16 are respectively used for receiving the first clock signal to the sixth clock signal. When the currents of the clock signals accessed by the first original gate drive line L1 and the second original gate drive line L1 are equal to or greater than a preset current, the first original gate drive line L1 and the second original gate drive line L1 are short-circuited, a large amount of heat is generated, and the chip on film COF provided with the first original gate drive line and the second original gate drive line is burned.

[0069] Therefore, based on the above situation, referring to the circuit board 40 shown in Figure 4 There are six switch modules 20 and six clock signal output ends CK corresponding to the six switch modules 20, that is, three first switch modules 20① are respectively arranged corresponding to the first clock signal output end CK1, the third clock signal output end CK3 and the fifth clock signal output end CK5, and three second switch modules 20② are respectively arranged corresponding to the second clock signal output end CK2, the fourth clock signal output end CK4 and the sixth clock signal output end CK6. Therefore, the first standby gate drive line L2① can receive the first clock signal, the third clock signal and the fifth clock signal through the three first switch modules 20① respectively. The second standby gate drive line L2② can receive the second clock signal, the fourth clock signal and the sixth clock signal through the three second switch modules 20② respectively.

[0070] That is, the embodiment adopts the method of diverging into the same standby gate drive line L2, so that the adjacent two original gate drive lines L1 can use different standby gate drive lines L2 as standby transmission paths, thereby avoiding the short circuit caused by the burning of the adjacent two original gate drive lines L1. It should be noted that although one standby gate drive line L2 can receive multiple clock signals, in actual work of the display device, only the adjacent two original gate drive lines L1 are usually burned and short-circuited. Therefore, the two standby gate drive lines L2 can respectively transmit the clock signals corresponding to the two original gate drive lines L1 which are short-circuited, so as to meet the demand of signal transmission.

[0071] Referring to Figure 5 The circuit board and the display panel 10 are sequentially connected with N chip on films COF, and the standby gate drive line L2 and the original gate drive line L1 are arranged on the first chip on film COF and the Nth chip on film COF.

[0072] It should be noted that the chip on film COF provided with the original gate drive line L1 only exists on the first chip on film COF and the last chip on film COF (i.e. the Nth chip on film COF) of the entire display device, and the 2nd chip on film COF to the N-1th chip on film COF can not be provided with the original gate drive line L1. Therefore, the embodiment only needs to add the standby gate drive line L2 to the first chip on film COF and the last chip on film COF of the entire display device.

[0073] For example, the order of all chip on films COF included in the display device is chip on film COF ①, chip on film COF ②, chip on film COF ③, chip on film COF ④, chip on film COF ⑤ and chip on film COF ⑥, a total of six chip on films COF, so at this time only chip on film COF ① and chip on film COF ⑥ need to be provided with the standby gate drive line L2. Referring to Figure 6 , chip on film COF ① and chip on film COF ⑥ are connected to two groups of clock signals respectively, so at this time two standby gate drive lines L2 are provided on chip on film COF ① and chip on film COF ⑥ respectively, plus the original one clock signal corresponding to one original gate drive line L1, so at this time chip on film COF ① and chip on film COF ⑥ each have eight gate drive lines.

[0074] Among them, because the standby gate drive line L2 is provided on the chip on film COF, the area of the chip on film COF needs to be expanded for applicability, while ensuring the distance between the gate drive lines, in the embodiment, the distance between the original gate drive line L1 and the standby gate drive line L2 is 36μm.

[0075] Further, referring to Figure 6 , the width of the standby gate drive line L2 is greater than the width of the original gate drive line L1.

[0076] By setting the width of the standby gate drive line L2 to be greater than the width of the original gate drive line L1, the resistivity of the standby gate drive line L2 is reduced, the safety of the standby gate drive line L2 is improved, and the burning of the standby gate drive line L2 is avoided. In other embodiments, the width of the standby gate drive line L2 can also be equal to the width of the original gate drive line L1.

[0077] Further, referring to Figure 5The display panel 10 is provided with reserved channels L4, input ends of the reserved channels L4 are connected with output ends of the backup gate drive lines L2, the number of the reserved channels L4 is consistent with the number of the backup gate drive lines L2, and the reserved channels L4 are arranged at positions corresponding to the chip on film COF provided with the backup gate drive lines L2 on the display panel 10. Figure 5 L3 in the formula is an original channel connected with an output end of an original gate drive line L1.

[0078] Because the input end of the reserved channel L4 is connected with the output end of the backup gate drive line L2, and is used for receiving the clock signal transmitted by the backup gate drive line L2, the number of the reserved channels L4 arranged on the display panel 10 in the embodiment is consistent with the number of the backup gate drive lines L2. Assuming that two backup gate drive lines L2 are added to the first chip on film COF and the last chip on film COF respectively, a total of four backup gate drive lines L2 are added to the display device, and correspondingly, four reserved channels L4 are added to the display panel 10, and the reserved channels L4 are also added to positions corresponding to the first chip on film COF and the last chip on film COF, so as to avoid that the length of the reserved channel L4 is too long.

[0079] For example, the reserved channels L4 corresponding to the backup gate drive lines L2 can be arranged on the side of the display panel 10. In addition, the display panel 10 is also provided with original channels L3 corresponding to the original gate drive lines L1. The number of the original channels L3 is equal to the number of the original gate drive lines L1. It should be noted that, Figure 5 All the original channels L3 are not shown.

[0080] Referring to Figure 7 , Figure 7 is a flowchart of an embodiment of a driving method of the display device, and the driving method of the display device comprises the following steps.

[0081] In step S10, the change of the current of the clock signal is detected.

[0082] As shown in Figure 3 , the gate of the first field effect transistor M1 of the switch module 20 is connected with the clock signal output end CK through a resistor R, so that the gate of the first field effect transistor M1 can automatically detect the change of the current. In other embodiments, the switch module of the display device can also be provided with a current detection module for detecting the change of the current of the clock signal, the current detection module is connected with the gate of the first field effect transistor M1, so as to timely switch the transmission mode of the clock signal.

[0083] Step S20, determine a preset current, compare the current of the clock signal with the current of the preset current.

[0084] Step S30, determine the transmission mode of the clock signal based on the current size relationship, so as to transmit the clock signal to the display panel and drive the display panel.

[0085] After determining the maximum current value, i.e. the preset current, that the original gate drive line can bear, the current size relationship between the input clock signal and the preset current is compared, so as to determine the transmission mode of the clock signal based on the current size relationship, thereby avoiding burning of the chip on film while ensuring that the clock signal can be normally transmitted to the GOA circuit for normal display of the display screen.

[0086] Optionally, the step of determining the transmission mode of the clock signal based on the current size in step S30 comprises:

[0087] Step S301, in the case that the current of the clock signal is equal to or greater than the preset current, determining that the transmission mode is the backup transmission mode.

[0088] Step S302, in the backup transmission mode, the switch module is opened, and the clock signal is input to the display panel through the backup gate drive line.

[0089] When the current of the clock signal output by the clock signal output terminal reaches or is greater than the preset current, the current detection module outputs an enable signal for turning on the switch module, so that the backup transmission mode is triggered, the clock signal is input to the backup gate drive line based on the opened switch module, so as to transmit the input clock signal to the GOA circuit, thereby ensuring that the chip on film can still normally transmit the clock signal to the GOA circuit in the case that the current of the input clock signal is equal to or greater than the preset current, and the effects of preventing burning and normal display of the display screen are taken into account.

[0090] Optionally, the step of determining the transmission mode of the clock signal based on the current size in step S30 comprises:

[0091] Step S303, in the case that the current of the clock signal is less than the preset current, determining that the transmission mode is the original transmission mode.

[0092] Step S304, in the original transmission mode, the switch module is closed, and the clock signal is input to the display panel through the original gate drive line.

[0093] When the current of the clock signal output by the clock signal output end is detected by the current detection module and is less than the preset current, the original transmission mode is triggered, the current of the clock signal fails to activate the switch module, and the clock signal is directly transmitted to the GOA circuit through the original gate drive circuit, thereby ensuring normal transmission of the clock signal.

[0094] In the embodiment, the preset current is determined by detecting the current change of the accessed clock signal, the current of the clock signal is compared with the preset current, the transmission mode of the clock signal is determined based on the current relationship, and the clock signal is transmitted to the display panel to drive the display panel, thereby ensuring normal transmission of the clock signal to the GOA circuit and normal display of the display image while avoiding burning of the COF.

[0095] It should be noted that in this document, the terms "comprise", "comprise", or any other variant thereof are intended to cover non-exclusive inclusion, so that a process, method, article or system including a series of elements includes not only those elements, but also other elements not explicitly listed, or other elements inherent to such a process, method, article or system. Without more limitations, the element defined by the statement "comprises a" does not exclude the presence of another identical element in the process, method, article or system that includes the element.

[0096] The above-mentioned serial numbers of the embodiments of the application are only for description, and do not represent the advantages and disadvantages of the embodiments.

[0097] Through the above description of the embodiments, those skilled in the art can clearly understand that the above-mentioned embodiment method can be realized by software and necessary general hardware platform, of course, it can also be realized by hardware, but in many cases, the former is a better embodiment. Based on such understanding, the technical solutions of the present application can be embodied in the form of software product, which is stored in the above-mentioned storage medium (such as ROM / RAM, magnetic disk, optical disk), including a plurality of instructions for making a terminal device (which can be a mobile phone, computer, server, air conditioner or network device) execute the method of each embodiment of the present application.

[0098] The above is only the preferred embodiment of the present application, and does not limit the patent scope of the present application. Any equivalent structure or equivalent process transformation made by using the contents of the specification and drawings, or directly or indirectly applied to other related technical fields, is also included in the patent protection scope of the present application.

Claims

1. A display device, characterized by comprising: The display device comprises a circuit board, a display panel, and a chip on film (COF) connected between the circuit board and the display panel. The circuit board is provided with a clock signal output end and a switch module. The COF is provided with a standby gate drive circuit and an original gate drive circuit. The original gate drive circuit is directly connected to the clock signal output end. When the current of the clock signal output from the clock signal output end is less than a preset current, the switch module is closed, and the clock signal is connected to the display panel through the original gate drive circuit. When the current of the clock signal output from the clock signal output end is greater than or equal to the preset current, the switch module is opened, and the clock signal is connected to the display panel through the standby gate drive circuit.

2. The display device according to claim 1, wherein the switch module comprises a resistor and a first field effect transistor. One end of the resistor is connected to the clock signal output end, the other end of the resistor is connected to the control end of the first field effect transistor, the input end of the first field effect transistor is connected to the clock signal output end, and the output end of the first field effect transistor is connected to the input end of the standby gate drive circuit. The COF is sequentially provided with a first original gate drive circuit to an Mth original gate drive circuit, and the first original gate drive circuit to the Mth original gate drive circuit are respectively used for receiving a first clock signal to an Mth clock signal.

3. The display device according to any one of claims 1-2, characterized in that, The switch module comprises a first switch module and a second switch module. The standby gate drive circuit comprises a first standby gate drive circuit connected to the first switch module and a second standby gate drive circuit connected to the second switch module. The first switch module can receive odd-numbered clock signals in the first clock signal to the Mth clock signal, and the second switch module can receive even-numbered clock signals in the first clock signal to the Mth clock signal. The circuit board and the display panel are sequentially connected with N COFs, and the standby gate drive circuit and the original gate drive circuit are arranged on a first COF and an Nth COF.

4. The display device of any one of claims 1, wherein, The width of the standby gate drive circuit is greater than the width of the original gate drive circuit.

5. The display device of any one of claims 1, wherein, 6. The display device according to any one of claims 1-2, wherein the display panel is provided with a reserved channel, and an input end of the reserved channel is connected to an output end of the standby gate drive circuit. The number of the reserved channels is consistent with the number of the standby gate drive circuits, and the reserved channels are arranged at positions of the display panel corresponding to the COFs provided with the standby gate drive circuits. The driving method of the display device is applied to the display device according to any one of claims 1-7, and the driving method of the display device comprises the following steps:

7. The display device according to claim 3, wherein detecting the change of the current of the clock signal; 8. A driving method of a display device, comprising the steps of: determining a preset current, and comparing and determining the current size relationship between the current of the clock signal and the preset current, ​ ​ Determine a transmission mode of the clock signal based on the current magnitude relationship, and transmit the clock signal to the display panel in the transmission mode to drive the display panel.

9. The driving method of a display device according to claim 8, wherein The transmission mode includes a backup transmission mode, and the step of determining the transmission mode of the clock signal based on the current magnitude relationship includes: In a case where the current of the clock signal is equal to or greater than the preset current, determine the transmission mode as the backup transmission mode; In the backup transmission mode, the switch module is opened, and the clock signal is input to the display panel through the backup gate driving line.

10. The driving method of a display device according to claim 8, wherein The transmission mode further includes an original transmission mode, and the step of determining the transmission mode of the clock signal based on the current magnitude relationship includes: In a case where the current of the clock signal is less than the preset current, determine the transmission mode as the original transmission mode; In the original transmission mode, the switch module is closed, and the clock signal is input to the display panel through the original gate driving line.

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